NOR flash memory manufacturing method
By forming drain zone grooves and peripheral isolation grooves on the semiconductor substrate of NOR flash memory, and filling the trench isolation oxides, combined with the process of forming an air gap at the source zone groove, the problem of increasing the coupling effect of the polysilicon gate at the source end at the lower technology node is solved, and the effect of improving device performance and reliability is achieved, while meeting the independent Pickup requirements at the drain end.
Patent Information
- Application Number
- CN202311413739.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-27
- Publication Date
- 2025-04-29
AI Technical Summary
During the development of NOR flash memory at lower technology nodes, the coupling effect between the polysilicon gates at the source end increases, affecting device performance and reliability. The leakage end requires an independent Pickup structure and cannot use the air gap process.
By forming a drain zone groove and an outer isolation groove on the semiconductor substrate and filling the trench isolation oxide, then forming an air gap at the source zone groove, an air gap process at the source end is achieved while ensuring good filling of the drain end.
The coupling effect between the polysilicon gates at the source end is reduced, the performance and reliability of NOR flash memory is improved, and the independent Pickup requirements at the leakage end are met.
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Figure CN119907243A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to semiconductor manufacturing technology, and in particular to a NOR flash memory manufacturing method. Background Art
[0002] NOR (or non-) type ETOX (Erasable Programmable Read Only Memory with Tunnel Oxide or EPROM with Tunnel Oxide, erasable programmable read-only register tunnel oxide layer) flash memory (hereinafter referred to as NOR flash memory) is a non-volatile flash memory with high read speed, high reliability and in-chip execution capability. It has become one of the most widely used non-volatile memories. With the advancement of manufacturing technology and the increasing market demand for large-capacity, high-density, and low-power NOR flash memory, NOR flash memory has gradually transitioned from the mass-produced 65nm / 55nm node to the research and development and mass production of 40nm+ nodes. The source polysilicon gate gap (Gap) of NOR flash memory with smaller technology nodes is further reduced compared with 65 / 55nm NOR flash memory, and the coupling effect between polysilicon gates will continue to increase, which will affect its performance and reliability. In the development of NOR flash memory with lower nodes, new process flows need to be developed to reduce its coupling effect to improve device performance and reliability.
[0003] An effective way to reduce the coupling effect of the polysilicon gates on both sides of the source end is to use a filling medium with a lower dielectric constant. Among the optional filling media, air has a very low dielectric constant. For reference, the relative dielectric constant of the most commonly used filling material, silicon dioxide, is about 3.9, while the relative dielectric constant of air is about 1. Therefore, replacing the existing silicon dioxide as the filling material between the source end polysilicon gates with an air gap can significantly reduce its coupling effect.
[0004] On the other hand, the drain space of NOR flash memory is large, and the coupling effect of the polysilicon gate on both sides of the drain is very weak, so the impact on performance and reliability can be ignored. However, unlike the structure where multiple sources share a pickup point, each bit of NOR flash memory must have an independent drain pickup point. Considering the subsequent contact process of the drain pickup, the drain needs to be well filled, and the air gap process cannot be used. Summary of the invention
[0005] The technical problem to be solved by the present invention is to provide a NOR flash memory manufacturing method, which can form an air gap at the source end of the NOR flash memory and ensure that the drain end is well filled at the same time, thereby reducing the coupling effect between the source end polysilicon gates, weakening the coupling effect between the polysilicon gates on both sides, and improving the performance and reliability of the NOR flash memory.
[0006] In order to solve the above technical problems, the present invention provides a method for manufacturing a NOR flash memory, which comprises the following steps:
[0007] S1. Providing a semiconductor substrate 100, which is divided into a storage area A and a logic area B, and the storage area A includes a source area AA and a drain area AB;
[0008] S2. forming a gate oxide layer 210 on the surface of the semiconductor substrate 100, and forming a gate structure 220 on the gate oxide layer 210 located in the storage area A, and forming a peripheral polysilicon layer 230 on the gate oxide layer 210 located in the logic area B; wherein the gate structure 220 includes a floating gate polysilicon layer 221, an inter-gate dielectric layer 222, and a control gate polysilicon layer 223 stacked sequentially from bottom to top;
[0009] S3. Photolithography opens the drain area AB window of storage area A;
[0010] S4. Etching and removing the gate structure 220 of the drain region AB to expose the gate oxide layer 210, forming a drain groove 310;
[0011] The peripheral polysilicon layer 230 is etched to form a peripheral polysilicon gate 230a, and peripheral isolation trenches 320 are formed on both sides of the peripheral polysilicon gate 230a;
[0012] S5. Depositing a barrier silicon nitride layer 820;
[0013] S6. Depositing a trench isolation oxide 410, the trench isolation oxide 410 is filled with and higher than the drain region trench 310 and the peripheral isolation trench 320;
[0014] S7. Chemical mechanical polishing removes the trench isolation oxide 410 on the upper surface of the peripheral polysilicon gate 230a and the source gate structure 220, and stops at the blocking silicon nitride layer 820;
[0015] S8. Photolithography, opening the window in the middle of the source gate structure 220 and the window of the source gate structure 220 adjacent to the peripheral isolation trench 320;
[0016] S9. Etching to expose the semiconductor substrate 100 at the middle of the source gate structure and the semiconductor substrate 100 at the source gate structure adjacent to the peripheral isolation trench 320 to form a source trench 330;
[0017] S10. Remove the photoresist;
[0018] S11. Forming a source region gate sidewall 701 on the source region trench 330 side of the storage region gate structure;
[0019] S12. Removing the blocking silicon nitride layer 820 on the upper surface of the storage area gate structure and the peripheral polysilicon gate 230a;
[0020] S13. Deposition of SiH4 layer 420 is performed; due to poor filling of SiH4, an air gap is formed at the source region groove 330;
[0021] S14. Deposition of protective oxide layer 430 and chemical mechanical polishing;
[0022] S15. Photolithography and etching are performed to expose the semiconductor substrate 100 at the center of the drain groove 310 to form a drain contact hole 900;
[0023] S16 . Fill the contact hole 900 with metal 910 .
[0024] Optionally, after step S2, a hard mask layer 610 and a bottom anti-reflective coating 620 are sequentially deposited, and then step S3 is performed;
[0025] In step S4, the gate structure 220 of the drain area AB is first etched away to expose the gate oxide layer 210 to form a drain groove 310, and the photoresist and the bottom anti-reflective coating 620 are removed; then the peripheral polysilicon layer 230 is etched to form a peripheral polysilicon gate 230a, and peripheral isolation grooves 320 are formed on both sides of the peripheral polysilicon gate 230a, and the hard mask layer 610 is removed.
[0026] Optionally, after step S4, source / drain regions and logic region sidewalls 700 are first formed on both sides of the gate structure of the storage region A and on both sides of the peripheral polysilicon gate 230a, and then step S5 is performed.
[0027] Optionally, after step S4, source and drain regions and logic region sidewalls 700 are first formed on both sides of the gate structure of storage area A and on both sides of the peripheral polysilicon gate 230a, and then metal silicide is formed on the upper end of the gate structure of storage area A and on the upper end of the peripheral polysilicon gate 230a, and then step S5 is performed.
[0028] Optionally, after step S12, a metal silicide 810 is formed on the upper end of the storage region gate structure and the upper end of the peripheral polysilicon gate 230a, and then step S13 is performed.
[0029] Optionally, in S12, pre-baking and dry etching are performed to remove the oxide and nitride on the polysilicon gate separately to expose the polysilicon.
[0030] Optionally, in step S9, self-aligned source etching is adopted to expose the semiconductor substrate 100 at the middle of the source region gate structure and the semiconductor substrate 100 near the peripheral isolation trench of the source region gate structure, forming a source region trench 330.
[0031] Optionally, in step S9, surface O2 treatment is first performed to increase the adhesion of the photoresist, and then etching is carried out.
[0032] Optionally, in step S9, after the source region trench 330 is formed, ion implantation is performed on the semiconductor substrate 100 at the source region trench 330 to form a source terminal take-out point.
[0033] Optionally, in step S6, the trench isolation oxide 410 is deposited by using a HDP chemical vapor deposition process;
[0034] In step S11, the source region gate sidewall 701 is deposited by using an ALD process;
[0035] The thickness of the source region gate sidewall 701 is
[0036] In step S14, a protective oxide layer 430 is formed by plasma enhanced chemical vapor deposition.
[0037] Optionally, after step S15, Ti / TiN is deposited on the surface of the semiconductor substrate 100 at the bottom of the drain region contact hole 900 and a thermal process is carried out to form a TiSi structure, and then step S16 is performed.
[0038] Optionally, the thickness of the Ti / TiN deposited on the surface of the semiconductor substrate 100 at the bottom of the drain region contact hole 900 is The annealing temperature of the subsequent thermal process is 500°C to 600°C.
[0039] Optionally, 4h1 < h2, where h1 is the thickness of the barrier silicon nitride layer 820 and h2 is the width of the drain region trench 310;
[0040] The width of the source region trench 330 is less than 55 nm.
[0041] Optionally, in step S16, the contact hole 900 is filled with tungsten metal and chemical mechanical polishing is carried out.
[0042] Optionally, in step S1, shallow trench isolation is formed in the semiconductor substrate 100;
[0043] The inter-gate dielectric layer 222 is composed of a bottom oxide layer 222a, a middle nitride layer 222b, and a top oxide layer 222c stacked in sequence.
[0044] The NOR flash memory manufacturing method of the present invention first forms a drain region groove 310 and a peripheral isolation groove 320 and fills the trench isolation oxide 410, then forms a source region groove 330, and then deposits a SiH4 layer 420; due to the poor filling property of SiH4, an air gap can be formed at the source region groove 330 with a smaller gap. At this time, since the drain region groove 310 of the drain region AB of the storage area and the peripheral isolation groove 320 at the logic area B have been filled in step S6, they will not be affected.
[0045] The NOR flash memory manufacturing method of the present invention forms an air gap (AirGap) at the source end of the NOR flash memory based on a source end post-preparation process, which can simultaneously ensure that the drain end is well filled, thereby reducing the coupling effect between the source end polysilicon gates, weakening the coupling effect between the polysilicon gates on both sides, and improving the performance and reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0046] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0047] Figure 1 to Figure 15 It is a cross-sectional structural schematic diagram of a formation process of an embodiment of a method for manufacturing a NOR flash memory of the present invention.
[0048] Description of reference numerals:
[0049] 100 semiconductor substrate; A storage area; B logic area; AA source area; AB drain area; 210 gate oxide layer; 220 gate structure; 230 peripheral polysilicon layer; 221 floating gate polysilicon layer; 222 intergate dielectric layer; 223 control gate polysilicon layer; 230a peripheral polysilicon gate; 310 drain area groove; 320 peripheral isolation groove; 820 blocking silicon nitride layer; 410 trench isolation oxide; 330 source area groove; 701 source area gate sidewall; 420 SiH4 layer; 430 protective oxide layer; 900 drain area contact hole; 610 hard mask layer; 620 bottom anti-reflective coating; 700 source and drain area and logic area sidewall; 810 metal silicide; 222a bottom oxide layer; 222b middle nitride layer; 222c top oxide layer; 910 metal. DETAILED DESCRIPTION
[0050] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0051] The words "first", "second" and similar terms used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprises" and similar terms mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", "front", "back" and the like are only used to indicate relative position relationships. When the absolute position of the object being described changes, the relative position relationship may also change accordingly.
[0052] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.
[0053] Embodiment 1
[0054] A method for manufacturing a NOR flash memory comprises the following steps:
[0055] S1. Provide a semiconductor substrate 100, which is divided into a storage area A and a logic area B, and the storage area A includes a source area AA and a drain area AB, such as Figure 1 As shown;
[0056] S2. forming a gate oxide layer 210 on the surface of the semiconductor substrate 100, and forming a gate structure 220 on the gate oxide layer 210 located in the storage area A, and forming a peripheral polysilicon layer 230 on the gate oxide layer 210 located in the logic area B; wherein the gate structure 220 includes a floating gate polysilicon layer 221, an inter-gate dielectric layer 222 and a control gate polysilicon layer 223 stacked in sequence from bottom to top, such as Figure 2 As shown;
[0057] S3. Photolithography opens the drain area AB window of storage area A, such as Figure 3 As shown;
[0058] S4. Etching and removing the gate structure 220 of the drain region AB to expose the gate oxide layer 210, forming a drain groove 310;
[0059] The peripheral polysilicon layer 230 is etched to form a peripheral polysilicon gate 230a. Peripheral isolation trenches 320 are formed on both sides of the peripheral polysilicon gate 230a. Figure 4 As shown;
[0060] S5. Depositing a barrier silicon nitride layer 820; the first deposited barrier silicon nitride layer 820 is used as a subsequent etch stop layer (CESL, Contact Etch Stop Layer);
[0061] S6. Depositing trench isolation oxide 410, trench isolation oxide 410 fills and is higher than drain region trench 310 and peripheral isolation trench 320, such as Figure 5 As shown;
[0062] S7. Chemical mechanical polishing (CMP) removes the peripheral polysilicon gate 230a and the trench isolation oxide 410 on the surface of the source gate structure 220, and stops at the blocking silicon nitride layer 820, such as Figure 6 As shown;
[0063] S8. Photolithography, open the middle window of the source gate structure 220 and the window of the source gate structure 220 adjacent to the peripheral isolation trench 320, such as Figure 7 As shown;
[0064] S9. Etching to expose the semiconductor substrate 100 at the middle of the source region gate structure and the semiconductor substrate 100 at the source region gate structure adjacent to the peripheral isolation trench 320 to form a source region trench 330, such as Figure 8 As shown;
[0065] S10. Remove the photoresist, such as Fig. 9 As shown;
[0066] S11. Forming a source region gate sidewall 701 on the source region groove 330 side of the storage region gate structure, such as Fig.10 As shown;
[0067] S12. Remove the blocking silicon nitride layer 820 on the upper surface of the storage area gate structure and the peripheral polysilicon gate 230a, such as Fig.11 As shown;
[0068] S13. Deposition of SiH4 layer 420 is performed; due to the poor filling property of SiH4, an air gap can be formed at the source region groove 330 with a smaller gap, such as Fig.12 As shown;
[0069] S14. Deposition of protective oxide layer 430 and chemical mechanical polishing (CMP) are performed, such as Fig.13 As shown;
[0070] S15. Photolithography and etching are performed to expose the semiconductor substrate 100 at the center of the drain region groove 310 to form a drain region contact hole 900, such as Fig.14 As shown;
[0071] S16. Fill the contact hole 900 with metal 910, such as Fig.15 shown.
[0072] In the NOR flash memory manufacturing method of the first embodiment, the drain region groove 310 and the peripheral isolation groove 320 are first formed and filled with the trench isolation oxide 410, and then the source region groove 330 is formed, and then the SiH4 layer 420 is deposited; due to the poor filling property of SiH4, an air gap can be formed at the source region groove 330 with a smaller gap. At this time, since the drain region groove 310 of the drain region AB of the storage area and the peripheral isolation groove 320 at the logic area B have been filled in step S6, they will not be affected.
[0073] The NOR flash memory manufacturing method of the first embodiment forms an air gap at the source end of the NOR flash memory based on a source end post-preparation process, which can simultaneously ensure that the drain end is well filled, thereby reducing the coupling effect between the source end polysilicon gates, weakening the coupling effect between the polysilicon gates on both sides, and improving the performance and reliability of the NOR flash memory.
[0074] Embodiment 2
[0075] Based on the NOR flash memory manufacturing method of the first embodiment, after step S2, a hard mask layer 610 and a bottom anti-reflection coating (Bottom Anti Reflection Coating, BARC) 620 are sequentially deposited, and then step S3 is performed;
[0076] In step S4, the gate structure 220 of the drain region AB is first etched away to expose the gate oxide layer 210 to form a drain region groove 310, and the photoresist and the bottom anti-reflection coating (Bottom Anti Reflection Coating, BARC) 620 are removed; then the peripheral polysilicon layer 230 is etched to form a peripheral polysilicon gate 230a, and peripheral isolation grooves 320 are formed on both sides of the peripheral polysilicon gate 230a, and the hard mask layer 610 is removed.
[0077] Preferably, after step S4, source / drain regions and logic region sidewalls 700 are first formed on both sides of the gate structure of the storage region A and on both sides of the peripheral polysilicon gate 230a, and then step S5 is performed.
[0078] Preferably, after step S4, source and drain regions and logic region sidewalls 700 are first formed on both sides of the gate structure of storage area A and on both sides of the peripheral polysilicon gate 230a, and then metal silicide is formed on the upper end of the gate structure of storage area A and on the upper end of the peripheral polysilicon gate 230a, and then step S5 is performed.
[0079] Embodiment 3
[0080] Based on the NOR flash memory manufacturing method of the first embodiment, after step S12, a metal silicide 810 is formed on the upper end of the storage region gate structure and the upper end of the peripheral polysilicon gate 230a, and then step S13 is performed.
[0081] Preferably, in S12, PREB (pre bake) and dry etching are performed to remove the oxide and nitride on the polysilicon gate separately, exposing the polysilicon to facilitate the formation of metal silicide.
[0082] Embodiment 4
[0083] Based on the NOR flash memory manufacturing method of the first embodiment, in step S9, self-aligned source (SAS) etching is used to expose the semiconductor substrate 100 in the middle of the source gate structure and the semiconductor substrate 100 near the peripheral isolation trench of the source gate structure to form a source trench 330.
[0084] Preferably, in step S9, since there is more silicon nitride on the surface at this time, the adhesion between the photoresist and the silicon nitride is not good, it is necessary to first perform surface treatment (O2 treatment) to increase the adhesion of the photoresist, and then perform etching.
[0085] Preferably, in step S9 , after the source trench 330 is formed, ion implantation is performed on the semiconductor substrate 100 at the source trench 330 to form a source terminal pickup.
[0086] Preferably, in step S6 , the trench isolation oxide 410 is deposited by using a HDP (high density plasma) chemical vapor deposition process, which has good filling properties.
[0087] Preferably, in step S11, the source region gate sidewall 701 is deposited by using an ALD (atomic layer deposition) process, which has a low temperature and good conformality.
[0088] Preferably, the thickness of the source region gate sidewall 701 is
[0089] Preferably, in step S14, a protective oxide layer 430 is formed by TEOS (Tetraethoxysilane) PECVD (Plasma Enhanced Chemical Vapor Deposition).
[0090] Embodiment Five
[0091] Based on the NOR flash memory manufacturing method of Embodiment One, after step S15, Ti / TiN is deposited on the surface of the semiconductor substrate 100 at the bottom of the drain region contact hole 900 and a thermal process is performed to form a TiSi structure, and then step S16 is carried out.
[0092] Preferably, the thickness of the Ti / TiN deposited on the surface of the semiconductor substrate 100 at the bottom of the drain region contact hole 900 is The annealing temperature of the subsequent thermal process is 500°C to 600°C.
[0093] Since nickel silicide is not formed at the drain end of the storage region and the source and drain of the logic device, after the drain region contact hole 900 is formed, Ti / TiN is deposited and a TiSi structure is formed through an appropriate thermal process. At the same time, the sidewall of the drain region contact hole 900 serves as an adhesion layer, which can reduce the contact resistance of the drain region contact hole 900 and ensure device performance.
[0094] Preferably, 4h1 < h2, where h1 is the thickness of the blocking silicon nitride layer 820 and h2 is the width of the drain region trench 310.
[0095] Preferably, the width of the source region trench 330 is less than 55 nm.
[0096] Preferably, in step S16, the contact hole 900 is filled with tungsten metal and chemical mechanical polishing (CMP) is performed.
[0097] Preferably, in step S1, a shallow trench isolation (STI) is formed in the semiconductor substrate 100.
[0098] Preferably, the inter-gate dielectric layer 222 is composed of a bottom oxide layer 222a, an intermediate nitride layer 222b, and a top oxide layer 222c stacked in sequence.
[0099] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.
Claims
1. A method for manufacturing a NOR flash memory, characterized in that: The following steps are involved: S1. Providing a semiconductor substrate, which is divided into a storage area and a logic area, and the storage area includes a source area and a drain area; S2. forming a gate oxide layer on the surface of the semiconductor substrate, forming a gate structure on the gate oxide layer located in the storage area A, and forming a peripheral polysilicon layer on the gate oxide layer located in the logic area; wherein the gate structure includes a floating gate polysilicon layer, an inter-gate dielectric layer, and a control gate polysilicon layer stacked in sequence from bottom to top; S3. Photolithography opens the drain window of the storage area; S4. Etching and removing the gate structure of the drain region to expose the gate oxide layer to form a drain groove; Etching the peripheral polysilicon layer to form a peripheral polysilicon gate, wherein peripheral isolation grooves are formed on both sides of the peripheral polysilicon gate; S5. depositing a barrier silicon nitride layer; S6. Depositing trench isolation oxide, the trench isolation oxide is filled and higher than the drain region and the peripheral isolation trench; S7. Chemical mechanical polishing removes the trench isolation oxide on the upper surface of the peripheral polysilicon gate and the source region gate structure, and stops at the blocking silicon nitride layer; S8. Photolithography, opening a window in the middle of the source gate structure and a window of the peripheral isolation trench adjacent to the source gate structure; S9. Etching to expose the semiconductor substrate at the middle of the source region gate structure and the semiconductor substrate at the source region gate structure adjacent to the peripheral isolation trench to form a source region trench; S10. Remove the photoresist; S11. Forming a source region gate sidewall on the source region trench side of the storage region gate structure; S12. Removing the blocking silicon nitride layer on the upper surface of the storage area gate structure and the peripheral polysilicon gate; S13. Deposition of SiH4 layer is performed; due to poor filling of SiH4, an air gap is formed in the source region groove; S14. Performing protective oxide layer deposition and chemical mechanical polishing; S15. Photolithography and etching are performed to expose the semiconductor substrate at the center of the drain groove to form a drain contact hole; S16. Fill the contact holes with metal.
2. The method for manufacturing a NOR flash memory according to claim 1, wherein: After step S2, a hard mask layer and a bottom anti-reflection coating are deposited in sequence, and then step S3 is performed; In step S4, the gate structure of the drain region is first etched away to expose the gate oxide layer to form a drain region groove, and the photoresist and bottom anti-reflective coating are removed; Then, the peripheral polysilicon layer is etched to form a peripheral polysilicon gate, peripheral isolation grooves are formed on both sides of the peripheral polysilicon gate, and the hard mask layer is removed.
3. The method for manufacturing a NOR flash memory according to claim 1 or 2, characterized in that: After step S4, source / drain regions and logic region sidewalls are formed on both sides of the gate structure of the storage region and both sides of the peripheral polysilicon gate, and then step S5 is performed.
4. The method for manufacturing a NOR flash memory according to claim 3, wherein: After step S4, source and drain regions and logic region sidewalls are first formed on both sides of the gate structure of the storage area and both sides of the peripheral polysilicon gate, and then metal silicide is formed on the upper end of the gate structure of the storage area and the upper end of the peripheral polysilicon gate, and then step S5 is performed.
5. The method for manufacturing a NOR flash memory according to claim 1, wherein: After step S12, metal silicide is formed on the upper end of the storage area gate structure and the upper end of the peripheral polysilicon gate, and then step S13 is carried out.
6. The method for manufacturing a NOR flash memory according to claim 5, wherein In S12, pre-baking and dry etching are carried out to separately remove the oxide and nitride on the polysilicon gate, exposing the polysilicon.
7. The method for manufacturing a NOR flash memory according to claim 1, wherein In step S9, self-aligned source etching is used to expose the semiconductor substrate at the middle part of the source area gate structure and the semiconductor substrate near the peripheral isolation trench of the source area gate structure, forming a source area trench.
8. The method for manufacturing a NOR flash memory according to claim 1, wherein In step S9, surface O2 treatment is first carried out to increase the adhesion of the photoresist, and then etching is carried out.
9. The method for manufacturing a NOR flash memory according to claim 1, wherein In step S9, after the source area trench is formed, ion implantation is carried out on the semiconductor substrate at the source area trench to form a source end connection point.
10. The method for manufacturing a NOR flash memory according to claim 1, wherein In step S6, a trench isolation oxide is deposited by an HDP chemical vapor deposition process; In step S11, the source area gate sidewall is deposited by an ALD process; The thickness of the source gate sidewall is In step S14, a protective oxide layer is formed by plasma enhanced chemical vapor deposition.
11. The method for manufacturing a NOR flash memory according to claim 1, wherein After step S15, Ti / TiN is deposited on the semiconductor substrate surface at the bottom of the drain area contact hole and a thermal process is carried out to form a TiSi structure, and then step S16 is carried out.
12. The method for manufacturing a NOR flash memory according to claim 11, wherein The thickness of Ti / TiN deposited on the semiconductor substrate surface at the bottom of the drain contact hole is The annealing temperature of the subsequent thermal process is 500°C to 600°C.
13. The method for manufacturing a NOR flash memory according to claim 1, wherein 4h1 < h2, where h1 is the thickness of the barrier silicon nitride layer and h2 is the width of the drain area trench; The width of the source area trench is less than 55 nm.
14. The method for manufacturing a NOR flash memory according to claim 1, wherein In step S16, tungsten metal is filled in the contact hole and chemical mechanical polishing is carried out.
15. The method for manufacturing a NOR flash memory according to claim 1, wherein In step S1, a shallow trench isolation is formed on the semiconductor substrate; The inter-gate dielectric layer is composed of a bottom oxide layer, an intermediate nitride layer and a top oxide layer stacked in sequence.