Capacitance-free nonvolatile dynamic memory and preparation method thereof

Abstract

The invention provides a capacitance-free nonvolatile dynamic memory. The capacitance-free nonvolatile dynamic memory comprises a first transistor and a second transistor, the first transistor adopts a vertical channel transistor; the second transistor is a ferroelectric transistor; the second transistor is over the first transistor. According to the 2T0C nonvolatile dynamic memory provided by the invention, one transistor adopts a ferroelectric transistor, and the nonvolatile dynamic random access memory obtained by introducing a ferroelectric material can solve the problems of storage density and energy consumption of a current dynamic random access memory, and can realize high-density and high-energy-efficiency storage; besides, in the preparation process of the vertical channel transistor adopted by the other transistor, the grid electrode surrounding the channel is formed through metal induction, the grid control capacity is higher, wafer-level three-dimensional integration is achieved, and compared with a traditional semiconductor process, the integrated density is high, the cost is low, and the wide application prospect is achieved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a capacitor-free non-volatile dynamic memory and a preparation method thereof. Background Art

[0002] Currently, DRAM (dynamic random access memory) has problems with energy consumption and storage density. Combining DRAM and NVM (non-volatile memory) to form NVDRAM (non-volatile dynamic random access memory) and integrating it into the memory hierarchy can solve the current DRAM storage density and energy consumption problems. Ferroelectric materials can retain their polarization state for a long time after polarization, and have a wide range of applications in the field of non-volatile ferroelectric memory.

[0003] In addition, traditional semiconductor processes are dominated by silicon-based processes, represented by 3D V-cache, which are usually implemented based on advanced bonding technology, with limited integration density and high cost.

[0004] In view of this, the present invention is proposed. Summary of the invention

[0005] The object of the present invention is to provide a capacitor-free non-volatile dynamic memory and a preparation method thereof, which can realize high-density and high-energy-efficiency storage and adopt wafer-level three-dimensional integration with high integration density and low cost.

[0006] A first aspect of the present invention provides a capacitor-free non-volatile dynamic memory, comprising: a first transistor and a second transistor; the first transistor is a vertical channel transistor (VCT transistor); the second transistor is a ferroelectric transistor; and the second transistor is located above the first transistor.

[0007] Preferably, the channel material of the first transistor is crystalline silicon formed by metal induction using amorphous silicon; preferably, the metal is Ni.

[0008] Preferably, the channel material of the second transistor is indium gallium zinc oxide.

[0009] Preferably, the second transistor is a horizontal transistor with a bottom-gate structure.

[0010] Preferably, the first transistor includes: a first source layer, a first drain layer, a first channel layer, a first gate layer and a first gate dielectric layer; one of the first source layer and the first drain layer is located on the upper surface of the first channel layer, and the other is located on the lower surface of the first channel layer, and the first source layer and the first drain layer are not connected to each other; the first gate layer surrounds the first channel layer, and the first gate dielectric layer is located between the first gate layer and the first channel layer.

[0011] Preferably, one of the first source layer and the first drain layer is made of NiSi2, and the other is made of crystalline silicon; the first gate layer is made of TiN; and the first gate dielectric layer is made of HfO2.

[0012] Preferably, the second transistor includes: a second source layer, a second drain layer, a second channel layer, a second gate layer, a ferroelectric material layer and a second gate dielectric layer; the second gate layer is sequentially provided with a ferroelectric material layer, a second gate dielectric layer and a second channel layer; the second source layer and the second drain layer are respectively located on the upper surface of the second channel layer and are not connected to each other; the second source layer or the second drain layer is connected to the first gate layer.

[0013] Preferably, the materials of the second source electrode layer, the second drain electrode layer and the first gate electrode layer are all TiN; and the material of the second gate dielectric layer is HfO2.

[0014] Preferably, the first transistor is a read transistor, and the second transistor is a write transistor.

[0015] A second aspect of the present invention provides a method for preparing a capacitor-free non-volatile dynamic memory, comprising the following steps:

[0016] S1. preparing a first transistor on a peripheral circuit; the first transistor is a vertical channel transistor; the channel of the first transistor is formed by metal induction;

[0017] S2, preparing a second transistor above the first transistor; the second transistor is a ferroelectric transistor with a horizontal structure; the channel of the second transistor is made of indium gallium zinc oxide material;

[0018] S3. Interconnect the first transistor and the second transistor.

[0019] The present invention has at least the following beneficial effects:

[0020] The 2T0C non-volatile memory provided by the present invention adopts a ferroelectric transistor in one transistor. The non-volatile dynamic random access memory obtained by introducing ferroelectric materials can solve the storage density and energy consumption problems of the current dynamic random access memory, and can achieve high-density and high-energy-efficiency storage; in addition, in the preparation process of the vertical channel transistor (VCT transistor) adopted by the other transistor, metal induction is used to form a gate surrounding the channel, and the gate control capability is stronger. The present invention realizes wafer-level three-dimensional integration. Compared with traditional semiconductor processes, the integration density is high and the cost is low, and it has broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 It is a cross-sectional view after the dielectric layer and the amorphous silicon film are grown on the peripheral circuit of the present invention;

[0023] Figure 2 It is a cross-sectional view of the present invention after the amorphous silicon film is etched;

[0024] Figure 3 is a cross-sectional view of the present invention after depositing a metal layer;

[0025] Figure 4 A cross-sectional view after forming a first source layer of the present invention;

[0026] Figure 5 It is a cross-sectional view after the dielectric layer, Si3N4 layer and dielectric layer are deposited in the present invention;

[0027] Figure 6 A cross-sectional view after etching the channel region of the first transistor according to the present invention;

[0028] Figure 7 It is a cross-sectional view after the channel region of the present invention is filled with amorphous silicon;

[0029] Figure 8 It is a cross-sectional view of amorphous silicon after being doped in the deposition of the present invention;

[0030] Fig. 9 A cross-sectional view after forming a first channel layer and a first drain layer of the present invention;

[0031] Fig.10 A cross-sectional view of the present invention after forming a first gate layer and a first gate dielectric layer;

[0032] Fig.11 A cross-sectional view after forming a second gate layer according to the present invention;

[0033] Fig.12 A cross-sectional view after forming a ferroelectric material layer, a second gate dielectric layer and a second channel layer according to the present invention;

[0034] Fig.13 A cross-sectional view after forming a second source electrode layer and a second drain electrode layer according to the present invention;

[0035] Fig.14A cross-sectional view of the capacitor-free nonvolatile dynamic memory prepared by the present invention;

[0036] Fig.15 The equivalent circuit diagram of the capacitor-free nonvolatile dynamic memory prepared by the present invention.

[0037] Explanation of the accompanying drawings: 1. peripheral circuit; 2. dielectric layer; 3. amorphous silicon thin film; 4. metal layer; 5. first source layer; 6. Si3N4 layer; 7. channel region; 8. amorphous silicon; 9. first channel layer; 10. first drain layer; 11. first gate dielectric layer; 12. first gate layer; 13. second gate layer; 14. ferroelectric material layer; 15. second gate dielectric layer; 16. second channel layer; 17. second source layer; 18. second drain layer; 19. conductive channel. DETAILED DESCRIPTION

[0038] It should be noted that the following detailed descriptions are illustrative and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present application belongs.

[0039] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form also includes the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0040] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] Example

[0042] This embodiment provides a capacitor-free non-volatile dynamic memory, including: a first transistor and a second transistor; the first transistor is a vertical channel transistor; the second transistor is a ferroelectric transistor; and the second transistor is located above the first transistor.

[0043] In this embodiment, the channel material of the first transistor is crystalline silicon formed by metal induction using amorphous silicon.

[0044] In this embodiment, the channel material of the second transistor is indium gallium zinc oxide (IGZO).

[0045] In this embodiment, the second transistor is a horizontal transistor with a bottom gate structure.

[0046] In this embodiment, the first transistor includes: a first source layer 5, a first drain layer 10, a first channel layer 9, a first gate layer 12 and a first gate dielectric layer 11; the first source layer 5 is located on the lower surface of the first channel layer 9, the first drain layer 10 is located on the upper surface of the first channel layer 9, and the first source layer 5 and the first drain layer 10 are not connected to each other; the first gate layer 12 surrounds the first channel layer 9, and the first gate dielectric layer 11 is located between the first gate layer 12 and the first channel layer 9.

[0047] In this embodiment, the material of the first source layer 5 is NiSi2, the material of the first drain layer 10 is crystalline silicon; the material of the first gate layer 12 is TiN; and the material of the first gate dielectric layer 11 is HfO2.

[0048] In this embodiment, the second transistor includes: a second source layer 17, a second drain layer 18, a second channel layer 16, a second gate layer 13, a ferroelectric material layer 14 and a second gate dielectric layer 15; the ferroelectric material layer 14, the second gate dielectric layer 15 and the second channel layer 16 are sequentially arranged on the second gate layer 13; the second source layer 17 and the second drain layer 18 are respectively located on the upper surface of the second channel layer 16 and are not connected to each other; the second source layer 17 or the second drain layer 18 is connected to the first gate layer 12.

[0049] In this embodiment, the materials of the second source electrode layer 17 , the second drain electrode layer 18 and the first gate electrode layer 12 are all TiN; and the material of the second gate dielectric layer 15 is HfO 2 .

[0050] In this embodiment, the first transistor is a read transistor, and the second transistor is a write transistor.

[0051] This embodiment also provides a method for preparing a capacitor-free non-volatile dynamic memory, comprising the following steps:

[0052] S1, preparing a first transistor on the peripheral circuit 1; the first transistor is a vertical channel transistor; the channel of the first transistor is formed by metal induction;

[0053] S2, preparing a second transistor above the first transistor; the second transistor is a ferroelectric transistor; the channel of the second transistor is made of indium gallium zinc oxide material;

[0054] S3. Interconnect the first transistor and the second transistor.

[0055] The preparation method of this embodiment is described in more detail below:

[0056] For step S1, Figure 1As shown, a SiO2 dielectric layer 2 and an amorphous silicon thin film 3 are sequentially grown on a CMOS peripheral circuit 1 by epitaxial method.

[0057] like Figure 2 As shown, the amorphous silicon film 3 is etched.

[0058] like Figure 3 As shown, an atomic layer deposition (ALD) process is used to deposit a Ni metal layer 4, the Ni thickness is less than 1 / 2 of the amorphous silicon, and covers the etched amorphous silicon film 3 and the SiO2 dielectric layer 2.

[0059] Preferably, a 2 nm thick SiO2 layer is deposited before depositing the Ni metal layer 4. The SiO2 layer can effectively control the reaction rate of nickel and silicon to prevent the reaction from being too fast, so as to better control the reaction. If the SiO2 layer is too thick, it is not conducive to the reaction. If the SiO2 layer is too thin, the effect of controlling the reaction rate is reduced. Therefore, a 2 nm thick SiO2 layer is the best condition for controlling the reaction rate of nickel and silicon.

[0060] like Figure 4 As shown, NiSi2 is formed by rapid thermal annealing at 450-575°C for 5-10 min as the first source layer 5, and unreacted Ni is removed (if a SiO2 layer is deposited, the SiO2 layer is removed together).

[0061] like Figure 5 As shown, a SiO2 dielectric layer, a Si3N4 layer 6 and a SiO2 dielectric layer are deposited in sequence.

[0062] like Figure 6 As shown, a through hole is etched for the bottom first transistor (read transistor) to serve as a channel region 7 .

[0063] like Figure 7 As shown, doped amorphous silicon 8 is deposited and then CMP is performed to remove the surface portion, and the channel region 7 is fully filled (doping concentration 1E18-1E19 / cm 3 ).

[0064] like Figure 8 As shown, the concentration of doped amorphous silicon 8 in the deposition is greater than 1E20 / cm 3 .

[0065] like Fig. 9 As shown, after annealing at 550℃ for 24 hours, amorphous silicon 8 will be crystallized into crystalline silicon (c-Si) with NiSi2 crystal phase as the mother plate under metal induction. Since NiSi2 has a face-centered cubic structure (FCC), which is very close to the lattice structure of single crystal silicon, and the lattice mismatch is only 0.4%, it can be considered that amorphous silicon 8 is crystallized into c-Si, forming the first channel layer 9 and the first drain layer 10.

[0066] like Fig.10As shown, phosphoric acid cleaning is used to remove the Si 3 N 4 layer 6 , and then TiN is deposited by the ALD method to form the first gate layer 12 and the first gate dielectric layer 11 .

[0067] For step S2, Fig.11 As shown, after depositing the SiO2 dielectric layer, it is flattened, TiN is deposited, and the second gate layer 13 (bottom gate structure) is photoetched. Since the critical temperature of indium gallium zinc oxide (IGZO) is about 500°C, when the IGZO material is affected by a high temperature environment, its performance and stability may be affected. Therefore, the bottom gate structure can better maintain the stability of the transistor.

[0068] like Fig.12 As shown, a ferroelectric material layer 14 and a second gate dielectric layer 15 (HfO 2 ) are deposited, and then an IGZO film is deposited as a second channel layer 16 .

[0069] like Fig.13 As shown, TiN metal is deposited and etched to form a second source layer 17 and a second drain layer 18 .

[0070] For step S3, Fig.14 As shown, an interlayer dielectric layer is deposited on the top, and a dielectric CMP is performed, and then contact hole lithography and etching are performed, and hole silicide is deposited to form contact holes that are respectively in contact with the source layer, the drain layer and the gate layer, and a conductive channel 19 is formed in the contact hole to form an interconnection between the first transistor and the second transistor, thereby obtaining the capacitor-free non-volatile dynamic memory, namely, 2T0C NVDRAM. The equivalent circuit diagram is shown in Fig.15 shown.

[0071] In summary, the 2T0C NVDRAM provided in this embodiment is composed of two transistors, namely a write transistor and a read transistor, wherein the write transistor adopts a ferroelectric transistor FeFet, the write transistor is a horizontal transistor with a bottom gate structure, and the read transistor is a vertical structure transistor located below the write transistor. The channel of the read transistor is formed by metal induction, and the channel material is IGZO oxide.

[0072] In the 2T0C NVDRAM provided by the present invention, one transistor adopts a ferroelectric transistor. The non-volatile dynamic random access memory obtained by introducing ferroelectric materials can solve the storage density and energy consumption problems of the current dynamic random access memory, and can achieve high-density and high-energy-efficiency storage; in addition, in the preparation process of the vertical channel transistor (VCT transistor) adopted by the other transistor, metal induction is used to form a gate surrounding the channel, the gate control capability is stronger, and wafer-level three-dimensional integration is achieved. Compared with traditional semiconductor processes, the integration density is high and the cost is low, and it has broad application prospects.

[0073] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A capacitor-free nonvolatile dynamic memory, characterized in that: include: A first transistor and a second transistor; the first transistor is a vertical channel transistor; The second transistor is a ferroelectric transistor; The second transistor is located above the first transistor.

2. The capacitor-free nonvolatile dynamic memory according to claim 1, characterized in that: The channel material of the first transistor is crystalline silicon formed by metal induction using amorphous silicon.

3. The capacitor-free nonvolatile dynamic memory according to claim 1, characterized in that: The channel material of the second transistor is indium gallium zinc oxide.

4. The capacitor-free nonvolatile dynamic memory according to claim 1, characterized in that: The second transistor is a horizontal transistor with a bottom gate structure.

5. The capacitor-free nonvolatile dynamic memory according to claim 1, characterized in that: The first transistor includes: a first source layer, a first drain layer, a first channel layer, a first gate layer and a first gate dielectric layer; one of the first source layer and the first drain layer is located on the upper surface of the first channel layer, and the other is located on the lower surface of the first channel layer, and the first source layer and the first drain layer are not connected to each other; the first gate layer surrounds the first channel layer, and the first gate dielectric layer is located between the first gate layer and the first channel layer.

6. The capacitor-free nonvolatile dynamic memory according to claim 5, characterized in that: One of the first source layer and the first drain layer is made of NiSi2, and the other is made of crystalline silicon; the first gate layer is made of TiN; and the first gate dielectric layer is made of HfO2.

7. The capacitor-free nonvolatile dynamic memory according to claim 5, characterized in that: The second transistor includes: a second source layer, a second drain layer, a second channel layer, a second gate layer, a ferroelectric material layer and a second gate dielectric layer; the second gate layer is sequentially provided with a ferroelectric material layer, a second gate dielectric layer and a second channel layer; the second source layer and the second drain layer are respectively located on the upper surface of the second channel layer and are not connected to each other; the second source layer or the second drain layer is connected to the first gate layer.

8. The capacitor-free non-volatile dynamic memory according to claim 7, characterized in that: The materials of the second source electrode layer, the second drain electrode layer and the first gate electrode layer are all TiN; the material of the second gate dielectric layer is HfO2.

9. The capacitor-free nonvolatile dynamic memory according to claim 1, characterized in that: The first transistor is a read transistor, and the second transistor is a write transistor.

10. A method for preparing a capacitor-free non-volatile dynamic memory, characterized in that: The steps include: S1. preparing a first transistor on a peripheral circuit; the first transistor is a vertical channel transistor; the channel of the first transistor is formed by metal induction; S2, preparing a second transistor above the first transistor; the second transistor is a ferroelectric transistor with a horizontal structure; the channel of the second transistor is made of indium gallium zinc oxide material; S3. Interconnect the first transistor and the second transistor.

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