Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device, a manufacturing method thereof and electronic equipment, and relates to a semiconductor technology. The manufacturing method of the semiconductor device comprises the following steps: sequentially forming a stacking structure of a first electrode, an insulating layer and a second electrode on a substrate; forming a hole extending in the direction perpendicular to the substrate on the stacked structure, wherein the hole exposes at least part of the first electrode and the second electrode; an atomic layer deposition process is adopted, a semiconductor layer is grown on the inner wall of the hole through an oxidizing agent, and the semiconductor layer is a metal oxide semiconductor layer; the semiconductor layer is respectively contacted with the exposed first electrode and the second electrode; growing a semiconductor layer on the inner wall of the hole through an oxidizing agent by adopting an atomic layer deposition process, comprising the following steps: introducing the oxidizing agent and a precursor into the cavity, the oxidizing agent being gas or plasma; wherein the oxidability of the gas or the plasma is enhanced in the process of increasing the thickness of the semiconductor layer; and oxidation of the first electrode and the second electrode in the oxidation process of the semiconductor layer is reduced.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to but are not limited to semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] Transistors with metal oxides as channel materials are becoming increasingly important in emerging fields, such as flexible displays, the Internet of Things, wearable electronics, and memory. However, during the growth of the channel layer of a transistor, metal oxides usually cause oxidation problems to the interface layer to varying degrees. This problem still exists between the interface of the metal source and drain electrodes of vertical channel devices and the metal oxide channel material. Especially for metal oxide semiconductor channel materials, excessive oxidation of the interface will limit the performance improvement of the device. Summary of the invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0004] The present disclosure provides a method for manufacturing a semiconductor device, comprising:

[0005] forming a stacking structure of a first electrode, an insulating layer and a second electrode in sequence on a substrate;

[0006] forming a hole extending in a direction perpendicular to the substrate on the stacked structure, wherein the hole exposes at least a portion of the first electrode and the second electrode;

[0007] Using an atomic layer deposition process, a semiconductor layer is grown on the inner wall of the hole by an oxidant, wherein the semiconductor layer is a metal oxide semiconductor layer; the semiconductor layer is in contact with the exposed first electrode and the second electrode respectively;

[0008] The method adopts an atomic layer deposition process to grow a semiconductor layer on the inner wall of the hole through an oxidant, comprising: introducing an oxidant and a precursor into a cavity, wherein the oxidant is a gas or plasma;

[0009] The oxidizing property of the gas or plasma is enhanced as the thickness of the semiconductor layer increases.

[0010] In an exemplary embodiment, using an atomic layer deposition process to grow a semiconductor layer on the inner wall of the hole by an oxidant includes:

[0011] The atomic layer deposition process is adopted to grow the semiconductor layer on the side wall of the hole firstly through weak oxidizing gas or plasma and then through strong oxidizing gas or plasma.

[0012] In an exemplary embodiment, the substance of the weak oxidizing gas or plasma is a weak oxidant; and the strong oxidizing gas or plasma is a strong oxidant.

[0013] In an exemplary embodiment, the weak oxidant includes water, hydrogen peroxide, or alcohols; and the strong oxidant includes ozone or fluorine gas.

[0014] In an exemplary embodiment, the weak oxidizing gas or plasma is ozone with a concentration range of 2% to 10%, or an active oxygen plasma with a power between 10W and 30W; the strong oxidizing gas or plasma is ozone with a concentration range of 10% to 20%, or an active oxygen plasma with a power between 30W and 60W.

[0015] In an exemplary embodiment, a semiconductor layer having a thickness greater than or equal to 0.5 nanometers and less than or equal to 2 nanometers is first grown by using a weakly oxidizing gas or plasma.

[0016] In an exemplary embodiment, after the semiconductor layer is grown by the weak oxidizing gas or plasma and before the semiconductor layer is grown by the strong oxidizing gas or plasma, the method further comprises:

[0017] The grown semiconductor layer is annealed in an oxygen atmosphere.

[0018] In an exemplary embodiment, a gas or plasma of the same substance is used as a weak oxidizing gas and a strong oxidizing gas to continuously manufacture a semiconductor layer, and an annealing process is performed after the semiconductor layer is obtained.

[0019] In an exemplary embodiment, as the thickness of the semiconductor layer increases, the oxygen concentration in the semiconductor layer gradually increases.

[0020] The disclosed embodiment also provides a semiconductor device, which is manufactured using any of the above-mentioned methods for manufacturing a semiconductor device.

[0021] In an exemplary embodiment, the material of the semiconductor layer includes at least one of indium gallium zinc oxide, indium gallium oxide, indium zinc oxide, indium tin oxide, indium tungsten oxide, and indium oxide.

[0022] An embodiment of the present disclosure also provides an electronic device, comprising the aforementioned semiconductor device.

[0023] The manufacturing process of the semiconductor device disclosed in the present invention increases the oxidizing property of the gas or plasma as the thickness of the semiconductor layer increases, thereby reducing oxidation of the first electrode and the second electrode during oxidation of the semiconductor layer, thereby increasing the contact resistance between the first electrode and the second electrode.

[0024] The manufacturing process of the semiconductor device disclosed in the present invention first uses a weak oxidizing gas or plasma, and then uses a strong oxidizing gas or plasma to grow the semiconductor layer on the side wall of the hole, thereby reducing the oxidation of the exposed first electrode and the second electrode during the growth of the semiconductor layer; the semiconductor layer formed by oxidation of the weak oxidizing gas or plasma is used as a barrier layer to reduce the oxidation of the first electrode and the second electrode by the strong oxidizing gas or plasma, thereby increasing the contact resistance of the first electrode and the second electrode.

[0025] The manufacturing process of the semiconductor device disclosed in the present invention forms a semiconductor layer by using a strong oxidizing gas or plasma, thereby improving the quality of the semiconductor layer.

[0026] The manufacturing process of the semiconductor device disclosed in the present invention gradually enhances the oxidizing property of gas or plasma, thereby reducing the oxidation of the exposed first electrode and the second electrode during the oxidation process of the semiconductor layer, thereby improving the contact resistance between the first electrode and the second electrode.

[0027] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The objects and advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description and the drawings.

[0028] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution.

[0030] Figure 1 A schematic cross-sectional view of a semiconductor device provided as an exemplary embodiment;

[0031] Figure 2 A schematic diagram of a manufacturing process of a semiconductor device according to an exemplary embodiment after a first electrode is formed;

[0032] Figure 3 A schematic diagram of a manufacturing process of a semiconductor device according to an exemplary embodiment after forming a second electrode;

[0033] Figure 4 A schematic diagram of a semiconductor device manufacturing process after forming a hole according to an exemplary embodiment;

[0034] Figure 5 A schematic diagram of a manufacturing process of a semiconductor device according to an exemplary embodiment after a semiconductor layer, a gate dielectric film and a gate electrode film are formed;

[0035] Figure 6a A partial schematic diagram of a manufacturing process of a semiconductor device according to an exemplary embodiment after a first growth film is formed;

[0036] Figure 6b A partial schematic diagram of a manufacturing process of a semiconductor device according to an exemplary embodiment after a second growth film is formed;

[0037] Figure 7 A schematic cross-sectional view of a semiconductor device is provided according to yet another exemplary embodiment. DETAILED DESCRIPTION

[0038] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other arbitrarily.

[0039] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the common meanings understood by one of ordinary skill in the art to which the present invention belongs.

[0040] The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values ​​shown in the drawings.

[0041] The ordinal numbers such as “first”, “second” and “third” in the present disclosure are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0042] In the present disclosure, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the present specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the disclosure and can be appropriately replaced according to the circumstances.

[0043] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0044] In the present disclosure, a transistor refers to an element including at least three terminals: a gate, a drain electrode, and a source electrode. The transistor has a first channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the first channel region, and the source electrode. In the present disclosure, the first channel region refers to a region where current mainly flows.

[0045] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" may be interchanged.

[0046] In the present disclosure, "electrical connection" includes the situation where components are connected together through an element having some kind of electrical function. There is no particular limitation on the "element having some kind of electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some kind of electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0047] In the present disclosure, "parallel" means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°.

[0048] In the present disclosure, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film" in some cases. Similarly, "insulating film" may be replaced with "insulating layer" in some cases.

[0049] The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process. "The orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0050] In the embodiments of the present disclosure, "A and B are an integrated structure" may mean that there is no obvious boundary interface such as a fault or gap in the microstructure. Generally, a film layer patterned to form a connection is an integrated structure. For example, A and B use the same material to form a film layer and form a structure with a connection relationship at the same time through the same patterning process.

[0051] In a vertical channel oxide transistor, especially in a structure where the source electrode and the drain electrode surround the annular channel, it is necessary to first form the source electrode and the drain electrode, and then form a metal oxide semiconductor layer in contact with the source electrode and the drain electrode. In some embodiments, after forming the metal oxide semiconductor, it is possible to continue to form a gate insulating layer and / or a gate in an oxygen atmosphere. In particular, when using chemical vapor deposition to form a semiconductor layer, a gate insulating layer, a gate, etc., it is necessary to deposit a film layer in an oxygen atmosphere, for example, an atomic layer deposition method is used to prepare a semiconductor, an insulating layer, or a conductive film layer containing O.

[0052] In the process of growing metal oxide channel materials through atomic layer deposition, strong oxidants are required to grow metal oxide films. Excessive or overly concentrated oxidants will oxidize the surfaces of the source and drain electrodes of the transistor, significantly increasing the contact resistance of the source and drain electrodes, resulting in a decrease in the on-state current of the transistor, limiting the improvement of memory performance.

[0053] The embodiments of the present disclosure provide a semiconductor device, a manufacturing method, and an electronic device. The semiconductor device manufactured by the method can effectively improve the device performance.

[0054] The method for manufacturing a semiconductor device according to an embodiment of the present disclosure includes:

[0055] forming a stacking structure of a first electrode, an insulating layer and a second electrode in sequence on a substrate;

[0056] forming a hole extending in a direction perpendicular to the substrate on the stacked structure, wherein the hole exposes at least a portion of the first electrode and the second electrode;

[0057] Using an atomic layer deposition process, a semiconductor layer is grown on the inner wall of the hole by an oxidant, wherein the semiconductor layer is a metal oxide semiconductor layer; the semiconductor layer is in contact with the exposed first electrode and the second electrode respectively;

[0058] The method adopts an atomic layer deposition process to grow a semiconductor layer on the inner wall of the hole through an oxidant, comprising: introducing an oxidant and a precursor into a cavity, wherein the oxidant is a gas or plasma;

[0059] The oxidizing property of the gas or plasma is enhanced as the thickness of the semiconductor layer increases.

[0060] The semiconductor device disclosed in the present invention is described below by way of some exemplary embodiments.

[0061] Figure 1 FIG. 1 is a cross-sectional schematic diagram of a semiconductor device provided by an exemplary embodiment. In an exemplary embodiment, as Figure 1As shown, the semiconductor device includes: a substrate (not shown in the figure), a first insulating dielectric layer 11 arranged on the substrate, a first electrode 21 arranged on the side of the first insulating dielectric layer 11 away from the substrate, a second insulating dielectric layer 12 arranged on the side of the first electrode 21 away from the substrate, a second electrode 22 arranged on the side of the second insulating dielectric layer 12 away from the substrate, and a third insulating dielectric layer 13 arranged on the side of the second electrode 22 away from the substrate. The first electrode 21 and the second electrode 22 are conductive film layers, such as metal layers, extending in a direction parallel to the substrate, and the orthographic projections of the first electrode 21 and the second electrode 22 on the substrate overlap. Among them, the first electrode 21 and the second electrode 22 are patterned conductive film layers.

[0062] In an exemplary embodiment, the semiconductor device further includes: a hole 31, a semiconductor layer 14, a gate dielectric layer 15, and a gate electrode 16. The hole 31 extends in a direction perpendicular to the substrate, and the hole 31 extends from the surface of the third insulating dielectric layer 13 away from the substrate, sequentially penetrates the third insulating dielectric layer 13, the second electrode 22, and the second insulating dielectric layer 12, and extends to the surface of the first electrode 21, exposing the surface of the corresponding hole on the first electrode 21, the bottom wall of the hole 31 is the exposed surface of the first electrode 21, and the side wall of the hole 31 exposes the side of the corresponding hole on the second electrode 22.

[0063] In some embodiments, the hole extends into the first electrode, forming a groove on the first electrode, exposing the sidewalls and bottom wall of the groove; or, the hole penetrates the first electrode from the upper surface of the first electrode, exposing the sidewalls of the first electrode.

[0064] In some embodiments, the semiconductor device may not be provided with a third insulating dielectric layer on the side of the second electrode away from the substrate, which will not be elaborated in the present disclosure.

[0065] In an exemplary embodiment, the semiconductor layer 14 is a film structure. The semiconductor layer 14 can be prepared by an atomic layer deposition process. At least part of the semiconductor layer 14 covers the sidewalls and bottom wall of the hole 31, and the semiconductor layer 14 contacts the exposed surface of the first electrode 21 and the side of the second electrode 22 respectively.

[0066] In an exemplary embodiment, the semiconductor layer 14 is distributed at least on the bottom wall and the side wall of the hole 31. For example, the semiconductor layer 14 covers the bottom wall and the side wall of the hole 31 and extends to the surface located around the opening of the hole 31, that is, the surface of the third insulating dielectric layer 13 located around the opening of the hole 31.

[0067] In an exemplary embodiment, the gate dielectric layer 15 is a film layer structure. The gate dielectric layer 15 can be prepared by an atomic layer deposition process. The gate dielectric layer 15 is disposed on a side of the semiconductor layer 14 away from the inner wall of the hole 31 .

[0068] In an exemplary embodiment, the gate electrode 16 is disposed on a side of the gate dielectric layer 15 away from the semiconductor layer 14 and fills the hole 31. The gate dielectric layer 15 is located between the gate electrode 16 and the semiconductor layer 14, and the gate electrode 16 is connected to the semiconductor layer 14 through the gate dielectric layer 15.

[0069] In an exemplary embodiment, the semiconductor layer 14, the gate dielectric layer 15 and the gate electrode 16 all cover the bottom wall of the hole 31, and extend from the bottom wall of the hole 31 in a direction perpendicular to the substrate, covering the side walls of the hole 31, and extending to the surface located around the opening of the hole 31, thereby facilitating the preparation of the semiconductor layer, the gate dielectric layer and the gate electrode.

[0070] In an exemplary embodiment, in the thickness direction of the semiconductor layer 14 , the oxygen concentration on the side of the semiconductor layer 14 close to the exposed first electrode 21 and the second electrode 22 is lower than the oxygen concentration on the side of the semiconductor layer 14 away from the first electrode 21 and the second electrode 22 .

[0071] In an exemplary embodiment, in the thickness direction of the semiconductor layer 14 , the side of the semiconductor layer 14 close to the exposed first electrode 21 and the second electrode 22 isolates the side of the semiconductor layer 14 away from the exposed first electrode 21 and the second electrode 22 from the exposed first electrode 21 and the second electrode 22 .

[0072] The semiconductor device disclosed in the present invention reduces oxidation of the exposed first electrode and second electrode during oxidation of the semiconductor layer by making the oxygen concentration on the side of the semiconductor layer 14 close to the exposed first electrode 21 and second electrode 22 lower than the oxygen concentration on the side of the semiconductor layer 14 far from the first electrode 21 and second electrode 22, thereby increasing the contact resistance between the first electrode and the second electrode.

[0073] In an exemplary embodiment, in the thickness direction of the semiconductor layer 14 , the carrier concentration on the side of the semiconductor layer 14 close to the exposed first electrode 21 and the second electrode 22 is greater than the carrier concentration on the side of the semiconductor layer far from the exposed first electrode 21 and the second electrode 22 .

[0074] In an exemplary embodiment, the hole 31 penetrates the second insulating dielectric layer 12, the hole 31 exposes the side wall of the second insulating dielectric layer 12, the semiconductor layer 14 is in contact with the exposed second insulating dielectric layer 12, and in the thickness direction of the semiconductor layer 14, the oxygen concentration on the side of the semiconductor layer 14 close to the exposed second insulating dielectric layer 12 is less than the oxygen concentration on the side of the semiconductor layer 14 far from the exposed second insulating dielectric layer 12.

[0075] In the semiconductor device disclosed herein, the oxygen concentration on the semiconductor layer is lowered by making the oxygen concentration on the side of the semiconductor layer close to the second insulating dielectric layer lower than the oxygen concentration on the side of the semiconductor layer far from the second insulating dielectric layer.

[0076] In an exemplary embodiment, the material of the semiconductor layer includes at least one of indium gallium zinc oxide, indium gallium oxide, indium zinc oxide, indium tin oxide, indium tungsten oxide, and indium oxide.

[0077] In an exemplary embodiment, the material of the gate dielectric layer includes at least one of silicon oxide, aluminum oxide, hafnium oxide, hafnium aluminum oxide, and hafnium lanthanum oxide.

[0078] In an exemplary embodiment, the material of the gate electrode includes at least one of indium zinc oxide, indium tin oxide, titanium nitride, tungsten, molybdenum and nickel.

[0079] Figure 7 A cross-sectional schematic diagram of a semiconductor device provided for another exemplary embodiment. In an exemplary embodiment, as Figure 7 As shown, the semiconductor device further includes: a first lead 51, a second lead 52 and a third lead 53, the first lead 51, the second lead 52 and the third lead 53 all extend in a direction parallel to the substrate, and the first lead 51, the second lead 52 and the third lead 53 are all located on the side of the gate electrode 16 away from the substrate. The first lead 51 is connected to the first electrode 21 through a first via hole, and the first lead 51 is used to connect the first electrode 21 to an external circuit; the second lead 52 is connected to the gate electrode 16 through a second via hole, and the second lead 52 is used to connect the gate electrode 16 to an external circuit; the third lead 53 is connected to the second electrode 22 through a third via hole, and the third lead 53 is used to connect the second electrode 22 to an external circuit.

[0080] The technical solution of this embodiment is further explained below through the manufacturing process of the semiconductor device of this embodiment. The "patterning process" mentioned in this embodiment includes deposition of film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which are mature manufacturing processes in related technologies. The "photolithography process" mentioned in this embodiment includes coating of film layer, mask exposure and development, which are mature manufacturing processes in related technologies. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here. In the description of this embodiment, it should be understood that "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or a photolithography process during the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" still requires a patterning process or a photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern".

[0081] In an exemplary embodiment, a process for manufacturing a semiconductor device may include:

[0082] Step 101: forming a first electrode.

[0083] The first electrode is formed by providing a substrate; then forming a first insulating dielectric layer 11 on the substrate; then depositing a first conductive film on a side of the first insulating dielectric layer 11 away from the substrate, and forming the first conductive film into a first electrode 21 through a patterned etching process. Figure 2 As shown, the first electrode can be used as a source electrode or a drain electrode of the semiconductor device.

[0084] In an exemplary embodiment, in a direction parallel to the substrate, the first electrode 21 may be in a strip shape or a block shape.

[0085] In an exemplary embodiment, the substrate may be a semiconductor substrate, such as a silicon substrate, or a supporting base including an insulating layer or a functional layer. Figure 1 The first insulating dielectric layer 11 in the structure can be understood as a substrate.

[0086] In an exemplary embodiment, the first insulating dielectric layer 11 may be a low-K dielectric layer, that is, a dielectric layer with a dielectric constant K≤3.9, including but not limited to silicon oxide, such as silicon dioxide (SiO 2 )wait.

[0087] In some embodiments, the first insulating layer is optional, and the first electrode 21 can be directly formed on a substrate, such as a silicon substrate.

[0088] In an exemplary embodiment, the first electrode 21 may be made of a conductive material such as a metal, an alloy or a metal compound. For example, the first electrode 21 may be made of at least one of titanium nitride (TiN), tungsten (W), molybdenum (Mo), nickel (Ni), titanium aluminum alloy (TiAl), and indium tin oxide (ITO).

[0089] In an exemplary embodiment, the first insulating dielectric layer 11 and the first conductive film may be formed by atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, or the like.

[0090] Step 102: forming a second electrode.

[0091] The second electrode is formed by: forming a second insulating dielectric layer 12 on the side of the first electrode 21 away from the substrate on the basis of the substrate having the aforementioned pattern; then, depositing a second conductive film on the side of the second insulating dielectric layer 12 away from the substrate, and forming the second conductive film into a second electrode 22 through a patterned etching process, wherein the orthographic projections of the second electrode 22 and the first electrode 21 on the substrate overlap; then, optionally, forming a third insulating dielectric layer 13 on the side of the second electrode 22 away from the substrate; Figure 3 As shown. The second electrode 22 can be used as a source electrode or a drain electrode of the semiconductor device. The first electrode 21, the second insulating dielectric layer 12, the second electrode 22 and the third insulating dielectric layer 13 form a stacked structure.

[0092] In an exemplary embodiment, the second insulating dielectric layer 12 and the third insulating dielectric layer 13 play the role of isolating the conductive layer. At the same time, the second insulating layer contacts the semiconductor layer and needs to have a large H-blocking and O-blocking isolation effect. For example, both can be low-K dielectric layers, that is, dielectric layers with a dielectric constant K≤3.9, including but not limited to silicon oxides, such as silicon dioxide (SiO 2 ) or silicon dioxide doped materials, etc.

[0093] In an exemplary embodiment, the materials of the first insulating dielectric layer 11 , the second insulating dielectric layer 12 , and the third insulating dielectric layer 13 are the same or different.

[0094] In an exemplary embodiment, the second electrode 22 may be made of a conductive material such as a metal, an alloy or a metal compound. For example, the second electrode 22 may be made of at least one of titanium nitride (TiN), tungsten (W), molybdenum (Mo), nickel (Ni), titanium aluminum alloy (TiAl), and indium tin oxide (ITO).

[0095] In an exemplary embodiment, the second electrode 22 may be made of the same material as or different from the first electrode 21 .

[0096] In an exemplary embodiment, the second insulating dielectric layer 12 and the second conductive film may be formed by a single atom deposition process, a chemical vapor deposition process or a sputtering method.

[0097] Step 103: forming holes.

[0098] The hole formation includes: on the basis of the substrate formed with the aforementioned pattern, a patterned etching process is used to form a hole 31 extending in a direction perpendicular to the substrate on the above stacked structure, the hole 31 is formed from the surface of the third insulating dielectric layer 13 away from the substrate, sequentially penetrates the third insulating dielectric layer 13, the upper surface and the lower surface of the second electrode 22 and the second insulating dielectric layer 12, and extends to the upper surface of the first electrode 21, exposing the upper surface of the first electrode 21, the bottom wall of the hole 31 is the exposed upper surface of the first electrode 21, and the side wall of the hole 31 exposes the side wall of the second electrode 22 corresponding to the hole, such as Figure 4 The upper surface of the first electrode 21 is the surface of the first electrode 21 close to the second electrode 22 .

[0099] In another exemplary embodiment, the hole extends into the first electrode, extends into the first electrode, forms a groove on the first electrode, and the hole exposes the sidewall and bottom wall of the groove.

[0100] In another exemplary embodiment, the hole penetrates through the first electrode from the upper surface of the first electrode, exposing the sidewall of the first electrode corresponding to the hole.

[0101] Step 103, forming a semiconductor layer, a gate dielectric film and a gate electrode film.

[0102] The forming of the semiconductor layer, the gate dielectric film and the gate electrode film comprises: on the basis of the substrate formed with the aforementioned pattern, using an atomic layer deposition process, growing a semiconductor layer on the inner wall of the hole by an oxidant, wherein the semiconductor layer is a metal oxide semiconductor layer; the semiconductor layer is respectively in contact with the exposed first electrode and the second electrode;

[0103] The semiconductor layer is grown on the inner wall of the hole by an atomic layer deposition process using an oxidant, including: introducing an oxidant and a precursor into a cavity, and sequentially growing multiple metal oxide atomic layers on the inner wall surface of the hole 31, wherein the multiple metal oxide atomic layers serve as the semiconductor layer 14. The oxidant is a gas or plasma, and the oxidizing property of the gas or plasma increases as the thickness of the semiconductor layer increases.

[0104] It should be noted that the oxidizing property of the gas or plasma is the oxidizing power, which is related to the material type of the gas or plasma and the concentration of the gas or plasma. For the same gas or plasma, the gas concentration or plasma power can change the oxidizing power.

[0105] In an exemplary embodiment, the semiconductor layer 14 covers at least the sidewalls and the bottom wall of the hole 31 , and contacts the exposed surface of the first electrode 21 and the side surface of the second electrode 22 .

[0106] In an exemplary embodiment, the semiconductor layer may be formed by a single continuous deposition process or by two processes. A single continuous deposition process may be understood as using the same substance of gas or plasma to control the gas concentration or plasma power to successively form semiconductors with different film qualities, and then perform an annealing process. Two processes may be understood as successively forming semiconductors with different film qualities in two time periods, the materials of the gas or plasma in the two time periods may be the same or different, and an annealing process may be performed between the two time periods.

[0107] Subsequently, an atomic layer deposition process is used to sequentially deposit a gate dielectric film 42 and a gate electrode film 43 on the semiconductor layer 14, and the gate electrode film 43 fills the hole 31. Figure 5 shown.

[0108] In an exemplary embodiment, using an atomic layer deposition process to grow a semiconductor layer on the inner wall of the hole by an oxidant includes:

[0109] First, an atomic layer deposition process is used to grow a first growth film 411 at least on the sidewall and bottom wall of the hole 31 through a weak oxidizing gas or plasma. The first growth film 411 is in contact with the exposed first electrode 21 and the second electrode 22. Figure 6a As shown;

[0110] Subsequently, the first growth film 411 is annealed in an oxygen atmosphere to densify the first growth film 411, remove residual impurities in the first growth film 411, improve the quality of the first growth film 411, and fill oxygen vacancies in the growth process of the first growth film 411, so that the annealed first growth film 411 has the same or similar oxygen concentration as the metal oxide film grown by a strong oxidizing gas or plasma, thereby obtaining the same or similar turn-on voltage, and at the same time reducing the degree of oxidation of the first electrode 21 and the second electrode 22, thereby avoiding the formation of a high contact resistance after severe oxidation of the source and drain electrodes, and ensuring a higher on-state current.

[0111] Subsequently, a second growth film 412 is grown on the surface of the first growth film 411 by a strong oxidizing gas or plasma, and the second growth film 412 is connected to the exposed first electrode 21 and the second electrode 22 through the first growth film 411, and the first growth film 411 and the second growth film 412 form the semiconductor layer 14. Figure 6b As shown;

[0112] Subsequently, the second growth film 412 is annealed in an oxygen atmosphere to densify the second growth film 412 , remove residual impurities in the second growth film 412 , improve the quality of the second growth film 412 , and fill oxygen vacancies in the growth process of the second growth film 412 .

[0113] In an exemplary embodiment, the substance of the weak oxidizing gas or plasma is a weak oxidant; and the strong oxidizing gas or plasma is a strong oxidant.

[0114] In an exemplary embodiment, the weak oxidant includes water, hydrogen peroxide, or alcohols; and the strong oxidant includes ozone or fluorine gas.

[0115] In an exemplary embodiment, the weak oxidizing gas or plasma is ozone with a concentration range of 2% to 10%, or an active oxygen plasma with a power between 10W and 30W; for example, the weak oxidizing gas or plasma is ozone with a concentration range of greater than or equal to 5% and less than or equal to 8%, or an active oxygen plasma with a power of greater than or equal to 20W and less than or equal to 25W.

[0116] In an exemplary embodiment, the strong oxidizing gas or plasma is ozone with a concentration range of 10% to 20%, or an active oxygen plasma with a power between 30W and 60W; for example, the strong oxidizing gas or plasma is ozone with a concentration range of greater than 14% and less than or equal to 18%, or an active oxygen plasma with a power of greater than 40W and less than or equal to 50W.

[0117] The manufacturing process of the semiconductor device disclosed in the present invention increases the oxidizing property of the gas or plasma as the thickness of the semiconductor layer increases, thereby reducing oxidation of the first electrode and the second electrode during oxidation of the semiconductor layer, thereby increasing the contact resistance between the first electrode and the second electrode.

[0118] The manufacturing process of the semiconductor device disclosed in the present invention first uses a weak oxidizing gas or plasma and then uses a strong oxidizing gas or plasma to grow the semiconductor layer on the side wall of the hole, thereby reducing the oxidation of the exposed first electrode and the second electrode during the growth of the semiconductor layer; the semiconductor layer formed by oxidation of the weak oxidizing gas or plasma is used as a barrier layer to reduce the oxidation of the first electrode and the second electrode by the strong oxidizing gas or plasma, thereby increasing the contact resistance of the first electrode and the second electrode.

[0119] The manufacturing process of the semiconductor device disclosed in the present invention forms a semiconductor layer by using a strong oxidizing gas or plasma, thereby improving the quality of the semiconductor layer.

[0120] The manufacturing process of the semiconductor device disclosed in the present invention gradually enhances the oxidizing property of gas or plasma, thereby reducing the oxidation of the exposed first electrode and the second electrode during the oxidation process of the semiconductor layer, thereby improving the contact resistance between the first electrode and the second electrode.

[0121] In an exemplary embodiment, the materials of the first growth film 411 and the second growth film 412 may both be metal oxides. The semiconductor layer 14 formed by the first growth film 411 and the second growth film 412 is an integrated structure.

[0122] In an exemplary embodiment, the oxygen content of the first growth film 411 is substantially the same as the oxygen content of the second growth film 412 .

[0123] In an exemplary embodiment, the thickness of the first growth film 411 may be greater than or equal to 0.5 nanometers and less than or equal to 2 nanometers. For example, the thickness of the first growth film 411 may be greater than or equal to 1 nanometer and less than or equal to 1.5 nanometers.

[0124] In an exemplary embodiment, a semiconductor layer having a thickness greater than or equal to 0.5 nanometers and less than or equal to 2 nanometers is first grown by using a weakly oxidizing gas or plasma.

[0125] In some embodiments, the same gas or plasma may be used as a weak oxidizing gas and a strong oxidizing gas to continuously manufacture semiconductor layers, and an annealing process may be performed after the semiconductor layers are obtained.

[0126] In another exemplary embodiment, using an atomic layer deposition process to grow a semiconductor layer on the inner wall of the hole by an oxidant includes:

[0127] Using an atomic layer deposition process, a semiconductor layer is grown on the inner wall of the hole by an oxidant, wherein the semiconductor layer is a metal oxide semiconductor layer; the semiconductor layer is in contact with the exposed first electrode and the second electrode respectively;

[0128] The semiconductor layer is grown on the inner wall of the hole by an atomic layer deposition process using an oxidant, including: firstly introducing an oxidant and a precursor into the cavity, and sequentially growing multiple metal oxide atomic layers on the inner wall surface of the hole 31, wherein the multiple metal oxide atomic layers serve as the semiconductor layer 14; then, the grown semiconductor layer 14 is subjected to oxygen atmosphere annealing to densify the semiconductor layer. The oxidant is a gas or plasma, and the oxidizing property of the gas or plasma gradually increases as the thickness of the semiconductor layer increases. For example, an atomic layer deposition process is used, and a gas (such as ozone) is used as an oxidant. As the thickness of the semiconductor layer increases, the concentration of the gas increases gradually.

[0129] In an exemplary embodiment, as the thickness of the semiconductor layer increases, the oxygen concentration in the semiconductor layer gradually increases.

[0130] In an exemplary embodiment, during the process of forming the semiconductor layer, no annealing process is performed in between.

[0131] In an exemplary embodiment, gas (eg, ozone) related parameters may be controlled by an atomic layer deposition device so that the concentration of the gas (eg, ozone) gradually increases as the thickness of the semiconductor layer increases.

[0132] In another exemplary embodiment, using an atomic layer deposition process to grow a semiconductor layer on the inner wall of the hole by an oxidant includes:

[0133] Using an atomic layer deposition process, a semiconductor layer is grown on the inner wall of the hole by an oxidant, wherein the semiconductor layer is a metal oxide semiconductor layer; the semiconductor layer is in contact with the exposed first electrode and the second electrode respectively;

[0134] The atomic layer deposition process is adopted to grow a semiconductor layer on the inner wall of the hole by an oxidant, including: firstly introducing an oxidant and a precursor into the cavity, and sequentially growing multiple metal oxide atomic layers on the inner wall surface of the hole 31, and the multiple metal oxide atomic layers are used as the semiconductor layer 14; then, the grown semiconductor layer 14 is subjected to oxygen atmosphere annealing to densify the semiconductor layer. The oxidant is a gas or plasma, and the oxidizing property of the gas or plasma gradually increases as the thickness of the semiconductor layer increases. For example, the atomic layer deposition process is adopted, and plasma (such as active oxygen plasma) is used as the oxidant. As the thickness of the semiconductor layer increases, the power of the plasma gradually increases.

[0135] In an exemplary embodiment, during the process of forming the semiconductor layer, no annealing process is performed in between.

[0136] In an exemplary embodiment, the atomic layer deposition equipment may be used to control the plasma (eg, reactive oxygen plasma) related parameters so that the power of the plasma (eg, reactive oxygen plasma) gradually increases as the thickness of the semiconductor layer increases.

[0137] The manufacturing process of the semiconductor device disclosed in the present invention gradually increases the oxidative property of the gas or plasma to grow the semiconductor layer, thereby reducing the oxidation of the exposed first electrode and the second electrode during the oxidation process of the semiconductor layer, thereby increasing the contact resistance between the first electrode and the second electrode.

[0138] Step 104 , forming a patterned semiconductor layer, a gate dielectric layer and a gate electrode.

[0139] The formation of the semiconductor layer, the gate dielectric layer and the gate electrode comprises: on the basis of the substrate formed with the aforementioned pattern, etching the semiconductor layer, the gate dielectric film and the gate electrode film by a patterned etching process, retaining the semiconductor layer, the gate dielectric film and the gate electrode film in the hole 31, etching and removing a part of the semiconductor layer, the gate dielectric film and the gate electrode film on the surface of the third insulating dielectric layer 13, retaining the semiconductor layer, the gate dielectric film and the gate electrode film on the surface of the third insulating dielectric layer 13 around the opening of the hole 31, so that the gate dielectric film forms a gate dielectric layer 15, and the gate electrode film forms a gate electrode 16, the semiconductor layer 14 covers the bottom wall and the side wall of the hole 31, and extends to the surface of the third insulating dielectric layer 13 around the opening of the hole 31, the gate dielectric layer 15 and the gate electrode 16 both extend to the surface of the third insulating dielectric layer 13 around the opening of the hole, and the semiconductor layer 14 extending to the surface of the third insulating dielectric layer 13 around the opening of the hole 31 is located between the surface of the third insulating dielectric layer 13 and the gate dielectric layer 15, such as Figure 1 shown.

[0140] In an exemplary embodiment, the semiconductor layer may be a metal oxide, and the metal oxide may be at least one of indium gallium zinc oxide (IGZO), indium gallium oxide (InGaO), indium zinc oxide (IZO), indium tin oxide (ITO), indium tungsten oxide (IWO), and indium oxide (InO). For example, when the metal oxide material is IGZO, the leakage current of the transistor is small (the leakage current is less than or equal to 1E-18A), where 1E-18A refers to 10 to the negative 18th power of amperes, thereby ensuring a low refresh rate of the dynamic memory. It should be noted that the material of the metal oxide may also be IWO, ZnOx, InOx, In 2 O 3 、InWO、SnO 2 、TiO x 、InSnO x 、Zn x O yN z Mg x Zn y O z 、In x Zn y O z 、In x Ga y Zn z Oa、Zr x In y Zn z O a , Hf x In y Zn z O a Sn x In y Zn z O a 、Al x Sn y In z Zn a O d 、Si x In y Zn z O a 、Zn x Sn y O z 、Al x Zn y Sn z O a , Ga x Zn y Sn z O a 、Zr x Zn y Sn z O a , InG a For materials such as SiO, it is sufficient to ensure that the leakage current of the transistor can meet the requirements, and the specific adjustments can be made according to the actual situation.

[0141] In an exemplary embodiment, the material of the gate dielectric layer may be a high-K dielectric material, i.e., a dielectric material with a dielectric constant K ≥ 3.9. The high-K dielectric material may include, but is not limited to, at least one of the following: silicon oxide, aluminum oxide, hafnium oxide, hafnium aluminum oxide, and hafnium lanthanum oxide. The high-K dielectric material may be a ferroelectric material layer.

[0142] In an exemplary embodiment, the material of the gate electrode may be at least one of indium zinc oxide (IZO), indium tin oxide (ITO), titanium nitride (TiN), tungsten (W), molybdenum (Mo), and nickel (Ni).

[0143] In some embodiments, the leads may be formed after forming the transistor. In some embodiments, the leads and the source or drain are formed at the same time to form an integrated structure.

[0144] Step 105 , forming a first lead, a second lead, and a third lead.

[0145] The formation of the first lead, the second lead and the third lead includes: on the basis of the substrate formed with the aforementioned pattern, firstly forming a fourth insulating dielectric layer 17 covering the gate electrode 16 on the side of the gate electrode 16 away from the substrate; then, using a patterned etching process, forming a first via hole, a second via hole and a third via hole, the first via hole sequentially penetrates the fourth insulating dielectric layer 17, the third insulating dielectric layer 13 and the second insulating dielectric layer 12, and extends to the surface of the first electrode 21, exposing the surface of the first electrode 21; the second via hole penetrates the fourth insulating dielectric layer 17, extends to the surface of the gate electrode 16, and exposes the surface of the gate electrode 16; the third via hole sequentially penetrates the fourth insulating dielectric layer 17, extends to the surface of the gate electrode 16, and exposes the surface of the gate electrode 16; The first lead 51, the second lead 52 and the third lead 53 are formed on the side of the fourth insulating dielectric layer 17 away from the substrate, the first lead 51 is connected to the first electrode 21 through the first via hole, and the first lead 51 is used to connect the first electrode 21 to an external circuit; the second lead 52 is connected to the gate electrode 16 through the second via hole, and the second lead 52 is used to connect the gate electrode 16 to an external circuit; the third lead 53 is connected to the second electrode 22 through the third via hole, and the third lead 53 is used to connect the second electrode 22 to an external circuit, such as Figure 7 shown.

[0146] In an exemplary embodiment, the semiconductor device of the present application may be a transistor. Depending on the material of the semiconductor or channel layer of the transistor, the transistor may be an n-type or p-type metal oxide semiconductor transistor.

[0147] According to the type of gate insulating layer, the transistor can be a transistor with a low-K gate dielectric layer or a high-K gate dielectric layer. According to the material of the transistor, the transistor can be a transistor with a ferroelectric material as the gate dielectric layer (FeFET).

[0148] According to the application of transistors in the field of memory, transistors can be used in 1T memory cells, such as memory cells containing only one FeFET; transistors can be used in 1T1C memory cells; transistors can be used in 2T memory cells containing read transistors and write transistors, at least one of which can apply the transistor described in this application, and whether the 2T memory cell has additional capacitors or back gates and other features is not limited in this application; transistors can be used in SRAM memory cells, and any multi-transistor memory cell can use the transistor described in this application as needed.

[0149] The transistor described in the embodiments of the present application can be used in a two-dimensional memory cell array, or in a three-dimensional memory cell array.

[0150] The present disclosure also provides an electronic device, including the semiconductor device described in any of the above embodiments. The electronic device may be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply. The storage device may include a memory in a computer, etc., which is not limited here.

[0151] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted to facilitate understanding of the present invention and are not intended to limit the present invention. Any technician in the field to which the present invention belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present invention, but the patent protection scope of the present invention shall still be subject to the scope defined in the attached claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: forming a stacking structure of a first electrode, an insulating layer and a second electrode in sequence on a substrate; forming a hole extending in a direction perpendicular to the substrate on the stacked structure, wherein the hole exposes at least a portion of the first electrode and the second electrode; Using an atomic layer deposition process, a semiconductor layer is grown on the inner wall of the hole by an oxidant, wherein the semiconductor layer is a metal oxide semiconductor layer; the semiconductor layer is in contact with the exposed first electrode and the second electrode respectively; The method adopts an atomic layer deposition process to grow a semiconductor layer on the inner wall of the hole through an oxidant, comprising: introducing an oxidant and a precursor into a cavity, wherein the oxidant is a gas or plasma; The oxidizing property of the gas or plasma is enhanced as the thickness of the semiconductor layer increases.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: Growing a semiconductor layer on the inner wall of the hole by an oxidant using an atomic layer deposition process includes: The atomic layer deposition process is adopted to grow the semiconductor layer on the side wall of the hole firstly through weak oxidizing gas or plasma and then through strong oxidizing gas or plasma.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The weakly oxidizing gas or plasma substance is a weak oxidant; the strongly oxidizing gas or plasma substance is a strong oxidant.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: The weak oxidant includes water, hydrogen peroxide, or alcohols; the strong oxidant includes ozone or fluorine gas.

5. The method for manufacturing a semiconductor device according to claim 2, wherein: The weak oxidizing gas or plasma is ozone with a concentration range of 2% to 10%, or an active oxygen plasma with a power between 10W and 30W; the strong oxidizing gas or plasma is ozone with a concentration range of 10% to 20%, or an active oxygen plasma with a power between 30W and 60W.

6. The method for manufacturing a semiconductor device according to claim 2, wherein: First, a semiconductor layer having a thickness of 0.5 nanometers or more and 2 nanometers or less is grown by using a weakly oxidizing gas or plasma.

7. The method for manufacturing a semiconductor device according to claim 2, wherein: After the semiconductor layer is grown by the weak oxidizing gas or plasma and before the semiconductor layer is grown by the strong oxidizing gas or plasma, the method further comprises: The grown semiconductor layer is annealed in an oxygen atmosphere.

8. The method for manufacturing a semiconductor device according to claim 5, wherein: The semiconductor layer is continuously manufactured by using the same gas or plasma as the weak oxidizing gas and the strong oxidizing gas, and an annealing process is performed after the semiconductor layer is obtained.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: As the thickness of the semiconductor layer increases, the oxygen concentration in the semiconductor layer gradually increases.

10. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 9.

11. The semiconductor device according to claim 10, characterized in that The material of the semiconductor layer includes at least one of indium gallium zinc oxide, indium gallium oxide, indium zinc oxide, indium tin oxide, indium tungsten oxide, and indium oxide.

12. An electronic device, characterized in that: Comprising the semiconductor device according to any one of claims 10 or 11.

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