Semiconductor device and manufacturing method thereof

Abstract

A method of manufacturing a semiconductor device includes forming an epitaxial layer on a substrate, forming a well region and a source region in the epitaxial layer, forming a first trench in the epitaxial layer, the corners of the first trench having rounded corners protruding toward the well region, forming a second trench in the epitaxial layer, the bottom of the second trench being higher than the bottom of the first trench, and forming a second trench in the epitaxial layer, the width of the second groove is greater than that of the first groove, and forming a gate structure in the first groove and the second groove. According to the semiconductor device, the corner electric field concentration of the gate structure can be avoided, so that the on-resistance of the semiconductor device can be reduced.

Description

Technical Field

[0001] The present disclosure and some embodiments relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] In order to improve the channel density of metal oxide semiconductor field effect transistor (MOSFET), MOSFET may have a gate trench structure and may have a vertical channel. However, the corners of the gate trench structure may cause the on-resistance of the MOSFET to be too high due to the problem of excessive electric field concentration. Summary of the invention

[0003] Some embodiments of the present disclosure provide a method for manufacturing a semiconductor device, comprising forming an epitaxial layer on a substrate, forming a well region and a source region in the epitaxial layer, forming a first trench in the epitaxial layer, wherein the corners of the first trench have rounded corners protruding toward the well region, forming a second trench in the epitaxial layer, wherein the bottom of the second trench is higher than the bottom of the first trench, and the width of the second trench is greater than the width of the first trench, and forming a gate structure in the first trench and the second trench.

[0004] In some embodiments, forming a first trench in the epitaxial layer includes forming vertical sidewalls of the first trench in the epitaxial layer, and the bottom of the first trench exposes the drift region of the epitaxial layer, and performing a selective etching process to form rounded corners at the corners of the first trench protruding toward the well region, and the selective etching process etches the well region at a rate greater than the rate of etching the drift region.

[0005] In some embodiments, when the second trench is formed in the epitaxial layer, a bottom of the second trench exposes the well region.

[0006] In some embodiments, when the second trench is formed in the epitaxial layer, the bottom of the second trench is higher than the bottom of the source region.

[0007] In some embodiments, the gate structure includes a gate dielectric layer and a gate layer. The width of the gate dielectric layer in the second trench is greater than the width of the gate dielectric layer in the first trench. The gate layer is surrounded by the gate dielectric layer.

[0008] Some embodiments of the present disclosure provide a semiconductor device, comprising a substrate, an epitaxial layer, a gate structure, a source electrode, and a drain electrode. The epitaxial layer is on the substrate. The gate structure is in the epitaxial layer, wherein the gate structure has a first portion, a second portion, and a third portion from bottom to top, the width of the third portion is greater than the width of the second portion, and the width of the first portion is greater than the width of the second portion. The source electrode is on the epitaxial layer. The drain electrode is under the substrate.

[0009] In some embodiments, the epitaxial layer includes a source region and a well region. The source region is adjacent to the third portion of the gate structure, wherein the bottom of the third portion of the gate structure is higher than the bottom of the source region. The well region is adjacent to the source region and the gate structure.

[0010] In some embodiments, the epitaxial layer includes a source region and a well region. The source region is adjacent to the third portion of the gate structure. The well region is adjacent to the source region and the gate structure, wherein the third portion of the gate structure contacts the well region and the source region.

[0011] In some embodiments, the gate structure includes a gate dielectric layer and a gate layer. The width of the gate dielectric layer of the third portion of the gate structure is greater than the width of the gate dielectric layer of the first portion of the gate structure. The gate layer is surrounded by the gate dielectric layer.

[0012] In some embodiments, a width of the gate dielectric layer of a first portion of the gate structure is greater than a width of the gate dielectric layer of a second portion of the gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figures 1 to 6 A cross-sectional view of a semiconductor device formed in some embodiments of the present disclosure is shown.

[0014] Figure 7 The cross-sectional views of semiconductor devices according to other embodiments of the present disclosure are shown. DETAILED DESCRIPTION

[0015] Some embodiments of the present disclosure are related to a semiconductor device, and the gate structure of the semiconductor device has a first portion, a second portion and a third portion from bottom to top. The width of the third portion is greater than the width of the first portion, and the width of the first portion is greater than the width of the second portion. The first portion of the gate structure can be used to avoid electric field concentration at the corner of the gate structure, thereby reducing the on-resistance of the semiconductor device.

[0016] Figures 1 to 6 The cross-sectional view of a semiconductor device formed in some embodiments of the present disclosure is shown. Figure 1 , forming an epitaxial layer 120 on the substrate 110. The substrate 110 and the epitaxial layer 120 may be made of a semiconductor material, such as silicon, silicon carbide, the like, or a combination thereof. The substrate 110 and the epitaxial layer 120 may have a first conductor type, and the substrate 110 may be a heavily doped region, and the epitaxial layer 120 may be a lightly doped region. In some embodiments, the substrate 110 may be an N-type heavily doped substrate, and the epitaxial layer 120 may be an N-type lightly doped region. In some embodiments, the doped region of the first conductor type may include an N-type dopant, such as nitrogen, arsenic, or phosphorus.

[0017] Next, a well region 122 and a source region 124 are formed in the epitaxial layer 120. In some embodiments, a thermal oxidation process may be performed on the epitaxial layer 120 to form a silicon oxide layer on the surface of the epitaxial layer 120. Next, a first patterned photoresist layer may be formed on the epitaxial layer 120, and an ion implantation process may be performed to implant ions of the second conductor type into the epitaxial layer 120 to form the well region 122. The position of the well region 122 is defined by the first patterned photoresist layer. Next, the first patterned photoresist layer is removed, and a second patterned photoresist layer is formed on the epitaxial layer 120. An ion implantation process may be performed to implant ions of the first conductor type into the epitaxial layer 120 to form the source region 124. The position of the source region 124 is defined by the second patterned photoresist layer. After forming the source region 124 and the well region 122, the second patterned photoresist layer and the silicon oxide layer may be removed by a wet etching process. In some embodiments, one side of the source region 124 may be substantially aligned with one side of the well region 122, and the source region 124 does not completely cover the well region 122. That is, a portion of the top of the well region 122 is still exposed. In addition, the bottom of the well region 122 is lower than the bottom of the source region 124. The well region 122 may have a second conductor type, the source region 124 may have a first conductor type, and the well region 122 may be a lightly or moderately doped region, and the source region 124 may be a heavily doped region. In some embodiments, the well region 122 may be a P-type lightly or moderately doped region, and the source region 124 may be an N-type heavily doped region, that is, the doping concentration of the source region 124 is greater than the doping concentration of the well region 122. After the well region 122 and the source region 124 are formed, the remaining portion not occupied by the well region 122 and the source region 124 is the drift region 126, and the drift region 126 is a lightly doped region of the first conductor type, such as an N-type lightly doped region. The doping concentration of the source region 124 is greater than the doping concentration of the drift region 126. In some embodiments, the doping region of the first conductivity type may include an N-type dopant, such as nitrogen, arsenic, or phosphorus. In some embodiments, the doping region of the second conductivity type may include a P-type dopant, such as boron, aluminum, or gallium.

[0018] refer to Figure 2, a trench T1 is formed in the epitaxial layer 120. Specifically, a hard mask layer HM1 may be formed on the epitaxial layer 120, and the hard mask layer HM1 exposes a portion of the drift region 126 between adjacent source regions 124. In some embodiments, the hard mask layer HM1 may be formed of a dielectric material, such as silicon nitride, silicon oxide, the like, or a combination thereof. Next, the hard mask layer HM1 is used as an etching mask to form a trench T1 in the epitaxial layer 120. The trench T1 may be formed by a dry etching process. The trench T1 has a vertical sidewall (e.g., a sidewall substantially perpendicular to the bottom of the substrate 110), the bottom of the trench T1 exposes the drift region 126 of the epitaxial layer 120, and the bottom of the trench T1 is substantially flush with the well region 122, and the sidewall of the trench T1 exposes the well region 122 and the source region 124. Therefore, the drift region 126 and the well region 122 are simultaneously exposed near the corner of the trench T1. In some embodiments, the width W1 of the trench T1 may be between 0.8 micrometers and 1.1 micrometers. In some embodiments, the depth of the trench T1 may be between 2.2 micrometers and 2.5 micrometers.

[0019] refer to Figure 3 , a selective etching process is performed to form a fillet C protruding toward the well region 122 at the corner of the trench T1. Specifically, the drift region 126 and the well region 122 are exposed at the same time near the corner of the trench T1, and the drift region 126 and the well region 122 have dopants of different conductivity types. When the same material is doped with different types of dopants, it is selective to a specific etching process. For example, the selective etching process may have a higher etching rate for the P-type doped region and a lower etching rate for the N-type doped region. Therefore, an appropriate etching process may be selected to form a fillet C protruding toward the well region 122 at the corner of the trench T1. Specifically, the rate at which the selective etching process etches the well region 122 (e.g., the P-type doped region) is greater than the rate at which the drift region 126 (e.g., the N-type doped region) is etched, so the fillet C can be formed in the well region 122. At this point, a trench T1 may be formed in the epitaxial layer 120, the trench T1 having vertical sidewalls and a rounded corner C protruding toward the well region, and the width of the bottom of the trench T1 is greater than the width of the top of the trench T1. In some embodiments, the maximum width W2 of the trench T1 (the width of the portion of the trench T1 having the rounded corner C) may be between 1.2 microns and 1.5 microns. From another perspective, the outer edge of the rounded corner C exceeds the sidewall of the trench T1, and the bottom of the rounded corner C is lower than the bottom surface of the trench T1.

[0020] refer to Figure 4 After the rounded corner C of the trench T1 is formed, a shielding region 128 is formed at the bottom of the trench T1. Specifically, a hard mask layer HM1 (see Figure 3) is used as a mask, and an ion implantation process is performed to implant ions of the second conductor type into the epitaxial layer 120 to form a shielding region 128. The shielding region 128 may have the second conductor type, and the shielding region 128 may be a heavily doped region. In some embodiments, the shielding region 128 may be a heavily doped region, and the doping concentration of the shielding region 128 is greater than the doping concentration of the well region 122, and the doping concentration of the shielding region 128 is greater than the doping concentration of the drift region 126. After forming the shielding region 128, the hard mask layer HM1 is removed. In some embodiments, the doping region of the second conductor type may include a P-type dopant, such as boron, aluminum, or gallium.

[0021] Next, a hard mask layer HM2 may be formed on the epitaxial layer 120, and the hard mask layer HM2 exposes the trench T1 and a portion of the source region 124. In some embodiments, the hard mask layer HM2 may be formed of a dielectric material, such as silicon nitride, silicon oxide, the like, or a combination thereof. Next, a trench T2 is formed in the epitaxial layer 120 using the hard mask layer HM2 as an etching mask. The bottom of the trench T2 is higher than the bottom of the trench T1, and the width of the trench T2 is greater than the width of the trench T1. In some embodiments, the width W3 of the trench T2 may be between 1.6 microns and 1.8 microns. In some embodiments, the bottom of the trench T2 is higher than the bottom of the source region 124, so the trench T2 does not expose the well region 122. In some embodiments, after the trench T2 is formed, the length L of the vertical sidewall of the trench T1 is between 1.0 microns and 1.2 microns.

[0022] refer to Figure 5 , the hard mask layer HM2 is removed by a wet etching process. Then, a source electrode 130 is formed on the well region 122 and the source region 124, and a drain electrode 140 is formed under the substrate 110. In some embodiments, the source electrode 130 and the drain electrode 140 may be made of a conductive material, such as metal.

[0023] refer to Figure 6, a gate structure 150 is formed in the trench T1 and the trench T2. The gate structure 150 includes a gate dielectric layer 152 and a gate layer 154. The gate layer 154 is surrounded by the gate dielectric layer 152. The width W4 of the gate dielectric layer 152 in the trench T2 is greater than the widths W5 and W6 of the gate dielectric layer 152 in the trench T1. Specifically, a dielectric material may be first filled in the trench T1 and the trench T2, and a trench may be formed in the dielectric material. Then, a gate material layer is formed in the trench in the dielectric material. Therefore, the gate dielectric layer 152 and the gate layer 154 of the gate structure 150 may be formed in the trench T1 and the trench T2. The sidewalls of the gate layer 154 of the gate structure 150 are substantially perpendicular to the surface of the substrate 110, so the width W6 of the gate dielectric layer 152 surrounded by the fillet C of the trench T1 is greater than the width W5 of the gate dielectric layer 152 surrounded by the vertical sidewalls of the trench T1. In some embodiments, the gate dielectric layer 152 may be made of silicon oxide, silicon nitride, or the like. The gate layer 154 may be made of a semiconductor material or a conductor material, such as polysilicon or metal.

[0024] The obtained semiconductor device is Figure 6 As shown. The semiconductor device includes a substrate 110, an epitaxial layer 120, a gate structure 150, a source electrode 130 and a drain electrode 140. The epitaxial layer 120 is on the substrate 110. The gate structure 150 is formed in the trenches T1 and T2 of the epitaxial layer 120, so the gate structure 150 has the structure described above for the trenches T1 and T2, so the relevant details will not be repeated. From another perspective, the gate structure 150 has a first portion 150A, a second portion 150B and a third portion 150C from bottom to top, the width of the third portion 150C is greater than the width of the second portion 150B, and the width of the first portion 150A is greater than the width of the second portion 150B. The first portion 150A of the gate structure 150 has a rounded corner C protruding outward. In some embodiments, the width of the third portion 150C is also greater than the width of the first portion 150A. The source electrode 130 is on the epitaxial layer 120. The drain electrode 140 is below the substrate 110. The epitaxial layer 120 includes a source region 124, a well region 122, a drift region 126, and a shielding region 128. The source region 124 is adjacent to a third portion 150C of the gate structure 150, wherein the bottom of the third portion 150C of the gate structure 150 is higher than the bottom of the source region 124, and the first portion 150A of the gate structure 150 contacts the well region 122. The well region 122 is adjacent to the source region 124 and the gate structure 150. The shielding region 128 is at the bottom of the gate structure 150. In some embodiments, the source region 124 and the drift region 126 have a first conductor type, the well region 122 and the shielding region 128 have a second conductor type, and the second conductor type is different from the first conductor type.

[0025] The gate structure 150 of the semiconductor device of some embodiments of the present disclosure includes a gate dielectric layer 152 and a gate layer 154. The gate layer 154 is surrounded by the gate dielectric layer 152, wherein the width of the gate dielectric layer 152 of the third portion 150C of the gate structure 150 is greater than the width of the gate dielectric layer 152 of the first portion 150A of the gate structure 150, and the width of the gate dielectric layer 152 of the first portion 150A of the gate structure 150 is greater than the width of the gate dielectric layer 152 of the second portion 150B of the gate structure 150. The gate dielectric layer 152 of the first portion 150A of the gate structure 150 can be used to keep the current path away from the corner portion of the gate layer 154 of the gate structure 150, so that the current path will not be affected by the strong electric field of the corner portion of the gate layer 154 of the gate structure 150. In this way, a lower on-resistance of the semiconductor device can be achieved. The current path may flow from the drain electrode 140 through the drift region 126 , the boundary between the well region 122 and the gate structure 150 , the boundary between the well region 122 and the source region 124 , and to the source electrode 130 .

[0026] In addition, the semiconductor device disclosed in the present invention can reduce the capacitance between the source region 124 and the gate layer 154. Specifically, the capacitance between the source region 124 and the gate layer 154 can be reduced by the gate dielectric layer 152 (eg, Figure 6 The gate structure 150 has a third portion 150C and the third portion 150C overlaps the source region 124. When the gate structure 150 has a third portion 150C and the third portion 150C overlaps the source region 124, the portion of the second portion 150B of the gate structure 150 overlapping the source region 124 becomes less, so the portion of the gate dielectric layer 152 of the second portion 150B of the gate structure 150 overlapping the source region 124 also becomes less. In this way, the capacitance between the source region 124 and the gate layer 154 can be reduced to reduce the influence of this capacitance on the semiconductor device.

[0027] Figure 7 The cross-sectional views of semiconductor devices according to other embodiments of the present disclosure are shown. Figure 7 Semiconductor devices and Figure 6 The difference is that the semiconductor device is formed Figure 7 When the semiconductor device is formed, a trench T2 is formed in the epitaxial layer 120 (refer to Figure 4), the bottom of the trench T2 exposes the well region 122. Therefore, the third portion 150C of the gate structure 150 of the semiconductor device contacts the well region 122 and the source region 124. When the third portion 150C of the gate structure 150 contacts the well region 122, the area of ​​the channel region (the junction of the well region 122 and the gate structure 150) of the semiconductor device can be increased. However, since it will also cause the resistance of the semiconductor device to increase, the proportion of the third portion 150C of the gate structure 150 contacting the well region 122 can be controlled to control the resistance of the semiconductor device.

[0028] In summary, some embodiments of the present disclosure relate to a semiconductor device, and the gate structure of the semiconductor device has a first portion, a second portion, and a third portion from bottom to top. The width of the third portion is greater than the width of the first portion, and the width of the first portion is greater than the width of the second portion. The first portion of the gate structure can be used to avoid electric field concentration in the corners of the gate structure, thereby reducing the on-resistance of the semiconductor device. The third portion of the gate structure can be used to reduce the portion where the second portion of the gate structure overlaps with the source region to reduce the capacitance between the source region and the gate layer, thereby reducing the effect of this capacitance on the semiconductor device.

[0029] The above descriptions are only some embodiments of the present disclosure, not all embodiments. Any equivalent changes made to the technical solution of the present disclosure by ordinary technicians in this field after reading the specification of the present disclosure are covered by the claims of the present disclosure.

[0030]

Explanation of symbols

[0031] 110: Substrate

[0032] 120: Epitaxial layer

[0033] 122: Well region

[0034] 124: Source region

[0035] 126: Drift Zone

[0036] 128: Sheltered Area

[0037] 130: Source electrode

[0038] 140: Drain electrode

[0039] 150: Gate structure

[0040] 150A: Part I

[0041] 150B: Part 2

[0042] 150C: Part 3

[0043] 152: Gate dielectric layer

[0044] 154: Gate layer

[0045] C: Rounded corners

[0046] HM1, HM2: Hard mask layer

[0047] L: Length

[0048] M: Part

[0049] T1, T2: Grooves

[0050] W1, W2, W3, W4, W5, W6: width.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: Include: forming an epitaxial layer on a substrate; forming a well region and a source region in the epitaxial layer; forming a first trench in the epitaxial layer, wherein a corner of the first trench has a rounded corner protruding toward the well region; forming a second trench in the epitaxial layer, wherein the bottom of the second trench is higher than the bottom of the first trench and the width of the second trench is greater than the width of the first trench; as well as A gate structure is formed in the first trench and the second trench.

2. The method according to claim 1, characterized in that: Forming the first trench in the epitaxial layer comprises: forming a vertical sidewall of the first trench in the epitaxial layer, wherein the bottom of the first trench exposes the drift region of the epitaxial layer; as well as A selective etching process is performed to form the rounded corner at the corner of the first trench protruding toward the well region, and the selective etching process etches the well region at a rate greater than a rate of etching the drift region.

3. The method according to claim 1, characterized in that When the second trench is formed in the epitaxial layer, the bottom of the second trench exposes the well region.

4. The method according to claim 1, characterized in that When the second trench is formed in the epitaxial layer, the bottom of the second trench is higher than the bottom of the source region.

5. The method according to claim 1, characterized in that The gate structure comprises: a gate dielectric layer, wherein a width of the gate dielectric layer in the second trench is greater than a width of the gate dielectric layer in the first trench; and A gate layer is surrounded by the gate dielectric layer.

6. A semiconductor device, characterized in that: Include: substrate; an epitaxial layer on the substrate; A gate structure, in the epitaxial layer, wherein the gate structure has a first portion, a second portion and a third portion from bottom to top, the width of the third portion is greater than the width of the second portion, and the width of the first portion is greater than the width of the second portion; a source electrode on the epitaxial layer; as well as A drain electrode is under the substrate.

7. The semiconductor device according to claim 6, wherein: The epitaxial layer comprises: a source region adjacent to the third portion of the gate structure, wherein a bottom of the third portion of the gate structure is higher than a bottom of the source region; and The well region is adjacent to the source region and the gate structure.

8. The semiconductor device according to claim 6, wherein: The epitaxial layer comprises: a source region adjacent to the third portion of the gate structure; and The well region is adjacent to the source region and the gate structure, wherein the third portion of the gate structure contacts the well region and the source region.

9. The semiconductor device according to claim 6, wherein: The gate structure comprises: a gate dielectric layer, wherein a width of the gate dielectric layer of the third portion of the gate structure is greater than a width of the gate dielectric layer of the first portion of the gate structure; as well as A gate layer is surrounded by the gate dielectric layer.

10. The semiconductor device according to claim 9, wherein: The width of the gate dielectric layer of the first portion of the gate structure is greater than the width of the gate dielectric layer of the second portion of the gate structure.

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