Semiconductor structure and preparation method thereof

Abstract

The invention discloses a semiconductor structure and a preparation method thereof. The preparation method comprises the following steps: providing a semiconductor substrate; forming a first isolation layer on the semiconductor substrate, wherein the first isolation layer comprises at least two sub-isolation layers which are sequentially stacked on the semiconductor substrate; in the direction perpendicular to the semiconductor substrate, under a specific etching condition, the etching rate of the sub-isolation layer farthest from the semiconductor substrate is smaller than that of other sub-isolation layers; sequentially depositing a gate layer and a second isolation layer on the first isolation layer; a groove penetrating through the second isolation layer, the gate layer and the first isolation layer is formed, and in the portion, penetrating through the first isolation layer, of the groove, the size of the groove located at the end face portion, away from the semiconductor substrate, of the first isolation layer is the smallest. According to the invention, the inverted trapezoidal structure at the bottom of the trench can be optimized after etching, the resistance is reduced, and the control capability of the gate to the trench is improved, so that the saturation current of the transistor is increased, and the performance of the transistor is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor thin film deposition, and in particular to a semiconductor structure and a preparation method thereof. Background Art

[0002] In the related art, for example, a semiconductor structure of a surround-gate transistor usually requires first forming a stacked structure of a first isolation layer / gate material layer / second isolation on a substrate, and then etching the stacked structure through photolithography and anisotropic etching processes (such as plasma etching in dry etching) to form a groove that penetrates the stacked structure, and then forming a gate oxide layer and a polysilicon protective layer on the side walls of the trench in sequence, and then etching the gate oxide layer and the polysilicon protective layer at the bottom of the trench to expose the substrate, and then depositing a channel layer (such as a phosphorus-doped amorphous silicon film) on the side walls and bottom of the trench. In the prior art, since the grooves to be formed by etching have a certain depth, when the grooves are anisotropically etched, the etchant (such as plasma) will find it difficult to reach the bottom of the groove, resulting in a characteristic size at the bottom of the groove that is smaller than the characteristic size at the top. Therefore, the grooves usually formed are in an inverted trapezoidal shape, which also causes a "bottleneck" phenomenon to occur in the formed channel layer at the bottom of the groove, that is, the thickness of the channel layer in some areas at the bottom of the groove is too thin, which increases the resistance and forms a channel conduction bottleneck. In addition, the inverted trapezoidal structure causes the electric field distribution to change, and the gate electric field's ability to control the channel layer in the bottom area of ​​the groove decreases, which in turn leads to a decrease in the saturation current of the prepared surround-gate transistor and a deterioration in performance. Summary of the invention

[0003] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0004] In view of the existing problems, according to one aspect of the present application, a method for preparing a semiconductor structure is provided, the preparation method comprising:

[0005] providing a semiconductor substrate;

[0006] Forming a first isolation layer on the semiconductor substrate, wherein the first isolation layer comprises at least two sub-isolation layers sequentially stacked on the semiconductor substrate; wherein, in a direction perpendicular to the semiconductor substrate, under specific etching conditions, an etching rate of the sub-isolation layer farthest from the semiconductor substrate is lower than an etching rate of other sub-isolation layers;

[0007] Depositing a gate layer and a second isolation layer in sequence on the first isolation layer;

[0008] A groove penetrating the second isolation layer, the gate layer and the first isolation layer is formed by photolithography and etching processes, wherein, among the portions of the groove penetrating the first isolation layer, the groove size at the end surface of the first isolation layer away from the semiconductor substrate is the smallest.

[0009] Exemplarily, in a direction perpendicular to the semiconductor substrate, under specific etching conditions, the farther the sub-isolation layer is from the semiconductor substrate, the smaller the etching rate, and the closer the sub-isolation layer is to the semiconductor substrate, the larger the etching rate, and the cross-sectional shape of the portion of the formed groove that passes through the first isolation layer is a right trapezoid, and the cross-section is perpendicular to the surface of the semiconductor substrate.

[0010] Exemplarily, the material of the sub-isolation layer farthest from the semiconductor substrate is silicon nitride, and the material of at least one of the other sub-isolation layers is boron-doped silicon nitride.

[0011] Exemplarily, the material of the sub-isolation layer farthest from the semiconductor substrate is silicon nitride, and the material of at least one of the other sub-isolation layers is silicon nitride doped with at least one of carbon and oxygen.

[0012] Exemplarily, the first isolation layer includes a first sub-isolation layer, a second sub-isolation layer and a third sub-isolation layer stacked in sequence on the semiconductor substrate, wherein the materials of the first sub-isolation layer and the second sub-isolation layer are both boron-doped silicon nitride, the material of the third sub-isolation layer is silicon nitride, and the boron doping concentration in the first sub-isolation layer is greater than the boron doping concentration in the second sub-isolation layer.

[0013] Exemplarily, the material of the sub-isolation layer closest to the semiconductor substrate is silicon oxide, and the material of at least one of the other sub-isolation layers is silicon nitride.

[0014] Exemplarily, the materials of the other sub-isolation layers are all silicon nitride and the density of silicon nitride in each sub-isolation layer is different, wherein the density of silicon nitride in the sub-isolation layer farthest from the semiconductor substrate is the highest.

[0015] Exemplarily, the materials of the other sub-isolation layers are all silicon nitride and are all prepared by a plasma enhanced chemical vapor deposition process. When other deposition parameters are kept unchanged, the density of the grown silicon nitride is controlled by adjusting the power of the plasma during the process. The greater the plasma power, the lower the density of the grown silicon nitride, and the smaller the plasma power, the higher the density of the grown silicon nitride.

[0016] Exemplarily, the material of the other sub-isolation layers is silicon nitride, and the density of the silicon nitride in the sub-isolation layer that is farther away from the semiconductor substrate is higher, and the density of the silicon nitride in the sub-isolation layer that is closer to the semiconductor substrate is lower.

[0017] Another aspect of the present application provides a semiconductor structure, which is prepared by the above-mentioned preparation method, and includes:

[0018] Semiconductor substrate;

[0019] A first isolation layer, disposed on the semiconductor substrate, wherein the first isolation layer comprises at least two sub-isolation layers stacked on the semiconductor substrate;

[0020] A gate layer, disposed on the first isolation layer;

[0021] A second isolation layer, disposed on the gate layer;

[0022] A groove penetrates the second isolation layer, the gate layer and the first isolation layer, wherein, in a portion of the groove penetrating the first isolation layer, a groove size located at an end surface of the first isolation layer away from the semiconductor substrate is the smallest.

[0023] The semiconductor structure and preparation method of the present application form a first isolation layer on a semiconductor substrate, wherein the first isolation layer includes at least two layers of sub-isolation layers stacked and etched at different rates in a direction perpendicular to the semiconductor substrate. Due to the different etching rates, the size of the etched groove can be minimized at the end surface of the first isolation layer away from the semiconductor substrate, while it is larger than the size of the groove at other locations. In particular, the size of the portion of the groove closer to the semiconductor substrate relative to the end surface is increased, so that the inverted trapezoidal structure is optimized, which is more conducive to the deposition of the channel layer. Therefore, the thickness of the channel layer at the "bottleneck" position at the bottom of the groove in the prior art is increased, thereby reducing the resistance and avoiding or reducing the appearance of a conductive bottleneck. In addition, the embodiments of the present application can achieve lateral expansion of the bottom of the groove according to the different etching rates of the sub-isolation layers. The bottom of the groove after lateral expansion can make the bottom of the channel closer to the electric field, thereby improving the control ability of the surrounding gate over the channel, thereby increasing the saturation current of the transistor and improving its performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The following drawings of the present invention are used to understand the present invention as part of the present invention. The embodiments of the present invention are shown in the drawings and the description thereof is used to explain the principle of the present invention.

[0025] In the attached figure:

[0026] Figure 1A-1EA cross-sectional schematic diagram of a semiconductor structure obtained by implementing a method for manufacturing a semiconductor structure in the related art is shown;

[0027] Figure 2 A flow chart showing a method for preparing a semiconductor structure according to a specific embodiment of the present application is shown;

[0028] Figure 3A-Figure 3F A cross-sectional schematic diagram of a semiconductor structure obtained by sequentially implementing a method for manufacturing a semiconductor structure according to a specific embodiment of the present application is shown. DETAILED DESCRIPTION

[0029] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present invention. However, it is apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features well known in the art are not described.

[0030] It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0031] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0032] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0033] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0034] In order to fully understand the present invention, detailed steps and structures will be presented in the following description to illustrate the technical solution proposed by the present invention. The preferred embodiments of the present invention are described in detail below, but in addition to these detailed descriptions, the present invention may also have other implementations.

[0035] In a related technique, Figure 1A-1E As shown, it shows a cross-sectional schematic diagram of a semiconductor structure obtained by implementing a method for manufacturing a semiconductor structure of the related art. Figure 1A As shown, a stacked structure of thin films is deposited on a semiconductor substrate 100 through semiconductor process steps. The stacked structure is composed of a first silicon nitride layer 101, a titanium nitride layer 102, a tungsten layer 103 and a second silicon nitride layer 104 from bottom to top. The titanium nitride layer 102 and the tungsten layer 103 will be used as a gate layer of the semiconductor structure. Then, as shown in FIG. Figure 1BAs shown, the stacked structure is etched by photolithography and etching processes to form a groove 105 that penetrates the first silicon nitride layer 101, the titanium nitride layer 102, the tungsten layer 103 and the second silicon nitride layer 104. Since the first silicon nitride layer 101 is located at the bottom of the stacked structure, and the current plasma dry etching process accumulates more by-products on the sidewalls as the etching proceeds, the protective effect on the sidewalls is enhanced, and the etching rate of the sidewalls is lower than the etching rate at the bottom of the groove, so that the cross-sectional shape of the portion of the groove in the first silicon nitride layer 101 is an inverted trapezoid; then as shown in Figure 1C As shown, a gate oxide layer 106 and a gate oxide protection layer 107 are formed on the trench 105; then, as shown Figure 1D As shown, the gate oxide layer 106 and the gate oxide protection layer 107 at the bottom of the trench 105 are etched to form an opening to expose a portion of the semiconductor substrate 100. Figure 1E As shown, Figure 1E Figure B in Figure 1E A local enlarged view of A in the left figure, a channel layer 108 is formed on the gate oxide protection layer 107 so that the channel layer 108 covers the above opening and the gate oxide protection layer 107. The gate oxide protection layer 107 and the channel layer 108 are both made of polysilicon and are used together as a channel. Then, a dielectric layer 109 is filled in the trench 105. After the stacked structure is etched, the bottom of the trench is an inverted trapezoidal structure. This structure makes the thickness of the channel layer deposited on the side wall of the bottom of the trench very thin, which is easy to be at the position where the first silicon nitride layer contacts the source and drain, that is, Figure 1E A conductive bottleneck is formed at point A in the figure. Since the channel layer is relatively thin at this point, the resistance is increased, resulting in a conductive bottleneck. In addition, the inverted trapezoidal structure makes the channel layer on its side wall far away from the electric field, and the gate's ability to control its electric field is reduced, thereby reducing the saturation current of the surround-gate transistor and deteriorating its performance.

[0036] In view of the above problems, the present invention provides a method for preparing a semiconductor structure. Figure 2 As shown, the preparation method comprises the following steps:

[0037] Step S210: providing a semiconductor substrate;

[0038] Step S220: forming a first isolation layer on the semiconductor substrate, wherein the first isolation layer includes at least two sub-isolation layers sequentially stacked on the semiconductor substrate; wherein, in a direction perpendicular to the semiconductor substrate, under specific etching conditions, an etching rate of the sub-isolation layer farthest from the semiconductor substrate is less than an etching rate of other sub-isolation layers;

[0039] Step S230: depositing a gate layer and a second isolation layer on the first isolation layer in sequence;

[0040] Step S240: using photolithography and etching processes to form a groove penetrating the second isolation layer, the gate layer and the first isolation layer, wherein, among the portions of the groove penetrating the first isolation layer, the groove size at the end surface of the first isolation layer away from the semiconductor substrate is the smallest.

[0041] The method for preparing the semiconductor structure of the embodiment of the present application forms a first isolation layer on a semiconductor substrate, wherein the first isolation layer includes at least two layers of sub-isolation layers stacked and etched at different rates in a direction perpendicular to the semiconductor substrate. Due to the different etching rates, the size of the etched groove can be minimized at the end surface of the first isolation layer away from the semiconductor substrate, while it is larger than the size of the groove at other locations. In particular, the size of the portion of the groove closer to the semiconductor substrate relative to the end surface is increased, so that the inverted trapezoidal structure is optimized, which is more conducive to the deposition of the channel layer. Therefore, the thickness of the channel layer at the "bottleneck" position at the bottom of the groove in the prior art is increased, thereby reducing the resistance and avoiding or reducing the occurrence of a conductive bottleneck. In addition, the embodiment of the present application can achieve lateral expansion of the bottom of the groove according to the different etching rates of the sub-isolation layers. The bottom of the groove after lateral expansion can make the bottom of the channel closer to the electric field, thereby improving the control ability of the surrounding gate over the channel, thereby increasing the saturation current of the transistor and improving its performance.

[0042] Embodiment 1

[0043] Below, reference Figure 2 and FIG. 3A to FIG. 3F The preparation method of the semiconductor structure of the present application is described in detail, wherein: Figure 2 A flowchart showing a method for preparing a semiconductor structure according to a specific embodiment; Figures 3A-3F A cross-sectional schematic diagram of a semiconductor structure obtained by sequentially implementing a method for preparing a semiconductor structure according to a specific embodiment of the present application is shown.

[0044] Illustratively, the method for preparing the semiconductor structure of the present application comprises the following steps:

[0045] First, if Figure 2 As shown, step S210 is executed. Figure 3A As shown, a semiconductor substrate 200 is provided.

[0046] Exemplarily, the semiconductor substrate 200 may also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, including a multilayer structure composed of these semiconductor materials, etc., or it may also be silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or it may also be double-sided polished silicon wafers (Double Side Polished Wafers, DSP), etc.

[0047] Next, execute step S220, such as Figure 3A As shown, a first isolation layer 201 is formed on a semiconductor substrate 200, wherein the first isolation layer 201 includes at least two sub-isolation layers stacked in sequence on the semiconductor substrate; wherein, in a direction perpendicular to the semiconductor substrate, under specific etching conditions, an etching rate of the sub-isolation layer farthest from the semiconductor substrate is less than an etching rate of other sub-isolation layers.

[0048] Exemplarily, the material of the sub-isolation layer farthest from the semiconductor substrate is silicon nitride, that is, the material of the top sub-isolation layer in the first isolation layer 201 is silicon nitride, and the material of at least one sub-isolation layer in the other sub-isolation layers is boron-doped silicon nitride, so that there is at least one sub-isolation layer made of boron-doped silicon nitride under the top sub-isolation layer, and under the same dry etching conditions, the etching rate of the boron-doped silicon nitride sub-isolation layer is higher than the etching rate of the top silicon nitride. Therefore, in the process of forming the groove by subsequent lithography and etching processes, due to the presence of the boron-doped silicon nitride sub-isolation layer in the first isolation layer, the size of the part of the groove that passes through the boron-doped silicon nitride can be laterally expanded.

[0049] Optionally, the boron doping concentration in the boron-doped silicon nitride of different layers may be different. For example, the boron doping concentration in the boron-doped silicon nitride away from the semiconductor substrate 200 is less than the boron doping concentration in the boron-doped silicon nitride close to the semiconductor substrate 200, or the boron doping concentration in the boron-doped silicon nitride away from the semiconductor substrate 200 is greater than the boron doping concentration in the boron-doped silicon nitride close to the semiconductor substrate 200. The specific concentration may be reasonably selected according to actual needs.

[0050] For example, continue as Figure 3AAs shown, the first isolation layer 201 includes a first sub-isolation layer 2011, a second sub-isolation layer 2012 and a third sub-isolation layer 2013 stacked in sequence on a semiconductor substrate, wherein the first sub-isolation layer 2011 and the second sub-isolation layer 2012 are made of boron-doped silicon nitride, the third sub-isolation layer 2013 is made of silicon nitride, and the doping concentration of boron in the first sub-isolation layer 2011 is greater than the doping concentration of boron in the second sub-isolation layer 2012. In one example, the doping concentration of boron in the second sub-isolation layer 2012 and the first sub-isolation layer 2011 gradually changes from low to high, so that the etching speed gradually increases, and then after the subsequent etching process, a positive trapezoidal structure is formed at the bottom of the trench. In another example, the material of the third sub-isolation layer 2013 is silicon nitride, and the doping concentration of boron in the first sub-isolation layer 2011 is lower than the doping concentration of boron in the second sub-isolation layer 2012. In this case, although the boron doping concentrations in the second sub-isolation layer 2012 and the first sub-isolation layer 2011 change from high to low, the etching rate of the second sub-isolation layer 2012 is higher than that of the first sub-isolation layer 2011, but since the material of the top layer, the third sub-isolation layer 2013, is silicon nitride, its etching rate is lower than that of the second sub-isolation layer 2012 and also lower than that of the first sub-isolation layer 2011. Therefore, the size of the portion where the groove passes through the boron-doped silicon nitride can eventually be made larger than the size of the portion where the groove passes through the silicon nitride.

[0051] It should be noted that the number of sub-isolation layers in the first isolation layer 201 is designed according to actual needs and is not limited here. When the number of sub-isolation layers in the first isolation layer 201 is greater than 3 layers, the material of the sub-isolation layer farthest from the semiconductor substrate 200 is silicon nitride, and the materials of the other sub-isolation layers are all boron-doped silicon nitride. The design of the boron doping concentration in each sub-isolation layer can refer to the above embodiment and will not be repeated here.

[0052] Exemplarily, the material of the sub-isolation layer farthest from the semiconductor substrate 200 is silicon nitride, and the material of at least one of the other sub-isolation layers is silicon nitride doped with at least one of carbon and oxygen, for example, the material of at least one of the other sub-isolation layers is doped materials such as SiCN and / or SiCON. By doping carbon and / or oxygen in silicon nitride, the etching rate of the doped silicon nitride is greater than the etching rate of the undoped silicon nitride during etching, so that when the groove is subsequently etched to form a groove, in the part where the groove passes through the first isolation layer 201, the groove size located at the end surface of the first isolation layer 201 away from the semiconductor substrate is the smallest. It should be noted that the design concept of the concentration of carbon and / or oxygen doped in other sub-isolation layers is similar to the design concept of boron doping in the above-mentioned embodiment, which will not be repeated here. Exemplarily, the material of the sub-isolation layer closest to the semiconductor substrate 200 is silicon oxide, and the material of at least one of the other sub-isolation layers is silicon nitride. Under the same dry etching conditions, the etching rate of silicon nitride is lower than that of silicon oxide, and silicon oxide is at the bottom layer of all sub-isolation layers, that is, the etching rate of the bottom sub-isolation layer is the fastest, so that after the subsequent etching process, the cross-sectional shape of the bottom of the groove (that is, the part of the groove that passes through the first isolation layer) can be a right trapezoid.

[0053] Exemplarily, the material of the sub-isolation layer closest to the semiconductor substrate 200 is silicon oxide, and the materials of the other sub-isolation layers are all silicon nitride, and the density of silicon nitride in each sub-isolation layer is different, among which the density of silicon nitride in the sub-isolation layer farthest from the semiconductor substrate is the highest. For the same material to be etched under the same dry etching conditions, the higher the density of the film layer, the lower its etching rate. Therefore, in this example, the density of silicon nitride in the sub-isolation layer farthest from the semiconductor substrate 200 is the highest. Then, during etching, the etching rate of the sub-isolation layer farthest from the semiconductor substrate 200 is the lowest, and the etching rates of all sub-isolation layers below it are higher than the etching rate of the sub-isolation layer farthest from the semiconductor substrate 200. Therefore, the sub-isolation layer made of silicon nitride can also form a structure with a small top and a large bottom after the subsequent etching process. Since the material of the sub-isolation layer closest to the semiconductor substrate is silicon oxide, and the etching rate of silicon oxide is greater than that of silicon nitride, after the subsequent etching process, the size of the silicon oxide portion of the groove penetrating the first isolation layer can be made larger than the size of the silicon nitride portion of the groove penetrating the first isolation layer. Optionally, the material of other sub-isolation layers is silicon nitride and the density of silicon nitride in each sub-isolation layer is different, wherein the density of silicon nitride in the sub-isolation layer farthest from the semiconductor substrate 200 is the highest, and the density of silicon nitride between the silicon nitride with the highest density and silicon oxide can gradually increase or decrease or can also be irregular changes, which is not specifically limited here.

[0054] In some specific examples, the material of the sub-isolation layer closest to the semiconductor substrate 200 is silicon oxide, and the density of silicon nitride in the sub-isolation layer farther from the semiconductor substrate 200 is higher, and the density of silicon nitride in the sub-isolation layer closer to the semiconductor substrate 200 is lower. In this example, since the higher the density of the film layer, the lower its etching rate, and the material of the sub-isolation layer closest to the semiconductor substrate 200 is silicon oxide, the etching rate of silicon oxide is greater than the etching rate of silicon nitride, therefore, these silicon nitride sub-isolation layers and the sub-isolation layer closest to the semiconductor substrate 200 constitute the first isolation layer with the etching rate from low to high, and similarly, after the subsequent etching process, the cross-sectional shape of the bottom of the trench (i.e., the portion of the trench penetrating the first isolation layer) can be a positive trapezoid.

[0055] In one example, the material of the sub-isolation layer closest to the semiconductor substrate 200 is silicon oxide, and the materials of the other sub-isolation layers are all silicon nitride and are all prepared by a plasma enhanced chemical vapor deposition (PECVD) process. For example, a first sub-isolation layer 2011 is first formed on the semiconductor substrate 200 by a PECVD process, and the material of the first sub-isolation layer 2011 is silicon oxide. Then, PECVD is continued to be used on the first sub-isolation layer 2011 to sequentially deposit to form a stacked second sub-isolation layer 2012 and a third sub-isolation layer 2013, and the materials of the second sub-isolation layer 2012 and the third sub-isolation layer 2013 are both silicon nitride.

[0056] The density of silicon nitride can be adjusted by adjusting the deposition parameters when PECVD is used to deposit silicon nitride. For example, when PECVD is used to deposit silicon nitride, other deposition parameters are controlled to remain unchanged, wherein other deposition parameters include but are not limited to deposition temperature, flow rate, and pressure. The density of the grown silicon nitride is controlled by adjusting the power of the plasma. The greater the power of the plasma, the faster the growth rate of silicon nitride, and the lower the density of the grown silicon nitride. The smaller the power of the plasma, the slower the growth rate of silicon nitride, and the higher the density of the grown silicon nitride. Exemplarily, when PECVD is used to deposit and grow silicon nitride, the power of the plasma from top to bottom increases from low to high, thereby obtaining silicon nitride with lower and lower density from top to bottom, and then forming a first isolation layer 201 with an increasingly higher etching rate, i.e., a gradient change, together with the sub-isolation layer closest to the semiconductor substrate, so that after the subsequent etching process, the cross-sectional shape of the bottom of the groove (i.e., the portion of the groove that passes through the first isolation layer) can also be a positive trapezoid.

[0057] It should be noted that in addition to adjusting the power during the PECVD process, other deposition parameters can also be adjusted to control the speed of generated silicon nitride and thus control the density of the grown silicon nitride. The relationship between the density of silicon nitride and the etching speed has been described in the previous article and will not be repeated here. Among them, other deposition parameters include but are not limited to deposition temperature, flow rate, and pressure.

[0058] Next, step S230 is performed to sequentially deposit a gate layer 202 and a second isolation layer 203 on the first isolation layer 201 .

[0059] Continue as Figure 3A As shown, a gate layer 202 is deposited on the first isolation layer 201, and the gate layer 202 can be formed by a conventional deposition process in the art. Exemplarily, the gate layer 202 includes a titanium nitride layer 2021 and a tungsten layer 2022 sequentially deposited on the first isolation layer 201. Next, a second isolation layer 203 is formed on the gate layer 202, and the second isolation layer 203 can be formed by a conventional deposition process in the art. Exemplarily, the material of the second isolation layer 203 includes but is not limited to silicon nitride.

[0060] Next, step S240 is performed, and a groove 210 penetrating the second isolation layer 203, the gate layer 202 and the first isolation layer 201 is formed by using a photolithography and etching process, wherein, among the portions of the groove 210 penetrating the first isolation layer 201, the groove 210 located at the end surface of the first isolation layer 201 away from the semiconductor substrate 200 has the smallest size.

[0061] Exemplarily, a patterned mask layer is formed on the second isolation layer using a photolithography process. Exemplarily, the patterned mask layer can be a patterned photoresist layer. In a specific example, the patterned mask layer is formed on the second isolation layer using a photolithography process, including: firstly spin coating a photoresist layer on the second isolation layer, and then patterning the photoresist layer using a photolithography process to form a patterned photoresist layer as a mask. Then, a dry etching process is performed using the mask layer as a mask to form a patterned photoresist layer as shown in FIG. Figure 3B Groove 210 is shown.

[0062] For example, Figure 3B As shown, in the direction perpendicular to the semiconductor substrate 200, under specific etching conditions, the etching rate of the sub-isolation layer farther away from the semiconductor substrate 200 is smaller, and the etching rate of the sub-isolation layer closer to the semiconductor substrate 200 is larger, that is, in this embodiment, the etching rate of the first sub-isolation layer 2011 is the largest, and the etching rate of the third sub-isolation layer 2013 is the smallest, so that the cross-sectional shape of the portion of the groove 210 formed after etching that passes through the first isolation layer 201 is generally a right trapezoid, and the cross-section is perpendicular to the surface of the semiconductor substrate 200.

[0063] Then, if Figure 3C As shown, a gate oxide layer 204 and a gate oxide protection layer 205 are sequentially deposited on the sidewall and bottom of the trench 210 and the second isolation layer 203. Exemplarily, the gate oxide layer 204 includes silicon dioxide, and the gate oxide protection layer 205 includes amorphous silicon.

[0064] Then, if Figure 3D As shown, photolithography and etching processes are used to etch the gate oxide layer 204 and the gate oxide protection layer 205 at the bottom of the groove 210 to form an opening to expose at least a portion of the semiconductor substrate 200. During this process, the gate oxide protection layer 205 on the second isolation layer 203 is removed, and part of the gate oxide protection layer 205 on the side wall of the groove 210 is also removed. The gate oxide protection layer 205 can protect the gate oxide layer 204 when etching to form the opening, thereby avoiding excessive consumption of the gate oxide layer 204 during etching, resulting in the gate oxide layer 204 being too thin and affecting the performance of the device.

[0065] Then, if Figure 3E As shown, a channel layer 206 is formed on the gate oxide protection layer 205 so that the channel layer 206 covers the above-mentioned opening and the gate oxide layer 204. It is worth mentioning that in other examples, the gate oxide protection layer 205 may not be formed, but etching is performed after the gate oxide layer 204 is deposited to form an opening exposing at least a portion of the semiconductor substrate 200, and then the channel layer 206 is formed. The method of directly etching the gate oxide layer 204 is easy to consume too much of the gate oxide layer 204. Therefore, after the gate oxide layer 204 is formed, the gate oxide protection layer 205 is then formed, and then the gate oxide layer 204 on the groove 210 is etched to protect the gate oxide layer 204, so as to avoid excessive consumption of the gate oxide layer 204, so that the thickness of the gate oxide layer 204 is insufficient and the performance of the semiconductor structure is affected. The gate oxide protection layer 205 and the channel layer 206 are used as a channel together. Optionally, the channel layer 206 and the gate oxide protection layer 205 may be doped amorphous silicon layers, and the specific doping impurity type may be determined according to the type of transistor to be formed. For example, when the transistor is of N-type, the channel layer 206 and the gate oxide protection layer 205 may be amorphous silicon layers doped with P-type doped impurities, such as boron-doped amorphous silicon layers. If the transistor is of P-type, the channel layer 206 and the gate oxide protection layer 205 may be amorphous silicon layers doped with N-type doped impurities, such as phosphorus-doped amorphous silicon layers.

[0066] Then, if Figure 3FAs shown, a first dielectric layer 207 is deposited to fill the groove 210. Exemplarily, the first dielectric layer 207 includes but is not limited to silicon dioxide. Then, the first dielectric layer 207 is back-etched to form an inner groove. Then, a source and drain electrode 208 is deposited on the first dielectric layer 207 after back-etching. The source and drain electrode 208 fills the inner groove. In a specific example, the method for forming the source and drain electrode 208 includes first depositing a source and drain electrode material layer to cover the channel layer on the second isolation layer and fill the inner groove, and planarizing the source and drain electrode material layer, stopping at the channel layer, so as to form the drain electrode 208 in the inner groove. Exemplarily, the material of the source and drain electrode 208 includes but is not limited to silicon or other suitable semiconductor materials. The semiconductor substrate 200 in the corresponding area below the groove 210 can be used as another source and drain of the transistor. The titanium nitride layer 2021 and the tungsten layer 2022 in this embodiment can be used as a gate. The source-drain electrode 208 and the other source-drain electrode may be a doped semiconductor material layer, such as a silicon layer doped with N-type dopant impurities or a silicon layer doped with P-type dopant impurities, which may be determined according to the type of transistor to be formed. For example, when the transistor is of N-type, the source-drain electrode 208 and the other source-drain electrode may be a silicon layer doped with N-type dopant impurities, such as a phosphorus-doped silicon layer. If the transistor is of P-type, the source-drain electrode 208 and the other source-drain electrode may be a silicon layer doped with P-type dopant impurities, such as a boron-doped silicon layer.

[0067] So far, the description of the key steps of the method for preparing the semiconductor structure of the present application has been completed. The method for preparing a complete semiconductor structure may also include other steps, which will not be described one by one here. It is worth mentioning that the order of the above steps can be adjusted without conflict.

[0068] In summary, in the embodiment of the present application, a first isolation layer is formed on a semiconductor substrate, the first isolation layer includes at least two layers of sub-isolation layers stacked together, and in a direction perpendicular to the semiconductor substrate, the etching rates of the sub-isolation layers are different. Due to the different etching rates, the groove size after etching can be minimized at the end surface of the first isolation layer away from the semiconductor substrate, while it is larger than the groove size at other locations. In particular, the size of the portion of the groove closer to the semiconductor substrate relative to the end surface is increased, so that the inverted trapezoidal structure is optimized, which is more conducive to the deposition of the channel layer. Therefore, the thickness of the channel layer at the "bottleneck" position at the bottom of the groove in the prior art is increased, thereby reducing the resistance and avoiding or reducing the occurrence of a conductive bottleneck. In addition, in the embodiment of the present application, the bottom of the groove can be expanded laterally according to the different etching rates of the sub-isolation layers. The bottom of the groove after the lateral expansion can make the bottom of the channel closer to the electric field, thereby improving the control ability of the surrounding gate over the channel, thereby increasing the saturation current of the transistor and improving its performance.

[0069] Embodiment 2

[0070] The present application also provides a semiconductor structure, which can be prepared by the method for preparing the semiconductor structure in the above-mentioned embodiment 1. Some details of this embodiment can be referred to the relevant description of the method in the above text, and will not be repeated here.

[0071] Specifically, Figure 3F As shown, the semiconductor structure includes: a semiconductor substrate 200, a first isolation layer 201, a gate layer 202, a second isolation layer 203 stacked in sequence on the semiconductor substrate 200, and a groove 210 penetrating the second isolation layer 203, the gate layer 202 and the first isolation layer 201. Among the parts of the groove 210 penetrating the first isolation layer 201, the groove size located at the end surface of the first isolation layer 201 away from the semiconductor substrate 200 is the smallest.

[0072] For example, Figure 3F As shown, the first isolation layer 201 includes at least two sub-isolation layers stacked on the semiconductor substrate 200 , the gate layer 202 is disposed on the first isolation layer 201 , and the second isolation layer 203 is disposed on the gate layer.

[0073] For example, continue as Figure 3F As shown, the semiconductor structure also includes a gate oxide layer 204 located on the upper surface of the second isolation layer 203 and the sidewalls of the trench 210, a gate oxide protection layer 205 located on the gate oxide layer 204 and covering the sidewalls of the trench 210, and a channel layer 206 located on the gate oxide protection layer 205 and covering a portion of the semiconductor substrate 200 exposed by the trench 210, wherein the channel layer 206 covers the bottom of the trench. At the same time, the remaining space of the trench 210 is also filled with a first dielectric layer 207 and a source and drain 208 in sequence, the first dielectric layer 207 covers the channel layer 206 at the bottom of the trench 210 and a portion of the channel layer 206 on the sidewalls of the trench, the gate protection layer 205 and the channel layer 206 are used together as a channel, and the source and drain 208 cover the first dielectric layer 207.

[0074] The semiconductor structure of the present invention has been introduced so far. The complete semiconductor structure may also include other components, which will not be described one by one here. Since the semiconductor structure of the present application is prepared by the above-mentioned preparation method, it has the same advantages as the above-mentioned method.

[0075] Although example embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above example embodiments are merely exemplary and are not intended to limit the scope of the present application to this. Those of ordinary skill in the art may make various changes and modifications therein without departing from the scope and spirit of the present application. All these changes and modifications are intended to be included within the scope of the present application as required by the appended claims.

[0076] Similarly, it should be understood that in order to streamline the present application and help understand one or more of the various application aspects, in the description of the exemplary embodiments of the present application, the various features of the present application are sometimes grouped together into a single embodiment, figure, or description thereof. However, the method of the present application should not be interpreted as reflecting the following intention: the claimed application requires more features than the features clearly stated in each claim. More specifically, as reflected in the corresponding claims, the application point is that the corresponding technical problem can be solved with less than all the features of a single disclosed embodiment. Therefore, the claims following the specific embodiment are hereby explicitly incorporated into the specific embodiment, wherein each claim itself serves as a separate embodiment of the present application.

[0077] In addition, those skilled in the art will appreciate that, although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present application and form different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.

[0078] It should be noted that the above embodiments illustrate rather than limit the present application, and that those skilled in the art may devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbol between brackets should not be construed as a limitation to the claims. The use of the words first, second, and third, etc. does not indicate any order. These words may be interpreted as names.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The preparation method comprises: providing a semiconductor substrate; Forming a first isolation layer on the semiconductor substrate, wherein the first isolation layer comprises at least two sub-isolation layers sequentially stacked on the semiconductor substrate; wherein, in a direction perpendicular to the semiconductor substrate, under specific etching conditions, an etching rate of the sub-isolation layer farthest from the semiconductor substrate is lower than an etching rate of other sub-isolation layers; Depositing a gate layer and a second isolation layer in sequence on the first isolation layer; A groove penetrating the second isolation layer, the gate layer and the first isolation layer is formed by photolithography and etching processes, wherein, among the portions of the groove penetrating the first isolation layer, the groove size at the end surface of the first isolation layer away from the semiconductor substrate is the smallest.

2. The preparation method according to claim 1, characterized in that In a direction perpendicular to the semiconductor substrate, under specific etching conditions, the farther the sub-isolation layer is from the semiconductor substrate, the smaller the etching rate is, and the closer the sub-isolation layer is to the semiconductor substrate, the larger the etching rate is. The cross-sectional shape of the portion of the formed groove that passes through the first isolation layer is a right trapezoid, and the cross-section is perpendicular to the surface of the semiconductor substrate.

3. The preparation method according to claim 1, characterized in that: The material of the sub-isolation layer farthest from the semiconductor substrate is silicon nitride, and the material of at least one of the other sub-isolation layers is boron-doped silicon nitride.

4. The preparation method according to claim 1, characterized in that: The material of the sub-isolation layer farthest from the semiconductor substrate is silicon nitride, and the material of at least one of the other sub-isolation layers is silicon nitride doped with at least one of carbon and oxygen.

5. The preparation method according to claim 3, characterized in that: The first isolation layer includes a first sub-isolation layer, a second sub-isolation layer and a third sub-isolation layer stacked in sequence on the semiconductor substrate, wherein the first sub-isolation layer and the second sub-isolation layer are both made of boron-doped silicon nitride, the third sub-isolation layer is made of silicon nitride, and the boron doping concentration in the first sub-isolation layer is greater than the boron doping concentration in the second sub-isolation layer.

6. The preparation method according to claim 1, characterized in that: The material of the sub-isolation layer closest to the semiconductor substrate is silicon oxide, and the material of at least one of the other sub-isolation layers is silicon nitride.

7. The preparation method according to claim 6, characterized in that: The materials of the other sub-isolation layers are all silicon nitride and the density of the silicon nitride in each sub-isolation layer is different, wherein the density of the silicon nitride in the sub-isolation layer farthest from the semiconductor substrate is the highest.

8. The preparation method according to claim 7, characterized in that: The materials of the other sub-isolation layers are all silicon nitride and are all prepared by plasma enhanced chemical vapor deposition process. When other deposition parameters are kept unchanged, the density of the grown silicon nitride is controlled by adjusting the power of the plasma during the process. The greater the plasma power, the lower the density of the grown silicon nitride, and the smaller the plasma power, the higher the density of the grown silicon nitride.

9. The preparation method according to claim 6, characterized in that: The material of the other sub-isolation layers is silicon nitride, and the density of the silicon nitride in the sub-isolation layer that is farther away from the semiconductor substrate is higher, and the density of the silicon nitride in the sub-isolation layer that is closer to the semiconductor substrate is lower.

10. A semiconductor structure, characterized in that: Prepared by the preparation method according to any one of claims 1 to 9, the semiconductor structure comprises: Semiconductor substrate; A first isolation layer, disposed on the semiconductor substrate, wherein the first isolation layer comprises at least two sub-isolation layers stacked on the semiconductor substrate; A gate layer, disposed on the first isolation layer; A second isolation layer, disposed on the gate layer; A groove penetrates the second isolation layer, the gate layer and the first isolation layer, wherein, in a portion of the groove penetrating the first isolation layer, a groove size located at an end surface of the first isolation layer away from the semiconductor substrate is the smallest.

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