Semiconductor device and forming method

Abstract

Semiconductor devices and methods of forming are provided. The semiconductor device includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, a source electrode, a drain electrode, and a conductive portion. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The source electrode and the drain electrode are respectively arranged on the barrier layer and are respectively arranged on opposite sides of the gate electrode. The conductive portion is disposed on the compound semiconductor layer and between the gate electrode and the drain electrode. Wherein the conductive part is in ohmic contact with the compound semiconductor layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for forming the same, and more particularly to a semiconductor device including a conductive portion and a method for forming the same. Background Art

[0002] Since GaN materials have a wide band-gap and a strong polarization effect, GaN materials are widely used. For example, GaN-based semiconductors are currently widely used in power devices, such as high electron mobility transistors (HEMTs) including heterojunction structures.

[0003] However, in high electron mobility transistors, there may be excessive concentration of electric field distribution, resulting in uneven electric field distribution, insufficient on-current, degradation of dynamic resistance characteristics, insufficient reliability, etc. Therefore, although existing semiconductor devices and their formation methods have gradually met their intended uses, they still do not fully meet the requirements in all aspects. Therefore, there are still some problems to be overcome regarding semiconductor devices and their formation methods. Summary of the invention

[0004] The present invention includes a gate electrode and a conductive portion on a compound semiconductor layer, wherein the gate electrode and the compound semiconductor layer are in Schottky contact, and the conductive portion and the compound semiconductor layer are in ohmic contact. Accordingly, holes provided to the compound semiconductor layer by the ohmic contact can be used to neutralize the trapped electrons in the dielectric layer (e.g., the first dielectric layer 700 or the second dielectric layer 720) or the channel layer (e.g., the channel layer 300), thereby adjusting the electric field distribution of the semiconductor device. For example, when viewed from a top view, the conductive portion of the present invention can be located between the gate electrode and the drain electrode, so that the holes provided by the conductive portion can be neutralized with the trapped electrons, and the trapped electrons are prevented from existing between the gate electrode and the drain electrode to affect the electric field distribution. Thus, the conductive portion can reduce the excessive concentration of the electric field distribution and make the electric field distribution more uniform, increase the on-current, improve the dynamic resistance characteristics and / or improve the reliability.

[0005] In some embodiments, a semiconductor device is provided. The semiconductor device includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, a source electrode, a drain electrode, and a conductive portion. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The source electrode and the drain electrode are respectively disposed on the barrier layer and are respectively disposed on opposite sides of the gate electrode. The conductive portion is disposed on the compound semiconductor layer and is disposed between the gate electrode and the drain electrode. The conductive portion is in ohmic contact with the compound semiconductor layer.

[0006] In some embodiments, a method for forming a semiconductor device is provided. The method for forming a semiconductor device includes providing a substrate. Forming a channel layer on the substrate. Forming a barrier layer on the channel layer. Forming a compound semiconductor layer on the barrier layer. Forming a source electrode and a drain electrode on the barrier layer. Forming a conductive portion on the compound semiconductor layer. Forming a gate electrode on the compound semiconductor layer, and the gate electrode is disposed between the source electrode and the drain electrode. The conductive portion is disposed between the gate electrode and the drain electrode, and the conductive portion is in ohmic contact with the compound semiconductor layer.

[0007] The semiconductor device and the method for forming the same of the present invention can be applied to various types of electronic devices and the methods for forming the same. To make the components and advantages of the present invention more clearly understood, various embodiments are given below and described in detail with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] When read together with the drawings, the invention can be more fully understood from the following detailed description. It is worth noting that, in accordance with standard practice in the industry, the components are not drawn to scale. In fact, the size of each component can be arbitrarily enlarged or reduced for clarity.

[0009] Figures 1 to 4 The figures are cross-sectional schematic diagrams of different stages of a method for forming a semiconductor device according to an embodiment of the present invention.

[0010] Figure 5 FIG. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

[0011] Figure 6 is a schematic top view of a semiconductor device according to an embodiment of the present invention.

[0012] Figure 7 FIG. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

[0013] Figure 8 is a schematic top view of a semiconductor device according to an embodiment of the present invention.

[0014] Fig. 9 FIG. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

[0015] Fig.10 is a schematic top view of a semiconductor device according to an embodiment of the present invention.

[0016] Fig.11 FIG. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

[0017] Fig.12 is a schematic top view of a semiconductor device according to an embodiment of the present invention.

[0018] Fig.13 FIG. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

[0019] Reference numerals:

[0020] 1,2,3,4,5:Semiconductor devices

[0021] 100:Substrate

[0022] 200: Buffer layer

[0023] 300: Channel layer

[0024] 310: Two-dimensional electron gas

[0025] 400: Barrier layer

[0026] 410: Compound semiconductor layer

[0027] 411: Part 1

[0028] 412: Part 2

[0029] 413: Part 3

[0030] 500: Conductive part

[0031] 501: first conductive part

[0032] 502: second conductive portion

[0033] 520: Source electrode

[0034] 540: Drain electrode

[0035] 600: Gate electrode

[0036] 700: first dielectric layer

[0037] 720: Second dielectric layer

[0038] 722: first connecting member

[0039] 724: Second connecting piece

[0040] 740: Source field plate

[0041] 760: Drain field plate

[0042] A-A': Section

[0043] D1: First direction

[0044] D2: Second direction

[0045] D3: Third direction

[0046] G,G1,G1',G2,G2': Gap

[0047] W1: First width

[0048] W2: Second width

[0049] W21,W22: Width DETAILED DESCRIPTION

[0050] The following is a detailed description of the semiconductor device of each embodiment of the present invention. It should be understood that the following description provides many different embodiments for implementing different aspects of some embodiments of the present invention. The specific elements and arrangements described below are only for simple and clear description of some embodiments of the present invention. Of course, these are only used as examples and are not limitations of the present invention. In addition, similar and / or corresponding element symbols may be used in different embodiments to indicate similar and / or corresponding elements to clearly describe the present invention. However, the use of these similar and / or corresponding element symbols is only for the simple and clear description of some embodiments of the present invention, and does not represent any correlation between the different embodiments and / or structures discussed.

[0051] It should be understood that relative terms may be used in various embodiments, such as "lower" or "bottom" or "upper" or "top" to describe the relative relationship of one element of the diagram to another element. It is understood that if the device of the diagram is turned upside down, the element described on the "lower" side will become the element on the "upper" side. The embodiments of the present invention can be understood in conjunction with the drawings, and the drawings of the present invention are also considered to be part of the disclosure.

[0052] Furthermore, when a first material layer is said to be located on or over a second material layer, it may include a situation where the first material layer is in direct contact with the second material layer, or the first material layer and the second material layer may not be in direct contact, that is, there may be one or more other material layers between the first material layer and the second material layer. However, if the first material layer is directly located on the second material layer, it means that the first material layer and the second material layer are in direct contact.

[0053] In addition, it should be understood that the ordinal numbers used in the specification and claims, such as "first", "second", etc., to modify the elements, are not intended to imply any previous ordinal numbers of the element (or elements), nor do they represent the order of one element and another element, or the order of the manufacturing method. The use of these ordinal numbers is only used to make a component with a certain name clearly distinguishable from another component with the same name. The same words may not be used in the claims and the specification. For example, the first element in the specification may be the second element in the claims.

[0054] In some embodiments of the present invention, terms related to bonding and connection, such as "connect", "interconnect", "bond", etc., unless otherwise defined, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, wherein other structures are disposed between the two structures. Such terms related to connection and bonding may also include situations where both structures are movable, or both structures are fixed. In addition, the terms "electrically connected" or "electrically coupled" include any direct and indirect electrical connection means.

[0055] In the text, the terms "approximate", "about", and "substantially" usually mean within 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. The quantity given here is an approximate quantity, that is, in the absence of specific instructions for "about", "approximately", or "substantially", the meaning of "about", "approximately", or "substantially" can still be implied. The term "range is between a first value and a second value" or "first value to second value" means that the range includes the first value, the second value, and other values ​​therebetween. Furthermore, there may be a certain error between any two values ​​or directions used for comparison. If the first value is equal to the second value, it implies that there may be an error of about 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% between the first value and the second value.

[0056] Certain words are used throughout the specification and claims of the present invention to refer to specific components. It should be understood by those skilled in the art that electronic equipment manufacturers may refer to the same components by different names. It is not intended to distinguish between components that have the same function but different names. In the following specification and claims, words such as "comprise", "contain", "have" are open-ended words, so they should be interpreted as "including but not limited to...". Therefore, when the terms "comprise", "contain" and / or "have" are used in the description of the present invention, they specify the existence of corresponding parts, areas, steps, operations and / or elements, but do not exclude the existence of one or more corresponding parts, areas, steps, operations and / or elements.

[0057] It should be understood that the following embodiments may replace, reorganize, or combine components in different embodiments to complete other embodiments without departing from the spirit of the present invention. Components between embodiments may be used in any combination as long as they do not violate the spirit of the invention or conflict with each other.

[0058] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as commonly understood by those skilled in the art. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present invention, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present invention.

[0059] In the present invention, each direction is not limited to three axes of a rectangular coordinate system such as the X-axis, the Y-axis, and the Z-axis, and can be interpreted in a broader sense. For example, the X-axis, the Y-axis, and the Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other, but are not limited thereto. For ease of explanation, in the following, the X-axis direction is the first direction D1 (width direction), the Y-axis direction is the second direction D2 (length direction), and the Z-axis direction is the third direction D3 (thickness direction). In some embodiments, the top view schematic diagram described herein is a schematic diagram for observing the XY plane (the plane formed by the first direction D1 and the second direction D2), and the cross-sectional schematic diagram described herein is a schematic diagram for observing the XZ plane (the plane formed by the first direction D1 and the third direction D3).

[0060] In the following, the current-to-voltage characteristic curve (I-V curve) of the "Schottky contact" presents a nonlinear relationship, and is unidirectionally conductive with rectification characteristics; while the current-to-voltage characteristic curve of the "ohmic contact" presents a linear relationship, and is bidirectionally conductive without rectification characteristics. For the same element, the barrier height of a material that is in Schottky contact with the element is greater than the barrier height of another material that is in ohmic contact with the element.

[0061] Reference Figure 1 , which is a cross-sectional schematic diagram of different stages of a method for forming a semiconductor device 1 according to an embodiment of the present invention. Figure 1 As shown, in some embodiments, a substrate 100 may be provided. In some embodiments, the substrate 100 may include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like. A semiconductor-on-insulator substrate includes a semiconductor layer formed on an insulator. For example, the insulating layer may include silicon oxide, silicon nitride, polysilicon, or a combination thereof, and the semiconductor substrate may include silicon, aluminum nitride (AlN), or the like. The substrate 100 may be an undoped or doped substrate, such as a substrate doped with p-type or n-type dopants. In some embodiments, the substrate 100 may include a multi-layered substrate or a gradient substrate. In some embodiments, the substrate 100 may include a semiconductor substrate or a ceramic substrate, such as a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, an aluminum nitride substrate, or a sapphire substrate. In some embodiments, the substrate 100 may be a silicon substrate.

[0062] like Figure 1As shown, in some embodiments, a buffer layer 200 may be formed on the substrate 100 to enhance the compatibility between the substrate 100 and other elements disposed on the substrate 100, such as reducing the difference in thermal expansion coefficient and / or reducing the difference in lattice constant. In some embodiments, the buffer layer 200 may include a III-V compound semiconductor material, such as a III-V nitride. For example, the buffer layer 200 may include gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), the like, or a combination thereof, but the present invention is not limited thereto. In some embodiments, the buffer layer 200 may be formed by a deposition process. For example, the deposition process may be chemical vapor deposition (CVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), the like, or a combination thereof, but the present invention is not limited thereto.

[0063] In some embodiments, a nucleation layer may be further disposed between the substrate 100 and the buffer layer 200 to reduce the lattice difference between the substrate 100 and other layers disposed on the substrate 100, thereby improving the epitaxial quality and reliability. In some embodiments, the nucleation layer may include aluminum nitride (AlN), aluminum gallium nitride (AlGaN), the like, or a combination thereof, but the present invention is not limited thereto. In some embodiments, the nucleation layer may be formed by a deposition process. In other embodiments, the buffer layer 200 may be omitted.

[0064] like Figure 1 As shown, in some embodiments, a channel layer 300 may be formed on the substrate 100. Specifically, the channel layer 300 may be formed on the buffer layer 200. In some embodiments, the channel layer 300 may include a III-V compound semiconductor material, such as a III-V nitride, but the present invention is not limited thereto. For example, the channel layer 300 may include gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum gallium nitride (InAlGaN), the like or a combination thereof, but the present invention is not limited thereto. In some embodiments, the channel layer 300 may be gallium nitride. In some embodiments, the channel layer 300 may be formed by a deposition process.

[0065] like Figure 1As shown, in some embodiments, a barrier layer 400 may be formed on the channel layer 300. In some embodiments, the barrier layer 400 may include a III-V compound semiconductor material, such as a III-V nitride, but the present invention is not limited thereto. For example, the barrier layer may include aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium aluminum gallium nitride (InAlGaN), the like, or a combination thereof, but the present invention is not limited thereto. In some embodiments, the barrier layer 400 may be aluminum gallium nitride. In some embodiments, the barrier layer 400 may be formed by a deposition process. Due to the presence of a heterogeneous interface between the channel layer 300 and the barrier layer 400, and the difference in lattice constant between the channel layer 300 and the barrier layer 400, a two-dimensional electron gas (2DEG) 310 may be formed near the top surface of the channel layer 300 and serve as a current path.

[0066] Reference Figure 2 , which is a cross-sectional schematic diagram of different stages of a method for forming a semiconductor device 1 according to an embodiment of the present invention. Figure 2 As shown, in some embodiments, a compound semiconductor layer 410 may be formed on the barrier layer 400, so that the compound semiconductor layer 410 may be disposed between the barrier layer 400 and a gate electrode formed subsequently. In some embodiments, the compound semiconductor layer 410 may be formed by a deposition process. In some embodiments, the compound semiconductor layer 410 may be a semiconductor material doped with a p-type dopant. In some embodiments, the compound semiconductor layer 410 may include p-doped gallium nitride (p-GaN). Accordingly, since the compound semiconductor layer 410 may suppress the formation of the two-dimensional electron gas 310 at a position corresponding to the compound semiconductor layer 410 (for example, located below the compound semiconductor layer 410), the two-dimensional electron gas 310 is depleted. Therefore, providing the compound semiconductor layer 410 may make the semiconductor device 1 normally-off.

[0067] Reference Figure 3 , which is a cross-sectional schematic diagram of different stages of a method for forming a semiconductor device 1 according to an embodiment of the present invention. Figure 3As shown, in some embodiments, a source electrode 520 and a drain electrode 540 may be formed on the barrier layer 400. In some embodiments, the source electrode 520 and the drain electrode 540 may be in contact with the barrier layer 400, respectively. In some embodiments, the source electrode 520 and the drain electrode 540 may include a conductive material. In some embodiments, the conductive material may include a metal, a metal nitride, a semiconductor material, the like, or a combination thereof, but the present invention is not limited thereto. In some embodiments, the metal may include gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), titanium nitride (TiN), the like, or a combination thereof, but the present invention is not limited thereto. In some embodiments, the semiconductor material may include polycrystalline silicon or polycrystalline germanium. In some embodiments, the conductive material may be formed by chemical vapor deposition, sputtering, resistance heating evaporation, electron beam evaporation, the like, or a combination thereof, but the present invention is not limited thereto. In some embodiments, the source electrode 520 and the drain electrode 540 may form ohmic contacts with the barrier layer 400 .

[0068] like Figure 3 As shown, in some embodiments, a conductive portion 500 may be formed on the compound semiconductor layer 410. In some embodiments, the material and formation method of the conductive portion 500 may be the same as or different from the material and formation method of the source electrode 520. In some embodiments, the conductive portion 500 may be formed in the same process as the source electrode 520 and the drain electrode 540, or the conductive portion 500 may be formed in a different process from the source electrode 520 and the drain electrode 540. In some embodiments, the conductive portion 500 may be the same electrode as the gate electrode formed subsequently, or the conductive portion 500 may be independent of the gate electrode formed subsequently.

[0069] Reference Figure 4 , which is a cross-sectional schematic diagram of a semiconductor device 1 according to an embodiment of the present invention. Figure 4 As shown, in some embodiments, a gate electrode 600 may be formed on the compound semiconductor layer 410. In some embodiments, the gate electrode 600 is formed after the source electrode 520 and the drain electrode 540 are formed (which may be a gate-last process). In this embodiment, the source electrode 520 and the drain electrode 540 may contact the top surface of the barrier layer 400. In other embodiments, the gate electrode 600 is formed before the source electrode 520 and the drain electrode 540 are formed (which may be a gate-first process). In this embodiment, the source electrode 520 and the drain electrode 540 may penetrate the barrier layer 400 and contact the channel layer 300.

[0070] In some embodiments, the material and formation method of the gate electrode 600 may be the same as or different from the material and formation method of the source electrode 520. In some embodiments, the source electrode 520 and the drain electrode 540 may be disposed on opposite sides of the gate electrode 600, respectively. In some embodiments, the gate electrode 600 may be disposed between the source electrode 520 and the drain electrode 540. In some embodiments, the conductive portion 500 may be disposed between the gate electrode 600 and the drain electrode 540.

[0071] In some embodiments, the conductive portion 500 may be in ohmic contact with the compound semiconductor layer 410, and the gate electrode 600 may be in Schottky contact with the compound semiconductor layer 410. In other words, two portions (e.g., the conductive portion 500 and the gate electrode 600) located on the compound semiconductor layer 410 may be in ohmic contact and Schottky contact with the compound semiconductor layer 410, respectively. That is, both ohmic contact and Schottky contact may be included in the semiconductor device 1.

[0072] In some embodiments, the conductive portion 500 may include a multilayer structure. In some embodiments, the multilayer structure of the conductive portion 500 may include a bottom conductive portion (not shown) and a top conductive portion (not shown). In some embodiments, the bottom conductive portion may be disposed on the compound semiconductor layer 410, and the top conductive portion may be disposed on the bottom conductive portion. In some embodiments, the gate electrode 600 may include a multilayer structure. In some embodiments, the multilayer structure of the gate electrode 600 may include a bottom gate electrode (not shown) and a top gate electrode (not shown). In some embodiments, the bottom gate electrode may be disposed on the compound semiconductor layer 410, and the top gate electrode may be disposed on the bottom gate electrode. For example, the compound semiconductor layer 410 may be p-GaN, the bottom conductive portion of the conductive portion 500 may be Ti, the top conductive portion of the conductive portion 500 may be Al or Au, the bottom gate electrode of the gate electrode 600 may be TiN, and the top gate electrode of the gate electrode 600 may be Ni or Au, but the present invention is not limited thereto.

[0073] Generally speaking, at the electric field concentration, hot carriers may undergo impactionization, thereby generating electron-hole pairs. The electron-hole pairs will move to the layers in the semiconductor device or at the interfaces of the layers, and then be captured as trapped charges, thereby reducing the on-current, reducing the dynamic resistance characteristics, and reducing the reliability. However, since the present invention may include a dual-gate or hybrid gate structure, and the dual-gate or hybrid gate structure includes both a gate electrode 600 that is a Schottky contact and a conductive portion 500 that is an ohmic contact, the conductive portion 500 that is an ohmic contact may be equivalent to or similar to a gate-injection transistor (GIT), thereby providing holes. Accordingly, since the holes provided by the conductive portion 500 can neutralize the trapped charges, the electric field distribution can be made more uniform, the on-current can be increased, the dynamic resistance characteristics can be increased, and / or the reliability can be increased. For example, the conductive portion 500 may be between the gate electrode 600 and the drain electrode 540 , thereby making the electric field distribution between the gate electrode 600 and the drain electrode 540 more uniform.

[0074] In some embodiments, in the first direction D1, the gate electrode 600 has a first width W1, the conductive portion 500 has a second width W2, and the ratio of the first width W1 to the second width W2 (first width W1 / second width W2) may be less than or equal to 10 and may be greater than or equal to 0.3. For example, the ratio of the first width W1 to the second width W2 may be 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0.9, 0.8, 0.7, 0.6, 0.5, 0.4, 0.3 or any value between the aforementioned values ​​or a range of values ​​composed of any values, but the present invention is not limited thereto. Accordingly, the ratio of the Schottky contact to the ohmic contact in the dual gate structure can be adjusted by adjusting the first width W1 and the second width W2. When the ratio of the first width W1 to the second width W2 is greater than 10, the ratio of the ohmic contact is too low, and it is impossible to effectively provide holes, resulting in difficulty in neutralizing the trapped charges. When the ratio of the first width W1 to the second width W2 is less than 0.3, the ratio of the ohmic contact is too high, resulting in excessive leakage current and excessive power loss in the semiconductor device.

[0075] Reference Figure 5 , which is a cross-sectional schematic diagram of a semiconductor device 1 according to an embodiment of the present invention. Figure 5As shown, in some embodiments, a first dielectric layer 700 may be formed on the barrier layer 400. In some embodiments, the first dielectric layer 700 may be between the source electrode 520 and the gate electrode 600, and between the conductive portion 500 and the drain electrode 540. In some embodiments, the first dielectric layer 700 may serve as a passivation layer or a planarization layer. In some embodiments, the first dielectric layer 700 may include an oxide such as silicon oxide, a nitride such as silicon nitride, an oxynitride such as silicon oxynitride, the like, or a combination thereof, but the present invention is not limited thereto.

[0076] In some embodiments, a second dielectric layer 720 may be formed on the first dielectric layer 700, the conductive portion 500, the source electrode 520, the drain electrode 540, and the gate electrode 600. In some embodiments, the material and formation method of the second dielectric layer 720 may be the same as or different from that of the first dielectric layer 700. In some embodiments, the second dielectric layer 720 may serve as an interlayer dielectric layer. In some embodiments, a first connector 722 and a second connector 724 may be formed in the second dielectric layer 720. In some embodiments, the first connector 722 and the second connector 724 may be formed to penetrate the second dielectric layer 720. In some embodiments, the first connector 722 and the second connector 724 may include a conductive material. In some embodiments, the first connector 722 may be used to electrically connect the source electrode 520 and a subsequently formed source field plate, and the second connector 724 may be used to electrically connect the drain electrode 540 and a subsequently formed drain field plate.

[0077] In some embodiments, a source field plate 740 and a drain field plate 760 may be formed on the second dielectric layer 720 to obtain the semiconductor device 1. In some embodiments, the source field plate 740 and the drain field plate 760 may be used to adjust the electric field distribution. In some embodiments, the source field plate 740 and the drain field plate 760 may include a conductive material. In some embodiments, the projection of the source electrode 520 on the substrate 100 may be located within the projection of the source field plate 740 on the substrate 100.

[0078] In some embodiments, the projection of the gate electrode 600 on the substrate 100 may be located within the projection of the source field plate 740 on the substrate 100. Accordingly, the source field plate 740 may uniformly distribute the electric field adjacent to the source electrode 520 and the gate electrode 600. In some embodiments, the projection of the drain electrode 540 on the substrate 100 may be located within the projection of the drain field plate 760 on the substrate 100. Accordingly, the drain field plate 760 may uniformly distribute the electric field adjacent to the drain electrode 540.

[0079] In some embodiments, Figure 5As shown, the conductive portion 500 is in direct contact with the gate electrode 600, so that the conductive portion 500 is electrically connected to the gate electrode 600. In some embodiments, since the conductive portion 500 is in direct contact with the gate electrode 600, the voltage applied to the conductive portion 500 and the gate electrode 600 can be controlled together, so that the potentials applied to the conductive portion 500 and the gate electrode 600 are equal. For example, when the conductive portion 500 and the gate electrode 600 are controlled together, when the semiconductor device 1 is in an on-state, a first voltage (e.g., a gate voltage) can be applied to the gate electrode 600, and the first voltage will be applied to the conductive portion 500 together to turn on the semiconductor device 1 and cause the conductive portion 500 to provide holes.

[0080] Reference Figure 6 , which is a schematic top view of a semiconductor device 1 according to an embodiment of the present invention. Figure 6 The section A-A' of Figure 5 For the sake of explanation, Figure 6 The conductive portion 500, the source electrode 520, the drain electrode 540, the gate electrode 600 and the first dielectric layer 700 are shown, and other elements are omitted. In some embodiments, the gate electrode 600, the source electrode 520 and the drain electrode 540 may extend along the second direction D2, and the conductive portion 500 may extend along the second direction D2. In some embodiments, in the first direction D1, the conductive portion 500 may be between the gate electrode 600 and the drain electrode 540, and the conductive portion 500 may directly contact the gate electrode 600. In some embodiments, in the first direction D1, the conductive portion 500 may be closer to the gate electrode 600 than the drain electrode 540. Accordingly, the conductive portion 500 may provide holes near the gate electrode 600 to neutralize the charges.

[0081] Hereinafter, the same or similar element numbers and descriptions may be omitted.

[0082] Reference Figure 7 and Figure 8 , which is a cross-sectional schematic diagram and a top view schematic diagram of a semiconductor device 2 according to an embodiment of the present invention. Figure 8 The section A-A' of Figure 7In some embodiments, the conductive portion 500 and the gate electrode 600 may be spaced apart by a distance. In some embodiments, a gap G may be provided between the conductive portion 500 and the gate electrode 600 to separate the conductive portion 500 and the gate electrode 600 through the gap G. In some embodiments, air, the material of the first dielectric layer 700, or other dielectric materials may be filled into the gap G. Accordingly, since the conductive portion 500 and the gate electrode 600 are separated from each other, even if the conductive portion 500 and the gate electrode 600 are both disposed on the compound semiconductor layer 410, the voltage applied to the conductive portion 500 and the gate electrode 600 can still be independently controlled or jointly controlled.

[0083] For example, when the conductive portion 500 and the gate electrode 600 are independently controlled, when the semiconductor device 2 is in an off-state, a second voltage (e.g., an additional voltage) different from the first voltage may be applied to the conductive portion 500 to enable the conductive portion 500 to provide holes. When the semiconductor device 2 is in an on-state, a first voltage may be applied to the gate electrode 600 and a second voltage may be applied to the conductive portion 500 to enable the semiconductor device 2 to be turned on and enable the conductive portion 500 to provide holes.

[0084] Reference Fig. 9 and Fig.10 , which is a cross-sectional schematic diagram and a top view schematic diagram of a semiconductor device 3 according to an embodiment of the present invention. Fig.10 The section A-A' of Fig. 9 In some embodiments, the conductive portion 500 may include a first conductive portion 501 and a second conductive portion 502. In some embodiments, the first conductive portion 501 may be disposed on the compound semiconductor layer 410 and between the gate electrode 600 and the drain electrode 540. In some embodiments, the second conductive portion 502 may be disposed on the compound semiconductor layer 410 and between the gate electrode 600 and the source electrode 520. Accordingly, the first conductive portion 501 may make the electric field distribution between the gate electrode 600 and the drain electrode 540 more uniform, and the second conductive portion 502 may make the electric field distribution between the gate electrode 600 and the source electrode 520 more uniform.

[0085] In some embodiments, the first conductive portion 501 may be in direct contact with the gate electrode 600, and the second conductive portion 502 may be in direct contact with the gate electrode 600. In some embodiments, in the first direction D1, the first conductive portion 501 may have a width W21, the second conductive portion 502 may have a width W22, and the sum of the width W21 and the width W22 is the second width W2. In some embodiments, the ratio of the first width W1 and the sum of the width W21 and the width W22 (first width W1 / (sum of the width W21 and the width W22)) may be less than or equal to 10 and may be greater than or equal to 0.3.

[0086] Reference Fig.11 and Fig.12 , which is a cross-sectional schematic diagram and a top view schematic diagram of a semiconductor device 4 according to an embodiment of the present invention. Fig.12 The section A-A' of Fig.11 In some embodiments, the first conductive portion 501 may be spaced apart from the gate electrode 600 by a distance, and the second conductive portion 502 may be spaced apart from the gate electrode 600 by a distance. In some embodiments, a gap G1 may be provided between the first conductive portion 501 and the gate electrode 600, and a gap G2 may be provided between the second conductive portion 502 and the gate electrode 600, so that the first conductive portion 501, the second conductive portion 502, and the gate electrode 600 are separated by the gaps G1 and G2. In some embodiments, air, the material of the first dielectric layer 700, or other dielectric materials may be filled into the gaps G1 and G2. Accordingly, since the first conductive portion 501, the second conductive portion 502, and the gate electrode 600 are separated from each other, the voltages applied to the first conductive portion 501, the second conductive portion 502, and the gate electrode 600 may be independently controlled or jointly controlled.

[0087] In other embodiments, when forming Fig.11 After the first conductive portion 501 and the second conductive portion 502 are formed, and before the gate electrode 600 is formed between the first conductive portion 501 and the second conductive portion 502, an isolation layer (not shown) may be blanket formed on the sidewalls of the first conductive portion 501, the top surface of the compound semiconductor layer 410, and the sidewalls of the second conductive portion 502. Then, the gate electrode 600 is formed on the isolation layer and between the first conductive portion 501 and the second conductive portion 502. In this embodiment, the isolation layer may include a dielectric material. Accordingly, the voltages applied to the first conductive portion 501, the second conductive portion 502, and the gate electrode 600 may be independently controlled or jointly controlled, and the possibility of generating leakage current may be further reduced.

[0088] Reference Fig.13, which is a schematic cross-sectional view of a semiconductor device 5 according to an embodiment of the present invention. In some embodiments, the compound semiconductor layer 410 may include a first portion 411, a second portion 412, and a third portion 413. In some embodiments, the first portion 411 may be disposed between the barrier layer 400 and the gate electrode 600, the second portion 412 may be disposed between the barrier layer 400 and the first conductive portion 501, and the third portion 413 may be disposed between the barrier layer 400 and the second conductive portion 502. In some embodiments, in the first direction D1, the first portion 411 is spaced apart from the second portion 412 by a distance, and the second portion 412 is spaced apart from the third portion 413 by a distance. In some embodiments, the first portion 411, the second portion 412, and the third portion 413 may be separated from each other. Accordingly, the concentration and distribution of the two-dimensional electron gas 310 in the channel layer 300 may be adjusted by adjusting the distances between the first portion 411, the second portion 412, and the third portion 413.

[0089] In some embodiments, there may be a gap G1' between the first portion 411 and the second portion 412, and there may be a gap G2' between the first portion 411 and the third portion 413, so that the first portion 411, the second portion 412 and the third portion 413 are separated by the gaps G1' and G2'. In some embodiments, air, the material of the first dielectric layer 700 or other dielectric materials may be filled into the gaps G1' and G2'. Accordingly, since the first portion 411, the second portion 412 and the third portion 413 are separated from each other, the voltage applied to the first conductive portion 501, the second conductive portion 502 and the gate electrode 600 may be independently controlled or jointly controlled to improve reliability. Furthermore, when the second voltage applied to the first conductive portion 501 and / or the second conductive portion 502 is less than the first voltage applied to the gate electrode 600, the possibility of generating leakage current may be further reduced.

[0090] In some embodiments, the semiconductor devices 1 to 5 of the present invention may be used in any combination and may be used as a high electron mobility transistor. In other embodiments, any of the semiconductor devices 1 to 5 may be further processed to form a high electron mobility transistor.

[0091] Accordingly, the present invention reduces the electric field concentrated at the electrode edge (e.g., the edge of the gate electrode, the edge of the drain electrode, and / or the edge of the source electrode) by setting the conductive part of the ohmic contact between the gate electrode and the drain electrode, or further between the source electrode and the gate electrode. Thus, the conductive part of the ohmic contact can provide electric holes to make the electric field distribution more uniform, improve the on-current, improve the dynamic resistance characteristics, and / or improve the reliability.

[0092] The scope of protection of the present invention is not limited to the processes, machines, manufactures, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any technician in the relevant technical field can understand from the disclosure of the present invention that the processes, machines, manufactures, material compositions, devices, methods and steps currently or in the future can be used according to the present invention as long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein. Therefore, the scope of protection of the present invention includes the aforementioned processes, machines, manufactures, material compositions, devices, methods and steps. Any embodiment or claim of the present invention is not required to achieve all the purposes, advantages and / or features described in the present invention.

[0093] The above summarizes a plurality of embodiments so that those skilled in the art to which the present invention belongs can better understand the concepts of the embodiments of the present invention. Those skilled in the art to which the present invention belongs should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments herein. Those skilled in the art to which the present invention belongs should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and replacements without violating the spirit and scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: a substrate; a channel layer, disposed on the substrate; a barrier layer disposed on the channel layer; a compound semiconductor layer disposed on the barrier layer; a gate electrode disposed on the compound semiconductor layer; A source electrode and a drain electrode are respectively disposed on the barrier layer and on opposite sides of the gate electrode; as well as a conductive portion disposed on the compound semiconductor layer and between the gate electrode and the drain electrode, The conductive part is in ohmic contact with the compound semiconductor layer.

2. The semiconductor device according to claim 1, wherein The gate electrode is in Schottky contact with the compound semiconductor layer.

3. The semiconductor device according to claim 1, wherein The gate electrode has a first width, the conductive portion has a second width, and a ratio of the first width to the second width is less than or equal to 10.

4. The semiconductor device according to claim 1, wherein: The conductive portion is in direct contact with the gate electrode.

5. The semiconductor device according to claim 1, wherein: The conductive portion is spaced a distance from the gate electrode.

6. The semiconductor device according to claim 1, wherein: The conductive part includes: a first conductive portion disposed on the compound semiconductor layer and between the gate electrode and the drain electrode; and A second conductive portion is disposed on the compound semiconductor layer and between the gate electrode and the source electrode.

7. The semiconductor device according to claim 6, wherein: The first conductive portion is in direct contact with the gate electrode, and the second conductive portion is in direct contact with the gate electrode.

8. The semiconductor device according to claim 6, wherein: The first conductive portion is spaced a distance from the gate electrode, and the second conductive portion is spaced a distance from the gate electrode.

9. The semiconductor device according to claim 6, wherein: The compound semiconductor layer includes: a first portion disposed between the barrier layer and the gate electrode; a second portion disposed between the barrier layer and the first conductive portion; and a third portion disposed between the barrier layer and the second conductive portion, The first part, the second part and the third part are separated from each other.

10. A method for forming a semiconductor device, characterized in that: include: providing a substrate; forming a channel layer on the substrate; forming a barrier layer on the channel layer; forming a compound semiconductor layer on the barrier layer; forming a source electrode and a drain electrode on the barrier layer; forming a conductive portion on the compound semiconductor layer; as well as A gate electrode is formed on the compound semiconductor layer, and the gate electrode is disposed between the source electrode and the drain electrode. The conductive part is arranged between the gate electrode and the drain electrode, and the conductive part is in ohmic contact with the compound semiconductor layer.

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