Self-aligned gate structure

Abstract

The present disclosure generally relates to semiconductor processing for self-aligned gate structures and corresponding semiconductor devices. In an example, a semiconductor device includes a semiconductor substrate (102), a semiconductor gate layer (110), an offset dielectric layer (112), and a gate metal contact (114). The semiconductor gate layer (110) is over the semiconductor substrate (102). The offset dielectric layer (112) is over the semiconductor gate layer (110). The gate metal contact (114) is over the offset dielectric layer (112) and passes through an opening through the offset dielectric layer (112). The gate metal contact (114) contacts the semiconductor gate layer (110) through the opening through the offset dielectric layer (112). A first sidewall (140) of the semiconductor gate layer (110), a second sidewall (142) of the offset dielectric layer (112), and a third sidewall (144) of the gate metal contact (114) are vertically aligned over the semiconductor substrate (102).

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of U.S. Provisional Patent Application No. 63 / 593,961, filed on October 27, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to semiconductor devices, and more particularly, to self-aligned gate structures. Background Art

[0004] One type of semiconductor device is a high electron mobility transistor (HEMT). A HEMT typically employs different semiconductor materials to form a heterojunction, wherein a channel may be formed near the heterojunction and between a source and a drain. A HEMT may have high speed operation, which makes the HEMT attractive for high frequency applications, among other things. Summary of the invention

[0005] The examples described herein are a semiconductor device. The semiconductor device includes a semiconductor substrate, a semiconductor gate layer, an offset dielectric layer, and a gate metal contact. The semiconductor gate layer is above the semiconductor substrate. The offset dielectric layer is above the semiconductor gate layer. The gate metal contact is above the offset dielectric layer and passes through an opening through the offset dielectric layer. The gate metal contact contacts the semiconductor gate layer through the opening through the offset dielectric layer. A first sidewall of the semiconductor gate layer, a second sidewall of the offset dielectric layer, and a third sidewall of the gate metal contact are vertically aligned above the semiconductor substrate.

[0006] Another example is a semiconductor device. The semiconductor device includes a high electron mobility transistor (HEMT) on a semiconductor substrate. The HEMT includes a semiconductor gate layer, an offset dielectric layer, and a gate metal contact. The semiconductor gate layer is above a barrier layer above the semiconductor substrate. The offset dielectric layer is above the semiconductor gate layer. The offset dielectric layer has an opening to the semiconductor gate layer. The gate metal contact is on the offset dielectric layer and contacts the semiconductor gate layer in the opening. A first sidewall of the semiconductor gate layer, a second sidewall of the offset dielectric layer, and a third sidewall of the gate metal contact are vertically aligned above the semiconductor substrate.

[0007] Another example is a method. A semiconductor gate layer is formed above a semiconductor substrate. An offset dielectric layer is formed above the semiconductor gate layer. The offset dielectric layer has an opening that exposes the semiconductor gate layer. A gate metal contact layer is formed above the offset dielectric layer and on the semiconductor gate layer through the opening. After forming the gate metal contact layer, the gate metal contact layer, the offset dielectric layer, and the semiconductor gate layer are patterned.

[0008] The foregoing summary of the invention has been quite extensively summarized various features of examples of the present disclosure so that the following detailed description may be better understood. Various features and advantages of such examples will be described below. The described examples may be readily used as a basis for modifying or designing other examples within the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to understand the above features in detail, reference is made to the following detailed description in conjunction with the accompanying drawings.

[0010] Figure 1 is a cross-sectional view of a semiconductor device according to some examples.

[0011] Figure 2 is a cross-sectional view of a semiconductor device according to some examples.

[0012] Figure 3 , 4 , 5, 6, 7, 8, and 9 are respective cross-sectional views of semiconductor devices at intermediate fabrication stages according to some examples.

[0013] The drawings and accompanying detailed description are provided to understand the features of the various examples and do not limit the scope of the appended claims. The examples shown in the drawings and described in the accompanying detailed description can be easily used as a basis for modifying or designing other examples within the scope of the appended claims. Where possible, the same reference numerals may be used to refer to the same elements that are shared among the drawings. The drawings are drawn to clearly illustrate related elements or features and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0014] Various features will be described below with reference to the drawings. Other examples may include any arrangement of the described inclusion or exclusion aspects or features. The illustrated examples may not have all aspects or advantages shown. Aspects or advantages described in conjunction with a particular example are not necessarily limited to that example, and may be practiced in any other example, even if not so described or not explicitly described. In addition, the methods described herein may be described in a particular order of operations, but other methods according to other examples may be implemented with various other orders of more or fewer operations (e.g., including different serial or parallel performance of various operations).

[0015] The present disclosure generally (but not exclusively) relates to semiconductor processing for self-aligned gate structures and corresponding semiconductor devices, such as semiconductor processing for high electron mobility transistors (HEMTs). Generally, the semiconductor device includes a semiconductor gate layer, an offset dielectric layer, and a gate metal contact. The semiconductor gate layer is above a semiconductor substrate. The offset dielectric layer is above the semiconductor gate layer. The gate metal contact is above the offset dielectric layer and extends through an opening through the offset dielectric layer. The gate metal contact contacts the semiconductor gate layer through the opening through the offset dielectric layer. The respective sidewalls of the semiconductor gate layer, the offset dielectric layer, and the gate metal contact are vertically aligned above the semiconductor substrate. Generally, the semiconductor gate layer can be formed above the semiconductor substrate, and the offset dielectric layer can be formed above the semiconductor gate layer. An opening can be formed through the offset dielectric layer, which exposes the semiconductor layer. The gate metal contact layer can be formed above the offset dielectric layer and in the opening, thereby contacting the semiconductor gate layer through the opening. The gate metal contact layer, the offset dielectric layer, and the gate layer can be patterned together, for example, by using a single photomask.

[0016] The examples described herein can avoid forming metal stringers on the passivation or dielectric layer at the sidewalls of the gate layer that can be formed by other processes. Additionally and / or alternatively, over-etching damage to the passivation or dielectric layer that may occur when removing the metal stringers can be avoided. This can improve the yield of manufacturing semiconductor devices and improve the reliability of semiconductor devices. Compared to other processes, the examples described herein can avoid etching-induced damage to the surface of the semiconductor gate layer, which can cause leakage of the lower gate. In addition, fewer photolithography processes (fewer photomasks may be required) may be required to manufacture semiconductor devices, which can reduce manufacturing costs. Other benefits and advantages can be achieved.

[0017] Various examples are then described.While specific examples may illustrate various aspects of the features generally described above, examples may incorporate any combination generally described above (which are described in more detail in the examples below).

[0018] Figure 1A cross-sectional view of a semiconductor device 100 according to some examples is shown. In this example, the semiconductor device 100 is or includes an enhancement mode (Emode) HEMT. The semiconductor device 100 may be rated for low voltage (LV) applications (e.g., equal to or less than 100V), medium voltage (MV) applications (e.g., in a range from 100V to 300V), or high voltage (HV) applications (e.g., equal to or greater than 400V, and more specifically, equal to or greater than 600V). The LV, MV, or HV application rating of a semiconductor device does not indicate a specific threshold voltage for the semiconductor device. A semiconductor device rated for HV applications may have a low threshold voltage magnitude. Conversely, a semiconductor device rated for LV applications may have a high threshold voltage magnitude. The voltage rating may be based at least in part on the lateral distance between the drain region and the gate structure.

[0019] Figure 1 A semiconductor substrate 102 and one or more transition layers 104 are shown above and over semiconductor substrate 102. A channel layer 106 is above and over an uppermost transition layer 104. A barrier layer 108 is above and over channel layer 106. In some examples, semiconductor substrate 102, transition layers 104, channel layer 106, and barrier layer 108 may be considered together as a semiconductor substrate.

[0020] The semiconductor substrate 102 may be a bulk semiconductor substrate, a semiconductor on insulator (SOI) substrate, or any other suitable substrate. For example, the semiconductor substrate 102 may be or include a bulk silicon wafer. The transition layer 104 may include any number of layers of any material configured to accommodate the lattice mismatch between the semiconductor substrate 102 and the channel layer 106 (e.g., to reduce or minimize the generation and / or propagation of lattice defects in the channel layer 106). For example, the transition layer 104 may have a gradient concentration of one or more elements in a direction orthogonal to the upper surface of the semiconductor substrate 102. In addition, one layer of the transition layer 104 may be a doped buffer layer.

[0021] The channel layer 106 is configured to conduct and confine charge carriers (e.g., electrons) in two dimensions, possibly in combination with the barrier layer 108. In some examples, the channel layer 106 is configured to include a two-dimensional electron gas (2DEG). The 2DEG may be formed by band bending caused by the barrier layer 108 above and on the channel layer 106. In some examples, the channel layer 106 may be part of a semiconductor substrate (e.g., without a transition layer), and / or the semiconductor substrate 102 with the transition layer 104 and the channel layer 106 may be considered a semiconductor substrate. In some examples, the channel layer 106 includes a gallium nitride (GaN) layer, and in such examples, may be referred to as a GaN channel layer. In some examples, the material of the channel layer 106 is or includes an unintentionally doped material, such as a material doped by diffusion of a dopant from another layer, or is or includes an intrinsic material. In some examples, the barrier layer 108 may be or include an aluminum gallium nitride (AlGaN) layer, and in such examples, may be referred to as an AlGaN barrier layer. In some examples, the channel layer 106 may be or include an indium aluminum gallium nitride (In i Al j Ga 1-i-j N) (where 0≤i≤1, 0≤j≤1, and 0≤i+j≤1), and the barrier layer 108 may be or include indium aluminum gallium nitride (In k Al l Ga 1-k-l N) (wherein 0≤k≤1, 0≤l≤1, and 0≤k+l≤1). Other materials may be implemented for the channel layer 106 and / or the barrier layer 108.

[0022] The gate layer 110 is above and on the upper surface of the barrier layer 108. In some examples, the gate layer 110 is or includes a semiconductor layer of a semiconductor material. Furthermore, in some examples, the gate layer 110 is doped with a dopant. In some examples, the gate layer 110 is doped with a p-type dopant. In some examples, the gate layer 110 may be or include a gallium nitride (GaN) layer, such as an indium aluminum gallium nitride (InAluminum Gallium Nitride). m Al n Ga 1-m-n N) (wherein 0≤m<1, 0≤n<1, and 0≤m+n≤1), and the dopant doped with the gate layer 110 is a p-type dopant, and the p-type dopant may be or include magnesium (Mg), carbon (C), zinc (Zn), etc. or a combination thereof. In the example where the gate layer 110 is gallium nitride (GaN) doped with a p-type dopant, the gate layer 110 may be referred to as a p-type doped GaN (pGaN) layer. In addition, in the example where the gate layer 110 is gallium nitride (GaN) doped with magnesium, the gate layer 110 may be referred to as a magnesium-doped gallium nitride (GaN:Mg) layer. In some examples, the concentration of the dopant in the electrically activated gate layer 110 is equal to or greater than 1×10 17 cm-3 In some examples, the concentration is equal to or greater than 1×10 18 cm -3 In some examples, the dopant in the gate layer 110 can have a uniform concentration. In some examples, the dopant in the gate layer 110 can have a gradient concentration. In other examples, other materials, dopants, and / or concentrations can be implemented.

[0023] Offset dielectric layer 112 is above and on the upper surface of gate layer 110. Offset dielectric layer 112 may be or include silicon nitride, silicon oxide, another dielectric material, or the like. Offset dielectric layer 112 is at the lateral perimeter of gate layer 110, as described in more detail subsequently.

[0024] The gate metal contact 114 extends through the offset dielectric layer 112 and contacts the gate layer 110. The gate metal contact 114 is above and on the offset dielectric layer 112 at the lateral perimeter of the gate layer 110. The gate metal contact 114 may include or be any suitable metal. In some semiconductor devices, the gate metal contact 114 may form a Schottky junction with the gate layer 110. As an example, when the gate layer 110 is magnesium-doped gallium nitride (GaN:Mg), the metal that may form a Schottky junction with the gate layer 110 may be or include titanium (Ti), titanium tungsten (TiW), titanium nitride (TiN), nickel (Ni), platinum (Pt), tantalum nitride (TaN), copper (Cu), tungsten (W), or an alloy thereof. In some semiconductor devices, the gate metal contact 114 may form an ohmic junction with the gate layer 110. For example, when the gate layer 110 is magnesium-doped gallium nitride (GaN:Mg), the metal that can form an ohmic junction with the gate layer 110 can be or include gold (Au), nickel (Ni), aluminum (Al), or an alloy thereof, which can include titanium tungsten aluminum (TiWAl) and titanium aluminum nitride (TiAlN). In some examples, the gate metal contact 114 includes: a first portion that includes a metal that forms a Schottky junction with the gate layer 110; and a second portion that includes a metal that forms an ohmic junction with the gate layer 110, such as described in U.S. Patent Application No. 18 / 361,997 filed on July 31, 2023, which is incorporated herein by reference in its entirety.

[0025] The gate layer 110, the offset dielectric layer 112, and the gate metal contact 114 have outer sidewalls that are vertically aligned. On the drain side, the sidewall 140 of the gate layer 110, the outer sidewall 142 of the offset dielectric layer 112, and the sidewall 144 of the gate metal contact 114 are vertically aligned. On the source side, the sidewall 150 of the gate layer 110, the outer sidewall 152 of the offset dielectric layer 112, and the sidewall 154 of the gate metal contact 114 are vertically aligned. An outer lateral dimension 160 (e.g., gate length) is between the sidewalls 140, 150 of the gate layer 110, and therefore also between the outer sidewalls 142, 152 of the offset dielectric layer 112 and between the sidewalls 144, 154 of the gate metal contact 114. The offset dielectric layer 112 has an opening with an inner lateral dimension 162 through which the gate metal contact 114 contacts the gate layer 110. The offset dielectric layer 112 has a first offset lateral dimension 164 from an outer sidewall 142 of the offset dielectric layer 112 to a corresponding (e.g., nearest) sidewall of an opening through the offset dielectric layer 112, and has a second offset lateral dimension 166 from an outer sidewall 152 of the offset dielectric layer 112 to a corresponding (e.g., nearest) sidewall of an opening through the offset dielectric layer 112. In some examples, the offset lateral dimensions 164, 166 may be equal, but in some examples, the offset lateral dimensions 164, 166 may not be equal (e.g., due to misalignment of a photomask or device design optimization). The outer lateral dimension 160 (e.g., gate length) is equal to the sum of the inner lateral dimension 162, the first offset lateral dimension 164, and the second offset lateral dimension 166. The lateral dimensions 160-166 are parallel to a direction from the drain region D to the source region S, which is described more later.

[0026] In some examples, each of first offset lateral dimension 164 and second offset lateral dimension 166 may be greater than or equal to 2% of outer lateral dimension 160, may be less than or equal to 40% of outer lateral dimension 160, or may be in a range from 2% to 40% of outer lateral dimension 160. In some examples, inner lateral dimension 162 may be greater than or equal to 30% of outer lateral dimension 160, may be less than or equal to 95% of outer lateral dimension 160, or may be in a range from 30% to 95% of outer lateral dimension 160. In some examples, each of first offset lateral dimension 164 and second offset lateral dimension 166 may each be in a range from 10 nm to 500 nm, and outer lateral dimension 160 may be in a range from 100 nm to 3,000 nm.

[0027] More specifically, for example, LV applications, each of the first offset lateral dimension 164 and the second offset lateral dimension 166 may be in a range from 10 nm to 200 nm, and the outer lateral dimension 160 may be in a range from 150 nm to 400 nm. For example, MV applications, each of the first offset lateral dimension 164 and the second offset lateral dimension 166 may be in a range from 60 nm to 500 nm, and the outer lateral dimension 160 may be in a range from 400 nm to 1.7 μm. For example, HV applications, each of the first offset lateral dimension 164 and the second offset lateral dimension 166 may be in a range from 200 nm to 500 nm, and the outer lateral dimension 160 may be in a range from 1.7 μm to 3 μm.

[0028] Additionally, the offset dielectric layer 112 has a thickness 168, which may be in a range from 5 nm to 1,000 nm. More specifically, for example, LV applications, the thickness 168 may be in a range from 5 nm to 100 nm. For example, MV applications, the thickness 168 may be in a range from 5 nm to 200 nm. For example, HV applications, the thickness 168 may be in a range from 10 nm to 1,000 nm.

[0029] The passivation layer 116 is conformally above and over the upper surface of the barrier layer 108, on and along the sidewalls 140, 150, 142, 152, 144, 154 of the gate layer 110, the offset dielectric layer 112, and the gate metal contact 114, and above and over the upper surface of the gate metal contact 114. In some examples, the passivation layer 116 may be or include silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide (Al2O3), aluminum nitride (AlN), aluminum oxynitride (AlON), hafnium dioxide (HfO2), any other dielectric material, or a combination thereof. In some examples, the regeneration barrier layer may be above and over the gate metal contact 114, and the passivation layer 116 may be above and over the regeneration barrier layer. In such examples, the regeneration barrier layer may be or include an aluminum gallium nitride (AlGaN) layer.

[0030] Drain metal contact 118 and source metal contact 120 extend through passivation layer 116 and barrier layer 108 and contact channel layer 106. In some examples, drain metal contact 118 and source metal contact 120 do not extend through barrier layer 108 and may contact an upper surface of barrier layer 108 or extend into barrier layer 108. In some examples, drain metal contact 118 and source metal contact 120 may be or include a metal that forms an ohmic junction with channel layer 106 and / or barrier layer 108. Drain metal contact 118 and source metal contact 120 may be or include a metal, such as titanium nitride (TiN), tantalum nitride (TaN), titanium (Ti), aluminum (Al), copper (Cu), tungsten (W), the like, or a combination thereof.

[0031] A dielectric layer 122, which may be an interlayer dielectric layer (ILD), is above and over the passivation layer 116 and the metal contacts 118, 120. The dielectric layer 122 may be a single dielectric layer or may include multiple dielectric layers of the same dielectric material or different dielectric materials. For example, the dielectric layer 122 may include silicon nitride, a silicon oxide-based material such as phosphosilicate glass (PSG) or tetraethyl orthosilicate (TEOS) oxide, polytetrafluoroethylene, or the like.

[0032] Metal vias 124, 126 pass through dielectric layer 122. Metal via 124 contacts drain metal contact 118. Metal via 126 contacts source metal contact 120. Metal lines 128, 130 are above and over dielectric layer 122. Metal line 128 is further above and over (and electrically connected to) metal via 124. Metal line 130 is further above and over (and electrically connected to) metal via 126. Metal vias 124, 126 may each include: (i) one or more metal barrier layers and / or adhesion layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), the like, or a combination thereof) conformally in respective openings through dielectric layer 122; and (ii) a fill metal (e.g., aluminum (Al), copper (Cu), tungsten (W), the like, or a combination thereof) above and / or over the metal barrier layers and / or adhesion layers. Metal lines 128, 130 may each include one or more metal barrier and / or adhesion layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), the like, or a combination thereof) and a bulk metal (e.g., aluminum (Al), copper (Cu), the like, or a combination thereof) above and / or on the metal barrier and / or adhesion layers.

[0033] The semiconductor device 100 has a gate-drain lateral dimension 170. The gate-drain lateral dimension 170 is from the sidewall 140 of the gate layer 110 to the center of the drain metal contact 118 and is parallel to the direction from the drain region D to the source region S. In some examples, for LV applications, the gate-drain lateral dimension 170 is in a range from 0.1 μm to 1 μm. In some examples, for MV applications, the gate-drain lateral dimension 170 is in a range from 1 μm to 10 μm. In some examples, for HV applications, the gate-drain lateral dimension 170 is in a range from 10 μm to 100 μm.

[0034] The semiconductor device 100 includes a source region S, a channel region C, a drain region D, and a gate terminal G. The gate terminal G is or includes a gate layer 110. The channel region C is in the channel layer 106 below the gate terminal G. The channel region C is laterally between the drain region D and the source region S, which are also in the channel layer 106. The drain metal contact 118 is electrically coupled to the drain region D, and the source metal contact 120 is electrically coupled to the source region S. The gate metal contact 114 is electrically coupled to the gate terminal G (e.g., the gate layer 110). The gate terminal G and the gate metal contact 114 are laterally between the drain metal contact 118 and the source metal contact 120.

[0035] In general, at smaller device dimensions (e.g., when the semiconductor device 100 is scaled to a smaller size), the electric field may increase between the gate layer 110 and the source region S and between the gate layer 110 and the drain region D. Without the presence of the offset dielectric layer 112, due to the increased electric field, positive gate leakage may occur at the lateral periphery (e.g., at the sidewalls) of the gate layer 110. The offset dielectric layer 112 may be an isolation member that disconnects the direct conductive path at the periphery of the gate layer 110 from the gate metal contact 114, which may reduce gate forward leakage and also increase the gate forward breakdown voltage.

[0036] The offset lateral dimensions 164, 166 of the offset dielectric layer 112 may be determined based on the target performance of the semiconductor device 100. For a given outer lateral dimension 160, increasing the offset lateral dimensions 164, 166 results in reducing the inner lateral dimension 162. Too small an inner lateral dimension 162 may increase the gate resistance (R G ) and reduce gate control. With a smaller inner lateral dimension 162, less capacitive coupling occurs from the gate metal contact 114 to the channel region C to control the channel region C and turn on the semiconductor device 100, which also increases the drain-to-source on-resistance (R DSON ). Also, the saturation current capability of the semiconductor device 100 may be reduced. Therefore, the offset lateral dimensions 164, 166 of the offset dielectric layer 112 may be implemented in a manner that balances the following two aspects: (i) reducing gate forward leakage and increasing gate forward breakdown voltage, and (ii) increasing R G and R DSON And reduce the saturation current capability.

[0037] Figure 2 A cross-sectional view of a semiconductor device 200 is shown according to some examples. Figure 2 The semiconductor device 200 is substantially similar to Figure 1The semiconductor device 100 includes a source-coupled field plate 220. The source-coupled field plate 220 is above the passivation layer 116 and the gate metal contact 114, and extends laterally from the gate metal contact 114 and the gate layer 110 toward the drain metal contact 118 and / or the drain region D. In the example shown, the source metal contact 120 and the source-coupled field plate 220 are an integral metal piece, so that the source-coupled field plate 220 is electrically connected to the source region S. In other examples, the source metal contact 120 and the source-coupled field plate 220 may be separate components and may be electrically connected through other metal layers. Various other field plates and configurations of field plates may be implemented in other examples. For example, multiple field plates may be implemented. The field plate may be electrically coupled or connected to the gate layer 110 and / or the gate metal contact 114, and electrically coupled or connected to the source metal contact 120. The field plate may be substantially horizontal or tilted. Different configurations of field plates may be implemented to manage the electric field between the gate layer 110 and the channel layer 106 . Figure 2 The source-coupled field plate 220 is shown as an example only.

[0038] Figures 3 to 9 are corresponding cross-sectional views of a semiconductor device at an intermediate fabrication stage according to some examples. Figures 3 to 9 The example shown shows the manufacture of the above described Figure 1 and 2 A method for manufacturing the semiconductor device 100, 200.

[0039] refer to Figure 3 , one or more transition layers 104 are formed on and above the semiconductor substrate 102. A channel layer 106 is formed on and above the transition layer 104. A barrier layer 108 is formed on and above the channel layer 106. A gate layer 110 is formed on and above the barrier layer 108. In some examples, the transition layer 104, the channel layer 106, the barrier layer 108, and the gate layer 110 can be formed by using any suitable deposition process, which can further be an epitaxial growth process. For example, the transition layer 104, the channel layer 106, the barrier layer 108, and the gate layer 110 can each be epitaxially grown using metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), low pressure chemical vapor deposition (LPCVD), or another epitaxial process. The materials of the semiconductor substrate 102, the transition layer 104, the channel layer 106, the barrier layer 108, and the gate layer 110 can be as previously described. The gate layer 110 may be doped in situ during deposition (eg, epitaxial growth) or after deposition by implantation (eg, ion implantation).

[0040] refer to Figure 4, an offset dielectric layer 112 is formed above and on the gate layer 110. The offset dielectric layer 112 is formed with a thickness 168, as described above. The offset dielectric layer 112 may be formed by depositing the offset dielectric layer 112 using any suitable deposition process, such as LPCVD, plasma enhanced chemical vapor deposition (PECVD), etc. The material of the offset dielectric layer 112 may be as previously described.

[0041] refer to Figure 5 , a gate contact opening 502 is formed through the offset dielectric layer 112. The gate layer 110 is exposed through the gate contact opening 502 through the offset dielectric layer 112. The gate contact opening 502 has an inner lateral dimension 162, as described above. The gate contact opening 502 may be formed using an appropriate photolithography and etching process. For example, to pattern the offset dielectric layer 112 to have the gate contact opening 502, a photoresist is deposited (e.g., by spin coating) and patterned over and / or on the semiconductor substrate 102 (e.g., over and / or on the offset dielectric layer 112) using photolithography (e.g., with a photomask). The photoresist is patterned to expose the area of ​​the offset dielectric layer 112 where the gate contact opening 502 will be formed. Using the patterned photoresist as a mask, an etching process such as anisotropic etching such as reactive ion etching (RIE) is performed to form the gate contact opening 502 through the offset dielectric layer 112. After the etching process, the photoresist is removed, for example, by ashing and / or wet stripping.

[0042] refer to Figure 6 , a gate metal contact layer 114 is formed on and above the offset dielectric layer 112 and in the gate contact opening 502 to contact the gate layer 110. The gate metal contact layer 114 may be deposited using a suitable deposition process, such as sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD), or the like. The material of the gate metal contact layer 114 may be as described above with respect to the gate metal contact 114.

[0043] refer to Figure 7 , the gate metal contact 114, the offset dielectric layer 112 and the gate layer 110 are patterned. Figure 714, and the gate metal contact 114, the offset dielectric layer 112, and the gate layer 110 are patterned to form aligned sidewalls 140, 142, 144 and aligned sidewalls 150, 152, 154 of the gate layer 110, the offset dielectric layer 112, and the gate metal contact 114, respectively. The gate metal contact 114, the offset dielectric layer 112, and the gate layer 110 can be patterned using a single photomask. For example, photoresist 702 is deposited (e.g., by spin coating) and patterned over and / or on the semiconductor substrate 102 (e.g., over and / or on the gate metal contact layer 114) using photolithography (e.g., with a single photomask). The photoresist 702 is patterned to remain in the areas where the gate metal contact 114, the offset dielectric layer 112, and the gate layer 110 are to remain. Using the patterned photoresist 702 as a mask, an etching process, such as anisotropic etching such as RIE, is performed to pattern the gate metal contact 114, the offset dielectric layer 112, and the gate layer 110. After the etching process, the photoresist 702 is removed, such as by ashing and / or wet stripping. The offset dielectric layer 112 is patterned to have a first offset lateral dimension 164 and a second offset lateral dimension 166. Misalignment between the photomask used to form the gate contact opening 502 and the photomask used to pattern the gate metal contact 114, the offset dielectric layer 112, and the gate layer 110 can cause the offset lateral dimensions 164, 166 to be unequal. In other examples, ideal alignment of those photomasks can cause the offset lateral dimensions 164, 166 to be equal.

[0044] like Figures 3 to 7 As shown, metal stringers can be avoided by patterning the gate metal contact 114 and the gate layer 110 together (e.g., in a self-aligned process). In a non-self-aligned process, the gate layer can be patterned; a passivation layer can be conformally deposited over the patterned gate layer; and a gate metal contact can be formed over the passivation layer and through the passivation layer to the patterned gate layer. Forming the gate metal contact can include depositing a metal layer and patterning the metal layer into the gate metal contact. Patterning the metal layer in this non-self-aligned process can result in stringers at the sidewalls of the passivation layer along the sidewalls of the patterned gate layer, and / or can result in etch-induced damage to the passivation layer due to over-etching when patterning the metal layer. In general, the surface morphology of the passivation layer resulting from the patterned gate layer can result in metal stringers and / or etch-induced damage to the passivation layer. In Figures 3 to 7 In the example shown, there is almost no surface morphology in the gate layer 110, the offset dielectric layer 112, and the gate metal contact layer 114 outside the photoresist 702 used for patterning. This lack of surface morphology can avoid the formation of any metal stringers. In addition, without the involvement of metal stringers, over-etching can be avoided, which can avoid etch-induced damage to any passivation layer. As explained, in the example shown, there is no passivation layer that will experience any over-etching when patterning the gate metal contact 114.

[0045] As described, the metal stringer can be an electrically floating metal piece that can be capacitively coupled between the gate layer and the channel region. The metal stringer on the source side of the gate structure can increase the gate-source current (I GS ). Metal stringers can induce charge trapping (e.g., due to hot electrons during high drain voltage stress) because there may not be a direct conductive path to discharge the trapped charge. Charge trapping can induce undesirable instabilities such as dynamic R DSON and dynamic threshold voltage (V t ) input, such as a HEMT. The trapped charge can affect the electric field. When the trapped charge is negative, the electric field can be reduced and the channel region can be depleted, which can result in a higher R DSON When the trapped charge is positive, the electric field can increase, which can cause a reduction in time-dependent dielectric breakdown (TDDB). As described above, examples can avoid this metal stringer and, therefore, can have improved R DSON and TDDB.

[0046] In the non-self-aligned process described above, an over-etch may be performed when patterning the gate metal contact to remove any metal stringers. This over-etch may result in etch-induced damage to the underlying passivation layer. The etch-induced damage to the passivation layer may result in a thinner passivation layer, which may result in reduced TDDB. Figures 3 to 7 As shown in , the absence of a similar passivation layer may suffer from over-etching when patterning the gate metal contact 114. Therefore, the example may have an increased TDDB.

[0047] The offset dielectric layer 112 provides an offset from the lateral outer edge of the gate layer 110, wherein the gate metal contact 114 does not directly contact the gate layer 110. This can reduce gate leakage, especially when the gate is forward biased. The offset dielectric layer 112 can provide this offset to avoid etching to shrink the gate metal contact, which would expose the upper surface of the gate layer in the offset. Exposure of the upper surface of the gate layer and also the sidewalls of the gate layer to this etching can damage the exposed surface of the gate layer, which can increase gate leakage, reduce the gate breakdown voltage, and cause dynamic R DSON and V t Implementing an offset dielectric layer 112 can avoid these problems.

[0048] refer to Figure 8, passivation layer 116 is conformally formed on and over barrier layer 108, on and along sidewalls 140, 150, 142, 152, 144, 154, and on and over gate metal contact 114. Passivation layer 116 may be deposited using any suitable deposition process, such as LPCVD, PECVD, atomic layer deposition (ALD), or the like. The material of passivation layer 116 may be as described above.

[0049] refer to Fig. 9 , drain contact opening 902 and source contact opening 904 are formed through passivation layer 116. As illustrated, drain contact opening 902 and source contact opening 904 may also be formed through barrier layer 108. Drain contact opening 902 and source contact opening 904 may be formed using appropriate photolithography and etching processes. For example, to pattern passivation layer 116 and (if implemented) barrier layer 108 with drain contact opening 902 and source contact opening 904, photolithography (e.g., with a photomask) is used to deposit (e.g., by spin coating) a photoresist over and / or on semiconductor substrate 102 (e.g., over and / or on passivation layer 116). The photoresist is patterned to expose areas of passivation layer 116 where drain contact opening 902 and source contact opening 904 will be formed. Using the patterned photoresist as a mask, an etching process, such as anisotropic etching such as RIE, is performed to form drain contact openings 902 and source contact openings 904 through passivation layer 116 and (if implemented) into or through barrier layer 108. After the etching process, the photoresist is removed, such as by ashing and / or wet stripping.

[0050] refer to Figure 1 and 2, forming a drain metal contact 118, a source metal contact 120, and (where implemented) a source coupled field plate 220. The drain metal contact 118 is formed in the drain contact opening 902 and partially formed over the passivation layer 116. The source metal contact 120 is formed in the source contact opening 904 and partially formed over the passivation layer 116. If implemented, the source coupled field plate 220 is formed over the passivation layer 116 extending laterally from the source metal contact 120, over the gate metal contact 114, and from the gate metal contact 114 toward the drain metal contact 118. One or more metals are deposited into the drain contact opening 902 and the source contact opening 904 and over and on the passivation layer 116. The metals may be deposited using a suitable deposition process, such as sputtering, PVD, CVD, or the like. In some examples, the metal may be a respective conformal layer of drain contact opening 902 and source contact opening 904 that does not fill drain contact opening 902 and source contact opening 904, and in some examples, the metal may fill drain contact opening 902 and source contact opening 904. The metal over the upper surface of passivation layer 116 is patterned into portions of drain metal contact 118, source metal contact 120, and (where implemented) source-coupled field plate 220 on the upper surface of passivation layer 116. The one or more metals may be patterned using appropriate photolithography and etching processes.

[0051] A dielectric layer 122 is formed over and above the passivation layer 116, the drain metal contact 118, and the source metal contact 120. The dielectric layer 122 may be deposited using any suitable deposition process, such as PECVD or the like. The dielectric layer 122 may be any material described above with respect to the dielectric layer 122. The dielectric layer 122 may be planarized, for example, by chemical mechanical polishing (CMP).

[0052] Metal vias 124, 126 are formed through dielectric layer 122, and metal lines 128, 130 are formed above and on dielectric layer 122. Via openings to respective metal contacts 118, 120 may be formed through dielectric layer 122 using appropriate photolithography and etching processes. The metal of metal vias 124, 126 and metal lines 128, 130 is deposited above dielectric layer 122 and in the via openings. The metal may be deposited using an appropriate deposition process, such as CVD, PVD, or the like. The metal may be patterned into metal lines 128, 130 using appropriate photolithography and etching processes. The metal underlying metal lines 128, 130 and in respective via openings through dielectric layer 122 forms metal vias 124, 126.

[0053] Although various examples have been described in detail, it should be understood that various changes, substitutions and alterations could be made thereto without departing from the scope defined by the appended claims.

Claims

1. A semiconductor device comprising: Semiconductor substrate; a semiconductor gate layer, which is above the semiconductor substrate; an offset dielectric layer overlying the semiconductor gate layer; as well as A gate metal contact is disposed above the offset dielectric layer and through an opening through the offset dielectric layer, the gate metal contact contacting the semiconductor gate layer through the opening through the offset dielectric layer, wherein a first sidewall of the semiconductor gate layer, a second sidewall of the offset dielectric layer, and a third sidewall of the gate metal contact are vertically aligned above the semiconductor substrate.

2. The semiconductor device according to claim 1, further comprising: a channel layer over the semiconductor substrate; a barrier layer, which is above the channel layer, and the semiconductor gate layer is above the barrier layer; a drain metal contact electrically coupled to a drain region in the channel layer; as well as A source metal contact is electrically coupled to the source region in the channel layer.

3. The semiconductor device according to claim 1, wherein: The semiconductor gate layer is a component of a transistor; a fourth sidewall of the semiconductor gate layer, a fifth sidewall of the offset dielectric layer, and a sixth sidewall of the gate metal contact are vertically aligned above the semiconductor substrate; The first sidewall, the second sidewall and the third sidewall are respectively on the drain side of the semiconductor gate layer, the offset dielectric layer and the gate metal contact; and The fourth sidewall, the fifth sidewall, and the sixth sidewall are on the source side of the semiconductor gate layer, the offset dielectric layer, and the gate metal contact, respectively.

4. The semiconductor device according to claim 1, wherein: The semiconductor gate layer is a component of a transistor, and the transistor includes a drain region and a source region; The semiconductor gate layer has an outer lateral dimension parallel to a direction from the drain region to the source region, the outer lateral dimension being in a range from 100 nm to 3,000 nm; and The offset dielectric layer has an offset lateral dimension from the second sidewall of the offset dielectric layer to a corresponding sidewall of the opening, the offset lateral dimension being parallel to the direction from the drain region to the source region, the offset lateral dimension being in a range from 10 nm to 500 nm. 5 . The semiconductor device of claim 1 , further comprising a passivation layer on the first sidewall, the second sidewall, and the third sidewall and over the gate metal contact.

6. The semiconductor device of claim 5, further comprising a metal field plate over the passivation layer, wherein the semiconductor gate layer is a component of a transistor, the transistor including a drain region, the metal field plate extending laterally from over the semiconductor gate layer toward the drain region. 7 . The semiconductor device of claim 6 , wherein the transistor further comprises a source region, the metal field plate being electrically connected to the source region.

8. A semiconductor device comprising: A high electron mobility transistor (HEMT), on a semiconductor substrate, the HEMT comprising: a semiconductor gate layer over the barrier layer over the semiconductor substrate; an offset dielectric layer over the semiconductor gate layer, the offset dielectric layer having an opening to the semiconductor gate layer; as well as A gate metal contact contacts the semiconductor gate layer on the offset dielectric layer and in the opening, wherein a first sidewall of the semiconductor gate layer, a second sidewall of the offset dielectric layer, and a third sidewall of the gate metal contact are vertically aligned above the semiconductor substrate.

9. The semiconductor device according to claim 8, wherein: a fourth sidewall of the semiconductor gate layer, a fifth sidewall of the offset dielectric layer, and a sixth sidewall of the gate metal contact are vertically aligned above the semiconductor substrate; The first sidewall, the second sidewall and the third sidewall are respectively on the drain side of the semiconductor gate layer, the offset dielectric layer and the gate metal contact; and The fourth sidewall, the fifth sidewall, and the sixth sidewall are on the source side of the semiconductor gate layer, the offset dielectric layer, and the gate metal contact, respectively.

10. The semiconductor device according to claim 8, wherein: The semiconductor gate layer has an outer lateral dimension parallel to a direction from a drain region of the HEMT to a source region of the HEMT, the outer lateral dimension being in a range from 100 nm to 3,000 nm; and The offset dielectric layer has an offset lateral dimension from the second sidewall of the offset dielectric layer to a corresponding sidewall of the opening, the offset lateral dimension being parallel to the direction from the drain region of the HEMT to the source region of the HEMT, the offset lateral dimension being in a range from 10 nm to 500 nm.

11. The semiconductor device of claim 8, wherein the HEMT further comprises a passivation layer on the first sidewall, the second sidewall, and the third sidewall and over the gate metal contact. 12 . The semiconductor device of claim 11 , wherein the HEMT further comprises a field plate above the passivation layer, the field plate extending at least laterally from the semiconductor gate layer toward a drain region of the HEMT.

13. The semiconductor device according to claim 11, wherein the HEMT further comprises: a drain metal contact electrically coupled to a drain region of the HEMT, the drain metal contact penetrating the passivation layer; and A source metal contact is electrically coupled to a source region of the HEMT, the source metal contact passing through the passivation layer. 14 . The semiconductor device of claim 13 , wherein the HEMT further comprises a field plate above the passivation layer, the field plate extending at least laterally from the semiconductor gate layer toward the drain metal contact.

15. The semiconductor device of claim 14, wherein the field plate is electrically connected to the source metal contact.

16. The semiconductor device according to claim 8, wherein the HEMT further comprises: A channel layer, which is above the semiconductor substrate, the channel layer comprising a source region and a drain region; the barrier layer being above the channel layer, the semiconductor gate layer being above the barrier layer and laterally between the source region and the drain region; a passivation layer over the barrier layer, on the first sidewall, the second sidewall, and the third sidewall, and over the gate metal contact; a drain metal contact passing through the passivation layer and electrically coupled to the drain region; as well as A source metal contact passes through the passivation layer and is electrically coupled to the source region.

17. The semiconductor device according to claim 16, wherein: The channel layer includes indium aluminum gallium nitride (In i Al j Ga 1-i-j N), where 0≤i≤1, 0≤j≤1, and 0≤i+j≤1; The barrier layer comprises indium aluminum gallium nitride (In k Al l Ga 1-k-l N), where 0≤k≤1, 0≤l≤1, and 0≤k+l≤1; and The semiconductor gate layer includes p-doped gallium nitride.

18. A method comprising: forming a semiconductor gate layer over the semiconductor substrate; forming an offset dielectric layer above the semiconductor gate layer, the offset dielectric layer having an opening exposing the semiconductor gate layer; forming a gate metal contact layer through the opening over the offset dielectric layer and on the semiconductor gate layer; as well as After forming the gate metal contact layer, the gate metal contact layer, the offset dielectric layer and the semiconductor gate layer are patterned.

19. The method of claim 18, wherein patterning the gate metal contact layer, the offset dielectric layer, and the semiconductor gate layer forms a first sidewall of the gate metal contact layer, a second sidewall of the offset dielectric layer, and a third sidewall of the semiconductor gate layer, and the first sidewall, the second sidewall, and the third sidewall are vertically aligned.

20. The method of claim 19, further comprising forming a passivation layer on the first sidewall, the second sidewall, and the third sidewall and over the patterned gate metal contact layer.

21. The method of claim 18, wherein patterning the gate metal contact layer, the offset dielectric layer, and the semiconductor gate layer uses a single photomask.

22. The method of claim 18, wherein after patterning the gate metal contact layer, the offset dielectric layer, and the semiconductor gate layer: The semiconductor gate layer has outer lateral dimensions in a range from 100 nm to 3,000 nm; and The offset dielectric layer has an offset lateral dimension in a range from 10 nm to 500 nm.

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