Vertical capacitive coupling gate-controlled junction field effect transistor

Abstract

The vertical capacitive coupling grid-controlled junction field effect transistor comprises a drain electrode, a substrate, an epitaxial layer, two first doping type source regions which are formed downwards from the upper surface of the epitaxial layer and are arranged at an interval in the transverse direction, and a second doping type source region which is formed downwards from the upper surface of the epitaxial layer, the two source region deep grooves are formed downwards from the upper surface of the epitaxial layer, and the two source region deep grooves are formed on the outer sides of the two first doping type source regions respectively; the two second doping type source regions respectively form the second doping type source regions downwards from the bottom surface of the source region deep groove; the gate and the channel are formed between the two first doping type source regions; wherein the lower surfaces of the second doping type source regions are lower than the bottom of the channel, and the two second doping type source regions and the structure between the two second doping type source regions form a PN junction. According to the embodiment of the invention, the technical problem that the withstand voltage is insufficient when a traditional vertical capacitive coupling gate-controlled junction field effect transistor is turned off is solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a vertical capacitively coupled gate-controlled junction field effect transistor. Background Art

[0002] like Figure 1 As shown, the manufacturing process window of the vertical capacitively coupled gate-controlled junction field effect transistor in patent CN117637854B is relatively small.

[0003] In the case of deviation from the process window, it is easy to cause channel punch-through failure under withstand voltage. The reason is that the P-type bottom gate 3 is too shallow and cannot effectively shield the influence of the drain end (corresponding to the drain 13) on the channel (mainly channel 15) potential, resulting in the channel (mainly channel 15) potential being too high under withstand voltage, which in turn causes electrons to pass through the channel, resulting in the device being unable to withstand voltage and shut down.

[0004] If the withstand voltage capability is improved by increasing the injection depth of the P-type bottom gate 3, this will cause the on-resistance (Rdson) to become higher, resulting in poor device performance. Therefore, in the vertical capacitively coupled gate-controlled junction field effect transistor in patent CN117637854B, adjusting the injection depth of the P-type bottom gate 3 will make the withstand voltage (BV) and resistance contradictory. At the same time, under a smaller resistance, the withstand voltage is very sensitive to the injection of the P-type bottom gate 3, resulting in a smaller manufacturing process window. Therefore, adjusting the injection depth of the P-type bottom gate 3 is not an effective solution to improve the withstand voltage.

[0005] Among them, there are substrate 1, epitaxial layer 2, bottom gate 3, second doping type source region 4, channel 1 5, channel 2 52, source region 7, top gate 8, dielectric layer 9, coupling capacitor upper electrode 10, source 12, and drain 13.

[0006] The vertical capacitively coupled gate-controlled junction field effect transistor in patent CN117637854B has a problem that, when turned off, the channel is easily punched through due to insufficient withstand voltage.

[0007] Therefore, the conventional vertical capacitive-coupled gate-controlled junction field effect transistor has insufficient withstand voltage when turned off, which is a technical problem that those skilled in the art urgently need to solve.

[0008] The above information disclosed in the background section is only for enhancing understanding of the background of the present application and therefore it may contain information that does not form the prior art known to a person of ordinary skill in the art. Summary of the invention

[0009] The embodiment of the present application provides a vertical capacitive-coupled gate-controlled junction field effect transistor to solve the technical problem of insufficient withstand voltage of a traditional vertical capacitive-coupled gate-controlled junction field effect transistor when it is turned off.

[0010] A vertical capacitively coupled gate-controlled junction field effect transistor according to an embodiment of the present application includes:

[0011] A drain, a substrate of a first doping type and an epitaxial layer of a second doping type, wherein the epitaxial layer is located above the substrate, and the drain is formed on the back side of the substrate;

[0012] Two first doping type source regions are formed downward from the upper surface of the epitaxial layer, and the two first doping type source regions are spaced apart in a lateral direction;

[0013] Two source region deep trenches are formed downward from the upper surface of the epitaxial layer, and the two source region deep trenches are respectively formed outside the two first doping type source regions;

[0014] Two second doping type source regions, each of which is formed downward from the bottom surface of the source region deep trench;

[0015] A gate and a channel are formed between two source regions of the first doping type;

[0016] The lower surface of the second doping type source region is lower than the bottom of the channel, and the two second doping type source regions and the structure between the two second doping type source regions form a PN junction.

[0017] The embodiment of the present application adopts the above technical solution, which has the following technical effects:

[0018] When the vertical capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application is turned off, the current path of the leakage current is as follows: Figure 2-B , Figure 2-C , Figure 2-D The dotted line in the figure shows the leakage current path. Figure 2-A Location and Figure 2-BCorresponding to. At this time, on the one hand, the depletion region of the PN junction formed by the two second-doping type source regions 4 and the part of the epitaxial layer located between the two second-doping type source regions 4 extends to the middle between the second-doping type source regions 4 (that is, the electric field will be gathered at the corner of the second-doping type source region 4, thereby causing the depletion to expand), and the PN junction formed by the structure between the two second-doping type source regions 4 and the two second-doping type source regions 4 is in reverse bias, and assumes part of the voltage resistance function (that is, the potential at the bottom of the channel is reduced to prevent the channel electrons from punching through). At this time, the vertical capacitively coupled gate-controlled junction field effect transistor is protected (that is, the electric field at the two second-doping type source regions 4 is reduced to prevent the electric field concentration effect at the bottom of the channel), the leakage current is reduced, the voltage resistance is improved, and the vertical capacitively coupled gate-controlled junction field effect transistor is improved. The situation of the channel being punched through due to insufficient voltage resistance is thereby improved, so that the vertical capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application has a high reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0020] Figure 1 It is a schematic diagram of patent CN117637854B in the background technology;

[0021] Figure 2-A A schematic diagram of a first implementation of a vertical capacitively coupled gate-controlled junction field effect transistor according to an embodiment of the present application;

[0022] Figure 2-B A schematic diagram of a second implementation of a vertical capacitively coupled gate-controlled junction field effect transistor according to an embodiment of the present application;

[0023] Figure 2-C A schematic diagram of a third implementation of a vertical capacitively coupled gate-controlled junction field effect transistor according to an embodiment of the present application;

[0024] Figure 2-D A schematic diagram of a fourth implementation of a vertical capacitively coupled gate-controlled junction field effect transistor according to an embodiment of the present application;

[0025] Figure 3-A It is a simulation diagram of a vertical capacitively coupled gate-controlled junction field effect transistor without a source region deep trench;

[0026] Figure 3-B The source region has a depth of 0.3 microns. Figure 2-D Simulation diagram of a vertical capacitively coupled gate-controlled junction field effect transistor with a structure;

[0027] Figure 3-C The source region has a depth of 0.5 microns. Figure 2-D Simulation diagram of a vertical capacitively coupled gate-controlled junction field effect transistor with a structure;

[0028] Figure 3-D The source region has a depth of 0.8 microns. Figure 2-D Simulation diagram of a vertical capacitively coupled gate-controlled junction field effect transistor with a structure;

[0029] Figure 3-E The source region has a depth of 1.0 micron. Figure 2-D Simulation diagram of a vertical capacitively coupled gate-controlled junction field effect transistor with a structure;

[0030] Figure 3-F for Figure 3-A to Figure 3-E Potential curve of vertical capacitively coupled gate controlled junction field effect transistor;

[0031] Figure 4-A It is a simulation diagram of leakage current of a vertical capacitively coupled gate-controlled junction field effect transistor without a source region deep trench;

[0032] Figure 4-B The source region has a depth of 0.3 microns. Figure 2-D Simulation diagram of leakage current of vertical capacitively coupled gate-controlled junction field effect transistor with structure;

[0033] Figure 4-C The source region has a depth of 0.5 microns. Figure 2-D Simulation diagram of leakage current of vertical capacitively coupled gate-controlled junction field effect transistor with structure;

[0034] Figure 4-D The source region has a depth of 0.8 microns. Figure 2-D Simulation diagram of leakage current of vertical capacitively coupled gate-controlled junction field effect transistor with structure;

[0035] Figure 4-E The source region has a depth of 1.0 micron. Figure 2-D Simulation diagram of leakage current of vertical capacitively coupled gate-controlled junction field effect transistor with structure;

[0036] Figure 4-F for Figure 4-A to Figure 4-E Drain current curve of vertical capacitively coupled gate junction field effect transistor.

[0037] Reference numerals:

[0038] In the background technology:

[0039] Substrate 1, epitaxial layer 2, bottom gate 3, second doping type source region 4, channel 1 51,

[0040] Channel 2 52, first doping type source region 7, top gate inner region 8, dielectric layer 9,

[0041] Coupling capacitor upper electrode 10, source 12, drain 13;

[0042] In this application:

[0043] Substrate 1, epitaxial layer 2, bottom gate 3, second doping type source region 4, channel 1 51,

[0044] Channel 2 52, current spreading layer 6, first doping type source region 7, source region deep trench 71,

[0045] Top gate inner region 81, top gate outer region 82,

[0046] Dielectric layer 9, buffer layer 100,

[0047] The coupling capacitor has an upper electrode 10 , a gate electrode 11 , a source electrode 12 , and a drain electrode 13 . DETAILED DESCRIPTION

[0048] In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0049] Embodiment 1

[0050] like Figure 2-A , Figure 2-B , Figure 2-C and Figure 2-D As shown, the vertical capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application includes:

[0051] A substrate 1 of a first doping type and an epitaxial layer 2 of a second doping type, wherein the epitaxial layer 2 is located above the substrate 1;

[0052] A drain electrode 13 formed on the back side of the substrate 1;

[0053] Two first doping type source regions 7 are formed downward from the upper surface of the epitaxial layer 2, and the two first doping type source regions 7 are spaced apart in the lateral direction;

[0054] Two source region deep trenches are formed downward from the upper surface of the epitaxial layer 2, and the two source region deep trenches are respectively formed outside the two first doping type source regions 7;

[0055] Two second doping type source regions 4, each of which is formed downward from the bottom surface of the source region deep trench;

[0056] A gate and a channel are formed between two first doping type source regions 7;

[0057] Among them, the lower surface of the second doping type source region 4 is lower than the bottom of the channel, and the second doping type source region 4 and the structure located between two second doping type source regions 4 form a PN junction to reduce the bottom potential of the channel when the vertical capacitively coupled gate-controlled junction field effect transistor is turned off.

[0058] Specifically, the outer sides of the two first doping type source regions 7 , the opposite sides of the two first doping type source regions 7 are the outer sides, and the opposite sides of the two first doping type source regions 7 are the inner sides.

[0059] In the vertical capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application, since the lower surface of the second doping type source region 4 is lower than the bottom of the channel, the PN junction formed by the second doping type source region 4 and the structure between the two second doping type source regions 4 can reduce the bottom potential of the channel.

[0060] When the vertical capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application is working, that is, when it is connected to a positive voltage and forwardly conducted, the forward conducting current path is as follows: Figure 2-A The forward current path is shown in Figure 2-B , Figure 2-C , Figure 2-D The location and Figure 2-A When the vertical capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application is turned off, the current path of the leakage current is consistent with the forward conduction current path.

[0061] When the vertical capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application is turned off, the current path of the leakage current is as follows: Figure 2-B , Figure 2-C , Figure 2-D At this time, on the one hand, the depletion region of the PN junction formed by the second doping type source region 4 and the part of the epitaxial layer located between the two second doping type source regions 4 extends to the middle between the second doping type source regions 4 (that is, the electric field will be gathered at the corner of the second doping type source region 4, thereby causing the depletion to expand), and the PN junction formed by the second doping type source region 4 and the structure between the two second doping type source regions 4 is in reverse bias, and bears part of the withstand voltage effect (that is, the potential at the bottom of the channel is reduced to prevent channel electrons from penetrating), so the leakage current is small.

[0062] At this time, the vertical capacitively coupled gate-controlled junction field effect transistor is protected (i.e., the electric field at the two second doping type source regions 4 is reduced to prevent the electric field concentration effect at the bottom of the channel), the leakage current is reduced, and the withstand voltage is improved, thereby improving the channel punch-through situation of the vertical capacitively coupled gate-controlled junction field effect transistor due to insufficient withstand voltage, so that the vertical capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application has a higher reliability.

[0063] The second doping type source region 4 of the capacitively coupled gate-controlled junction field effect transistor of the present application is formed by first digging a groove to form a source region deep groove, and then implanting downward from the upper surface of the source region deep groove. The method of first digging a source region deep groove and then implanting to form the second doping type source region 4 on the upper surface of the source deep groove makes it easier to implement and operate the second doping type source region 4 without the need for high-energy ion implantation. The depth of the second doping type source region 4 in the capacitively coupled gate-controlled junction field effect transistor can be deeper, and the doping concentration of the lower surface of the second doping type source region 4 can be higher.

[0064] The capacitively coupled gate-controlled junction field effect transistor of the present application avoids the method of forming the second doping type source region 4 by high-energy ion implantation. The reason is that high-energy ion implantation has many disadvantages. First, high-energy ion implantation greater than 2 microns causes great damage to the device surface and affects other processes; second, very deep implantation makes it difficult to control the morphology of the device.

[0065] The capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application first digs a source region deep groove and then implants the second doping type source region 4 on the upper surface of the source deep groove, so that the depth of the second doping type source region 4 can be determined by the depth of the source region deep groove. After the depth of the second doping type source region 4 is determined, the thickness of the second doping type source region 4 can be determined by ion implantation. The morphology of the capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application can be better controlled without affecting the electrical properties.

[0066] Specifically, the first doping type source region 7 and the second doping type source region 4 are both used to connect the source voltage.

[0067] In implementation, two source electrodes 12 are respectively filled in the source region deep trenches, connected to the second doping type source region 4 , and connected to the first doping type source region 7 .

[0068] The source electrode 12 is filled in the source region deep groove in such a way that the lower part of the source electrode 12 is connected to the second doping type source region 4, and the side of the source electrode 12 is connected to the outside of the first doping type source region 7, that is, the source electrode 12 is fully connected to the second doping type source region 4 and the first doping type source region 7, respectively. That is, the second doping type source region 4 and the first doping type source region 7 have the same potential. When the source electrode 12 is connected to an external source voltage, the potentials of the second doping type source region 4 and the first doping type source region 7 are also the source voltage.

[0069] During implementation, when the vertical capacitively coupled gate-controlled junction field effect transistor is turned off, and the PN junction of the second doping type source region 4 and the structure between the two second doping type source regions 4 in the epitaxial layer 2 forms a reverse bias, the PN junction reduces the potential at the bottom of the channel, shielding the influence of the electric field on the channel.

[0070] When the vertical capacitive-coupled gate-controlled junction field effect transistor is connected to a positive voltage and is forward-conducted, the vertical capacitive-coupled gate-controlled junction field effect transistor works.

[0071] The vertical capacitively coupled gate-controlled junction field effect transistor can be turned off by connecting to a negative voltage or by grounding. The focus of the vertical capacitively coupled gate-controlled junction field effect transistor of the present application is to reduce the potential at the bottom of the channel when it is turned off, and the implementation method is that the two second doping type source regions 4 and the PN junction of the structure located between the two second doping type source regions 4 in the epitaxial layer 2 form a reverse bias.

[0072] In implementation, the depth H of the second doping type source region 4 is in the range of greater than or equal to 1 μm and less than or equal to 2 μm;

[0073] The implantation dose of the second doping type source region 4 is in the range of greater than or equal to 10 15 cm -2 ;

[0074] A distance L between the upper surface of the second doping type source region 4 and the upper surface of the source region 7 is in a range of greater than or equal to 1.5 μm and less than or equal to 2.5 μm.

[0075] In an implementation, the gate is a vertical capacitive coupling gate, and the vertical capacitive coupling gate includes:

[0076] Two bottom gates 3 of the second doping type are formed in the epitaxial layer and are spaced apart in the lateral direction;

[0077] A combined top gate of the second doping type, wherein the top gate comprises a top gate inner region 81 and a top gate outer region 82, wherein the top gate inner region 81 is formed from top to bottom in the epitaxial layer, the top gate outer region 82 surrounds the bottom surface and the side surface of the top gate inner region 81, and there is a gap between the top gate outer region 82 and the bottom gate 3; wherein the doping concentration of the top gate outer region 82 is less than the doping concentration of the top gate inner region 81, and the top gate inner region 81 is in a floating state; the top gate outer region 82 can be connected to the source region 7 to be grounded, or the top gate outer region 82 can also be in a floating state;

[0078] A dielectric layer 9, located above the top gate;

[0079] A coupling capacitor upper electrode 10 is formed on the dielectric layer 9;

[0080] The top gate is indirectly controlled by the dielectric layer 9 between the upper electrode 10 of the coupling capacitor.

[0081] In the vertical capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application, the top gate outer region 82 surrounds the bottom and side surfaces of the top gate inner region 81, and the doping concentration of the top gate outer region 82 is less than the doping concentration of the top gate inner region 81, so that the potential difference of the top gate inner region 81 changes faster, and the potential difference of the top gate outer region 82 changes slowly. In this way, the flow channel for carriers is increased, and the process window of the vertical capacitively coupled gate-controlled junction field effect transistor is widened.

[0082] The theoretical basis for the slowing down of the potential difference in the top gate outer region 82 is as follows:

[0083] In the field of semiconductors, under uniform doping conditions, the potential expression at position x in a P-type doped region is The following relationship (1) is satisfied:

[0084]

[0085] Where e is the electron charge, N a is the doping concentration of the P-type doped region, εs is the semiconductor dielectric constant, x p is the position where the electric field E is zero.

[0086] From this, we can see that in two P-type doping regions with different doping concentrations, when the positions where the electric field E is zero in the two P-type doping regions are the same, which P-type doping region has the highest N? a The smaller the value, the electric potential at the same position (i.e. the same x) That is, the position x in the P-type doped region is relative to the position x where the electric field E is zero. p The potential difference is smaller, that is, the potential difference slows down. In this way, the flow channel for carriers increases, widening the process window of the vertical capacitively coupled gate-controlled junction field effect transistor.

[0087] Taking the vertical capacitor-coupled gate-controlled junction field effect transistor of the embodiment of the present application as an NMOS transistor as an example, the gate (i.e., the upper electrode 10 of the coupling capacitor) is connected to the positive voltage of the gate voltage (e.g., 15 volts), and the source of the field effect transistor is grounded. When the drain is connected to the positive voltage, an electric field is generated between the drain and the source, thereby generating a forward conduction current. The direction of the current is as follows: Figure 2-A shown.

[0088] When the gate (i.e., the upper electrode 10 of the coupling capacitor) bias voltage is less than or equal to 0V, the position where the electric field E is zero is at the upper surface of the top gate inner region 81, the potential in the top gate inner region 81 is less than or equal to 0V, the PN junction formed by the top gate outer region 82 and the channel 5 is reverse biased, the channel 5 is pinched off, and the transistor in the present application is turned off.

[0089] In the vertical type capacitive coupled gate controlled junction field effect transistor of the embodiment of the present application, the top gate of JFET region 1 is indirectly controlled by the dielectric layer 9 between the coupling capacitor upper electrode 10, and the gate voltage applied to the coupling capacitor upper electrode 10 is coupled to the top gate by coupling. At the same time, since the top gate is in a floating state and is not directly connected to the gate electrode, the potential of the coupling capacitor upper electrode 10 can be raised to more than 3V without causing the part between the top gate 8 and the bottom gate 3 to be turned on. At this time, JFET region 1 and JFET region 2 (the top gate of the second doping type, the part between the top gate and the bottom gate 3, and the bottom gate 3 form JFET region 1; the two bottom gates 3 and the part between the bottom gates 3 form JFET region 2) will not be turned on. The top gate 8 is indirectly controlled by the dielectric layer 9 between the coupling capacitor upper electrode 10, and the positive potential difference of the top gate 8 will not turn on the PN junction formed by the top gate 8 and the channel 5. Even if a high voltage (more than 3V, such as 15V, 18V) is applied to the top gate, the embodiment of the present application will not be turned on, and the device drain to source current characteristics will not be affected. At the same time, the transistor current in the present application flows through the channel 5 instead of the interface formed by the silicon carbide and the dielectric 9, and there is no influence of the interface state, so that the transistor of the present application has high reliability.

[0090] Specifically, the first doping type is P-type doping, and the second doping type is N-type doping; or the first doping type is N-type doping, and the second doping type is P-type doping.

[0091] In implementation, such as Figure 2-A , Figure 2-B , Figure 2-C and Figure 2-D As shown, the cross section of the top gate outer region 82 is U-shaped, the inner bottom of the top gate outer region 82 is wrapped around the bottom surface of the top gate inner region 81 , and the inner wall of the top gate outer region 82 is wrapped around the side surface of the top gate inner region 81 .

[0092] In this way, the top gate outer region 82 wraps the bottom and side surfaces of the top gate inner region 81, so that both the bottom and side surfaces of the top gate inner region 81 have the top gate outer region 82 with a slower potential change, making the overall process window of the top gate larger.

[0093] Specifically, the doping concentration of the top gate outer region 82 is 1 to 2 orders of magnitude lower than the doping concentration of the top gate inner region 81;

[0094] Specifically, the doping concentration of the top gate outer region 82 is in the range of greater than or equal to 2×10 17 cm -3 Less than or equal to 5×10 18 cm -3 The doping concentration of the top gate inner region 81 is in the range of greater than or equal to 1×10 19 cm -3 Less than or equal to 4×10 20 cm -3 .

[0095] Specifically, the thickness of the bottom of the top gate outer region 82 ranges from 0.02 μm to 0.2 μm, and the thickness of the sidewall of the top gate outer region 82 ranges from 0.02 μm to 0.2 μm.

[0096] The thickness of the top gate inner region 81 ranges from 0.02 μm to equal to 0.1 μm.

[0097] In implementation, such as Figure 2-A , Figure 2-B , Figure 2-C and Figure 2-D As shown, the coupling capacitor upper electrode 10, the dielectric layer 9, and the top gate constitute the gate structure of the field effect transistor;

[0098] A top gate of the second doping type, a portion between the top gate and the bottom gate 3, and the bottom gate 3 form a JFET region 1;

[0099] The two bottom gates 3 and the portion between the bottom gates 3 form a second JFET region;

[0100] The top gate of the JFET region 1 is indirectly controlled by the dielectric layer 9 between the coupling capacitor upper electrode 10 , so that the JFET region 1 and the JFET region 2 are controlled by the dielectric layer 9 between the coupling capacitor upper electrode 10 .

[0101] The first implementation method is Figure 2-A As shown, the JFET region 1 is specifically formed by the top gate, the portion of the epitaxial layer located between the top gate and the bottom gate 3, and the bottom gate 3;

[0102] The two bottom gates 3 and the portion of the epitaxial layer between the bottom gates 3 form a second JFET region.

[0103] exist Figure 2-A In the figure, the channel is located in the lateral portion between the top gate outer region 82 and the bottom gate 3.

[0104] After the second doping type source region 4 under the source region trench is implanted deeper, the potential of the channel will decrease, so it is not easy for electrons to flow through the channel.

[0105] The second implementation method is Figure 2-B As shown, the field effect transistor also includes:

[0106] A first doping type channel 51 is formed between the top gate and the bottom gate 3, the top gate is located above the channel 1, and the channel 1 51 serves as a channel of the field effect transistor;

[0107] Wherein, the JFET region 1 is specifically formed by a top gate, a channel 1 51, and a bottom gate 3;

[0108] The JFET region 2 is specifically formed by two bottom gates 3 and a portion of the epitaxial layer located between the bottom gates 3;

[0109] When the vertical capacitively coupled gate-controlled junction field effect transistor is turned off, and the PN junction of the two second-doped type source regions 4 and the portion of the epitaxial layer 2 located between the two second-doped type source regions 4 forms a reverse bias, the PN junction reduces the potential at the bottom of the channel 1 51.

[0110] After the second doping type source region 4 under the source region trench is implanted deeper, the potential of the channel (ie, channel one 51) will decrease, so it is not easy for electrons to flow through the channel (ie, channel one 51).

[0111] The third implementation method is Figure 2-C As shown, the field effect transistor also includes:

[0112] A first doping type channel 51 is formed in a portion between the top gate and the bottom gate 3, wherein the top gate is located above the channel 1;

[0113] A second channel 52 of the first doping type is formed between the two bottom gates; the first channel 51 and the second channel 52 together serve as a channel of a field effect transistor;

[0114] The JFET region 1 is specifically formed by a top gate, a channel 1 51 , and a bottom gate 3 , and the JFET region 2 is specifically formed by two bottom gates 3 and a channel 2 52 ;

[0115] When the vertical capacitively coupled gate-controlled junction field effect transistor is turned off, and the PN junction of the two second-doped type source regions 4 and the portion of the epitaxial layer 2 located between the two second-doped type source regions 4 forms a reverse bias, the PN junction reduces the potential at the bottom of the channel 2 52 .

[0116] After the second doping type source region 4 under the source region trench is implanted deeper, the potential of the channel 1 51 will decrease, so it is not easy for electrons to flow through the channel 1 51.

[0117] The third implementation method is Figure 2-D As shown, the field effect transistor also includes:

[0118] A first doping type channel 51 is formed in a portion between the top gate and the bottom gate 3, wherein the top gate is located above the channel 1;

[0119] A second channel 52 of the first doping type is formed between the two bottom gates; the first channel 51 and the second channel 52 together serve as a channel of a field effect transistor;

[0120] A current spreading layer 6 of a first doping type is formed in the epitaxial layer 2 below the bottom gate 3 and the second channel 52; the doping concentration of the current spreading layer 6 is greater than the doping concentration 2 of the epitaxial layer;

[0121] The JFET region 1 is specifically formed by a top gate, a channel 1 51, and a bottom gate 3, and the JFET region 2 is specifically formed by two bottom gates 3, a channel 2 52, and a current spreading layer 6;

[0122] When the vertical capacitively coupled gate-controlled junction field effect transistor is turned off, the PN junction of the two second doping type source regions 4 and the portion of the epitaxial layer 2 located between the two second doping type source regions 4 forms a reverse bias, and the PN junction reduces the potential at the bottom of the second channel 52 .

[0123] The doping concentrations of the first channel 51 , the second channel 52 and the current spreading layer 6 are greater than the doping concentration of the epitaxial layer, which is beneficial to reducing the on-resistance of the device and improving the device performance.

[0124] After the second doping type source region 4 under the source region trench is implanted deeper, the potential of the channel 1 51 will decrease, so it is not easy for electrons to flow through the channel 1 51.

[0125] In implementation, such as Figure 2-A , Figure 2-B , Figure 2-C and Figure 2-D As shown, two first doping type source regions 7 are respectively located on the two bottom gates, and the two first doping type source regions 7 are connected to the portion between the top gate and the bottom gate 3;

[0126] Two second doping type source regions 4 are respectively connected to both sides of the two bottom gates 3, and the second doping type source region 4, the source region 7 and the bottom gate 3 on the same side are connected;

[0127] Field effect transistors also include:

[0128] A gate electrode 11 is formed on the coupling capacitor upper electrode 10;

[0129] The buffer layer 100 is formed between the substrate 1 and the epitaxial layer 2 .

[0130] Specifically, the material of the dielectric layer 9 can be silicon dioxide or high-K dielectric. The use of high-K dielectric is more conducive to the control of the P+ type top gate by the upper electrode of the coupling capacitor, thereby improving the device performance.

[0131] Specifically, the coupling capacitor upper electrode 10 may be made of P+ type and N+ type heavily doped polysilicon to reduce the contact resistance with the gate metal and the gate parasitic resistance, thereby improving the device performance.

[0132] High-K dielectrics refer to materials with a high dielectric constant (high relative dielectric constant).

[0133] Specifically, by controlling the doping of the bottom gate 3 of the second doping type and the top gate of the second doping type, when the voltage of the electrode 10 on the coupling capacitor is zero, the region sandwiched by the bottom gate 3 and the top gate is in a depletion state, and the field effect transistor is a normally-off device;

[0134] Alternatively, by controlling the doping of the second doping type bottom gate 3 and the second doping type top gate, when the voltage of the coupling capacitor upper electrode 10 is zero, the region sandwiched by the bottom gate 3 and the top gate is in a conducting state, and the field effect transistor is a normally-on device.

[0135] The difference between the vertical capacitively coupled gate-controlled junction field effect transistor of the present application and the trench field effect transistor of the prior art is as follows:

[0136] 1. The deep trench in the source region and the second doping type source region 4 of the vertical capacitively coupled gate-controlled junction field effect transistor of the present application are used to reduce the potential at the bottom of the channel when the vertical capacitively coupled gate-controlled junction field effect transistor is turned off.

[0137] The trench field effect transistor of the prior art has a trench gate in its gate structure, and the trench gate is used to reduce the electric field strength of the gate oxide layer and enhance the stability of the gate oxide layer when the trench field effect transistor of the prior art is forward-conducted. The functions are completely different.

[0138] 2. The vertical capacitively coupled gate-controlled junction field effect transistor of the present application has a vertical capacitively coupled gate as the gate.

[0139] In the prior art trench field effect transistor, the gate is a trench gate.

[0140] They are two semiconductor devices with different structures and principles.

[0141] Figure 3-A : is a simulation diagram of a vertical capacitively coupled gate-controlled junction field effect transistor without a source region deep trench; wherein, Figure 3-A The vertical capacitively coupled gate controlled junction field effect transistor is represented by (1);

[0142] Figure 3-B : is a simulation diagram of a vertical capacitively coupled gate-controlled junction field effect transistor of an embodiment of the present application with a source region trench depth of 0.3 microns; wherein, Figure 3-B The vertical capacitively coupled gate controlled junction field effect transistor is represented by (2);

[0143] Figure 3-C : is a simulation diagram of a vertical capacitively coupled gate-controlled junction field effect transistor of an embodiment of the present application with a source region deep trench of 0.5 microns; wherein, Figure 3-C The vertical capacitively coupled gate controlled junction field effect transistor is represented by (3);

[0144] Figure 3-D : is a simulation diagram of a vertical capacitively coupled gate-controlled junction field effect transistor of an embodiment of the present application with a source region deep trench of 0.8 microns; wherein, Figure 3-D The vertical capacitively coupled gate controlled junction field effect transistor is represented by (4);

[0145] Figure 3-E : is a simulation diagram of a vertical capacitively coupled gate-controlled junction field effect transistor of an embodiment of the present application with a source region deep trench of 1.0 micron; wherein, Figure 3-E The vertical capacitively coupled gate controlled junction field effect transistor is represented by (5).

[0146] Figure 3-F for Figure 3-A to Figure 3-E Potential curve of a vertical capacitively coupled gate junction field effect transistor. Figure 3-F The horizontal axis is the lateral size of the device structure, in μm; the vertical axis is the potential of the channel, in V.

[0147] Combination Figure 3-A , Figure 3-B , Figure 3-C , Figure 3-D , Figure 3-E , Figure 3-F It can be seen that the deeper the source deep trench 71 is, the smaller the potential at the channel 1 51 position in the device is when the vertical capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application is turned off.

[0148] Figure 4-A It is a simulation diagram of leakage current of a vertical capacitively coupled gate-controlled junction field effect transistor without a source region deep trench;

[0149] Figure 4-B A leakage current simulation diagram of a vertical capacitively coupled gate-controlled junction field effect transistor of an embodiment of the present application with a source region trench depth of 0.3 microns;

[0150] Figure 4-C A leakage current simulation diagram of a vertical capacitively coupled gate-controlled junction field effect transistor of an embodiment of the present application with a source region trench depth of 0.5 microns;

[0151] Figure 4-D A leakage current simulation diagram of a vertical capacitively coupled gate-controlled junction field effect transistor of an embodiment of the present application with a source region trench depth of 0.8 microns;

[0152] Figure 4-E A leakage current simulation diagram of a vertical capacitively coupled gate-controlled junction field effect transistor of an embodiment of the present application with a source region trench depth of 1.0 micrometer;

[0153] Figure 4-F for Figure 4-A to Figure 4-E Drain current curve of vertical capacitively coupled gate junction field effect transistor. Figure 4-F The horizontal axis is the lateral size of the device structure, in μm; the vertical axis is the channel leakage current, in A.

[0154] Combination Figure 4-A , Figure 4-B , Figure 4-C , Figure 4-D , Figure 4-E , Figure 4-F It can be seen that the deeper the source deep trench is, the smaller the leakage current at the channel 1 51 position in the device is when the vertical capacitively coupled gate-controlled junction field effect transistor of the embodiment of the present application is turned off.

[0155] Figure 4-A , Figure 4-B , Figure 4-C , Figure 4-D , Figure 4-E , Figure 4-F The simulation shows that the channel potential of the structure with deep trenches in the active region is lower than that of the structure without deep trenches in the source region, and the potential is lower as the depth of the deep trenches in the source region increases. The channel leakage current of the structure with deep trenches in the active region is lower than that of the structure without deep trenches in the source region, and the channel leakage current is lower as the depth of the deep trenches in the source region increases.

[0156] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0157] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0158] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0159] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0160] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0161] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A vertical capacitively coupled gate controlled junction field effect transistor, characterized in that: include: A drain (13), a substrate (1) of a first doping type, and an epitaxial layer of a second doping type, wherein the epitaxial layer is located above the substrate (1), and the drain is formed on the back side of the substrate; Two first doping type source regions (7) are formed downward from the upper surface of the epitaxial layer, and the two first doping type source regions (7) are spaced apart in a lateral direction; Two source region deep grooves are formed downward from the upper surface of the epitaxial layer, and the two source region deep grooves are respectively formed outside the two first doping type source regions (7); Two second doping type source regions (4), each of which is formed downward from the bottom surface of the source region deep trench; A gate and a channel are formed between two source regions (7) of the first doping type; The lower surface of the second doping type source region (4) is lower than the bottom of the channel, and the second doping type source region (4) and the structure between two second doping type source regions (4) form a PN junction.

2. The vertical capacitively coupled gate controlled junction field effect transistor according to claim 1, characterized in that: Also includes: Two source electrodes (12) are respectively filled in the source region deep grooves, connected to the second doping type source region (4), and connected to the first doping type source region (7).

3. The vertical capacitively coupled gate controlled junction field effect transistor according to claim 2, characterized in that: The depth H of the second doping type source region (4) is in the range of greater than or equal to 1 μm and less than or equal to 2 μm; The implantation dose of the second doping type source region (4) is in the range of greater than or equal to 10 15 cm -2 ; The distance L between the upper surface of the second doping type source region (4) and the upper surface of the source region (7) is in the range of greater than or equal to 1.5 μm and less than or equal to 2.5 μm.

4. The vertical capacitively coupled gate controlled junction field effect transistor according to claim 2, characterized in that: The gate is a vertical capacitive coupling gate, and the vertical capacitive coupling gate includes: Two bottom gates (3) of the second doping type are formed in the epitaxial layer and are spaced apart in the lateral direction; A combined top gate of a second doping type, the top gate comprising a top gate inner region (81) and a top gate outer region (82), the top gate inner region (81) being formed from top to bottom in the epitaxial layer, the top gate outer region (82) surrounding the bottom surface and side surfaces of the top gate inner region (81), and a gap being provided between the top gate outer region (82) and the bottom gate (3); wherein the doping concentration of the top gate outer region (82) is less than the doping concentration of the top gate inner region (81), and the top gate inner region (81) is in a floating state; A dielectric layer (9), located above the top gate; A coupling capacitor upper electrode (10) formed on the dielectric layer (9); The top gate is indirectly controlled by a dielectric layer (9) spaced between the upper electrode (10) and the coupling capacitor.

5. The vertical capacitively coupled gate controlled junction field effect transistor according to claim 4, characterized in that: The cross section of the top gate outer region (82) is U-shaped, the inner bottom of the top gate outer region (82) is wrapped around the bottom surface of the top gate inner region (81), and the inner wall of the top gate outer region (82) is wrapped around the side surface of the top gate inner region (81).

6. The vertical capacitively coupled gate controlled junction field effect transistor according to claim 5, characterized in that: The doping concentration of the top gate outer region (82) is 1 to 2 orders of magnitude lower than the doping concentration of the top gate inner region (81).

7. The vertical capacitively coupled gate controlled junction field effect transistor according to claim 4, characterized in that: The coupling capacitor upper electrode (10), the dielectric layer (9), and the top gate constitute a gate structure of a field effect transistor; A top gate of the second doping type, a portion between the top gate and the bottom gate (3), and the bottom gate (3) form a JFET region 1; The two bottom gates (3) and the portion between the bottom gates (3) form a second JFET region; The top gate of the JFET region one is indirectly controlled by the dielectric layer (9) spaced between the coupling capacitor upper electrode (10), so that the JFET region one and the JFET region two are controlled by the dielectric layer (9) spaced between the coupling capacitor upper electrode (10).

8. The vertical capacitively coupled gate controlled junction field effect transistor according to claim 7, characterized in that: Also includes: A first doping type channel 1 (51), formed in a portion between the top gate and the bottom gate (3), the top gate being located above the channel 1, the channel 1 (51) serving as a channel of a field effect transistor; The JFET region 1 is specifically formed by a top gate, a channel 1 (51), and a bottom gate (3), and the JFET region 2 is specifically formed by two bottom gates (3) and a portion of the epitaxial layer located between the bottom gates (3); When the vertical capacitively coupled gate-controlled junction field effect transistor is turned off and the PN junction of the two second doping type source regions (4) and the portion of the epitaxial layer (2) located between the two second doping type source regions (4) forms a reverse bias, the PN junction reduces the potential at the bottom of the channel 1 (51).

9. The vertical capacitively coupled gate controlled junction field effect transistor according to claim 7, characterized in that: Also includes: A first doping type channel 1 (51), formed in a portion between the top gate and the bottom gate (3), the top gate being located above the channel 1; A second channel (52) of the first doping type is formed between the two bottom gates; the first channel (51) and the second channel (52) together serve as a channel of a field effect transistor; Wherein, JFET region 1 is specifically formed by a top gate, a channel 1 (51), and a bottom gate (3), and JFET region 2 is specifically formed by two bottom gates (3) and a channel 2 (52); When the vertical capacitively coupled gate-controlled junction field effect transistor is turned off and the two second doping type source regions (4) and the PN junction of the portion of the epitaxial layer (2) located between the two second doping type source regions (4) form a reverse bias, the PN junction reduces the potential at the bottom of the second channel (52).

10. The vertical capacitively coupled gate controlled junction field effect transistor according to claim 7, characterized in that: Also includes: A first doping type channel 1 (51), formed in a portion between the top gate and the bottom gate (3), the top gate being located above the channel 1; A second channel (52) of the first doping type is formed between the two bottom gates; the first channel (51) and the second channel (52) together serve as a channel of a field effect transistor; A current spreading layer (6) of a first doping type is formed in the epitaxial layer (2) at a position below the bottom gate (3) and the second channel (52); the doping concentration of the current spreading layer (6) is greater than the doping concentration of the epitaxial layer; Wherein, JFET region 1 is specifically formed by a top gate, a channel 1 (51), and a bottom gate (3), and JFET region 2 is specifically formed by two bottom gates (3) and a channel 2 (52); When the vertical capacitively coupled gate-controlled junction field effect transistor is turned off, the PN junction of the two second doping type source regions (4) and the portion of the epitaxial layer (2) located between the two second doping type source regions (4) forms a reverse bias, and the PN junction reduces the potential at the bottom of the second channel (52).

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