A high-density SiC MOSFET structure and its manufacturing process

Abstract

The present invention relates to the technical field of MOS semiconductors, and discloses a high-density SiC MOSFET structure and its manufacturing process, which is composed of a plurality of juxtaposed MOS cells. Each MOS cell includes a drain, a semiconductor epitaxial layer, a gate, and a source. The semiconductor epitaxial layer includes an N substrate layer, an N diffusion layer, a P well layer, an N well layer, and a P- layer. The cross-sectional profile of the gate is in a "T" shape, and the cross-sectional widths of the P well layer and the N well layer do not exceed the cross-sectional width of the gate. By introducing direct contact between polysilicon and the source, the present invention can amplify the electric field effect between the drain and the source. The charge of the drain mainly flows into the N diffusion layer from the metal deposition layer. Under the simultaneous action of the gate electric field and the source electric field, the charge mainly concentrates and flows towards the charge channel, which can reduce the diffusion of charge to adjacent MOS cells.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and particularly to a high-density SiC MOSFET structure and its manufacturing process. Background Art

[0002] The high-density SiC (silicon carbide) MOSFET structure aims to achieve higher current density, lower on-resistance, and faster switching speed by optimizing device design and manufacturing processes, while maintaining the high breakdown voltage, high-temperature, and high-frequency advantages of SiC materials.

[0003] A prior patent discloses a SiC MOSFET cell structure and its manufacturing method (publication number CN117976712A). The cell structure includes: source metal region source, source OHM region, source ohmic contact region N+, channel N-type doped region NC, channel P-type doped region PC, vertical conductive channel JFET region, Pwell region, drift layer N-, substrate N+, drain OHM region, gate electrode region gate, and gate-source isolation dielectric SiO2. In the technology disclosed in this patent, due to the electric field effect between the drain and the source, the charge of the drain will drift to the diffusion layer of adjacent MOS cells under the intervention of the gate electric field of adjacent MOS cells. Summary of the Invention

[0004] The main technical problem to be solved by the present invention is to provide a high-density SiC MOSFET structure and its manufacturing process, which solves the problems in the above background art.

[0005] To solve the above technical problem, according to one aspect of the present invention, more specifically, a high-density SiC MOSFET structure is provided, which is composed of a plurality of juxtaposed MOS cells. Each MOS cell includes a drain, a semiconductor epitaxial layer, a gate, and a source. The semiconductor epitaxial layer includes an N substrate layer, an N diffusion layer, a P well layer, an N well layer, and a P- layer. The cross-sectional profile of the gate is in the shape of a "T", and the cross-sectional widths of the P well layer and the N well layer do not exceed the cross-sectional width of the gate. The cross-sectional profile of the P well layer is in the shape of a "Z", and the cross-sectional profile of the N well layer is in the shape of an "L", where the P well layer and the N well layer fit together;

[0006] P- layers are formed on the left and right sides of each MOS cell by ion implantation, and polysilicon is etched and deposited inside the P- layers;

[0007] Two metal deposition layers are provided inside the N substrate layer of each MOS cell. The metal deposition layers are in ohmic contact with the drain, and the metal deposition layers are located below the connection between the P well layer and the P- layer.

[0008] Further, P-doped layers are formed on the left and right sides of the bottom of each MOS cell by ion implantation, and the P-doped layers are in contact with the metal deposition layer and the drain ohmic contact.

[0009] Further, an N+-doped layer is formed by ion implantation inside the N diffusion layer and directly above the metal deposition layer.

[0010] Further, an oxide field plate is provided inside each MOS cell and between two metal deposition layers, and the oxide field plate is in contact with the metal deposition layer and the drain.

[0011] A preparation process of a high-density SiC MOSFET structure includes the following steps:

[0012] S1. Etch the upper and lower surfaces of the semiconductor epitaxial layer forming the source region to form rectangular grooves;

[0013] S2. Fill the rectangular grooves on the upper surface with polysilicon, and form a metal deposition layer on the rectangular grooves on the lower surface by chemical vapor deposition;

[0014] S3. Deposit the drain and source after cleaning the surface of the semiconductor epitaxial layer;

[0015] S4. Measure the performance improvement of the SiC MOSFET structure.

[0016] Further, in the step S, the metal deposition layer in the rectangular groove on the lower surface includes TiSi , CoSi and NiSi materials.

[0017] Further, in the step S, passivation treatment is performed on the device formed with the drain and source.

[0018] Further, in the step S, according to the failure time of electromigration, the threshold voltage, and the turn-on time of the SiC MOSFET structure, the performance of the measured structure is determined, then there is:

[0019]

[0020] In the formula, represents the stability performance coefficient of the measured SiC MOSFET structure, represents the current density, represents the threshold voltage of the measured structure, represents the turn-on time of the measured structure.

[0021] A high-density SiC MOSFET structure and its preparation process provided by the present invention, compared with the prior art, the effects obtained by this method are:

[0022] 1. The present invention introduces direct contact between polysilicon and the source electrode, which can amplify the electric field effect between the drain and the source electrode. The charge of the drain mainly flows into the N diffusion layer from the metal deposition layer. Under the simultaneous action of the gate electric field and the source electrode electric field, the charge mainly concentrates and flows towards the charge channel, which can reduce the diffusion of charge to adjacent MOS cells.

[0023] 2. The present invention can alleviate the electric field concentration phenomenon near the drain through the P-doped layer, improve the breakdown voltage of the device, and the P-doped layer can improve the current distribution in the device, reduce the on-resistance. Moreover, the ohmic contact between the P-doped layer and the drain can improve the heat conduction path and reduce the thermal resistance of the device.

[0024] 3. The present invention can make the charge mainly flow into the charge channel and the charge channel along the vertical direction by setting an N+-doped layer directly above the metal deposition layer, which can block the conduction path of the parasitic bipolar transistor, thereby suppressing the latch-up effect. In high-voltage or high-current applications, the enhanced anti-latch-up ability can significantly improve the reliability of the device.

[0025] 4. The present invention can directly block the formation of the shortest path between the gate and the drain through the oxide field plate, so as to improve the breakdown resistance of the SiC MOSFET structure without reducing the gate electric field effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a schematic structural diagram of Embodiment 1 of the present invention;

[0027] Figure 2 It is a schematic structural diagram of Embodiment 2 of the present invention;

[0028] Figure 3 It is a schematic structural diagram of Embodiment 3 of the present invention;

[0029] Figure 4 It is a schematic structural diagram of Embodiment 4 of the present invention;

[0030] Figure 5 It is a schematic diagram of the electric field direction after the SiC MOSFET structure of the present invention is connected to the gate voltage;

[0031] Figure 6 It is a schematic diagram of the arrangement of MOS cells of the present invention.

[0032] In the figure: 1. Drain; 2. N substrate layer; 3. N diffusion layer; 4. P well layer; 5. N well layer; 6. Gate; 7. Source; 8. Polysilicon; 9. P layer; 10. Metal deposition layer; 11. P-doped layer; 12. N+-doped layer; 13. Oxide field plate. DETAILED DESCRIPTION OF THE INVENTION

[0033] To make the technical solution of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0034] A preparation process of a high-density SiC MOSFET structure includes the following steps:

[0035] Step 1: Etch the upper and lower surfaces of the semiconductor epitaxial layer forming the source region to form rectangular grooves.

[0036] Step 2: Fill the rectangular grooves on the upper surface to form polysilicon 8, and form a metal deposition layer 10 on the rectangular grooves on the lower surface by chemical vapor deposition; the metal deposition layer 10 in the rectangular grooves on the lower surface includes TiSi 、CoSi and NiSi materials.

[0037] Step 3: Deposit a drain 1 and a source 7 on the surface of the semiconductor epitaxial layer after cleaning; perform a passivation treatment on the device formed with the drain 1 and the source 7.

[0038] Step 4: Measure the performance improvement of the SiC MOSFET structure. According to the failure time of electromigration, the threshold voltage, and the turn-on time of the SiC MOSFET structure, the performance of the measured structure is determined. Then, there is:

[0039]

[0040] In the formula, g represents the comprehensive stability performance of the measured SiC MOSFET structure, which is a dimensionless coefficient used to quantify the performance improvement effect of the device under parameters such as current density, threshold voltage, and switching speed.

[0041] m represents the current intensity passing through per unit area, reflecting the current-carrying capacity of the device. The greater the current density, the stronger the conduction ability of the device, but it may lead to an increase in the thermal effect.

[0042] u represents the minimum gate voltage required for the MOSFET to start conducting, determining the turn-on characteristics of the device. The lower the threshold voltage, the easier it is for the device to turn on, but it may affect the turn-off stability.

[0043] t represents the time required for the device to change from the off state to the fully on state, reflecting the switching speed. The shorter the turn-on time, the better the high-frequency performance of the device.

[0044] Among them, when calculating the stability performance coefficient of the measured SiC MOSFET structure. The current density of the measured SiC MOSFET structure is taken (MA / cm²), and the threshold voltage of the measured SiC MOSFET structure is taken (V), the turn-on time of the measured SiC MOSFET structure is taken as (ns), then there is:

[0045]

[0046] It can be known from the above calculation that the stability performance coefficient of the measured SiC MOSFET structure this time is . If the stability performance coefficient of the SiC MOSFET structure under the traditional process is calculated to be , then the stability performance of the measured SiC MOSFET structure this time is improved by 7.2%.

[0047] Embodiment 1

[0048] As Figure 1 , 5 , shown in 6, according to one aspect of the present invention, a high-density SiC MOSFET structure is provided, which includes a plurality of MOS cells arranged side by side. A single MOS cell includes a drain 1, a semiconductor epitaxial layer, a gate 6, and a source 7. The semiconductor epitaxial layer includes an N substrate layer 2, an N diffusion layer 3, a P well layer 4, an N well layer 5, and a P- layer 9. It is characterized in that: the cross-sectional profile of the gate 6 is in a "T" shape, and the cross-sectional widths of the P well layer 4 and the N well layer 5 do not exceed the cross-sectional width of the gate 6. The cross-sectional profile of the P well layer 4 is in a "Z" shape, and the cross-sectional profile of the N well layer 5 is in an "L" shape, and the P well layer 4 and the N well layer 5 fit each other. P- layers 9 are formed on the left and right sides of a single MOS cell by ion implantation, and polysilicon 8 is etched and deposited inside the P- layers 9; two metal deposition layers 10 are provided in the N substrate layer 2 of a single MOS cell. The metal deposition layer 10 is in ohmic contact with the drain 1, and the metal deposition layer 10 is located below the connection between the P well layer 4 and the P- layer 9. After a gate voltage is applied to the gate 6, a charge channel 1 will be formed in the P well layer 4 (as Figure 6 shown), and at this time, a path can be formed between the drain 1 and the source 7. And under the action of the T-shaped gate 6, a weak charge channel 2 will also be formed between the P well layer 4 and the P- layer 9 to connect the N well layer 5 and the N diffusion layer 3.

[0049] And at this time, an electric field will also be formed directly between the drain 1 and the source 7, but the electric field strength will be weaker than the electric field formed between the gate 6 and the drain 1. At this time, polysilicon 8 is introduced into direct contact with the source 7, so as to amplify the electric field effect between the drain 1 and the source 7 (the principle is to increase the electric field effect by reducing the distance between the drain 1 and the source 7). The charge of the drain 1 mainly flows into the N diffusion layer 3 from the metal deposition layer 10. In this way, under the simultaneous action of the gate electric field and the source electric field, the charge mainly flows concentratedly to the charge channel 1 and the charge channel 2, so as to reduce the diffusion of the charge to adjacent MOS cells.

[0050] Example 2

[0051] As Figure 2 shown, P-doped layers 11 are formed by ion implantation on the left and right sides of the bottom of a single MOS cell. The P-doped layers 11 are in ohmic contact with the metal deposition layer 10 and the drain 1. The P-doped layers 11 can alleviate the electric field concentration phenomenon near the drain, improve the breakdown voltage of the device, and the P-doped layers 11 can improve the current distribution in the device, reduce the on-resistance, and the ohmic contact between the P-doped layers 11 and the drain 1 can improve the heat conduction path and reduce the thermal resistance of the device.

[0052] Example 3

[0053] As Figure 3 shown, an N+-doped layer 12 is formed by ion implantation inside the N diffusion layer 3 and directly above the metal deposition layer 10. Setting the N+-doped layer 12 directly above the metal deposition layer 10 can make the charge mainly flow into the charge channels 1 and 2 along the vertical direction, which can block the conduction path of the parasitic bipolar transistor, thereby suppressing the latch-up effect. In high-voltage or high-current applications, the enhanced anti-latch-up ability can significantly improve the reliability of the device.

[0054] Example 4

[0055] As Figure 4 shown, an oxide field plate 13 is provided inside a single MOS cell and between two metal deposition layers 10. The oxide field plate 13 is in contact with the metal deposition layer 10 and the drain 1. The oxide field plate 13 can directly block the formation of the shortest path between the gate 7 and the drain 1, so as to improve the breakdown resistance of the SiC MOSFET structure without reducing the effect of the gate electric field.

[0056] The above-described embodiments merely represent several implementation manners of the present invention, and their descriptions are relatively specific and detailed, but should not be construed as limiting the scope of the present invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention patent shall be subject to the appended claims.

Claims

1. A high-density SiC MOSFET structure, which is composed of a plurality of mutually juxtaposed MOS cells. Each single MOS cell sequentially includes a drain (1), a semiconductor epitaxial layer, a gate (6), and a source (7) from bottom to top; the semiconductor epitaxial layer sequentially includes an N substrate layer (2), an N diffusion layer (3), a P well layer (4), and an N well layer (5) from bottom to top, and is characterized in that: The cross-sectional profile of the gate (6) is in a "T" shape. The gate (6) includes a transverse part and a longitudinal part. The P-well layer (4) and the N-well layer (5) are located on both sides of the longitudinal part. The cross-sectional profile of the P-well layer (4) is in a "Z" shape, and the cross-sectional profile of the N-well layer (5) is in an "L" shape, where the P-well layer (4) and the N-well layer (5) fit each other; The semiconductor epitaxial layer further includes a P-layer (9), which is located on the left and right sides of a single MOS cell and contacts the source electrode (7). The inside of the P-layer (9) is etched and polysilicon (8) is deposited. The polysilicon (8) is located between the source electrode (7) and the P-layer (9), and the polysilicon (8) contacts the source electrode (7); Two metal deposition layers (10) are provided in the N-substrate layer (2) of a single MOS cell. The metal deposition layers (10) are in ohmic contact with the drain electrode (1), and the metal deposition layers (10) are located below the connection of the P-well layer (4) and the P-layer (9).

2. The high-density SiC MOSFET structure according to claim 1, characterized in that: P-doped layers (11) are formed by ion implantation on the left and right sides at the bottom of a single MOS cell, where the P-doped layers (11) are in ohmic contact with the metal deposition layers (10) and the drain electrode (1).

3. The high-density SiC MOSFET structure according to claim 1, characterized in that: An N+-doped layer (12) is formed by ion implantation inside the N-diffusion layer (3) and directly above the metal deposition layer (10).

4. The high-density SiC MOSFET structure according to claim 1, characterized in that: An oxide field plate (13) is provided inside a single MOS cell and between the two metal deposition layers (10), where the oxide field plate (13) contacts the metal deposition layers (10) and the drain electrode (1).

5. A manufacturing process for a high-density SiC MOSFET structure, characterized in that, Applied to the SiC MOSFET structure according to any one of claims 1-4, the preparation process of the high-density SiC MOSFET structure includes the following steps: S1. Etch the upper and lower surfaces of the semiconductor epitaxial layer forming the source region to form rectangular grooves; S2. Fill the rectangular groove on the upper surface to form polysilicon (8), and form a metal deposition layer (10) on the rectangular groove on the lower surface by chemical vapor deposition; S3. After cleaning the surface of the semiconductor epitaxial layer, deposit the drain electrode (1) and the source electrode (7); S4. Measure the performance improvement of the SiC MOSFET structure.

6. The manufacturing process of the high-density SiC MOSFET structure according to claim 5, characterized in that: In the step S2, the metal deposition layer (10) in the rectangular groove on the lower surface includes TiSi2, CoSi2, and NiSi materials.

7. The manufacturing process of the high-density SiC MOSFET structure according to claim 5, characterized in that: In the step S3, passivate the device formed with the drain electrode (1) and the source electrode (7).

8. The manufacturing process of the high-density SiC MOSFET structure according to claim 5, characterized in that: In the step S4, determine the performance of the measured structure according to the failure time of electromigration, the threshold voltage, and the turn-on time of the SiC MOSFET structure in the SiC MOSFET structure. Then there is: In the formula, g represents the stability performance coefficient of the measured SiC MOSFET structure, m represents the current density, u represents the threshold voltage of the measured structure, and t represents the turn-on time of the measured structure.

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