Thin film transistor and manufacturing method thereof

Abstract

The invention provides a thin film transistor and a manufacturing method thereof, and the thin film transistor comprises a substrate, a source-drain functional layer located on the substrate, and a channel layer located on the source-drain functional layer. Wherein the source-drain functional layer comprises a source electrode, a drain electrode and a dielectric layer used for isolating the source electrode from the drain electrode; the dielectric layer comprises a first part and a second part which are connected in sequence; the first part extends along a first direction, is positioned between the source electrode and the drain electrode, and is in direct contact with the side wall of the source electrode and the side wall of the drain electrode; the second part extends along a second direction intersected with the first direction, is positioned between the drain electrode and the substrate, and is in direct contact with the bottom of the drain electrode; and the source electrode, the first part and the drain electrode are in contact with the channel layer.

Description

Technical Field

[0001] The present invention relates to the technical field of thin film transistors, and in particular to a thin film transistor and a manufacturing method thereof. Background Art

[0002] At present, with the improvement of the resolution of flat panel displays and sensor arrays, higher requirements are placed on the size of active drive element thin film transistors. The average channel length of existing oxide, polysilicon and other thin film transistors is 1-3um. Further size reduction will make its channel length enter the sub-micron region.

[0003] In the process of developing short-channel thin-film transistors, how to achieve sub-micron spacing in large-area glass-based semiconductor processes has become a technical problem that needs to be solved urgently. Summary of the invention

[0004] The invention provides a thin film transistor and a manufacturing method thereof, which are used to obtain a large-area glass-based short-channel thin film transistor.

[0005] In a first aspect, an embodiment of the present invention provides a thin film transistor, including:

[0006] A substrate, a source-drain functional layer located on the substrate, and a channel layer located on the source-drain functional layer;

[0007] Wherein, the source-drain functional layer includes a source, a drain and a dielectric layer for isolating the source and the drain; the dielectric layer includes a first part and a second part connected in sequence; the first part is extended along a first direction, and is located between the source and the drain, and is in direct contact with the side walls of the source and the drain; the second part is extended along a second direction intersecting with the first direction, and is located between the drain and the substrate, and is in direct contact with the bottom of the drain; the source, the first part and the drain are all in contact with the channel layer.

[0008] In a possible implementation manner, the source, the first portion, and the drain are arranged flush with each other on a side facing away from the substrate.

[0009] In a possible implementation manner, along the first direction, the sum of the thicknesses of the drain and the second portion is substantially equal to the thickness of the source.

[0010] In a possible implementation manner, it further includes a gate layer and a gate insulating layer located between the substrate and the source-drain functional layer, and the gate insulating layer is located between the source-drain functional layer and the gate layer.

[0011] In a possible implementation manner, it further includes a gate insulating layer and a gate layer which are sequentially arranged on a side of the channel layer away from the substrate.

[0012] In one possible implementation, the gate layer includes a first branch extending along the first direction and a second branch extending along the second direction, the first branch is connected to the second branch and is arranged in a T-shape, and the orthographic projection of the first branch on the substrate completely falls within the area of ​​the orthographic projection of the second branch on the substrate.

[0013] In a possible implementation manner, the material of the drain electrode is a high-functional metal, and the drain electrode contacts the channel layer to form a Schottky layer.

[0014] In a possible implementation manner, an orthographic projection of the first portion on the substrate completely falls within the region of an orthographic projection of the gate layer on the substrate.

[0015] In a possible implementation manner, an extension length of the first portion along the second direction is 100 nm to 500 nm.

[0016] In a second aspect, an embodiment of the present invention further provides a method for manufacturing a thin film transistor, comprising:

[0017] Depositing at least two metal layers sequentially on a substrate;

[0018] Performing patterning on the at least two metal layers to obtain a processed metal layer, wherein the top metal layer in the processed metal layer is a sacrificial layer;

[0019] forming a whole insulating layer on the processed metal layer;

[0020] forming a pattern of a drain metal layer on the insulating layer, wherein an orthographic projection of the drain metal layer on the substrate overlaps with an orthographic projection of the processed metal layer on the substrate;

[0021] Patterning the insulating layer according to the pattern of the drain metal layer to obtain a processed insulating layer;

[0022] The sacrificial layer is released, and the remaining portion of the at least two metal layers except the sacrificial layer is retained on the substrate, and the patterns of the processed insulating layer and the source-drain metal layer form a hollow cantilever beam structure;

[0023] The cantilever beam structure is removed along a side of the remaining portion away from the substrate, and a source-drain functional layer is formed on the substrate, wherein the source-drain functional layer includes a source electrode, a drain electrode, and a dielectric layer for isolating the source electrode and the drain electrode; the remaining portion forms the source electrode, the portion of the treated insulating layer except for the cantilever beam portion forms the dielectric layer, and the portion of the pattern of the drain metal layer except for the cantilever beam portion forms the drain electrode; the dielectric layer includes a first portion and a second portion connected in sequence; the first portion is extended along a first direction, and is located between the source electrode and the drain electrode, and is in direct contact with the sidewalls of the source electrode and the sidewalls of the drain electrode;

[0024] A pattern of a channel layer is formed on the source-drain functional layer, wherein the source electrode, the first portion and the drain electrode are all in contact with the channel layer.

[0025] In a possible implementation manner, the step of sequentially depositing at least two metal layers on the substrate includes:

[0026] forming a pattern of a gate layer on the substrate;

[0027] forming a pattern of a gate insulating layer on the gate layer;

[0028] At least two metal layers are sequentially deposited on a side of the gate insulating layer facing away from the substrate.

[0029] In a possible implementation manner, after forming a pattern of a channel layer on the source / drain functional layer, the method further includes:

[0030] forming a pattern of a gate insulating layer on a side of the channel layer facing away from the substrate;

[0031] A pattern of a gate layer is formed on a side of the gate insulating layer facing away from the substrate.

[0032] In a possible implementation manner, forming a pattern of a gate layer on a side of the gate insulating layer facing away from the substrate includes:

[0033] At least two glue layers are sequentially arranged on the gate insulating layer, wherein the exposure sensitivity of the glue layer close to the substrate among the at least two glue layers is less than the exposure sensitivity of the other glue layers;

[0034] Performing patterning treatment on the at least two adhesive material layers to obtain treated adhesive material layers;

[0035] forming a whole gate metal layer on the processed glue layer;

[0036] The processed glue layer is removed to form a pattern of the gate layer, wherein the gate layer includes a first branch extending along the first direction and a second branch extending along the second direction, wherein the first branch is connected to the second branch and is arranged in a T-shape, and the orthographic projection of the first branch on the substrate completely falls within the area of ​​the orthographic projection of the second branch on the substrate.

[0037] The beneficial effects of the present invention are as follows:

[0038] The embodiment of the present invention provides a thin film transistor and a manufacturing method thereof, wherein the thin film transistor includes a substrate, a source-drain functional layer located on the substrate, and a channel layer located on the source-drain functional layer; wherein the source-drain functional layer includes a source electrode, a drain electrode, and a dielectric layer for isolating the source electrode and the drain electrode; the dielectric layer includes a first part and a second part connected in sequence; the first part is extended along a first direction, and is located between the source electrode and the drain electrode, and is in direct contact with the side wall of the source electrode and the side wall of the drain electrode; exemplarily, the first direction is a direction perpendicular to the plane where the substrate is located; the second part is extended along a second direction intersecting with the first direction, and is located between the drain electrode and the substrate, and is in direct contact with the bottom of the drain electrode; exemplarily, the second direction is a direction parallel to the plane where the substrate is located; and the source electrode, the first part, and the drain electrode are all in contact with the channel layer. In this way, the first part in the dielectric layer can not only effectively isolate the source electrode and the drain electrode; but also, in actual preparation, the channel region of the thin film transistor can be set by adjusting the first part, thereby providing a guarantee for the subsequent realization of the short channel design of the thin film transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A schematic diagram of a structure of a thin film transistor provided by an embodiment of the present invention;

[0040] Figure 2 A schematic diagram of a structure of a thin film transistor provided by an embodiment of the present invention;

[0041] Figure 3 A schematic diagram of a structure of a thin film transistor provided by an embodiment of the present invention;

[0042] Figure 4 A schematic diagram of a structure of a thin film transistor provided by an embodiment of the present invention;

[0043] Figure 5 A schematic diagram of a structure of a thin film transistor provided by an embodiment of the present invention;

[0044] Figure 6 A method flow chart of a method for manufacturing a thin film transistor provided by an embodiment of the present invention;

[0045] Figure 7 for Figure 6 The method flow chart of step S101 in FIG.

[0046] Figure 8 For Figure 6 The method flow chart after step S108;

[0047] Fig. 9 for Figure 8 The method flow chart of step S302 in FIG.

[0048] Fig.10 for Figure 2 The process flow chart of manufacturing the thin film transistor shown;

[0049] Fig.11 for Figure 3 The process flow chart of manufacturing the thin film transistor shown;

[0050] Fig.12 for Figure 4 One of the process flow charts of the gate layer in the thin film transistor shown;

[0051] Fig.13 for Figure 4 Another process flow chart of a gate layer in a thin film transistor shown;

[0052] Description of reference numerals:

[0053] 10-substrate; 20-source-drain functional layer; 30-channel layer; 21-source; 22-drain; 23-dielectric layer; 231-first part; 232-second part; 40-gate layer; 50-gate insulating layer; 60-passivation layer; 41-first branch; 42-second branch; 70-first glue layer; 80-second glue layer; 90-third glue layer; 100-fourth glue layer; 110-fifth glue layer. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. And in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. Based on the described embodiments of the present invention, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present invention.

[0055] Unless otherwise defined, the technical terms or scientific terms used in the present invention should be understood by people with ordinary skills in the field to which the present invention belongs. The words "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0056] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual proportions, but are only intended to illustrate the content of the present invention. The same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions.

[0057] For large-area glass-based semiconductor processes, the resolution of commercial photolithography machines is relatively limited, and it is difficult to prepare sub-micron spacing patterns, which limits the development of sub-micron short-channel thin-film transistors. In the relevant technology, the following three process methods can be used to prepare sub-micron spacing on a large area: the first is electron beam exposure, through which patterns with a spacing as low as 8nm can be prepared, but its yield is low and not suitable for large-scale production; the second is nanoimprinting, through which patterns with a spacing of about 60nm can currently be prepared, but the process yield, such as glue residue, poor consistency, and difficult alignment, and the cost / area is still limited; the third is sub-micron high-precision ultraviolet exposure, but this equipment is generally suitable for wafer manufacturing and is not suitable for large-area glass-based semiconductor processes. Therefore, how to achieve sub-micron spacing in large-area glass-based semiconductor processes has become the primary technical problem to be solved in the process of developing short-channel thin-film transistors.

[0058] In view of this, an embodiment of the present invention provides a thin film transistor and a method for manufacturing the same, which are used to obtain a large-area glass-based short-channel thin film transistor.

[0059] like Figure 1 As shown, an embodiment of the present invention provides a thin film transistor, including:

[0060] A substrate 10, a source-drain functional layer 20 located on the substrate 10, and a channel layer 30 located on the source-drain functional layer 20;

[0061] The source-drain functional layer 20 includes a source 21, a drain 22 and a dielectric layer 23 for isolating the source 21 and the drain 22; the dielectric layer 23 includes a first part 231 and a second part 232 connected in sequence; the first part 231 is extended along a first direction, and is located between the source 21 and the drain 22, and is in direct contact with the side walls of the source 21 and the drain 22; the second part 232 is extended along a second direction intersecting the first direction, and is located between the drain 22 and the substrate 10, and is in direct contact with the bottom of the drain 22; the source 21, the first part 231 and the drain 22 are all in contact with the channel layer 30.

[0062] In the specific implementation process, the thin film transistor includes a substrate 10, a source-drain functional layer 20 located on the substrate 10, and a channel layer 30 located on the source-drain functional layer 20; illustratively, the substrate 10 can be a flexible substrate or a rigid substrate. For example, the substrate 10 is a glass-based substrate or a silicon-based substrate, which is not limited here. In addition, the material of the channel layer 30 can be IGZO, and its thickness can range from 40nm to 60nm. Exemplarily, the thickness of the channel layer 30 is 40nm. Of course, the material of the channel layer 30 can also be set according to the actual application needs, such as oxide, amorphous silicon, polycrystalline silicon, etc., which is not limited here.

[0063] Moreover, the source-drain functional layer 20 includes a source 21, a drain 22 and a dielectric layer 23 for isolating the source 21 and the drain 22; exemplarily, the dielectric layer 23 can be made of SiOx, and can also be made of SiNx. In this way, the short circuit between the source 21 and the drain 22 is effectively avoided, and the performance of the thin film transistor is guaranteed. Among them, the dielectric layer 23 includes a first part 231 and a second part 232 connected in sequence, and the first part 231 extends along a first direction and is located between the source 21 and the drain 22, and is in direct contact with the side walls of the source 21 and the drain 22; exemplarily, the first direction is a direction perpendicular to the plane where the substrate 10 is located, and the direction can be as follows Figure 1 As shown by the arrow X in the figure. The source 21 and the drain 22 are effectively isolated by the first part 231. In addition, the second part 232 is extended along a second direction intersecting the first direction, and is located between the drain 22 and the substrate 10, and is in direct contact with the bottom of the drain 22; the source 21, the first part 231 and the drain 22 are all in contact with the channel layer 30. Figure 1 In the exemplary embodiment shown, the cross-sectional shape of the dielectric layer 23 is “L”-shaped along a direction perpendicular to the plane of the substrate 10 ; accordingly, the first portion 231 and the second portion 232 of the dielectric layer 23 form an “L”-shaped structure.

[0064] In actual preparation, the channel region of the thin film transistor is set by adjusting the first portion 231 , for example, adjusting the deposition thickness of the dielectric layer 23 , thereby providing a guarantee for the subsequent implementation of the short channel design of the thin film transistor.

[0065] It should be noted that, in the embodiment of the present invention, the channel length of the thin film transistor is approximately equal to the distance between the source electrode 21 and the drain electrode 22, that is, the extension length of the first portion 231 in the dielectric layer 23 along the second direction. In the specific implementation process, by adjusting the deposition thickness of the dielectric layer 23, the channel length of the thin film transistor can be adaptively adjusted, which simplifies the manufacturing process of the thin film transistor.

[0066] In the embodiment of the present invention, the source 21 , the first portion 231 , and the drain 22 are arranged flush with each other on a side facing away from the substrate 10 .

[0067] Still combined Figure 1 In the exemplary embodiment shown, the source 21, the first portion 231 and the drain 22 are arranged flush on the side away from the substrate 10, and the dotted line L in the figure shows the edge of the source 21, the first portion 231 and the drain 22 on the side away from the substrate 10, and the dotted line L is parallel to the direction of the plane where the substrate 10 is located. In this way, the flatness of the subsequent film layer arrangement is guaranteed.

[0068] In the embodiment of the present invention, along the first direction, the sum of the thicknesses of the drain electrode 22 and the second portion 232 is substantially equal to the thickness of the source electrode 21 .

[0069] Still combined Figure 1 In the exemplary embodiment shown, d1 represents the thickness of the drain 22 along the first direction, d2 represents the thickness of the second portion 232 along the first direction, and d3 represents the thickness of the source 21 along the first direction. In actual preparation, the thickness relationship between the three satisfies the following relationship: d1+d2=d3. It should be noted that the "equal" here does not mean completely equal, but can be approximately equal or roughly equal. In practical applications, the specific values ​​of d1, d2 and d3 can be set as needed, and are not limited here. For example, d3 is 300nm, d1 is 100nm, and d2 is 200nm.

[0070] In the embodiment of the present invention, the thin film transistor may be a bottom gate structure or a top gate structure, which is not limited here.

[0071] In one exemplary embodiment, Figure 2 As shown, the thin film transistor further includes a gate layer 40 and a gate insulating layer 50 located between the substrate 10 and the source-drain functional layer 20 , and the gate insulating layer 50 is located between the source-drain functional layer 20 and the gate layer 40 .

[0072] Still combined Figure 2 In the exemplary embodiment shown, the thin film transistor can be a bottom gate structure. Specifically, the thin film transistor also includes a gate layer 40 and a gate insulating layer 50 located between the substrate 10 and the source and drain functional layer 20. Exemplarily, the gate layer 40 is prepared by a gate metal layer, and the gate metal layer can be Mo, and its thickness can range from 200nm to 300nm. In addition, the gate insulating layer 50 is located between the source and drain functional layer 20 and the gate layer 40, thereby ensuring the insulation performance between the source and drain functional layer 20 and the gate layer 40. Exemplarily, the material of the gate insulating layer 50 can be SiNx or SiOx, which is not limited here; the thickness of the gate insulating layer 50 can range from 100nm to 300nm. In the actual preparation process, the thickness of the gate insulating layer 50 is greater than the thickness of the gate layer 40, thereby ensuring that the gate insulating layer 50 effectively covers the gate. For example, the thickness of the gate layer 40 is 200nm, and the thickness of the gate insulating layer 50 is 300nm. Of course, the specific thickness of the gate layer 40 and the gate insulating layer 50 and the specific materials of the gate layer 40 and the gate insulating layer 50 may be set according to actual application requirements, which are not limited here.

[0073] Still combined Figure 2 In the exemplary embodiment shown, the thickness of the channel layer 30 ranges from 40nm to 60nm; the thin film transistor also includes a passivation layer 60 located on the side of the channel layer 30 away from the substrate 10. The material of the passivation layer 60 can be SiOx or SiNx, which is not limited here. On the one hand, it effectively isolates the corrosion of the thin film transistor by external water and oxygen; on the other hand, it provides the possibility for the subsequent related wiring and electrode extraction. It should be noted that in Figure 2 In the exemplary embodiment shown, the material of the source 21 and the drain 22 can be the same material, for example, one of Mo, Ti, and Cu. In addition, the materials of the source 21 and the drain 22 can also be different materials, for example, the material of the source 21 is Mo, and the material of the drain 22 is Ti. Of course, the specific materials of the source 21 and the drain 22 can be set according to actual application needs, and are not limited here.

[0074] It should be noted that in Figure 2 In the exemplary embodiment shown, the thin film transistor further includes a passivation layer 60 located on the side of the channel layer 30 facing away from the substrate 10. The material of the passivation layer 60 can be SiOx or SiNx. If the extension length of the first portion 231 along the second direction is 140nm, the material of the channel layer 30 is IGZO, and the corresponding thin film transistor is a bottom gate 140nm short channel IGZO transistor. In addition, Figure 2In the exemplary embodiment shown, the orthographic projection of the first part 231 on the substrate 10 completely falls within the area of ​​the orthographic projection of the gate layer 40 on the substrate 10, thereby ensuring that the orthographic projection of the effective channel in the channel layer 30 on the substrate 10 completely falls within the area of ​​the orthographic projection of the gate layer 40 on the substrate 10, thereby ensuring the performance of the thin film transistor.

[0075] In one exemplary embodiment, Figure 3 As shown, the thin film transistor further includes a gate insulating layer 50 and a gate layer 40 which are sequentially arranged on a side of the channel layer 30 away from the substrate 10 .

[0076] Still combined Figure 3 In the exemplary embodiment shown, the thin film transistor can be a top gate structure. Specifically, the thin film transistor also includes a gate insulating layer 50 and a gate layer 40 which are sequentially arranged on the side of the channel layer 30 away from the substrate 10. The gate insulating layer 50 is located between the gate layer 40 and the channel layer 30, thereby ensuring the insulation performance between the gate layer 40 and the channel layer 30. Exemplarily, the material of the gate insulating layer 50 can be SiNx or SiOx, which is not limited here; the gate layer 40 is prepared by a gate metal layer, and exemplary, the gate metal layer can be Mo, and its thickness is 300nm. In the actual preparation process, the thickness of the gate insulating layer 50 is greater than the thickness of the channel layer 30, thereby ensuring that the gate insulating layer 50 effectively covers the channel layer 30. Exemplarily, the thickness of the channel layer 30 ranges from 40nm to 60nm. Of course, the specific thickness of the gate insulating layer 50 and the channel layer 30, as well as the specific materials of the gate insulating layer 50 and the channel layer 30, can be set according to the actual application needs, which are not limited here.

[0077] Still combined Figure 3 In the exemplary embodiment shown, the orthographic projection of the first portion 231 on the substrate 10 completely falls within the region of the orthographic projection of the gate layer 40 on the substrate 10. In this way, it is ensured that the orthographic projection of the effective channel in the channel layer 30 on the substrate 10 completely falls within the region of the orthographic projection of the gate layer 40 on the substrate 10, thereby ensuring the performance of the corresponding thin film transistor. Figure 3 In the exemplary embodiment shown, the orthographic projection of the gate layer 40 on the substrate 10 completely falls within the region of the orthographic projection of the channel layer 30 on the substrate 10. In the specific implementation process, the specific structural parameters of the channel layer 30 and the gate layer 40 can be set according to actual application requirements, which are not limited here.

[0078] It should be noted that in Figure 3In the exemplary embodiment shown, the thin film transistor further includes a passivation layer 60 located on the side of the gate layer 40 facing away from the substrate 10. The material of the passivation layer 60 may be SiOx or SiNx. If the extension length of the first portion 231 along the second direction is 140nm, the material of the channel layer 30 is IGZO, and the corresponding thin film transistor is a top gate 140nm short channel IGZO transistor.

[0079] In one exemplary embodiment, Figure 4 As shown, the gate layer 40 includes a first branch 41 extending along the first direction and a second branch 42 extending along the second direction, the first branch 41 is connected to the second branch 42 and is arranged in a T-shape, and the orthographic projection of the first branch 41 on the substrate 10 completely falls within the area of ​​the orthographic projection of the second branch 42 on the substrate 10.

[0080] Still combined Figure 4 In the exemplary embodiment shown, the thin film transistor has a top gate structure. Figure 3 For the exemplary embodiment shown in the figure, except for the gate layer 40, the specific configuration of other structures can refer to the aforementioned Figure 3 The description of the corresponding part of the corresponding embodiment. Figure 4 In the exemplary embodiment shown, the gate layer 40 includes a first branch 41 extending along a first direction and a second branch 42 extending along a second direction, and the first branch 41 is connected to the second branch 42 and is arranged in a T-shape. In this way, a T-type gate thin film transistor is formed. Exemplarily, the gate layer 40 is a structure formed by integrating the first branch 41 and the second branch 42; the orthographic projection of the first branch 41 on the substrate 10 completely falls within the area of ​​the orthographic projection of the second branch 42 on the substrate 10. Accordingly, along the second direction, the extension length of the second branch 42 is greater than the extension length of the first branch 41. The specific structural parameters of the first branch 41 and the second branch 42 can be set according to the actual application needs and are not limited here.

[0081] It should be noted that in Figure 4 In the exemplary embodiment shown, the orthographic projection of the first portion 231 in the dielectric layer 23 on the substrate 10 completely falls within the region of the orthographic projection of the first branch 41 on the substrate 10. In this way, it is ensured that the orthographic projection of the effective channel in the channel layer 30 on the substrate 10 completely falls within the region of the orthographic projection of the first branch 41 in the gate layer 40 on the substrate 10, thereby ensuring the performance of the corresponding thin film transistor. In addition, Figure 4In the exemplary embodiment shown, the orthographic projection of the gate layer 40 on the substrate 10 completely falls within the region of the orthographic projection of the channel layer 30 on the substrate 10. In the specific implementation process, the specific structural parameters of the first branch 41 and the second branch 42 in the channel layer 30 and the gate layer 40 can be set according to actual application requirements, which are not limited here.

[0082] It should be noted that Figure 4 The T-gate thin film transistor shown in FIG. Figure 3 The thin film transistor shown in the figure greatly reduces the overlapping parasitic capacitance between the gate and the source 21 and the drain 22, and is more suitable for application in high-speed driving circuits. Figure 4 In the exemplary embodiment shown, the thin film transistor further includes a passivation layer 60 located on the side of the gate layer 40 facing away from the substrate 10. The material of the passivation layer 60 can be SiOx or SiNx. The orthographic projection of the gate layer 40 on the substrate 10 completely falls within the area of ​​the orthographic projection of the channel layer 30 on the substrate 10. In this way, the performance of the corresponding thin film transistor is guaranteed. Figure 4 In the exemplary embodiment shown, if the extension length of the first portion 231 along the second direction is 140 nm, the material of the channel layer 30 is IGZO, and the corresponding thin film transistor is a T-gate 140 nm short channel IGZO transistor.

[0083] In one exemplary embodiment, Figure 5 As shown, the material of the drain electrode 22 is a high-functional metal, and the drain electrode 22 contacts the channel layer 30 to form a Schottky layer.

[0084] Still combined Figure 5 In the exemplary embodiment shown, the material of the drain 22 is a high-function metal, such as Pd, Au, Pt, etc. The material of the source 21 can be Mo, Ti, Cu, etc. In this exemplary embodiment, the drain 22 contacts the channel layer 30 to form a Schottky contact, thereby forming a source-controlled thin film transistor. Compared with traditional thin film transistors, the source-controlled thin film transistor in this exemplary embodiment has a low saturation voltage, a large output resistance, and can suppress the short channel effect. The thin film transistor can be applied to high-gain amplifiers, high-resolution display driver transistors and other fields.

[0085] It should be noted that in Figure 5 In the exemplary embodiment shown, the orthographic projection of the gate layer 40 on the substrate 10 completely falls within the region of the orthographic projection of the channel layer 30 on the substrate 10. In this way, the performance of the corresponding thin film transistor is guaranteed. Figure 5In the exemplary embodiment shown, if the extension length of the first portion 231 along the second direction is 140 nm, the material of the channel layer 30 is IGZO, and the corresponding thin film transistor is a source-controlled thin film transistor with a short channel of 140 nm.

[0086] In the embodiment of the present invention, the extension length of the first portion 231 along the second direction is 100 nm to 500 nm, for example, 140 nm. In this way, it is possible to construct a short-channel thin film transistor. In practical applications, the first portion 231 can be set according to the actual needs of the channel length, which is not limited here.

[0087] Based on the same inventive concept, Figure 6 As shown, an embodiment of the present invention further provides a method for manufacturing a thin film transistor, the manufacturing method comprising:

[0088] S101: depositing at least two metal layers on a substrate in sequence;

[0089] S102: performing patterning on the at least two metal layers to obtain a processed metal layer, wherein the top metal layer in the processed metal layer is a sacrificial layer;

[0090] S103: forming a whole insulating layer on the processed metal layer;

[0091] S104: forming a pattern of a drain metal layer on the insulating layer, wherein an orthographic projection of the drain metal layer on the substrate overlaps with an orthographic projection of the processed metal layer on the substrate;

[0092] S105: patterning the insulating layer according to the pattern of the drain metal layer to obtain a processed insulating layer;

[0093] S106: releasing the sacrificial layer, retaining the remaining portion of the at least two metal layers except the sacrificial layer on the substrate, and the processed insulating layer and the pattern of the source-drain metal layer form a hollow cantilever beam structure;

[0094] S107: removing the cantilever beam structure along a side of the remaining portion away from the substrate, and forming a source-drain functional layer on the substrate, wherein the source-drain functional layer includes a source electrode, a drain electrode, and a dielectric layer for isolating the source electrode and the drain electrode; the remaining portion forms the source electrode, the portion of the treated insulating layer except for the cantilever beam portion forms the dielectric layer, and the portion of the pattern of the drain metal layer except for the cantilever beam portion forms the drain electrode; the dielectric layer includes a first portion and a second portion connected in sequence; the first portion extends along a first direction and is located between the source electrode and the drain electrode, and is in direct contact with the sidewalls of the source electrode and the sidewalls of the drain electrode;

[0095] S108: forming a pattern of a channel layer on the source-drain functional layer, wherein the source electrode, the first portion and the drain electrode are all in contact with the channel layer.

[0096] In one exemplary embodiment, Figure 7 As shown, step S101: depositing at least two metal layers on the substrate in sequence, including:

[0097] S201: forming a pattern of a gate layer on the substrate;

[0098] S202: forming a pattern of a gate insulating layer on the gate layer;

[0099] S203: depositing at least two metal layers in sequence on a side of the gate insulation layer facing away from the substrate.

[0100] In one exemplary embodiment, Figure 8 As shown, in step S108: after forming a pattern of a channel layer on the source / drain functional layer, the method further includes:

[0101] S301: forming a pattern of a gate insulating layer on a side of the channel layer away from the substrate;

[0102] S302: forming a pattern of a gate layer on a side of the gate insulating layer facing away from the substrate.

[0103] In one exemplary embodiment, Fig. 9 As shown, step S302: forming a pattern of a gate layer on a side of the gate insulating layer away from the substrate, comprising:

[0104] S401: sequentially disposing at least two adhesive layers on the gate insulating layer, wherein the exposure sensitivity of the adhesive layer close to the substrate among the at least two adhesive layers is less than the exposure sensitivity of the other adhesive layers;

[0105] S402: performing patterning processing on the at least two adhesive material layers to obtain processed adhesive material layers;

[0106] S403: forming a whole gate metal layer on the processed glue layer;

[0107] S404: removing the processed glue layer to form a pattern of the gate layer, wherein the gate layer includes a first branch extending along the first direction and a second branch extending along the second direction, wherein the first branch is connected to the second branch and is arranged in a T-shape, and the orthographic projection of the first branch on the substrate completely falls within the area of ​​the orthographic projection of the second branch on the substrate.

[0108] Combine the following Fig.10 The process flow diagram shown is Figure 2 The preparation process of the thin film transistor shown is explained in detail.

[0109] First, a glass substrate with a thickness of 0.5 mm is cleaned by a standard cleaning process; then, a gate metal Mo with a thickness of 200 nm to 300 nm is prepared on the cleaned glass substrate by magnetron sputtering; then, a gate pattern is formed by photolithography and wet etching; then, a gate insulating layer is prepared by plasma enhanced chemical vapor deposition (PECVD), and the material is SiNx or SiOx with a thickness of 100 nm to 300 nm; then, Mo / Al is deposited by magnetron sputtering, and the thickness is 300 nm, wherein 01 represents the Al layer, which is a sacrificial layer; then, a source pattern is formed by photolithography, wet or dry etching, and a stripping process; then, a 200 nm insulating layer corresponding to SiOx or SiNx is prepared by a PECVD process; then, Mo is magnetron sputtered with a thickness of about 100 nm, and a drain pattern layer is formed by photolithography and wet etching; in actual preparation, the drain pattern layer has a certain overlap with the source pattern. In this way, it is guaranteed that the source, the first part and the side of the drain facing away from the substrate are flushly arranged.

[0110] Then, dry etching is performed to remove the portion of the insulating layer other than the portion corresponding to the drain pattern to obtain a processed insulating layer; then, a KOH solution is used to selectively etch the Al layer in the source metal layer, and the processed insulating layer and the drain pattern layer form a hollow cantilever beam structure (i.e., the structure shown in the dotted box Q in the figure); then, the cantilever beam structure is removed along the side of the remaining Mo layer in the source metal layer away from the substrate; for example, an ultrasonic method can be used to remove the cantilever beam structure; for another example, a PDMS pick & place method can be used to remove the cantilever beam structure; for another example, a chemical mechanical polishing (CMP) method can be used to remove the cantilever beam structure. In this way, a pattern of a source-drain functional layer is formed; wherein the source-drain functional layer includes a source, a drain, and a dielectric layer for isolating the source and the drain; the remaining part of the source metal layer (i.e., the remaining Mo layer) forms the source, and the part of the treated insulating layer except the cantilever beam part forms the dielectric layer; the pattern of the drain metal layer except the cantilever beam part forms the drain; the dielectric layer includes a first part and a second part connected in sequence; the first part is extended along a first direction and is located between the source and the drain, and is in direct contact with the sidewalls of the source and the drain; then, a layer of IGZO layer with a thickness of 40nm to 60nm is magnetron sputtered, photolithography, and wet etching are performed to form a channel pattern; exemplary, the channel length is about 140nm. wherein the source, the first part, and the drain are all in contact with the channel layer; then, the IGZO layer is treated by thermal annealing at 380 degrees for 1h; then, SiOx or SiNx is deposited by PECVD for surface passivation, and dry etching can be used to lead out the required vias and electrodes later.

[0111] It should be noted that in Fig.10 In the process flow shown, a dielectric layer for isolating the source and drain can be formed by sidewall thin film deposition, thereby achieving a highly uniform channel region spacing. In addition, by depositing at least two metal layers and selectively etching the top metal layer to form a hollow cantilever beam structure, a submicron-level electrode (i.e., source and drain) can be finally formed after the cantilever beam structure is removed by a mechanical stripping method, thereby achieving the preparation of a short channel thin film transistor.

[0112] Combine the following Fig.11 The process flow diagram shown is Figure 3 The preparation process of the thin film transistor shown is explained in detail.

[0113] First, a glass substrate with a thickness of 0.5 mm is cleaned by a standard cleaning process; then, Mo / Al is deposited on the cleaned glass substrate by magnetron sputtering, with a thickness of 300 nm; then, a source pattern is formed by photolithography, wet or dry etching, and stripping process; then, a 200 nm insulating layer is prepared by PECVD, and the material is SiNx or SiOx; then, Mo is magnetron sputtered with a thickness of about 100 nm, and a drain pattern layer is formed by photolithography, wet etching, and stripping process; in actual preparation, the drain pattern layer has a certain overlap with the source pattern. In this way, it provides a guarantee for the subsequent flush setting of the source, the first part, and the side of the drain away from the substrate. Then, dry etching is performed to remove the portion of the insulating layer other than the corresponding portion of the drain pattern to obtain the treated insulating layer; then, the Al layer in the source metal layer is selectively etched using a KOH solution, and the treated insulating layer and the drain pattern layer form a hollow cantilever beam structure (i.e., the structure shown in the dotted box Q in the figure);

[0114] Then, the cantilever beam structure is removed along the side of the remaining Mo layer in the source metal layer away from the substrate; for example, the cantilever beam structure can be removed by ultrasonic method; for another example, the cantilever beam structure can be removed by PDMS pick & place method; for another example, the cantilever beam structure can be removed by CMP. In this way, the pattern of the source and drain functional layer is formed; wherein the source and drain functional layer includes a source electrode, a drain electrode and a dielectric layer for isolating the source electrode and the drain electrode; the remaining part of the source metal layer (i.e., the remaining Mo layer) forms the source electrode, and the part of the treated insulating layer except the cantilever beam part forms the dielectric layer; the pattern of the drain metal layer except the cantilever beam part forms the drain electrode; the dielectric layer includes a first part and a second part connected in sequence; the first part extends along the first direction and is located between the source electrode and the drain electrode, and is in direct contact with the side wall of the source electrode and the side wall of the drain electrode; then, a layer of IGZO layer with a thickness of 40nm to 60nm is magnetron sputtered, photolithography, and wet etching are performed to form a channel pattern; the channel length is about 140nm. Among them, the source, the first part and the drain are all in contact with the channel layer; then, the IGZO layer is treated by thermal annealing at 380 degrees for 1h; then, PECVD is used to deposit SiOx or SiNx as a gate insulating layer, and dry etching can be used to lead out the required vias and electrodes; then, magnetron sputtering is used to prepare gate metal Mo on the gate insulating layer with a thickness of 200nm to 300nm; photolithography and wet etching are used to form a gate layer pattern; then, PECVD is used to deposit SiOx or SiNx for surface passivation.

[0115] In the embodiment of the present invention, in addition to the gate layer, Figure 4 The preparation process of the thin film transistor shown in FIG. Figure 3The process of preparing the thin film transistor shown in FIG. In one exemplary embodiment, the Fig.12 The double-layer glue process shown is formed Figure 4 The gate layer of the T-shaped structure in the embodiment of the present invention is formed. First, a first glue layer 70 and a second glue layer 80 are sequentially spin-coated on the gate insulating layer in a direction away from the substrate, and the exposure sensitivity of the first glue layer 70 is lower than that of the second glue layer 80. Exemplarily, the material of the first glue layer 70 is PMMA, and the material of the second glue layer 80 is a mixture of PMMA and MA. Then, the first glue layer 70 and the second glue layer 80 are subjected to electron beam exposure; then, they are developed; then, a gate metal layer is deposited; then, the remaining first glue layer 70 and the second glue layer 80 are peeled off to obtain a gate layer of the T-shaped structure.

[0116] In one exemplary embodiment, it is possible to use Fig.13 The three-layer glue process shown is prepared to form Figure 4 The gate layer of the T-shaped structure in the process. First, along the direction away from the substrate, the third glue layer 90, the fourth glue layer 100 and the fifth glue layer 110 are sequentially spin-coated on the gate insulating layer, and the exposure sensitivity of the fifth glue layer 110 is greater than the exposure sensitivity of the third glue layer 90, and less than the exposure sensitivity of the fourth glue layer 100; illustratively, the material of the third glue layer 90 is PMMA, the material of the fourth glue layer 100 is a mixture of PMMA and MA, and the material of the fifth glue layer 110 is PMMA. Then, the third glue layer 90, the fourth glue layer 100 and the fifth glue layer 110 are subjected to electron beam exposure; then, they are developed; then, a gate metal layer is deposited; then, the remaining third glue layer 90, the fourth glue layer 100 and the fifth glue layer 110 are peeled off to obtain a gate layer of the T-shaped structure.

[0117] It should be noted that in Fig.12 and Fig.13 In the exemplary embodiment shown, the specific materials of the first adhesive layer 70, the second adhesive layer 80, the third adhesive layer 90, the fourth adhesive layer 100 and the fifth adhesive layer 110 can also be set according to the actual application needs, which is not limited here. In addition, in the embodiment of the present invention, the relevant process flow chart does not fully illustrate the structure of all steps. Those skilled in the art can use relevant technologies to prepare the corresponding structure according to the actual application needs, which will not be described in detail here.

[0118] The embodiment of the present invention provides a thin film transistor and a manufacturing method thereof, wherein the thin film transistor includes a substrate, a source-drain functional layer located on the substrate, and a channel layer located on the source-drain functional layer; wherein the source-drain functional layer includes a source electrode, a drain electrode, and a dielectric layer for isolating the source electrode and the drain electrode; the dielectric layer includes a first part and a second part connected in sequence; the first part is extended along a first direction, and is located between the source electrode and the drain electrode, and is in direct contact with the side wall of the source electrode and the side wall of the drain electrode; exemplarily, the first direction is a direction perpendicular to the plane where the substrate is located; the second part is extended along a second direction intersecting with the first direction, and is located between the drain electrode and the substrate, and is in direct contact with the bottom of the drain electrode; exemplarily, the second direction is a direction parallel to the plane where the substrate is located; and the source electrode, the first part, and the drain electrode are all in contact with the channel layer. In this way, the first part in the dielectric layer can not only effectively isolate the source electrode and the drain electrode; but also, in actual preparation, the channel region of the thin film transistor can be set by adjusting the first part, thereby providing a guarantee for the subsequent realization of the short channel design of the thin film transistor.

[0119] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0120] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A thin film transistor, characterized in that: include: A substrate, a source-drain functional layer located on the substrate, and a channel layer located on the source-drain functional layer; Wherein, the source-drain functional layer includes a source electrode, a drain electrode, and a dielectric layer for isolating the source electrode and the drain electrode; The dielectric layer includes a first part and a second part connected in sequence; the first part is extended along a first direction, and is located between the source and the drain, and is in direct contact with the side walls of the source and the drain; the second part is extended along a second direction intersecting the first direction, and is located between the drain and the substrate, and is in direct contact with the bottom of the drain; the source, the first part and the drain are all in contact with the channel layer.

2. The thin film transistor according to claim 1, wherein: The source, the first portion and the drain are arranged flush with each other on a side facing away from the substrate.

3. The thin film transistor according to claim 1, wherein: Along the first direction, the sum of the thicknesses of the drain electrode and the second portion is substantially equal to the thickness of the source electrode.

4. The thin film transistor according to any one of claims 1 to 3, characterized in that: It also includes a gate layer and a gate insulating layer located between the substrate and the source-drain functional layer, and the gate insulating layer is located between the source-drain functional layer and the gate layer.

5. The thin film transistor according to any one of claims 1 to 3, characterized in that: It also includes a gate insulating layer and a gate layer which are sequentially arranged on a side of the channel layer away from the substrate.

6. The thin film transistor according to claim 5, characterized in that: The gate layer includes a first branch extending along the first direction and a second branch extending along the second direction, the first branch is connected to the second branch and is arranged in a T-shape, and the orthographic projection of the first branch on the substrate completely falls within the area of ​​the orthographic projection of the second branch on the substrate.

7. The thin film transistor according to claim 5, characterized in that: The material of the drain electrode is a high-functional metal, and the drain electrode contacts the channel layer to form a Schottky layer.

8. The thin film transistor according to any one of claims 1 to 3, characterized in that: The orthographic projection of the first portion on the substrate completely falls within the region of the orthographic projection of the gate layer on the substrate.

9. The thin film transistor according to claim 8, wherein: An extension length of the first portion along the second direction is 100 nm to 500 nm.

10. A method for manufacturing a thin film transistor, characterized in that: include: Depositing at least two metal layers sequentially on a substrate; Performing patterning on the at least two metal layers to obtain a processed metal layer, wherein the top metal layer in the processed metal layer is a sacrificial layer; forming a whole insulating layer on the processed metal layer; forming a pattern of a drain metal layer on the insulating layer, wherein an orthographic projection of the drain metal layer on the substrate overlaps with an orthographic projection of the processed metal layer on the substrate; Patterning the insulating layer according to the pattern of the drain metal layer to obtain a processed insulating layer; The sacrificial layer is released, and the remaining portion of the at least two metal layers except the sacrificial layer is retained on the substrate, and the patterns of the processed insulating layer and the source-drain metal layer form a hollow cantilever beam structure; The cantilever beam structure is removed along a side of the remaining portion away from the substrate, and a source-drain functional layer is formed on the substrate, wherein the source-drain functional layer includes a source electrode, a drain electrode, and a dielectric layer for isolating the source electrode and the drain electrode; the remaining portion forms the source electrode, the portion of the treated insulating layer except for the cantilever beam portion forms the dielectric layer, and the portion of the pattern of the drain metal layer except for the cantilever beam portion forms the drain electrode; the dielectric layer includes a first portion and a second portion connected in sequence; the first portion is extended along a first direction, and is located between the source electrode and the drain electrode, and is in direct contact with the sidewalls of the source electrode and the sidewalls of the drain electrode; A pattern of a channel layer is formed on the source-drain functional layer, wherein the source electrode, the first portion and the drain electrode are all in contact with the channel layer.

11. The method according to claim 10, characterized in that The step of sequentially depositing at least two metal layers on the substrate comprises: forming a pattern of a gate layer on the substrate; forming a pattern of a gate insulating layer on the gate layer; At least two metal layers are sequentially deposited on a side of the gate insulating layer facing away from the substrate.

12. The method according to claim 10, characterized in that After forming a pattern of a channel layer on the source / drain functional layer, the method further comprises: forming a pattern of a gate insulating layer on a side of the channel layer facing away from the substrate; A pattern of a gate layer is formed on a side of the gate insulating layer facing away from the substrate.

13. The method according to claim 12, characterized in that Forming a pattern of a gate layer on a side of the gate insulating layer away from the substrate, comprising: At least two glue layers are sequentially arranged on the gate insulating layer, wherein the exposure sensitivity of the glue layer close to the substrate among the at least two glue layers is less than the exposure sensitivity of the other glue layers; Performing patterning treatment on the at least two adhesive material layers to obtain treated adhesive material layers; forming a whole gate metal layer on the processed glue layer; The processed glue layer is removed to form a pattern of the gate layer, wherein the gate layer includes a first branch extending along the first direction and a second branch extending along the second direction, wherein the first branch is connected to the second branch and is arranged in a T-shape, and the orthographic projection of the first branch on the substrate completely falls within the area of ​​the orthographic projection of the second branch on the substrate.

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