Stacked polycrystalline or monocrystal-like nanosheet device and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, in particular to a stacked polycrystalline or monocrystal-like nanosheet device and a preparation method thereof, and the preparation method comprises the following steps: forming a multi-layer stacked nanosheet structure on a substrate; defining an active region through photoetching and etching processes, and forming a gate structure; etching a metal induction window on one side of the gate structure, and inducing the multiple layers of stacked amorphous nanosheets to crystallize into a polycrystal or monocrystal-like nanosheet channel through metal; a contact hole is etched in the other side of the gate structure, and a second-stage silicide is formed; and completing the integration of the stacked polycrystal or monocrystal-like nanosheet device through an interconnection through hole process. According to the invention, the complexity of the traditional epitaxial process is simplified, the production cost is reduced, the problem of parasitic channel effect is effectively solved, and a feasible solution is provided for the manufacturing of high-performance transistors under advanced process nodes.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a stacked polycrystalline or quasi-single-crystalline nanosheet device and a preparation method thereof. Background Art

[0002] With the rapid development of semiconductor technology, especially at advanced process nodes, device miniaturization and performance improvement have become the focus of research. In this context, the channel structure is one of the key factors that determine the performance of transistors, and its design and manufacturing process innovation is particularly important. Traditional channel structures mainly include nanowires and nanosheets, each with its own advantages and disadvantages, but in terms of performance driving, the nanosheet structure shows more significant advantages due to its larger contact area and more efficient charge transfer characteristics.

[0003] However, the complexity of the nanosheet stacking process and its accompanying high cost have always been the main bottleneck restricting its widespread application. Traditional nanosheet stacking is usually manufactured using an epitaxial process, which precisely controls the growth of materials to alternately form a channel layer and a sacrificial layer on a substrate, and then removes the sacrificial layer by chemical or physical methods, leaving the desired nanosheet structure. Although this method can produce high-quality nanosheets, its high cost and extremely high requirements for equipment precision limit its application in large-scale production.

[0004] In addition, the traditional nanosheet stacking manufacturing process has a problem that cannot be ignored - the parasitic channel effect of the liner. The existence of the parasitic channel will seriously affect the performance of the transistor, leading to an increase in leakage current and power consumption, thereby reducing the overall efficiency and reliability of the device.

[0005] In view of this, exploring new nanosheet manufacturing processes to reduce costs, improve production efficiency, and effectively suppress parasitic channel effects has become a technical problem that technical personnel in this field urgently need to solve. Summary of the invention

[0006] The purpose of the present invention is to provide a stacked polycrystalline or quasi-single-crystalline nanosheet device and a preparation method thereof, which not only simplifies the complexity of the traditional epitaxial process and reduces the production cost, but also effectively solves the problem of parasitic channel effect.

[0007] In a first aspect, the present invention provides a method for preparing a stacked polycrystalline or quasi-single-crystalline nanosheet device, comprising the following steps:

[0008] forming a multi-layer stacked nanosheet structure on a substrate;

[0009] Through photolithography and etching processes, the active area is defined and the gate structure is formed;

[0010] A metal-induced window is etched on one side of the gate structure, and the multi-layer stacked amorphous nanosheets are crystallized into polycrystalline or single-crystal-like nanosheet channels by metal induction;

[0011] Etching a contact hole on the other side of the gate structure and forming a second level of silicide;

[0012] The integration of stacked polycrystalline or single-crystal-like nanosheet devices is completed through the interconnection through-hole process.

[0013] As a preferred embodiment of this technical solution, the following steps are included:

[0014] S1. Deposit SiO on the substrate in sequence 2 / a-Si stack, SiO 2 / a-GeSi or SiO 2 / a-Ge stack, and ion implantation and thinning of a-Si, a-GeSi or a-Ge layer;

[0015] S2, repeat step S1, in SiO 2 / a-Si stack, SiO 2 / a-GeSi or SiO 2 / A plurality of stacked structures are formed on the a-Ge stack;

[0016] S3, define the active area through photolithography and etching process, deposit Si 3 N 4 And perform flattening treatment;

[0017] S4, etching a gate structure to form a boundary of a channel region, and sequentially depositing a gate dielectric layer and a gate electrode material to form a gate structure;

[0018] S5, etching a metal induction window on one side of the gate structure, depositing Ni in the metal induction window, and performing annealing and pickling to obtain a first-level silicide;

[0019] S6, annealing the first-level silicide to diffuse the first-level silicide along the a-Si, a-GeSi or a-Ge nanosheets to the SiN / a-Si, SiN / a-GeSi or SiN / a-Ge interface, and inducing the a-Si, a-GeSi or a-Ge to crystallize into polycrystalline or quasi-single crystal;

[0020] S7, etching a contact hole on the other side of the gate structure, depositing Ni in the metal induction window, and performing annealing and pickling to obtain a second-level silicide;

[0021] S8. Complete the integration of stacked polycrystalline or single-crystal-like nanosheet devices through interconnection through-hole process.

[0022] As a preferred embodiment of the present technical solution, in step S1, for the a-Si layer, during the ion implantation, the implanted ions are P, the energy is 10-20 keV, and the dose is 5e14 / cm 2 ;

[0023] During the thinning, the a-Si layer is thinned to 8-12 nm by an etching process.

[0024] As a preferred embodiment of the present technical solution, in step S2, the SiO 2 The thickness is less than that of SiO 2 Thickness.

[0025] As a preferred embodiment of the present technical solution, the material of the gate dielectric layer includes any one of silicon dioxide, silicon nitride and high-K material.

[0026] As a preferred embodiment of the present technical solution, in step S4, the gate electrode material includes any one of polysilicon, heavily doped polysilicon and metal gate material.

[0027] As a preferred embodiment of the present technical solution, in step S5 and step S7, during the annealing treatment, the temperature is controlled to be 300-450° C. and the time is 1-10 min.

[0028] As a preferred embodiment of the present technical solution, in step S5 and step S7, during the pickling, aqua regia is used to remove unreacted Ni.

[0029] As a preferred embodiment of the present technical solution, in step S6, during the annealing treatment, the temperature is controlled to be 350-575°C and the time is 12-24h.

[0030] In the second aspect, the present invention also discloses stacked polycrystalline or quasi-single-crystalline nanosheet devices prepared by the above-mentioned preparation method, which should also fall within the protection scope of the present invention.

[0031] The method for preparing the stacked polycrystalline or quasi-single-crystalline nanosheet device of the present invention has at least the following beneficial effects:

[0032] First, through the metal-induced crystallization process, the present invention can transform the multi-layer stacked nanosheet structure into a polycrystalline or quasi-single-crystal nanosheet channel. Compared with amorphous or low-crystalline materials, polycrystalline or quasi-single-crystal materials have higher carrier mobility and lower resistivity, thereby significantly improving the conductivity and operating speed of the device; in addition, the quasi-single-crystal nanosheet channel also has excellent structural stability and thermal stability, which helps to improve the performance stability of the device under long-term operation and high-temperature environment. Secondly, the present invention uses photolithography and etching processes to define the active area and form the gate structure. The precise graphic technology can ensure the accuracy and consistency of the device structure, laying a solid foundation for the subsequent crystallization and contact hole formation steps. Thus, through the etching of the metal-induced window and the metal-induced crystallization process, the local crystallization control of the nanosheet structure is achieved, avoiding the material waste and process complexity that may be caused by global crystallization. In addition, the stacked nanosheet structure itself can achieve a high degree of device integration, and the present invention further completes the integration of stacked polycrystalline or quasi-single-crystal nanosheet devices through an interconnected through-hole process, so that the device can achieve higher integration and smaller size while maintaining high performance, which is of great significance for meeting the needs of modern electronic devices for high performance, miniaturization and low power consumption. Finally, although the preparation process of the present invention involves multiple delicate steps, efficient batch preparation can be achieved by optimizing process parameters and process control, thereby reducing the preparation cost of a single device. At the same time, since the stacked nanosheet structure can achieve a high degree of device integration, more devices can be prepared on the same chip area, further improving production efficiency and reducing costs.

[0033] Therefore, the preparation method of stacked polycrystalline or quasi-single-crystalline nanosheet devices provided by the present invention has shown significant technical advantages in improving device performance, optimizing preparation process, improving device integration, enhancing device reliability and reducing preparation cost. It not only simplifies the complexity of traditional epitaxial process and reduces production cost, but also effectively solves the problem of parasitic channel effect, providing a practical solution for the manufacture of high-performance transistors at advanced process nodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0035] Figure 1 In step S1 of the present invention, SiO is deposited on the substrate. 2 / a-Si stacking, and ion implantation into the a-Si layer;

[0036] Figure 2 This is a schematic diagram of thinning the a-Si layer in step S1 of the present invention;

[0037] Figure 3 In step S2 of the present invention, SiO 2 Schematic diagram of a stacked structure formed by stacking / a-Si layers;

[0038] Figure 4 In step S2 of the present invention, SiO 2 / a-Si stacking to form a stacked structure and schematic diagram of thinning the a-Si layer;

[0039] Figure 5 A schematic diagram of replacing an a-Si layer in a stacked structure with an a-Ge layer in the present invention;

[0040] Figure 6 A schematic diagram of defining an active area by photolithography and etching processes in step S3 of the present invention;

[0041] Figure 7 In step S3 of the present invention, Si is deposited in the active area. 3 N 4 And a schematic diagram of flattening process;

[0042] Figure 8 This is a schematic diagram of etching a gate structure in step S4 of the present invention;

[0043] Fig. 9 It is a schematic diagram of depositing a gate dielectric layer and a gate dielectric at the etched gate structure in step S4 of the present invention;

[0044] Fig.10 A schematic diagram of etching a metal induction window on one side of the gate structure in step S5 of the present invention;

[0045] Fig.11 This is a schematic diagram of depositing Ni in the metal induction window in step S5 of the present invention, and obtaining the first-level silicide through annealing and pickling;

[0046] Fig.12 Schematic diagram of annealing the first-level silicide in step S6 of the present invention, so that the first-level silicide diffuses along the a-Si nanosheet to the SiN / a-Si interface, and induces the a-Si to crystallize into polycrystalline or quasi-single crystal;

[0047] Fig.13 A schematic diagram of annealing the first-level silicide in step S6 of the present invention to diffuse the first-level silicide along the a-Ge nanosheet to the SiN / a-Ge interface and induce the a-Ge to crystallize into polycrystalline or quasi-single crystal;

[0048] Fig.14 A schematic diagram of etching a contact hole on the other side of the gate structure in step S7 of the present invention, depositing Ni in the metal induction window, and obtaining a second-level silicide after annealing and pickling;

[0049] Fig.15 This is a schematic diagram of completing the integration of stacked polycrystalline or quasi-single-crystalline nanosheet devices through an interconnection through-hole process in step S8 of the present invention. DETAILED DESCRIPTION

[0050] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0051] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0052] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined. In addition, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0053] Example

[0054] like Figure 1-15 As shown, this embodiment provides a method for preparing a stacked polycrystalline or quasi-single-crystalline nanosheet device, which specifically includes the following steps:

[0055] S1. First, a layer of SiO is deposited on the substrate.2 As an insulating layer, the thickness can be adjusted according to specific needs, but sufficient isolation effect should be ensured. A layer of amorphous silicon (a-Si) with a thickness of 30-50nm is further deposited as the initial channel layer, and then the a-Si layer is ion implanted, such as implanting P ions, with an implantation energy of 10-20keV and an implantation dose of 5e14 / cm 2 , in order to improve the efficiency and effect of the subsequent crystallization process, and finally thin the a-Si layer to 10nm through the etching process. On the one hand, the thinner channel layer reduces the transmission distance of electrons in the channel, improves the mobility of electrons, and thus improves the response speed of the device. On the other hand, thinning the a-Si layer to an appropriate thickness can ensure that the crystallization process is carried out evenly in the entire channel layer, thereby forming a high-quality polycrystalline or single-crystal-like nanosheet channel; at the same time, thinning the a-Si layer to 10nm also helps to reduce the influence of parasitic capacitance, thereby further improving the performance and reliability of the device;

[0056] In this embodiment, in order to further expand the performance drive of the device, the a-Si layer can also be replaced by amorphous germanium silicon (a-GeSi) or amorphous germanium (a-Ge);

[0057] When amorphous germanium silicon (a-GeSi) is used as the initial channel layer, P ions can be implanted during ion implantation of a-GeSi, with an implantation energy of 10-20keV and an implantation dose of 5E14 / cm 2 , and finally the a-GeSi layer is thinned to less than 8-12nm through an etching process;

[0058] When amorphous germanium (a-Ge) is used as the initial channel layer, P ions can be implanted during ion implantation of a-Ge, with an implantation energy of 10-20 keV and an implantation dose of 5E14 / cm 2 , and finally the a-Ge layer is thinned to less than 8-12nm through an etching process.

[0059] S2, repeat step S1, first deposit SiO 2 layer, and then deposit an a-Si layer, an a-GeSi layer or an a-Ge layer to form a 2 / a-Si stack, SiO 2 / a-GeSi or SiO 2 / a-Ge stacking layer to form multiple stacking structures, and in this stacking structure, SiO 2 The thickness of the layer is less than that of SiO 2 Layer thickness, SiO 2 The thinning of the layer helps to precisely control the subsequent processes and optimize the device performance;

[0060] S3, define the active area through photolithography and etching process to lay the foundation for the subsequent gate structure preparation, and then deposit a layer of Si 3 N 4 And perform flattening treatment to eliminate the impact of surface unevenness on subsequent processes;

[0061] S4, etching a gate structure to form a boundary of a channel region, and sequentially depositing a gate dielectric layer and a gate electrode material to form a gate structure;

[0062] The material of the gate dielectric layer includes SiO 2 , silicon nitride (SiNx) and high-K materials, among which high-K materials include hafnium oxide (HfO 2 ), titanium oxide (TiO 2 ), zirconium oxide (ZrO 2 ), Tantalum pentoxide (Ta 2 O 5 ), etc. In this embodiment, the gate dielectric layer may be selected from conventional SiO 2 ;

[0063] The gate electrode materials include polysilicon, metal gate materials and heavily doped polysilicon, among which the metal gate materials include tungsten (W), titanium (Ti), nickel (Ni), etc., and their alloys or compounds. In the present embodiment, the gate electrode material is preferably TiN / W.

[0064] S5, in Si 3 N 4 SiO is deposited on the gate structure 2 , and etch a metal induction window on one side of the gate structure to provide a channel for the subsequent metal induced crystallization process, then deposit Ni in the metal induction window and anneal at 300-450℃ for 1-10min to form NiSi 2 , then pickling with aqua regia to remove unreacted Ni to ensure the purity of the crystallization process and obtain the first-level silicide;

[0065] S6, annealing the first-level silicide at 350-575°C for 12-24h, during which the first-level silicide NiSi 2 Diffusion along a-Si, a-GeSi or a-Ge amorphous nanosheets to SiN / a-Si, SiN / a-GeSi or SiN / a-Ge interfaces, inducing a-Si, a-GeSi or a-Ge to crystallize into polycrystalline or quasi-single crystal, thereby achieving crystallization of the channel layer;

[0066] Specifically, when a metal (such as Ni) is deposited in an initial channel layer such as amorphous silicon (a-Si), amorphous germanium silicon (a-GeSi) or amorphous germanium (a-Ge) and annealed at a certain temperature, the metal atoms diffuse into the amorphous material and react with it to form a metal silicide (such as NiSi2). In this reaction process, the metal atoms act as a "catalyst" in the crystal nucleus or amorphous material, promoting the crystallization process of the amorphous material. As the annealing process proceeds, the metal silicide diffuses along the amorphous nanosheets, inducing the surrounding amorphous material to gradually transform into a polycrystalline or single-crystal-like structure.

[0067] First, the crystallized channel layer has higher electron mobility and lower resistivity, which not only helps to reduce the transmission loss of electrons in the channel and improve the response speed and switching speed of the device, but also the crystallization process can reduce defects and scattering centers in the channel, further improving the performance of the device; secondly, the crystallized channel layer has better thermal stability and chemical stability, and can maintain stable performance in harsh environments such as high temperature and high humidity, which helps to extend the service life of the device and improve its reliability; finally, through the metal-induced crystallization process, the degree of crystallization and grain size of the channel layer can also be precisely controlled, thereby optimizing the structure and performance of the device and achieving more sophisticated device design and higher integration.

[0068] S7, etching a contact hole on the other side of the gate structure, and depositing Ni in the metal induction window, and obtaining a second-level silicide after annealing and pickling to prepare for subsequent metallization connection;

[0069] S8. Finally, the integration of stacked polycrystalline or single-crystal-like nanosheet devices is completed through the interconnection through-hole process. The interconnection through-hole process can be referred to the existing technology and will not be described in detail here.

[0070] In summary, the high-performance stacked polycrystalline or quasi-single-crystalline nanosheet channel device prepared by the present invention through multi-layer stacking and metal-induced crystallization technology has excellent electrical performance and stability. It not only avoids the high cost problem of traditional epitaxial process, but also reduces the preparation cost of the device through innovative stacking and crystallization technology. Moreover, by precisely controlling process parameters and material selection, it effectively suppresses the parasitic channel effect and improves the reliability and stability of the device. In practical applications, the number of stacking layers and material selection can be adjusted according to specific needs, which provides the possibility for further optimization of device performance.

[0071] In the above description, the technical details of patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above.

[0072] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing a stacked polycrystalline or single-crystal-like nanosheet device, characterized in that: The following steps are involved: forming a multi-layer stacked nanosheet structure on a substrate; Through photolithography and etching processes, the active area is defined and the gate structure is formed; A metal-induced window is etched on one side of the gate structure, and the multi-layer stacked amorphous nanosheets are crystallized into polycrystalline or single-crystal-like nanosheet channels by metal induction; Etching a contact hole on the other side of the gate structure and forming a second level of silicide; The integration of stacked polycrystalline or single-crystal-like nanosheet devices is completed through the interconnection through-hole process.

2. The preparation method according to claim 1, characterized in that: The following steps are involved: S1. Depositing SiO2 / a-Si stacked layers, SiO2 / a-GeSi or SiO2 / a-Ge stacked layers on a substrate in sequence, and performing ion implantation and thinning on the a-Si, a-GeSi or a-Ge layer; S2, repeating step S1 to form a plurality of stacked structures on the SiO2 / a-Si stack, the SiO2 / a-GeSi or the SiO2 / a-Ge stack; S3, defining the active area through photolithography and etching processes, depositing Si3N4 and performing planarization; S4, etching a gate structure to form a boundary of a channel region, and sequentially depositing a gate dielectric layer and a gate electrode material to form a gate structure; S5, etching a metal induction window on one side of the gate structure, depositing Ni in the metal induction window, and performing annealing and pickling to obtain a first-level silicide; S6, annealing the first-level silicide to diffuse the first-level silicide along the a-Si, a-GeSi or a-Ge nanosheets to the SiN / a-Si, SiN / a-GeSi or SiN / a-Ge interface, and inducing the a-Si, a-GeSi or a-Ge to crystallize into polycrystalline or quasi-single crystal; S7, etching a contact hole on the other side of the gate structure, depositing Ni in the metal induction window, and performing annealing and pickling to obtain a second-level silicide; S8. Complete the integration of stacked polycrystalline or single-crystal-like nanosheet devices through interconnection through-hole process.

3. The preparation method according to claim 2, characterized in that: In step S1, for the a-Si layer, during the ion implantation, the implanted ions are P, the energy is 10-20keV, and the dose is 5e14 / cm 2 ; During the thinning, the a-Si layer is thinned to 8-12 nm by an etching process.

4. The preparation method according to claim 2, characterized in that: In step S2, the thickness of SiO2 in the stacked structure is smaller than the thickness of SiO2 in step S1.

5. The preparation method according to claim 2, characterized in that: In step S4, the material of the gate dielectric layer includes any one of silicon dioxide, silicon nitride and high-K material.

6. The preparation method according to claim 2, characterized in that: In step S4, the gate electrode material includes any one of polysilicon, heavily doped polysilicon and metal gate material.

7. The preparation method according to claim 2, characterized in that: In step S5 and step S7, during the annealing treatment, the temperature is controlled to be 300-450° C. and the time is 1-10 min.

8. The preparation method according to claim 2, characterized in that: In step S5 and step S7, during the pickling, aqua regia is used to remove unreacted Ni.

9. The preparation method according to claim 2, characterized in that: In step S6, during the annealing treatment, the temperature is controlled to be 350-575° C. and the time is 12-24 hours.

10. A stacked polycrystalline or quasi-single-crystalline nanosheet device, characterized in that: Prepared according to the preparation method according to any one of claims 1 to 9.

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