Semiconductor structure, manufacturing method thereof and chip
By introducing buried oxygen layer and light doped layer into the base structure of the VDMOS transistor, the problem of parasitic capacitance limiting switching speed is solved, and efficient switching and voltage withstandness of the transistor are achieved.
Patent Information
- Application Number
- CN202510103320.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-22
- Publication Date
- 2025-04-29
AI Technical Summary
The switching speed of existing VDMOS transistors is limited by parasitic capacitance. How to reduce the parasitic capacitance to increase the switching speed of the transistor is an important technical challenge.
By introducing a buried oxygen layer and a light doped layer into the substrate structure, an isolation structure between the doped region and the underlying substrate layer is formed, thereby reducing parasitic capacitance.
It effectively reduces the parasitic capacitance, improves the switching speed of the transistor, and improves its withstand voltage and service life.
Smart Images
Figure CN119907287A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of semiconductor technology, and relate to but are not limited to a semiconductor structure, a manufacturing method thereof, and a chip. Background Art
[0002] Vertical Double-Diffused MetalOxide Semiconductor Field Effect Transistor (VDMOS) is a voltage-controlled transistor device with acoustic effect power transistor, whose source and drain are on different sides of the semiconductor substrate, and the current flows vertically through double diffusion. Under the control of appropriate gate voltage, the semiconductor surface of VDMOS is inverted to form a conductive channel, so that an appropriate amount of current can flow between the drain and the source.
[0003] The switching characteristics of VDMOS are determined by its intrinsic capacitance and parasitic capacitance, including gate-source capacitance, gate-drain capacitance, and source-drain capacitance. As power devices develop towards high-frequency applications, the improvement of transistor switching speed is particularly important, and the charging and discharging of capacitance is one of the main factors limiting the switching speed of transistors. Therefore, how to reduce parasitic capacitance to increase transistor switching speed is one of the important technical issues to be solved in this field. Summary of the invention
[0004] In view of this, an embodiment of the present application provides a semiconductor structure, a manufacturing method thereof, and a chip.
[0005] On the one hand, an embodiment of the present application provides a semiconductor structure, including:
[0006] A substrate; the substrate comprises a substrate layer, a buried oxide layer and a doping layer stacked in sequence;
[0007] The doping layer includes a first doping region and a second doping region spaced apart from each other in a direction parallel to the surface of the substrate;
[0008] A control electrode, located on the surface of the substrate and covering at least a region between the first doping region and the second doping region;
[0009] A first electrode, located on the surface of the substrate and covering at least a portion of the first doped region;
[0010] The second electrode is located on the surface of the substrate and covers at least a portion of the second doped region.
[0011] In some embodiments, the semiconductor structure further includes: a third electrode located on a surface of the substrate opposite to the control electrode;
[0012] The first doping region and the second doping region have the same doping type;
[0013] The buried oxide layer includes: a first buried oxide region located under the first doping region and a second buried oxide region located under the second doping region.
[0014] In some embodiments, the semiconductor structure further comprises:
[0015] A lightly doped layer is located between the first buried oxide layer and the second buried oxide layer, and between the first doped region and the second doped region; wherein the thickness of the lightly doped layer is greater than or equal to the thickness of the first buried oxide layer and the second buried oxide layer.
[0016] In some embodiments, the lightly doped layer, the first doped region, and the tops of the second doped region are located on the same surface;
[0017] The doping type of the lightly doped layer is the same as the doping type of the substrate layer, and the doping concentration of the lightly doped layer is less than the doping concentration of the substrate layer.
[0018] In some embodiments, the substrate layer comprises:
[0019] a first substrate layer with a first doping concentration and a second substrate layer with a second doping concentration; the first doping concentration is greater than the second doping concentration;
[0020] The bottom of the lightly doped layer is located in the second substrate layer;
[0021] The lightly doped layer has a third doping concentration, and the third doping concentration is less than the second doping concentration.
[0022] In some embodiments, the first doping region and the second doping region each include: a first doping sub-region and a second doping sub-region having different doping types;
[0023] The tops of the first doped sub-region and the second doped sub-region are located on the same surface; and the second doped sub-region is surrounded by the first doped sub-region.
[0024] On the other hand, an embodiment of the present application further provides a method for manufacturing a semiconductor structure, the method comprising:
[0025] Providing a substrate, the substrate comprising: a substrate layer, a buried oxide layer and a semiconductor layer stacked in sequence;
[0026] Performing ion implantation in the semiconductor layer to form a first doping region and a second doping region spaced apart from each other in a direction parallel to the surface of the substrate;
[0027] forming a control electrode on the surface of the substrate, so that the control electrode at least covers the area between the first doping region and the second doping region;
[0028] A first electrode and a second electrode are formed on the surface of the substrate, so that the first electrode covers at least a portion of the first doped region, and the second electrode covers at least a portion of the second doped region.
[0029] In some embodiments, the method further comprises:
[0030] A recessed region is formed on the substrate; the recessed region is located between the first doping region and the second doping region, and the buried oxide layer is separated into a first buried oxide region and a second buried oxide region; the bottom of the recessed region is located in the substrate layer;
[0031] The recessed area is filled with a lightly doped semiconductor material to form a lightly doped layer.
[0032] In some embodiments, forming a recessed area on the substrate comprises:
[0033] forming a hard mask on the surface of the substrate;
[0034] patterning the hard mask to expose a portion of the surface of the substrate;
[0035] The exposed surface area of the substrate is etched to form the recessed area.
[0036] In some embodiments, the method further comprises:
[0037] removing the hard mask;
[0038] The surfaces of the substrate and the lightly doped layer are planarized.
[0039] In some embodiments, filling the recessed region with a lightly doped semiconductor material to form a lightly doped layer includes:
[0040] Filling the lightly doped semiconductor material in the recessed area by an epitaxial growth process to form the lightly doped layer; or
[0041] Filling the recessed area with an intrinsic semiconductor material by an epitaxial growth process, and performing a first ion implantation on the intrinsic semiconductor material to form the lightly doped layer;
[0042] The doping type of the lightly doped layer is the same as the doping type of the substrate layer, and the doping concentration of the lightly doped layer is less than the doping concentration of the substrate layer.
[0043] In some embodiments, the step of performing ion implantation on the semiconductor layer to form a first doping region and a second doping region spaced apart from each other in a direction parallel to the surface of the substrate includes:
[0044] Performing a second ion implantation in the semiconductor layer to form a first doped sub-region;
[0045] A third ion implantation is performed within the range where the first doped sub-region is located to form a second doped sub-region surrounded by the first doped sub-region; wherein the top of the first doped sub-region and the second doped sub-region are located on the same surface; and the doping types of the second ion implantation and the third ion implantation are different.
[0046] In some embodiments, the method further comprises:
[0047] forming a third electrode on the surface of the substrate opposite to the control electrode;
[0048] The first doping region and the second doping region have the same doping type.
[0049] On the other hand, an embodiment of the present application provides a chip, including: a memory cell array and / or an integrated circuit; wherein the memory cell array and / or the integrated circuit includes one or more of any of the above-mentioned semiconductor structures.
[0050] In the semiconductor structure of the embodiment of the present application, a buried oxide layer is arranged under the doping layer constituting the transistor, so that the doping region and the underlying substrate layer are isolated by the buried oxide layer and no depletion region is formed. This can effectively reduce the parasitic capacitance, improve the response speed of the transistor, and improve the voltage resistance of the transistor, thereby optimizing the application range and service life of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS
[0051] Figure 1 is a schematic diagram of a semiconductor structure in an embodiment of the present application;
[0052] Figure 2 A schematic diagram of a semiconductor structure provided in an embodiment of the present application;
[0053] Figure 3 A process for manufacturing a semiconductor structure provided in an embodiment of the present application Figure 1 ;
[0054] Figure 4 A schematic diagram of a method for manufacturing a semiconductor structure provided in an embodiment of the present application;
[0055] Figure 5 A process for manufacturing a semiconductor structure provided in an embodiment of the present application Figure 2 ;
[0056] Figure 6 A structural block diagram of a chip provided in an embodiment of the present application. DETAILED DESCRIPTION
[0057] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in a variety of different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art to which the present application belongs. The terms used herein in the specification of the present application are only for the purpose of realizing the description of specific embodiments and are not intended to limit the present application. The term "and / or" used herein includes any and all combinations of one or more related listed items. In the present application embodiment, the terms "first", "second", "third", "fourth" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the feature defined as "first", "second", "third", "fourth" can explicitly or implicitly include one or more of the features.
[0059] In the related art, the structure of the VDMOS transistor is as follows Figure 1 As shown, it includes a main structure 110 after multiple ion implantation of a silicon substrate, a gate electrode 120 located on the entire surface of the main structure 110, a source 130 on both sides of the gate electrode 120, and a drain 140 located on the back of the main structure 110. The main structure 110 includes an N-type heavily doped (N+) region 111 in contact with the drain 140, an N-type lightly doped (N-) region 112 located on the region, a P-type (P-) base region 113 located below the source 130, and an N-type doped (N+) region 114 located below the source 130 and surrounded by the P-type base region 113. The N-type doped region 114, the P-type base region 113 (P-BASE) and the N-type lightly doped layer 112 form an NPN structure. When a voltage is applied to the gate electrode 120, a depletion region is formed in the N-type lightly doped layer 112. At this time, there is a parasitic capacitance Cgs between the gate and the source, specifically including the parasitic capacitance Cgs(P) of the P-type doping region and the parasitic capacitance Cgs(N) of the N-type doping region; there is a parasitic capacitance Cgd between the gate and the drain, specifically including the parasitic capacitance Cgs(P) and the parasitic capacitance Cgs(N) of the N-type doping region; there is a parasitic capacitance Cds between the source and the drain. The parasitic capacitance affects the switching speed of the VDMOS, resulting in its insufficient performance.
[0060] The above example shows the principle that the parasitic capacitance of the VDMOS transistor affects its switching rate. Other transistors, such as NMOS (Negative Channel Metal Oxide Semiconductor), PMOS (Positive Channel Metal Oxide Semiconductor) or SGT (Shield Gate Trench MOSFET) / SJ (Super Junction MOSFET) / IGBT (Insulated Gate Bipolar Transistor) and other transistors may also have parasitic capacitance that leads to low switching speed and affects transistor performance.
[0061] In view of this, an embodiment of the present application provides a semiconductor structure, such as Figure 2 As shown, the semiconductor structure 200 includes:
[0062] The substrate 210 includes a substrate layer 211, a buried oxide layer 212 and a doping layer 213 stacked in sequence;
[0063] The doping layer 213 includes a first doping region 213 a and a second doping region 213 b spaced apart from each other in a direction parallel to the surface of the substrate 210 ;
[0064] The control electrode 220 is located on the surface of the substrate 210 and covers at least the area between the first doping region 213a and the second doping region 213b;
[0065] The first electrode 230 is located on the surface of the substrate 210 and covers at least a portion of the first doped region 213a;
[0066] The second electrode 240 is located on the surface of the substrate 210 and covers at least a portion of the second doped region 213 b.
[0067] The thickness of the buried oxide layer 212 may be set to be greater than or equal to the thickness of the depletion region formed under the first doping region 213 a and / or the second doping region 213 b when the buried oxide layer 212 is absent.
[0068] Since the width of the depletion region generated at the junction of the doped region and the substrate is relatively narrow, it is easy to generate a large parasitic capacitance, for example, the parasitic capacitance formed by the P-type doped region, the Si dielectric layer in the depletion region, and the N-type substrate. Therefore, in the embodiment of the present application, a buried oxide layer 212 is provided in the substrate 210, and the buried oxide layer 212 is located below the doped layer 213 to form a depletion region, replacing the original depletion region, forming a parasitic capacitance composed of the P-type substrate, the buried oxide layer, and the N-type substrate, so that the plate spacing of the parasitic capacitance is increased, thereby reducing the parasitic capacitance. Refer to the following formula (1)
[0069]
[0070] Among them, ∈ is the dielectric constant, S is the plate area, d is the plate spacing, and k is the electrostatic force constant. It can be understood that the width of the depletion region can be increased through the above-mentioned buried oxide layer, that is, the d of the above-mentioned parasitic capacitance generated is increased, thereby reducing the size of the capacitor C. In addition, since the material of the buried oxide layer is an oxide material such as silicon oxide (SiO2), its dielectric constant is smaller than the dielectric constant of the silicon (Si) substrate, so the size of the parasitic capacitance C can be further reduced.
[0071] It should be noted that the control electrode 220 may include a gate oxide layer covering the substrate 210 and a gate electrode located on the gate oxide layer, thereby forming a gate of the MOS device. The first electrode 230 and the second electrode 240 may be the source and drain of the MOS device, respectively, or both may be the source of the VDMOS. If the semiconductor structure is used to form a VDMOS device, then in some embodiments, such as Figure 2 As shown, the semiconductor structure 200 further includes: a third electrode 250 located on the surface of the substrate 210 opposite to the control electrode 220 .
[0072] It is understandable that if the semiconductor structure 200 is used to form a VDMOS device, the first doping region 213a and the second doping region 213b have the same doping type. Since the first electrode 230 and the second electrode 240 are both source electrodes, the first electrode and the first doping region 213a as a whole can be consistent with the second electrode and the second doping region 213b, and can be symmetrically distributed relative to the center line of the control electrode.
[0073] In addition, since the charge transfer path of VDMOS is between the first doping region and the second doping region, perpendicular to the direction of the substrate, the buried oxide layer 212 does not cover the area directly below the control electrode 220, but is distributed at intervals on both sides, that is, the buried oxide layer 212 includes: a first buried oxide region 212a located under the first doping region 213a and a second buried oxide region 212b located under the second doping region 213b.
[0074] In this way, the plate width of the parasitic capacitor formed under the first doping region 213 a and the second doping region 213 b is increased, so that the parasitic capacitance Cds between the source and drain of the VDMOS and the parasitic capacitance Cgd between the gate and drain can be reduced.
[0075] Furthermore, in some embodiments, the first doping region 213 a and the second doping region 213 b each include: a first doping sub-region P+ and a second doping sub-region N+ having different doping types;
[0076] The tops of the first doped sub-region P+ and the second doped sub-region N+ are located on the same surface; and the second doped sub-region is surrounded by the first doped sub-region.
[0077] Surrounding here means that the other regions of the second doped sub-region except the top surface are surrounded by the first doped sub-region, and the second doped sub-region is in contact with the first electrode or the second electrode to form a source.
[0078] In some embodiments, Figure 2 As shown, the semiconductor structure 200 further includes:
[0079] The lightly doped layer 260 is located between the first buried oxide layer 212a and the second buried oxide layer 212b, and between the first doped region 213a and the second doped region 213b; wherein the thickness of the lightly doped layer is greater than or equal to the thickness of the first buried oxide layer 212a and the second buried oxide layer 212b.
[0080] The lightly doped layer 260 can be used to form a charge channel between the source and the drain. Its doping concentration is low, so that the width of the depletion region formed under the control electrode 220 can be increased, thereby further reducing the parasitic capacitance Cgd between the gate and the drain, and the parasitic capacitance Cds between the source and the drain.
[0081] In the embodiment of the present application, the lightly doped layer 260 may be a doped region formed separately, and its doping concentration is different from the doping concentrations of the substrate layer 211 and the doping layer 213. Exemplarily, the lightly doped layer 260 may be formed separately by grooving the substrate, for example, by photolithography or other etching processes to form a groove on the substrate, and filling the groove with a low-doped semiconductor material, for example, by epitaxial growth or other deposition methods.
[0082] Taking the case where both the lightly doped layer 260 and the substrate layer 211 are N-type doped, the first doped sub-region is P-type doped, and the second doped sub-region is N-type doped, so that an NPN structure can be formed in the source region. When a voltage is applied to the control electrode 220, the NPN is forward biased to form a current path, thereby making the source and drain of the transistor conductive.
[0083] On the contrary, if the lightly doped layer 260 and the substrate layer 211 are both P-type doped, the first doped sub-region is N-type doped, and the second doped sub-region is P-type doped, so that a PNP structure can be formed in the source region.
[0084] In some embodiments, the lightly doped layer 260 , the first doped region 213 a , and the top of the second doped region 213 b are located on the same surface;
[0085] The doping type of the lightly doped layer 260 is the same as the doping type of the substrate layer 211 , and the doping concentration (N−) of the lightly doped layer 260 is less than the doping concentration (N−) of the substrate layer 211 .
[0086] By reducing the doping concentration of the lightly doped layer 260 , the width of the depletion region can be effectively increased, thereby reducing the above-mentioned parasitic capacitance.
[0087] In some embodiments, as described above Figure 2 As shown, the substrate layer 211 includes:
[0088] A first substrate layer 211a having a first doping concentration (N+) and a second substrate layer 211b having a second doping concentration (N-); the first doping concentration is greater than the second doping concentration;
[0089] The bottom of the lightly doped layer 260 is located in the second substrate layer 211b;
[0090] The lightly doped layer 260 has a third doping concentration (N--), and the third doping concentration is less than the second doping concentration.
[0091] It can be understood that the first substrate layer 211a can actually be used as a doping region of the VDMOS drain, so heavy doping is adopted. The embodiment of the present application takes N-type doping as an example, and in actual applications, P-type doping can also be sampled.
[0092] The second substrate layer 211b has the same doping type as the first substrate layer 211a. The second substrate layer 211b is lightly doped, and its doping concentration is lower than that of the first substrate layer 211a. This region serves as a well region of the transistor.
[0093] The lightly doped layer 260 is partially located in the second substrate layer 211b, and its bottom is lower than the bottom of the buried oxide layer. The doping type of the lightly doped layer 260 is the same as that of the substrate layer, but the doping concentration is lower than that of the second substrate layer 211b.
[0094] In the embodiment of the present application, the doping of the substrate layer can be achieved by ion implantation in stages. The first ion implantation can have a higher energy, so that the implantation depth is deeper, thereby forming a heavily doped first substrate layer 211a located at the bottom of the substrate. The second ion implantation has a lower energy, forming a second substrate layer 211b located above the first substrate layer 211a. Taking the formation of an N-type doped substrate layer as an example, it can be achieved by ion implantation of P (phosphorus ions), and if P-type doping is used, it can be achieved by ion implantation of B (boron ions).
[0095] Based on the same inventive concept, the present application also provides a method for manufacturing a semiconductor structure, the method comprising: Figure 3 The following steps are shown. For the specific implementation process, refer to Figure 4 :
[0096] Step S101, providing a substrate 210, such as Figure 4 (a) The substrate 210 includes: a substrate layer 211 (exemplarily, including a heavily doped silicon substrate Si Sub (N+) and a lightly doped well region (N-)), a buried oxide layer 212 (BOX) and a semiconductor layer 214 stacked in sequence; Here, the semiconductor layer 214 (Top Si, top silicon layer) is used to form a doping layer 213 in the final structure. Before forming the doping layer 213, the film layer can be an intrinsic semiconductor, such as a polycrystalline silicon layer or a single crystal silicon layer;
[0097] Step S102, ion implantation is performed in the semiconductor layer to form a first doping region 213a and a second doping region 213b spaced apart from each other in a direction parallel to the substrate surface; the first doping region 213a and the second doping region 213b constitute the above-mentioned doping layer 213;
[0098] Step S103, forming a control electrode 220 on the surface of the substrate 210, so that the control electrode 220 at least covers the area between the first doping region 213a and the second doping region 213b;
[0099] Step S104, forming a first electrode 230 and a second electrode 240 on the surface of the substrate 210, so that the first electrode 230 covers at least a portion of the first doping region 213a, and the second electrode 240 covers at least a portion of the second doping region 213b;
[0100] The thickness of the buried oxide layer 212 may be greater than or equal to the thickness of the depletion region formed under the first doping region 213 a and / or the second doping region 213 b when the buried oxide layer 212 is not provided.
[0101] It is understandable that it should be noted that the control electrode 220 may include a gate oxide layer covering the substrate 210 and a gate electrode located on the gate oxide layer, thereby forming a gate of the MOS device. The first electrode 230 and the second electrode 240 may be the source and drain of the MOS device, respectively, or both may be the source of the VDMOS. If the period is VDMOS, then in some embodiments, the method may further include:
[0102] Step S105 , forming a third electrode 250 on the surface of the substrate 210 opposite to the control electrode 220 ; wherein the first doping region 213 a and the second doping region 213 b have the same doping type.
[0103] It should be noted that the above-mentioned substrate 210 can be purchased according to demand, or it can be obtained by forming a substrate layer 211 on a silicon wafer through ion implantation, then covering it with a buried oxide layer 212, and finally forming a semiconductor layer 214 on the buried oxide layer 212 through an epitaxial growth or deposition process.
[0104] The thickness of the buried oxide layer 212 can be determined according to the size of the semiconductor structure to be manufactured. For example, for a transistor with a larger size (such as a larger channel width-to-length ratio), the required buried oxide layer 212 thickness is larger; for a transistor with a smaller size, the required buried oxide layer 212 thickness is smaller.
[0105] In addition, the doping concentration of each of the above-mentioned doping regions can also be set according to actual needs. For example, for a transistor with a larger size, the doping concentration can be higher, and for a transistor with a smaller size, the doping concentration can be lower. Alternatively, for a transistor with lower switching characteristics requirements, the doping concentration can be lower, and for a transistor with higher switching characteristics requirements, the doping concentration can be higher.
[0106] In some embodiments, the method further comprises: Figure 5 The steps shown are as follows. For the specific process, please refer to Figure 4 :
[0107] Step S201, forming a recessed area 410 on a substrate; Figure 4 As shown in (c), the recessed region 410 is located between the first doping region 213a and the second doping region 213b, separating the buried oxide layer 212 into the first buried oxide region 212a and the second buried oxide region 212b; the bottom of the recessed region 410 is located in the substrate layer 211;
[0108] Step S202: Fill the recessed area 410 with a lightly doped semiconductor material to form a lightly doped layer 260, such as Figure 4 (d) as shown.
[0109] In the embodiment of the present application, the lightly doped layer 260 can be manufactured separately, referring to Figure 4, a groove is dug on the surface of the substrate where the buried oxide layer 212 and the semiconductor layer 214 are formed to form a recessed area 410, which is the area where the lightly doped layer 260 is finally formed. The depth of the recessed area 260 can be greater than or equal to the total thickness of the buried oxide layer 212 and the doped layer 213, so the bottom of the recessed area 260 is located in the substrate layer 211, or in the plane where the interface between the substrate layer 211 and the buried oxide layer 212 is located. The recessed area 410 is located between the first doped area 213a and the second doped area 213b, and separates the buried oxide layer 212 into the first buried oxide area 212a and the second buried oxide area 212b. In other words, the formation of the recessed area 410 will separate the original entire buried oxide layer 212 and the semiconductor layer 214 above the buried oxide layer 212.
[0110] In some embodiments, in the above step S202, filling the recessed region 410 with a lightly doped semiconductor material to form the lightly doped layer 260 includes:
[0111] Filling the recessed area 410 with a lightly doped semiconductor material by an epitaxial growth process to form a lightly doped layer 260; or
[0112] Filling the recessed area 410 with an intrinsic semiconductor material by an epitaxial growth process, and performing a first ion implantation on the intrinsic semiconductor material to form a lightly doped layer 260;
[0113] The doping type of the lightly doped layer 260 is the same as the doping type of the substrate layer, and the doping concentration of the lightly doped layer 260 is less than the doping concentration of the substrate layer.
[0114] The lightly doped layer 260 can be used as a charge channel of the VDMOS. During fabrication, the recessed region 410 can be filled with silicon or other semiconductor materials, and then a first ion implantation can be performed to form a doped semiconductor material; or the recessed region 410 can be directly filled with a semiconductor material that has been lightly doped. The filling method can be an epitaxial growth process (EPI), including chemical vapor deposition and molecular beam epitaxy.
[0115] It should be noted that the ion implantation operation performed in the semiconductor layer 214 in the above step 102 can be performed after the lightly doped layer 260 is formed, or before the lightly doped layer 260 is formed. If it is performed after the lightly doped layer 260 is formed, the area where the lightly doped layer 260 is formed can be shielded, and then ion implantation is performed on the semiconductor layer 214 on both sides thereof to form the first doped region 213a and the second doped region 213b, respectively. If it is performed before the lightly doped layer 260 is formed, ion implantation can be performed on the entire semiconductor layer 214 first, and then in the above step S201 when the lightly doped layer 260 is formed, the doped layer 213 after ion implantation is separated by forming a recessed area 410 to form the above-mentioned first doped region 213a and the second doped region 213b.
[0116] In some embodiments, ion implantation is performed in the semiconductor layer 214 to form a first doping region 213a and a second doping region 213b spaced apart from each other in a direction parallel to the surface of the substrate 210, including:
[0117] Performing a second ion implantation in the semiconductor layer to form a first doped sub-region P+;
[0118] A third ion implantation is performed within the range where the first doped sub-region P+ is located to form a second doped sub-region N+ surrounded by the first doped sub-region P+; wherein the first doped sub-region P+ and the top of the second doped sub-region N+ are located on the same surface; and the doping types of the second ion implantation and the third ion implantation are different.
[0119] The above-mentioned first doping region 213a and the second doping region 213b both include two doping types. For example, P-type ions can be firstly implanted into the semiconductor layer to form a P+ doping region, and then N-type ions can be implanted into the P+ doping region to form an N+ second doping sub-region, and the remaining P+ doping region constitutes the first doping sub-region.
[0120] It can be understood that the second ion implantation has a deeper implantation depth and a larger range, while the third ion implantation has a shallower implantation depth and a smaller range.
[0121] In some embodiments, the step S201 of forming a recessed area 410 on the substrate includes:
[0122] A hard mask 420 is formed on the surface of the substrate, such as Figure 4 (b)
[0123] patterning the hard mask 420 to expose a portion of the surface of the substrate;
[0124] The exposed surface area of the substrate is etched to form a recessed area 410, such as Figure 4 (c) as shown.
[0125] That is, through the hard mask photolithography technology, a patterned opening is formed on the hard mask to expose the substrate surface where the recessed region 410 is to be formed. Then, the substrate under the opening is etched to form the recessed region 410.
[0126] For example, the hard mask 420 may include a thin film made of one or more materials such as silicon oxide, titanium nitride, silicon nitride, and amorphous carbon. Figure 4 The stack of the pad oxide layer (Pad OX) and the silicon nitride layer (SiN) shown in the figure constitutes a hard mask 420. It is deposited by a process such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). The thickness of the hard mask 420 can also be adjusted according to the depth and width required for etching to form the recessed area 410.
[0127] In some embodiments, Figure 4 (e), the method further comprises:
[0128] removing the hard mask 420;
[0129] The surfaces of the substrate 210 and the lightly doped layer 260 are planarized.
[0130] It should be noted that after the lightly doped layer 260 is formed in the recessed region 410, the remaining hard mask 420 can be removed by using an etching solution or other substances, so that the substrate formed with the lightly doped layer 260 is exposed. Then, the surface of the substrate is planarized by using a CMP (Chemical Mechanical Polishing) or other technology.
[0131] Then, the above steps S102 to S105 may be performed to form the above control electrode 220, the first electrode 230, the second electrode 240 and the third electrode 250 respectively. Figure 4 (f) as shown.
[0132] Thus, through the above steps provided in the embodiment of the present application, a buried oxide layer is formed under the doped region below the source and / or drain of the transistor, and the inter-plate distance of the parasitic capacitor is increased through the buried oxide layer, and the dielectric constant of the dielectric material of the parasitic capacitor is increased, thereby reducing the parasitic capacitance. In addition, by using the above lightly doped layer, the depletion region under the charge channel can also be made wider, thereby reducing the parasitic capacitance. In this way, the switching speed and withstand voltage strength of the transistor can be effectively improved, and the performance of the transistor can be improved.
[0133] Based on the same inventive concept, the present application embodiment provides a chip, such as Figure 6As shown, the chip 600 includes: a memory cell array 610 and / or an integrated circuit 620; wherein the memory cell array 610 and / or the integrated circuit 620 includes one or more semiconductor structures 200 ( Figure 6 Only an exemplary situation is shown, and the embodiments of the present application are not limited thereto).
[0134] It should be understood that "some embodiments", "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the sequence number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned sequence numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments.
[0135] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.
[0136] The above is only an implementation method of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.
Claims
1. A semiconductor structure, characterized in that: include: substrate; The substrate comprises a substrate layer, a buried oxide layer and a doping layer stacked in sequence; The doping layer includes a first doping region and a second doping region spaced apart from each other in a direction parallel to the surface of the substrate; A control electrode, located on the surface of the substrate and covering at least a region between the first doping region and the second doping region; A first electrode, located on the surface of the substrate and covering at least a portion of the first doped region; The second electrode is located on the surface of the substrate and covers at least a portion of the second doped region.
2. The semiconductor structure according to claim 1, characterized in that: Also includes: A third electrode is located on the surface of the substrate opposite to the control electrode; The first doping region and the second doping region have the same doping type; The buried oxide layer includes: a first buried oxide region located under the first doping region and a second buried oxide region located under the second doping region.
3. The semiconductor structure according to claim 2, characterized in that: Also includes: A lightly doped layer is located between the first buried oxide layer and the second buried oxide layer, and between the first doped region and the second doped region; wherein the thickness of the lightly doped layer is greater than or equal to the thickness of the first buried oxide layer and the second buried oxide layer.
4. The semiconductor structure according to claim 3, characterized in that: The lightly doped layer, the first doped region, and the tops of the second doped region are located on the same surface; The doping type of the lightly doped layer is the same as the doping type of the substrate layer, and the doping concentration of the lightly doped layer is less than the doping concentration of the substrate layer.
5. The semiconductor structure according to claim 4, characterized in that: The substrate layer comprises: a first substrate layer with a first doping concentration and a second substrate layer with a second doping concentration; the first doping concentration is greater than the second doping concentration; The bottom of the lightly doped layer is located in the second substrate layer; The lightly doped layer has a third doping concentration, and the third doping concentration is less than the second doping concentration.
6. The semiconductor structure according to any one of claims 1 to 5, characterized in that: The first doping region and the second doping region each include: a first doping sub-region and a second doping sub-region having different doping types; The tops of the first doped sub-region and the second doped sub-region are located on the same surface; and the second doped sub-region is surrounded by the first doped sub-region.
7. A method for manufacturing a semiconductor structure, characterized in that: The method comprises: Providing a substrate, the substrate comprising: a substrate layer, a buried oxide layer and a semiconductor layer stacked in sequence; Performing ion implantation in the semiconductor layer to form a first doping region and a second doping region spaced apart from each other in a direction parallel to the surface of the substrate; forming a control electrode on the surface of the substrate, so that the control electrode at least covers the area between the first doping region and the second doping region; A first electrode and a second electrode are formed on the surface of the substrate, so that the first electrode covers at least a portion of the first doped region, and the second electrode covers at least a portion of the second doped region.
8. The manufacturing method according to claim 7, characterized in that: The method further comprises: A recessed region is formed on the substrate; the recessed region is located between the first doping region and the second doping region, and the buried oxide layer is separated into a first buried oxide region and a second buried oxide region; the bottom of the recessed region is located in the substrate layer; The recessed area is filled with a lightly doped semiconductor material to form a lightly doped layer.
9. The manufacturing method according to claim 8, characterized in that: The forming of a recessed area on the substrate comprises: forming a hard mask on the surface of the substrate; patterning the hard mask to expose a portion of the surface of the substrate; The exposed surface area of the substrate is etched to form the recessed area.
10. The manufacturing method according to claim 9, characterized in that: The method further comprises: removing the hard mask; The surfaces of the substrate and the lightly doped layer are planarized.
11. The manufacturing method according to claim 8, characterized in that: The step of filling the recessed area with a lightly doped semiconductor material to form a lightly doped layer comprises: Filling the lightly doped semiconductor material in the recessed area by an epitaxial growth process to form the lightly doped layer; or Filling the recessed area with an intrinsic semiconductor material by an epitaxial growth process, and performing a first ion implantation on the intrinsic semiconductor material to form the lightly doped layer; The doping type of the lightly doped layer is the same as the doping type of the substrate layer, and the doping concentration of the lightly doped layer is less than the doping concentration of the substrate layer.
12. The manufacturing method according to any one of claims 7 to 11, characterized in that: The step of implanting ions into the semiconductor layer to form a first doping region and a second doping region spaced apart from each other in a direction parallel to the surface of the substrate comprises: Performing a second ion implantation in the semiconductor layer to form a first doped sub-region; A third ion implantation is performed within the range where the first doped sub-region is located to form a second doped sub-region surrounded by the first doped sub-region; wherein the top of the first doped sub-region and the second doped sub-region are located on the same surface; and the doping types of the second ion implantation and the third ion implantation are different.
13. The manufacturing method according to any one of claims 7 to 11, characterized in that: The method further comprises: forming a third electrode on the surface of the substrate opposite to the control electrode; The first doping region and the second doping region have the same doping type.
14. A chip, characterized in that: include: Memory cell arrays and / or integrated circuits; Wherein, the memory cell array and / or integrated circuit comprises one or more semiconductor structures as claimed in any one of claims 1 to 6.