Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The channel structure layer is located at the top of the substrate, and the channel structure layer comprises one or more two-dimensional material channel layers which are arranged at intervals in the longitudinal direction; the device gate structure is located on the substrate and stretches across the channel structure layer, and the device gate structure surrounds and covers the two-dimensional material channel layer; the source-drain contact layer is located in the channel structure layer on the two sides of the device gate structure; the inner wall layer is located between the side wall of the device gate structure below the two-dimensional material channel layer and the source-drain contact layer; and the interlayer dielectric layer is located at the top of the source-drain contact layer, and the interlayer dielectric layer covers the side wall of the device gate structure. The channel layer material of the semiconductor structure is a two-dimensional material, and the channel layer adopts the two-dimensional material, so that the charge migration rate can be improved, and the performance of the semiconductor structure can be further improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] High-performance integrated circuit technology developed since the 1960s is mainly based on silicon-based processes, especially thin-body field-effect transistor technology, such as fin transistors or silicon-on-insulator technology. However, as the size of silicon-based transistor devices decreases, below about 3nm in thickness, as the thickness of the thin layer of single-crystal silicon as the channel continues to decrease, the carrier transport in the channel is increasingly affected by the scattering of the rough interface, resulting in a significant decrease in mobility, which seriously affects the performance of silicon-based devices.

[0003] In order to better adapt to the requirements of proportional reduction of transistor size, semiconductor processes have gradually begun to transition from planar transistors to three-dimensional transistors with higher efficiency, such as fin field effect transistors (FinFETs), gate-all-around (GAA) transistors, etc. Among them, the surround-all-around gate transistors include vertical surround-all-around gate transistors and horizontal surround-all-around gate transistors. In the surround-all-around gate transistor, the gate surrounds the area where the channel is located from all sides. Compared with the planar transistor, the gate of the surround-all-around gate transistor has a stronger control ability over the channel and can better suppress the short channel effect. With the further reduction of device size, how to improve the performance of surround-all-around gate structure devices is becoming more and more difficult and challenging. Using two-dimensional semiconductors as channel materials, such as transition metal chalcogenides, graphene, black phosphorus, etc., has become an ideal material for the next generation of transistor devices after silicon-based transistors due to their high mobility, adjustable energy bands, good flexibility and uniform surface flatness. Using two-dimensional materials as channels can significantly improve carrier mobility and further reduce the thickness of the channel, controlling the channel thickness to below 1-2nm, greatly improving the density and performance of transistors in integrated circuits.

[0004] How to integrate high-performance two-dimensional channel materials into all-around gate transistors and large-scale integrated circuits while maintaining the performance improvements brought by the materials is an obstacle to the development of this field. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which is beneficial to further improve the performance of the semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate; a channel structure layer, located on the top of the substrate, the channel structure layer includes one or more two-dimensional material channel layers spaced apart in the vertical direction; a device gate structure, located on the substrate and spanning the channel structure layer, the device gate structure surrounds and covers the two-dimensional material channel layer; a source-drain contact layer, located in the channel structure layer on both sides of the device gate structure; an inner wall layer, located between the side wall of the device gate structure below the two-dimensional material channel layer and the source-drain contact layer; an interlayer dielectric layer, located on the top of the source-drain contact layer, and the interlayer dielectric layer covers the side wall of the device gate structure.

[0007] Optionally, with the direction parallel to the substrate surface and perpendicular to the extension direction of the device gate structure as the lateral direction, the lateral dimension of the inner wall layer is 2 nanometers to 6 nanometers.

[0008] Optionally, the material of the inner wall layer includes one or more of silicon nitride, silicon oxide and silicon oxynitride.

[0009] Optionally, the material of the two-dimensional material channel layer includes one or both of transition metal disulfide and transition metal diselenide.

[0010] Optionally, the interlayer dielectric layer includes a first interlayer dielectric layer located on the sidewall of the device gate structure, and a second interlayer dielectric layer located on the sidewall of the first interlayer dielectric layer, and the sidewall of the first interlayer dielectric layer opposite to the device gate structure is flush with the sidewall of the two-dimensional material channel layer.

[0011] Optionally, the device gate structure includes a gate dielectric layer surrounding and covering the two-dimensional material channel layer, and a gate electrode layer covering the gate dielectric layer; the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3; the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0012] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate, on which a sacrificial stack structure is formed, the sacrificial stack structure including one or more sacrificial stacks stacked in sequence in the vertical direction, the sacrificial stack including a first sacrificial layer and a second sacrificial layer located on the first sacrificial layer; removing the first sacrificial layer; forming a two-dimensional material channel layer at the bottom and top of the second sacrificial layer and at the top of the substrate; forming a third sacrificial layer between adjacent two-dimensional material channel layers, the third sacrificial layer covering the two-dimensional material channel layer; forming a gate structure spanning the second sacrificial layer, the two-dimensional material channel layer and the third sacrificial layer on the top of the substrate; forming a first groove in the second sacrificial layer, the two-dimensional material channel layer and the third sacrificial layer on both sides of the gate structure; and forming a source-drain contact layer covering the two-dimensional material channel layer in the first groove.

[0013] Optionally, the step of forming a two-dimensional material channel layer includes: forming a two-dimensional material channel material layer at the bottom, sidewall and top of the second sacrificial layer, and the top of the substrate; removing the two-dimensional material channel material layer on the sidewall of the second sacrificial layer, and the remaining two-dimensional material channel material layer located at the bottom and top of the second sacrificial layer, and the top of the substrate serves as the two-dimensional material channel layer.

[0014] Optionally, the process of forming the two-dimensional material channel layer includes a chemical vapor deposition process or a molecular beam epitaxy process.

[0015] Optionally, the number of film layers of the two-dimensional material channel layer is 1 or 2.

[0016] Optionally, the step of forming a third sacrificial material layer between adjacent two-dimensional material channel layers includes: forming a third sacrificial material layer on the top of the substrate to cover the top and bottom of the two-dimensional material channel layer and the side wall of the second sacrificial layer, the third sacrificial material layer filling the spatial area directly opposite the adjacent two-dimensional material channel layers; removing the side wall of the second sacrificial layer and the side wall of the two-dimensional material channel layer, and the third sacrificial material layer on the top of the topmost second sacrificial layer, and the remaining third sacrificial material layer located in the spatial area directly opposite the adjacent two-dimensional material channel layers serves as the third sacrificial layer.

[0017] Optionally, the material of the third sacrificial layer includes one or more of silicon oxide, amorphous silicon, aluminum oxide and SOC.

[0018] Optionally, the step of forming a gate structure spanning the second sacrificial layer, the two-dimensional material channel layer and the third sacrificial layer on the top of the substrate includes: forming a gate material layer spanning the second sacrificial layer, the two-dimensional material channel layer and the third sacrificial layer on the top of the substrate; forming a patterned first mask layer on the top of the gate material layer; using the first mask layer as a mask, patterning the gate material layer, and using the remaining gate material layer as the gate structure.

[0019] Optionally, after forming the first groove and before forming the source-drain contact layer, it also includes: laterally etching the second sacrificial layer and the third sacrificial layer along a direction parallel to the substrate surface and perpendicular to the extension direction of the gate structure to form a second groove, the second groove is surrounded by the adjacent two-dimensional material channel layer and the second sacrificial layer; or, the second groove is surrounded by the adjacent two-dimensional material channel layer and the third sacrificial layer; forming an inner wall layer in the second groove; in the step of forming the source-drain contact layer, the source-drain contact layer covers the inner wall layer.

[0020] Optionally, along a direction parallel to the substrate surface and perpendicular to an extension direction of the gate structure as a lateral direction, a lateral dimension of the second groove is 3 nanometers to 7 nanometers.

[0021] Optionally, the material of the inner wall layer includes one or more of silicon nitride, silicon oxide and silicon oxynitride.

[0022] Optionally, the step of forming the first groove includes: forming a first interlayer dielectric layer covering the side walls of the gate structure on the top of the substrate; forming a patterned second mask layer on the top of the gate structure and the first interlayer dielectric layer, the second mask layer covering the gate structure and part of the first interlayer dielectric layer on both sides of the gate structure; using the second mask layer as a mask layer, patterning the first interlayer dielectric layer, the second sacrificial layer, the two-dimensional material channel layer and the third sacrificial layer to form a first groove; and removing the second mask layer.

[0023] Optionally, the step of forming a source-drain contact layer in the first groove includes: forming a source-drain doping material layer in the first groove and in the side area of ​​the gate structure; removing the source-drain doping material layer in the side area of ​​the gate structure, and the remaining source-drain doping material layer located in the first groove serves as the source-drain contact layer.

[0024] Optionally, after forming the source-drain contact layer, the method for forming the semiconductor structure also includes: forming a second interlayer dielectric layer covering the side walls of the gate structure on top of the source-drain contact layer; removing the gate structure and forming a gate opening in the second interlayer dielectric layer; removing the second sacrificial layer and the third sacrificial layer exposed by the gate opening, and forming a through groove connected to the gate opening above the two-dimensional material channel layer; forming a device gate structure in the gate opening and the through groove, wherein the device gate structure surrounds the two-dimensional material channel layer.

[0025] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0026] The method for forming a semiconductor structure provided by an embodiment of the present invention forms a two-dimensional material channel layer at the bottom and top of the second sacrificial layer and the top of the substrate, forms a third sacrificial layer between adjacent two-dimensional material channel layers, the third sacrificial layer covers the two-dimensional material channel layer, and forms a gate structure spanning the second sacrificial layer, the two-dimensional material channel layer and the third sacrificial layer on the top of the substrate, forms a first groove in the second sacrificial layer, the two-dimensional material channel layer and the third sacrificial layer on both sides of the gate structure, and forms a source-drain contact layer covering the two-dimensional material channel layer in the first groove, which means that the channel layer material of the semiconductor structure is a two-dimensional material, which can improve the volume miniaturization capability and device electrical performance of the semiconductor structure, and can increase the rate of charge migration, thereby further improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0028] Figures 2 to 25 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0029] At present, the performance and further size reduction capability of all-around gate structure devices need to be improved. As the process technology of semiconductor structure is further reduced, the charge migration in the channel of all-around gate structure devices decreases rapidly as the channel thickness decreases, resulting in the volume and electrical performance of all-around gate structure devices being limited.

[0030] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, on which a sacrificial stack structure is formed, the channel stack structure including one or more sacrificial stacks stacked in sequence in the vertical direction, the sacrificial stack including a first sacrificial layer and a second sacrificial layer located on the first sacrificial layer; removing the first sacrificial layer; forming a two-dimensional material channel layer at the bottom and top of the second sacrificial layer and at the top of the substrate; forming a third sacrificial layer between adjacent two-dimensional material channel layers, the third sacrificial layer covering the two-dimensional material channel layer; forming a gate structure spanning the second sacrificial layer, the two-dimensional material channel layer and the third sacrificial layer on the top of the substrate; forming a first groove in the second sacrificial layer, the two-dimensional material channel layer and the third sacrificial layer on both sides of the gate structure; and forming a source-drain contact layer covering the two-dimensional material channel layer in the first groove.

[0031] An embodiment of the present invention provides a method for forming a semiconductor structure, forming a two-dimensional material channel layer at the bottom and top of a second sacrificial layer and at the top of a substrate, forming a third sacrificial layer between adjacent two-dimensional material channel layers, the third sacrificial layer covering the two-dimensional material channel layer, forming a gate structure spanning the second sacrificial layer, the two-dimensional material channel layer and the third sacrificial layer on the top of the substrate, forming a first groove in the second sacrificial layer, the two-dimensional material channel layer and the third sacrificial layer on both sides of the gate structure, and forming a source-drain contact layer covering the two-dimensional material channel layer in the first groove, which means that the channel layer material of the semiconductor structure is a two-dimensional material, which can increase the rate of charge migration, and can improve the volume miniaturization capability and device electrical performance of the semiconductor structure, thereby further improving the performance of the semiconductor structure.

[0032] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0033] Figure 1 It is a schematic diagram of the corresponding structure in one embodiment of the semiconductor structure of the present invention.

[0034] The semiconductor structure includes: a substrate (not marked); a channel structure layer (not marked), located on the top of the substrate, the channel structure layer includes one or more two-dimensional material channel layers 221 spaced apart in the vertical direction; a device gate structure 270, located on the substrate and spanning the channel structure layer, the device gate structure 270 surrounds and covers the two-dimensional material channel layer 221; a source-drain contact layer 250, located in the channel structure layer on both sides of the device gate structure 270; an inner wall layer 290, located between the sidewall of the device gate structure 270 below the two-dimensional material channel layer 221 and the source-drain contact layer 250; an interlayer dielectric layer (not marked), located on the top of the source-drain contact layer 250, and the interlayer dielectric layer covers the sidewall of the device gate structure 270.

[0035] It should be noted that the device gate structure 270 surrounds and covers the two-dimensional material channel layer 221, and the channel structure layer includes one or more two-dimensional material channel layers 221 spaced apart in the longitudinal direction. The two-dimensional material channel layer 221 is used as a conductive channel of the semiconductor structure, and the material of the conductive channel is a two-dimensional material. The use of two-dimensional materials in the channel layer can increase the rate of charge migration, thereby further improving the performance of the semiconductor structure.

[0036] The substrate is used to provide a process platform for setting up gate-all-around (GAA) transistors.

[0037] In this embodiment, the base is a three-dimensional base, and the base includes a substrate 213 and a protruding portion 214 protruding from the substrate 213 .

[0038] In this embodiment, the substrate 213 is a silicon substrate 213. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.

[0039] The protrusion 214 exposes a portion of the substrate 213 , thereby providing a process basis for subsequently forming an isolation layer.

[0040] In this embodiment, the material of the protrusion 214 is the same as that of the substrate 213, and the material of the protrusion 214 is silicon. In other embodiments, the material of the protrusion may also be a semiconductor material suitable for forming a fin, such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, and the material of the protrusion may also be different from that of the substrate.

[0041] The channel structure layer is located on the top of the substrate, and the channel structure layer includes one or more two-dimensional material channel layers 221 spaced apart in the vertical direction.

[0042] The extending direction of the two-dimensional material channel layer 221 is the same as the extending direction of the protrusion 214 .

[0043] The channel structure layer is used as a conductive channel of the semiconductor structure.

[0044] It should be noted that the number of film layers of the two-dimensional material channel layer 221 should not be too many. If the number of film layers of the two-dimensional material channel layer 221 is too many, the probability of contact between the two-dimensional material channel layers 221 stacked at intervals increases, thereby causing the conductive channel of the semiconductor structure to fail, thereby increasing the probability of electrical failure of the semiconductor structure. For this reason, in this embodiment, the number of film layers of the two-dimensional material channel layer 221 is 1 to 2 layers.

[0045] In this embodiment, the material of the two-dimensional material channel layer 221 includes one or both of transition metal disulfide and transition metal diselenide.

[0046] Specifically, transition metal disulfides and transition metal diselenides refer to compounds containing transition metal elements and sulfur elements or selenium elements, which have good electrical properties. At the same time, the basic structure of transition metal disulfides and transition metal diselenides is generally a layered structure, which is a two-dimensional layered material composed of multiple atoms and has high mechanical strength, thermal stability and chemical stability.

[0047] As an example, the material of the two-dimensional material channel layer 221 includes one or more of MoS2, WS2 and WSe2.

[0048] The device gate structure 270 is used to control the opening and closing of the conductive channel when the device is working.

[0049] Specifically, the device gate structure 270 is a metal gate structure.

[0050] In this embodiment, the device gate structure includes a gate dielectric layer (not shown) surrounding the two-dimensional material channel layer 221 and a gate electrode layer (not shown) covering the gate dielectric layer.

[0051] In this embodiment, the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3.

[0052] Specifically, the gate dielectric layer includes a gate oxide layer that conformally covers a portion of the top, a portion of the sidewall, and a portion of the bottom of the two-dimensional material channel layer 221, and a high-k gate dielectric layer that conformally covers the gate oxide layer. The material of the high-k gate dielectric layer is a high-k dielectric material, which refers to a dielectric material having a relative dielectric constant greater than the relative dielectric constant of silicon oxide.

[0053] The gate electrode layer is used to electrically connect to an external structure. The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC. Specifically, the gate electrode layer may include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer may only include the work function layer.

[0054] In this embodiment, the source-drain contact layer 250 is located in the channel structure layer on both sides of the device gate structure 270 .

[0055] Specifically, the source-drain contact layer 250 is used as the source region and the drain region of the transistor.

[0056] The inner wall layer 290 can isolate the source-drain contact layer 250 from the device gate structure 270 , which is beneficial to reducing the parasitic capacitance between the source-drain contact layer 250 and the device gate structure 270 .

[0057] In this embodiment, the material of the inner wall layer 290 includes one or more of silicon nitride, silicon oxide, and silicon oxynitride.

[0058] Specifically, silicon nitride, silicon oxide, and silicon oxynitride are all dielectric materials that can electrically isolate the device gate structure 270 and the source-drain contact layer 250 .

[0059] It should be noted that, with the direction parallel to the substrate surface and perpendicular to the extension direction of the device gate structure 270 as the lateral direction, the lateral dimension of the inner wall layer 290 should not be too large or too small. If the lateral dimension of the inner wall layer 290 is too large, it will squeeze the channel length of the short channel device; if the lateral dimension of the inner wall layer 290 is too small, it will easily lead to a decrease in the effect of the inner wall layer 290 on the electrical isolation between the source-drain contact layer 250 and the device gate structure 270, thereby increasing the parasitic capacitance between the source-drain contact layer 250 and the device gate structure 270. For this reason, in this embodiment, with the direction parallel to the substrate surface and perpendicular to the extension direction of the device gate structure 270 as the lateral direction, the lateral dimension of the inner wall layer 290 is 2 nanometers to 6 nanometers.

[0060] The interlayer dielectric layer is used to achieve electrical isolation between adjacent devices.

[0061] In this embodiment, the interlayer dielectric layer includes a first interlayer dielectric layer 236 located on the side wall of the device gate structure 270, and a second interlayer dielectric layer 251 located on the side wall of the first interlayer dielectric layer 236. The side wall of the first interlayer dielectric layer 236 opposite to the device gate structure 270 is flush with the side wall of the two-dimensional material channel layer 221.

[0062] Specifically, in the formation process of the semiconductor structure, by setting a first interlayer dielectric layer 236 on the side wall of the device gate structure 270, the two-dimensional material channel layer 221 located directly below the first interlayer dielectric layer 236 can be retained, and the space area directly below the first interlayer dielectric layer 236 is used to form an inner wall layer 290, so that the two-dimensional material channel layer 221 directly below the device gate structure 270 can be surrounded and covered by the device gate structure 270, so that the contact area between the device gate structure 270 and the two-dimensional material channel layer 221 is increased, which can further improve the rate of charge migration in the conductive channel in the semiconductor structure and improve the performance of the semiconductor structure.

[0063] In this embodiment, the material of the first interlayer dielectric layer 236 includes silicon oxide.

[0064] The second interlayer dielectric layer 251 is used to protect the source-drain contact layer 250 and is also used to electrically isolate a device gate structure 270 that is subsequently formed.

[0065] In this embodiment, the material of the second interlayer dielectric layer 251 includes silicon oxide.

[0066] Accordingly, an embodiment of the present invention further provides a method for forming a semiconductor structure. Figures 2 to 25 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0067] refer to Figures 2 to 8 ,in, Figure 2 It is a top view. Figure 3 to Figure 4 yes Figure 2 Cross-sectional view along AA direction, Figure 5 It is a top view. Figures 6 to 8 yes Figure 5 A cross-sectional view along the AA direction provides a substrate 100 on which a sacrificial stack structure 108 is formed. The sacrificial stack structure 108 includes one or more sacrificial stacks 111 stacked in sequence in the longitudinal direction. The sacrificial stack 111 includes a first sacrificial layer 109 and a second sacrificial layer 110 located on the first sacrificial layer 109 .

[0068] The substrate 100 is used to provide a process platform for forming a gate-all-around (GAA) transistor.

[0069] In this embodiment, the substrate 100 is a three-dimensional substrate 100 , and the substrate 100 includes a substrate 113 and a protruding portion 114 protruding from the substrate 113 .

[0070] In this embodiment, the substrate 113 is a silicon substrate 113. In other embodiments, the substrate material may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.

[0071] The protrusion 114 exposes a portion of the substrate 113 , thereby providing a process basis for subsequently forming an isolation layer.

[0072] In this embodiment, the material of the protrusion 114 is the same as that of the substrate 113, and the material of the protrusion 114 is silicon. In other embodiments, the material of the protrusion may also be a semiconductor material suitable for forming a fin, such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, and the material of the protrusion may also be different from that of the substrate.

[0073] In this embodiment, the sacrificial stacked structure 108 is located on the top of the protruding portion 114 , and the extending direction of the sacrificial stacked structure 108 is the same as the extending direction of the protruding portion 114 .

[0074] In this embodiment, the sacrificial stack structure 108 includes one or more sacrificial stacks 111 stacked in sequence in the longitudinal direction.

[0075] Each sacrificial stack 111 includes a first sacrificial layer 109 and a second sacrificial layer 110 located on the first sacrificial layer 109. The sacrificial stack 111 provides a process basis for subsequently forming a two-dimensional material channel layer with suspended spacing.

[0076] Specifically, the first sacrificial layer 109 supports the second sacrificial layer 110, and the first sacrificial layer 109 can be removed subsequently to expose the second sacrificial layer 110, providing a process basis for the subsequent formation of a two-dimensional material channel layer at the bottom and top of the second sacrificial layer 110 and the top of the substrate 100, and at the same time, it also occupies a spatial position for the subsequent formation of a device gate structure.

[0077] In this embodiment, the material of the first sacrificial layer 109 is SiGe, and the material of the second sacrificial layer 110 is Si. In the subsequent process of removing the first sacrificial layer 109, the etching selectivity of SiGe and Si is relatively high, so by setting the material of the first sacrificial layer 109 to SiGe and the material of the second sacrificial layer 110 to Si, the effect of the removal process of the first sacrificial layer 109 on the second sacrificial layer 110 can be effectively reduced, and the damage to the surface of the second sacrificial layer 110 is reduced, providing a better growth interface for the subsequent formation of a two-dimensional material channel layer, which is conducive to the subsequent formation of a two-dimensional material channel layer on the exposed surface of the second sacrificial layer 110, and the two-dimensional material channel layer is used as a conductive channel of a surround gate transistor, thereby improving the electrical performance of the semiconductor structure.

[0078] Combined with reference Figures 2 to 8 , the steps of forming the sacrificial stack structure 108 on the substrate 100 are described in detail.

[0079] refer to Figures 2 to 3 , a first direction (such as Figure 2 in the Y direction) and in the second direction (as shown in Figure 2 The stacked material layer 104 extends in the first direction and the second direction, and the stacked material layer 104 includes one or more auxiliary stacks 103 stacked in sequence in the longitudinal direction, and the auxiliary stack 103 includes a first auxiliary sacrificial layer 102 and a second auxiliary sacrificial layer 101 located on the first auxiliary sacrificial layer 102.

[0080] The stack material layer 104 provides a process basis for subsequently forming a sacrificial stack structure 108 .

[0081] refer to Figure 4 , an opening 106 is formed in the stacked material layer 104 , and the opening 106 extends along the second direction.

[0082] The opening 106 provides a spatial position for the subsequent formation of a hard mask layer. At the same time, a hard mask layer is formed in the opening 106 so that the side walls of the first auxiliary sacrificial layer 102 and the side walls of the second auxiliary sacrificial layer 101 are in contact with the hard mask layer. In the subsequent process of removing the first sacrificial layer 109, the hard mask layer can support the second sacrificial layer 110, thereby reducing the probability of collapse of the second sacrificial layer 110 during the process of removing the first sacrificial layer 109.

[0083] In this embodiment, the process of forming the opening 106 includes an anisotropic dry etching process.

[0084] It should be noted that the opening 106 is formed by an anisotropic dry etching process, so that the sidewall morphology of the opening 106 is of high quality. In the subsequent process of forming a hard mask layer in the opening 106, the hard mask layer can be in contact with the sidewalls of the first auxiliary sacrificial layer 102 and the sidewalls of the second auxiliary sacrificial layer 101.

[0085] refer to Figure 5 to Figure 6 A hard mask layer 107 extending along the first direction and arranged in parallel with each other along the second direction is formed on the top of the stacked material layer 104 , and the hard mask layer 107 is also filled in the opening 106 .

[0086] The hard mask layer 107 is used as an etching mask for subsequently patterning the stacked material layer 104 to form a sacrificial stacked structure 108 .

[0087] In this embodiment, the material of the hard mask layer 107 includes one or both of silicon nitride and silicon oxide.

[0088] refer to Figures 7 and 8 , using the hard mask layer 107 as a mask, the stacked material layer 104 is patterned to form a sacrificial stacked structure 108 on the substrate 100 .

[0089] As an example, the process of patterning the stacked material layer 104 using the hard mask layer 107 as a mask includes a dry etching process.

[0090] It should be noted that, in the process of patterning the laminated material layer 104 , a partial thickness of the substrate 100 is also patterned to transform the substrate 100 into a three-dimensional substrate 100 , which includes a substrate 113 and a protruding portion 114 protruding from the substrate 113 .

[0091] refer to Fig. 9 , remove the first sacrificial layer 109.

[0092] Specifically, removing the first sacrificial layer 109 can expose the surface of the second sacrificial layer 110, so as to facilitate the subsequent formation of a two-dimensional material channel layer at the bottom and top of the second sacrificial layer 110 and the top of the substrate 100. Moreover, after removing the first sacrificial layer 109, the second sacrificial layer 110 is stacked at intervals in the longitudinal position, so that the two-dimensional material channel layers subsequently formed at the bottom and top of the second sacrificial layer 110 and the top of the substrate 100 are also stacked at intervals.

[0093] In this embodiment, the process of removing the first sacrificial layer 109 includes a wet etching process.

[0094] Specifically, the material of the first sacrificial layer 109 is SiGe, and the material of the first sacrificial layer 109 is Si. There is an etching selectivity ratio between SiGe and Si materials. Therefore, the first sacrificial layer 109 is removed by HCl vapor, and the etching rate of the first sacrificial layer 109 by the wet etching process is much greater than the etching rate of the second sacrificial layer 110 and the protrusion 114, thereby reducing the probability of etching damage to the second sacrificial layer 110 and the protrusion 114.

[0095] refer to Figures 10 to 12 A two-dimensional material channel layer 121 is formed on the bottom and top of the second sacrificial layer 110 and the top of the substrate 100 .

[0096] It should be noted that, by subsequently removing the first sacrificial layer 109 and the second sacrificial layer 110, a device gate structure surrounding the two-dimensional material channel layer 121 is formed, which means that the channel layer material of the semiconductor structure is a two-dimensional material. The use of two-dimensional materials in the channel layer can increase the rate of charge migration, thereby further improving the performance of the semiconductor structure.

[0097] In this embodiment, the step of forming a two-dimensional material channel layer 121 includes: forming a two-dimensional material channel material layer 118 at the bottom, sidewall and top of the second sacrificial layer 110, and the top of the substrate 100; removing the two-dimensional material channel material layer 118 on the sidewall of the second sacrificial layer 110, and the remaining two-dimensional material channel material layer 118 located at the bottom and top of the second sacrificial layer 110, and the top of the substrate 100 serves as the two-dimensional material channel layer 121.

[0098] Specifically, the two-dimensional material channel material layer 118 provides a process basis for forming the two-dimensional material channel layer 121 .

[0099] It should be noted that, in the process of forming the two-dimensional material channel material layer 118 , forming the two-dimensional material channel material layer 118 on the top of the substrate 100 means that the two-dimensional material channel material layer 118 is formed on the top of the protrusion 114 .

[0100] It should also be noted that, in the process of forming the two-dimensional material channel material layer 118 , the two-dimensional material channel material layer 118 is also formed on the sidewalls of the protrusion 114 and the top of the substrate 113 .

[0101] In the process of removing the two-dimensional material channel material layer 118 on the sidewall of the second sacrificial layer 110 , the two-dimensional material channel material layer 118 on the sidewall of the protrusion 114 and the top of the substrate 113 is also removed.

[0102] In this embodiment, the process of removing the two-dimensional channel material layer 118 on the sidewall of the second sacrificial layer 110 includes a dry etching process.

[0103] It should be noted that the number of film layers of the two-dimensional material channel layer 121 should not be too many. If the number of film layers of the two-dimensional material channel layer 121 is too many, the probability of contact between the two-dimensional material channel layers 121 stacked at intervals is increased, thereby causing the conductive channel of the semiconductor structure to fail, thereby increasing the probability of electrical failure of the semiconductor structure. At the same time, if the number of film layers of the two-dimensional material channel layer 121 is too many, the process difficulty of forming the two-dimensional material channel layer 121 on the top and bottom of the second sacrificial layer 110 is increased, and the adsorption force between the two-dimensional material channel layer 121 and the second sacrificial layer 110 is reduced, thereby increasing the probability of electrical failure of the semiconductor structure. For this reason, in this embodiment, the number of film layers of the two-dimensional material channel layer 121 is 1 to 2 layers.

[0104] In this embodiment, the material of the two-dimensional material channel layer 121 includes one or both of transition metal disulfide and transition metal diselenide.

[0105] Specifically, transition metal disulfides and transition metal diselenides refer to compounds containing transition metal elements and sulfur elements or selenium elements, which have good electrical properties. At the same time, the basic structure of transition metal disulfides and transition metal diselenides is generally a layered structure, which is a two-dimensional layered material composed of multiple atoms and has high mechanical strength, thermal stability and chemical stability.

[0106] As an example, the material of the two-dimensional material channel layer 121 includes one or more of MoS2, WS2 and WSe2.

[0107] In this embodiment, the process of forming the two-dimensional material channel layer 121 includes a chemical vapor deposition process or a molecular beam epitaxy process.

[0108] Chemical vapor deposition and molecular beam epitaxy are both common methods for growing epitaxial crystals. The two-dimensional material channel layer 121 formed by using the chemical vapor deposition process and the molecular beam epitaxy process has high mechanical strength, thermal stability and chemical stability.

[0109] It should be noted that the material of the hard mask layer 107 is not a crystalline material. During the process of forming the two-dimensional material channel layer 121 , the two-dimensional material channel layer 121 cannot be epitaxially grown on the hard mask layer 107 .

[0110] Continue to refer Figure 11 to Figure 12 , a third sacrificial layer 120 is formed between adjacent two-dimensional material channel layers 121 , and the third sacrificial layer 120 covers the two-dimensional material channel layers 121 .

[0111] Specifically, by forming the third sacrificial layer 120, a spatial position is occupied in advance for the subsequent formation of a device gate structure surrounding and covering the two-dimensional material channel layer 121. At the same time, the third sacrificial layer 120 covers the two-dimensional material channel layer 121 and also protects the two-dimensional material channel layer 121. In the subsequent process of forming a gate structure spanning the second sacrificial layer 110, the two-dimensional material channel layer 121 and the third sacrificial layer 120, the probability of the two-dimensional material channel layer 121 being damaged is reduced.

[0112] In this embodiment, the step of forming a third sacrificial layer 120 between adjacent two-dimensional material channel layers 121 includes: forming a third sacrificial material layer 119 on the top of the substrate 100 to cover the top and bottom of the two-dimensional material channel layer 121 and the side wall of the second sacrificial layer 110, and the third sacrificial material layer 119 fills the spatial area directly opposite the adjacent two-dimensional material channel layers 121; removing the third sacrificial material layer 119 on the side wall of the second sacrificial layer 110 and the side wall of the two-dimensional material channel layer 121, and the top of the topmost second sacrificial layer 110, and the remaining third sacrificial material layer 119 located in the spatial area directly opposite the adjacent two-dimensional material channel layers 121 serves as the third sacrificial layer 120.

[0113] It should be noted that in the process of forming the third sacrificial material layer 119, the third sacrificial material layer 119 fills the spatial region directly opposite to the adjacent two-dimensional material channel layer 121. In the subsequent process of forming the gate structure, the probability of forming a gate structure in the spatial region directly opposite to the adjacent two-dimensional material channel layer 121 can be reduced.

[0114] As an example, the process of forming the third sacrificial material layer 119 includes a chemical vapor deposition process.

[0115] It should be noted that removing the side walls of the second sacrificial layer 110 and the side walls of the two-dimensional material channel layer 121, as well as the third sacrificial material layer 119 on the top of the second sacrificial layer 110 can expose the side walls of the second sacrificial layer 110 and the side walls of the two-dimensional material channel layer 121, as well as the spatial area on the top of the second sacrificial layer 110, which can facilitate the subsequent formation of a gate structure spanning the second sacrificial layer 110, the two-dimensional material channel layer 121 and the third sacrificial layer 120 on the top of the substrate 100.

[0116] In this embodiment, the material of the third sacrificial layer 120 includes one or more of silicon oxide, amorphous silicon, aluminum oxide and SOC.

[0117] The material selected for the third sacrificial layer 120 has an etching selectivity ratio with the material selected for the subsequently formed gate structure. In the subsequent process of forming the gate structure, the material forming the gate structure needs to be patterned. During the patterning process, the third sacrificial layer 120 can protect the two-dimensional material channel layer 121, thereby reducing the probability of damage to the two-dimensional material channel layer 121. At the same time, the material selected for the third sacrificial layer is the same as the material selected for the hard mask layer 107. In the process of removing the side walls of the second sacrificial layer 110 and the side walls of the two-dimensional material channel layer 121, as well as the third sacrificial material layer 119 on the top of the second sacrificial layer 110, the hard mask layer 107 can also be removed at the same time, thereby reducing the process steps and the process cost.

[0118] It should be noted that the step of forming the third sacrificial layer 120 also includes removing the hard mask layer 107 , that is, the third sacrificial layer 120 is formed and the hard mask layer 107 is removed in the same step, which reduces the process steps and reduces the process cost.

[0119] refer to Figures 13 to 16 ,in, Fig.14 It is a top view. Fig.15 yes Fig.14 Cross-sectional view along BB direction, Fig.16 yes Fig.14 In the cross-sectional view along the AA direction, a gate structure 130 is formed on the top of the substrate 100 , spanning the second sacrificial layer 110 , the two-dimensional material channel layer 121 , and the third sacrificial layer 120 .

[0120] The gate structure 130 occupies a space position in advance for subsequently forming a device gate structure.

[0121] The step of forming a gate structure 130 spanning the second sacrificial layer 110, the two-dimensional material channel layer 121 and the third sacrificial layer 120 on the top of the substrate 100 includes: forming a gate material layer 126 spanning the second sacrificial layer 110, the two-dimensional material channel layer 121 and the third sacrificial layer 120 on the top of the substrate 100; forming a patterned first mask layer 127 on the top of the gate material layer 126; using the first mask layer 127 as a mask, patterning the gate material layer 126, and using the remaining gate material layer 126 as the gate structure 130.

[0122] As an example, the gate structure 130 is a dummy gate structure.

[0123] In this embodiment, the gate structure 130 includes a dummy gate layer, and the material of the dummy gate layer includes polysilicon.

[0124] It should be noted that, after forming the gate structure 130 , the method for forming the semiconductor structure further includes: removing the first mask layer 127 .

[0125] The process of removing the first mask layer 127 includes an ashing process or a wet etching process.

[0126] It should be noted that before forming the gate structure 130 , the process further includes: forming an isolation layer 122 on the substrate 113 at the side of the protrusion 114 , wherein the isolation layer 122 exposes the second sacrificial layer 110 , the two-dimensional material channel layer 121 and the third sacrificial layer 120 .

[0127] The isolation layer 122 is used to isolate adjacent protrusions 114 .

[0128] In this embodiment, the material of the isolation layer 122 is silicon oxide.

[0129] refer to Figure 17 to Figure 18 , a first groove 138 is formed in the second sacrificial layer 110 , the two-dimensional material channel layer 121 and the third sacrificial layer 120 on both sides of the gate structure 130 .

[0130] The first groove 138 provides a spatial position for the subsequent formation of a source-drain contact layer, and also provides a process window for the subsequent formation of a second groove.

[0131] In this embodiment, the step of forming the first groove 138 includes: forming a first interlayer dielectric layer 136 covering the side wall of the gate structure 130 on the top of the substrate 100; forming a patterned second mask layer (not shown) on the top of the gate structure 130 and the first interlayer dielectric layer 136, the second mask layer covers the gate structure 130 and part of the first interlayer dielectric layer 136 on both sides of the gate structure 130; using the second mask layer as the mask layer, the first interlayer dielectric layer 136, the second sacrificial layer 110, the two-dimensional material channel layer 121 and the third sacrificial layer 120 are patterned to form the first groove 138.

[0132] It should be noted that, in the process of forming the first groove 138, the first interlayer dielectric layer 136 protects the gate structure 130, reduces the probability of damage to the morphology of the gate structure 130, and provides a process basis for the subsequent formation of the device gate structure. At the same time, by forming the first interlayer dielectric layer 136 on the side wall of the gate structure 130, after the first groove 138 is formed, the two-dimensional material channel layer 121 located directly below the first interlayer dielectric layer 136 can be retained, and the space area directly below the first interlayer dielectric layer 136 can be used to form an inner wall layer, so that the two-dimensional material channel layer 121 directly below the gate structure 130 can be surrounded and covered by the subsequently formed device gate structure, so that the contact area between the device gate structure and the two-dimensional material channel layer 121 is increased, thereby further improving the rate of charge migration in the conductive channel in the semiconductor structure and improving the performance of the semiconductor structure.

[0133] It should also be noted that the first interlayer dielectric layer 136 also plays an electrical isolation role for the subsequently formed device gate structure.

[0134] In this embodiment, the material of the first interlayer dielectric layer 136 includes silicon oxide.

[0135] In this embodiment, the process of patterning the first interlayer dielectric layer 136 , the second sacrificial layer 110 , the two-dimensional material channel layer 121 and the third sacrificial layer 120 using the second mask layer as the mask layer includes a dry etching process.

[0136] It should be noted that after forming the first groove 138 , the method for forming the semiconductor structure further includes: removing the second mask layer.

[0137] In this embodiment, the process of removing the second mask layer includes an ashing process or a wet etching process.

[0138] refer to Fig.19 After forming the first groove 138 and before subsequently forming the source-drain contact layer, it also includes: laterally etching the second sacrificial layer 110 and the third sacrificial layer 120 along a direction parallel to the surface of the substrate 100 and perpendicular to the extension direction of the gate structure 130 to form a second groove 139, wherein the second groove 139 is surrounded by the adjacent two-dimensional material channel layer 121 and the second sacrificial layer 110; or, the second groove 139 is surrounded by the adjacent two-dimensional material channel layer 121 and the third sacrificial layer 120.

[0139] The second groove 139 provides a spatial position for the subsequent formation of an inner wall layer. At the same time, the inner wall layer is located between the subsequently formed source-drain contact layer and the device gate structure. The inner wall layer can isolate the source-drain contact layer and the device gate structure, which is beneficial to reducing the parasitic capacitance between the source-drain contact layer and the device gate structure.

[0140] As an example, the process of laterally etching the second sacrificial layer 110 and the third sacrificial layer 120 includes a wet etching process.

[0141] The wet etching process is an isotropic etching process, so that the second sacrificial layer 110 and the third sacrificial layer 120 can be etched in a direction parallel to the substrate 100 and perpendicular to the extension direction of the gate structure 130, and the wet etching process can easily achieve a larger etching selectivity ratio, which is beneficial to reduce the difficulty of etching the second sacrificial layer 110 and the third sacrificial layer 120 and reduce the probability of damage to other film layer structures.

[0142] As an example, in the same step, the second sacrificial layer 110 and the third sacrificial layer 120 are laterally etched. In other embodiments, the second sacrificial layer and the third sacrificial layer may be laterally etched in different steps.

[0143] It should be noted that the lateral dimension of the second groove 139 should not be too large or too small along the direction parallel to the surface of the substrate 100 and perpendicular to the extension direction of the gate structure 130. If the lateral dimension of the second groove 139 is too large, the difficulty of forming the inner wall layer in the second groove 139 is increased; if the lateral dimension of the second groove 139 is too small, the lateral dimension of the inner wall layer formed in the second groove 139 is also too small. In the process of removing the second sacrificial layer 110 and the third sacrificial layer 120, the protective effect of the inner wall layer formed in the second groove 139 on the source and drain contact layer formed subsequently is reduced, and the probability of the source and drain contact layer being damaged is increased, thereby affecting the performance of the semiconductor structure. For this reason, in the present embodiment, the lateral dimension of the second groove 139 is 3 nanometers to 7 nanometers along the direction parallel to the surface of the substrate 100 and perpendicular to the extension direction of the gate structure 130.

[0144] refer to Fig. 20 , an inner wall layer 190 is formed in the second groove 139 .

[0145] The inner wall layer 190 is located between the subsequently formed source-drain contact layer and the device gate structure. The inner wall layer 190 can isolate the source-drain contact layer and the device gate structure, which is beneficial to reducing the parasitic capacitance between the source-drain contact layer and the device gate structure.

[0146] In this embodiment, the material of the inner wall layer 190 includes one or more of silicon nitride, silicon oxide, and silicon oxynitride.

[0147] Specifically, silicon nitride, silicon oxide and silicon oxynitride are all dielectric materials that can electrically isolate the device gate structure and source-drain contact layer that are subsequently formed.

[0148] It should be noted that, with the direction parallel to the surface of the substrate 100 and perpendicular to the extension direction of the gate structure 130 as the lateral direction, the lateral dimension of the inner wall layer 190 should not be too large or too small. If the lateral dimension of the inner wall layer 190 is too large, it will affect the length of the effective channel; if the lateral dimension of the inner wall layer 190 is too small, it will easily lead to a decrease in the effect of the inner wall layer 190 on the electrical isolation between the source-drain contact layer and the device gate structure, thereby increasing the parasitic capacitance between the source-drain contact layer and the device gate structure. For this reason, in this embodiment, with the direction parallel to the surface of the substrate 100 and perpendicular to the extension direction of the gate structure 130 as the lateral direction, the lateral dimension of the inner wall layer 190 is 2 nanometers to 6 nanometers.

[0149] refer to Fig.21 , a source-drain contact layer 150 covering the two-dimensional material channel layer 121 is formed in the first groove 138 .

[0150] Specifically, the source-drain contact layer 150 is used as a source region and a drain region of the transistor.

[0151] In this embodiment, the process of forming the source-drain contact layer 150 includes an epitaxial process.

[0152] Specifically, the epitaxial process has the characteristics of fast growth rate and good filling performance. By using the epitaxial process to form the source-drain contact layer 150, the risk of generating voids in the source-drain contact layer 150 is reduced, and the performance of the source-drain contact layer 150 itself is improved.

[0153] In this embodiment, the step of forming a source-drain contact layer 150 in the first groove 138 includes: forming a source-drain doping material layer (not shown) in the first groove 138 and in the side area of ​​the gate structure 130; removing the source-drain doping material layer in the side area of ​​the gate structure 130, and the remaining source-drain doping material layer located in the first groove 138 serves as the source-drain contact layer 150.

[0154] Specifically, the source and drain doping material layers in the side regions of the gate structure 130 are removed to provide a space for the subsequent formation of the second interlayer dielectric layer.

[0155] It should be noted that in the step of forming the source-drain contact layer 150, the source-drain contact layer 150 covers the inner wall layer 190, so that the inner wall layer 190 can play an isolating role between the source-drain contact layer 150 and the device gate structure.

[0156] refer to Fig. 22 After forming the source-drain contact layer 150 , the method for forming the semiconductor structure further includes: forming a second interlayer dielectric layer 151 on top of the source-drain contact layer 150 to cover the sidewalls of the gate structure 130 .

[0157] Specifically, the second interlayer dielectric layer 151 protects the source-drain contact layer 150 and is also used to electrically isolate a device gate structure that is subsequently formed.

[0158] In this embodiment, the material of the second interlayer dielectric layer 151 is silicon oxide.

[0159] In this embodiment, the step of forming the second interlayer dielectric layer 151 includes: forming a dielectric material layer (not shown) on the substrate 100 on the side wall of the gate structure 130, the dielectric material layer also covering the top of the gate structure 130 and the top of the source-drain contact layer 150; removing the dielectric material layer above the top of the gate structure 130, and the remaining dielectric material layer serves as the second interlayer dielectric layer 151.

[0160] refer to Fig.23 , the gate structure 130 is removed, and a gate opening 160 is formed in the second interlayer dielectric layer 151 .

[0161] Specifically, the gate opening 160 provides a process window for the subsequent removal of the second sacrificial layer 110 and the third sacrificial layer 120 , and also provides a spatial position for the subsequent formation of a device gate structure.

[0162] In this embodiment, the process of removing the gate structure 130 includes a dry etching process.

[0163] refer to Fig.24 , the second sacrificial layer 110 and the third sacrificial layer 120 exposed by the gate opening 160 are removed, and a through groove 162 communicating with the gate opening 160 is formed above the two-dimensional material channel layer 121 .

[0164] Specifically, the second sacrificial layer 110 and the third sacrificial layer 120 are removed to form a through groove 162 to provide a space for the subsequent formation of a device gate structure.

[0165] In this embodiment, a wet etching process is used to remove the second sacrificial layer 110 and the third sacrificial layer 120 .

[0166] The second sacrificial layer 110 and the third sacrificial layer 120 are removed after the source-drain contact layers 150160 are formed. Therefore, after removing the second sacrificial layer 110 and the third sacrificial layer 120, along the extension direction of the protrusion 114, both ends of the two-dimensional material channel layer 121 are connected to the source-drain contact layer 150 and suspended in the through groove 162, thereby providing a basis for the subsequently formed device gate structure to surround the two-dimensional material channel layer 121.

[0167] refer to Fig.25 A device gate structure 170 is formed in the gate opening 160 and the through groove 162 , and the device gate structure 170 surrounds the two-dimensional material channel layer 121 .

[0168] The device gate structure 170 is used to control the opening and closing of the conductive channel when the device is working.

[0169] Specifically, the device gate structure 170 is a metal gate structure 130 .

[0170] In this embodiment, the device gate structure 170 includes a gate dielectric layer (not shown) surrounding the two-dimensional material channel layer 121 and a gate electrode layer (not shown) covering the gate dielectric layer.

[0171] In this embodiment, the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3.

[0172] Specifically, the gate dielectric layer includes a gate oxide layer that conformally covers a portion of the top, a portion of the sidewall, and a portion of the bottom of the two-dimensional material channel layer 121, and a high-k gate dielectric layer that conformally covers the gate oxide layer. The material of the high-k gate dielectric layer is a high-k dielectric material, which refers to a dielectric material having a relative dielectric constant greater than the relative dielectric constant of silicon oxide.

[0173] The gate electrode layer is used for subsequent electrical connection with an external structure. The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC. Specifically, the gate electrode layer may include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer may also include only the work function layer.

[0174] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A channel structure layer, located on the top of the substrate, the channel structure layer comprises one or more two-dimensional material channel layers spaced apart in the vertical direction; A device gate structure, located on the substrate and spanning the channel structure layer, the device gate structure surrounds and covers the two-dimensional material channel layer; A source-drain contact layer, located in the channel structure layer on both sides of the device gate structure; An inner wall layer, located between the side wall of the device gate structure below the two-dimensional material channel layer and the source-drain contact layer; An interlayer dielectric layer is located on top of the source-drain contact layer, and the interlayer dielectric layer covers the sidewalls of the device gate structure.

2. The semiconductor structure according to claim 1, wherein: With the direction parallel to the surface of the substrate and perpendicular to the extension direction of the device gate structure as the lateral direction, the lateral dimension of the inner wall layer is 2 nanometers to 6 nanometers.

3. The semiconductor structure according to claim 1, wherein: The material of the inner wall layer includes one or more of silicon nitride, silicon oxide and silicon oxynitride.

4. The semiconductor structure according to claim 1, wherein: The material of the two-dimensional material channel layer includes one or both of transition metal disulfide and transition metal diselenide.

5. The semiconductor structure according to claim 1, wherein: The interlayer dielectric layer includes a first interlayer dielectric layer located on the sidewall of the device gate structure and a second interlayer dielectric layer located on the sidewall of the first interlayer dielectric layer. The sidewall of the first interlayer dielectric layer opposite to the device gate structure is flush with the sidewall of the two-dimensional material channel layer.

6. The semiconductor structure according to claim 1, wherein: The device gate structure comprises a gate dielectric layer surrounding and covering the two-dimensional material channel layer, and a gate electrode layer covering the gate dielectric layer; The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3; The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

7. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, on which a sacrificial stack structure is formed, the sacrificial stack structure comprising one or more sacrificial stacks stacked in sequence in a longitudinal direction, the sacrificial stack comprising a first sacrificial layer and a second sacrificial layer located on the first sacrificial layer; removing the first sacrificial layer; forming a two-dimensional material channel layer on the bottom and top of the second sacrificial layer and on the top of the substrate; forming a third sacrificial layer between adjacent two-dimensional material channel layers, wherein the third sacrificial layer covers the two-dimensional material channel layer; forming a gate structure spanning the second sacrificial layer, the two-dimensional material channel layer and the third sacrificial layer on the top of the substrate; forming a first groove in the second sacrificial layer, the two-dimensional material channel layer and the third sacrificial layer on both sides of the gate structure; A source-drain contact layer covering the two-dimensional material channel layer is formed in the first groove.

8. The method for forming a semiconductor structure according to claim 7, wherein: The step of forming the two-dimensional material channel layer includes: forming a two-dimensional material channel material layer at the bottom, sidewall and top of the second sacrificial layer, and the top of the substrate; removing the two-dimensional material channel material layer on the sidewall of the second sacrificial layer, and the remaining two-dimensional material channel material layer located at the bottom and top of the second sacrificial layer, and the top of the substrate serves as the two-dimensional material channel layer.

9. The method for forming a semiconductor structure according to claim 7, wherein: The process of forming the two-dimensional material channel layer includes a chemical vapor deposition process or a molecular beam epitaxy process.

10. The method for forming a semiconductor structure according to claim 7, wherein: The number of film layers of the two-dimensional material channel layer is 1 or 2.

11. The method for forming a semiconductor structure according to claim 7, wherein: The step of forming a third sacrificial layer between adjacent two-dimensional material channel layers includes: forming a third sacrificial material layer on the top of the substrate to cover the top and bottom of the two-dimensional material channel layer and the sidewalls of the second sacrificial layer, wherein the third sacrificial material layer fills the spatial area directly opposite to the adjacent two-dimensional material channel layers; removing the sidewalls of the second sacrificial layer and the sidewalls of the two-dimensional material channel layer, as well as the third sacrificial material layer on the top of the second sacrificial layer, and the remaining third sacrificial material layer located in the spatial area directly opposite to the adjacent two-dimensional material channel layers serves as the third sacrificial layer.

12. The method for forming a semiconductor structure according to claim 11, wherein: The material of the third sacrificial layer includes one or more of silicon oxide, amorphous silicon, aluminum oxide and SOC.

13. The method for forming a semiconductor structure according to claim 7, wherein: The step of forming a gate structure spanning the second sacrificial layer, the two-dimensional material channel layer and the third sacrificial layer on the top of the substrate includes: forming a gate material layer spanning the second sacrificial layer, the two-dimensional material channel layer and the third sacrificial layer on the top of the substrate; forming a patterned first mask layer on the top of the gate material layer; using the first mask layer as a mask, patterning the gate material layer, and using the remaining gate material layer as the gate structure.

14. The method for forming a semiconductor structure according to claim 7, wherein: After forming the first groove and before forming the source-drain contact layer, the method further includes: laterally etching the second sacrificial layer and the third sacrificial layer in a direction parallel to the substrate surface and perpendicular to the extension direction of the gate structure to form a second groove, wherein the second groove is surrounded by the adjacent two-dimensional material channel layer and the second sacrificial layer; or, the second groove is surrounded by the adjacent two-dimensional material channel layer and the third sacrificial layer; forming an inner wall layer in the second groove; In the step of forming the source-drain contact layer, the source-drain contact layer covers the inner wall layer.

15. The method for forming a semiconductor structure according to claim 14, wherein: Along a direction parallel to the substrate surface and perpendicular to the extension direction of the gate structure as a lateral direction, a lateral dimension of the second groove is 3 nanometers to 7 nanometers.

16. The method for forming a semiconductor structure according to claim 14, wherein: The material of the inner wall layer includes one or more of silicon nitride, silicon oxide and silicon oxynitride.

17. The method for forming a semiconductor structure according to claim 7, wherein: The step of forming the first groove includes: forming a first interlayer dielectric layer covering the side wall of the gate structure on the top of the substrate; forming a patterned second mask layer on the top of the gate structure and the first interlayer dielectric layer, the second mask layer covering the gate structure and part of the first interlayer dielectric layer on both sides of the gate structure; using the second mask layer as a mask layer, patterning the first interlayer dielectric layer, the second sacrificial layer, the two-dimensional material channel layer and the third sacrificial layer to form the first groove; removing the second mask layer.

18. The method for forming a semiconductor structure according to claim 7, wherein: The step of forming a source-drain contact layer in the first groove includes: forming a source-drain contact material layer in the first groove and in the side area of ​​the gate structure; removing the source-drain contact material layer in the side area of ​​the gate structure, and the remaining source-drain contact material layer located in the first groove serves as the source-drain contact layer.

19. The method for forming a semiconductor structure according to claim 7, wherein: After forming the source-drain contact layer, the method for forming the semiconductor structure further includes: forming a second interlayer dielectric layer covering the sidewall of the gate structure on the top of the source-drain contact layer; removing the gate structure and forming a gate opening in the second interlayer dielectric layer; removing the second sacrificial layer and the third sacrificial layer exposed by the gate opening, and forming a through groove communicating with the gate opening above the two-dimensional material channel layer; A device gate structure is formed in the gate opening and the through groove, and the device gate structure surrounds the two-dimensional material channel layer.

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