Semiconductor element and manufacturing method thereof

Abstract

A semiconductor device includes a semiconductor substrate and a gate structure. The semiconductor substrate has source / drain regions and a channel region between the source / drain regions. The gate structure is over the channel region of the semiconductor substrate. The gate structure includes an interface layer, a zirconium-containing dielectric layer, and a gate electrode. The zirconium-containing dielectric layer is located above the interface layer and is in a tetragonal crystal phase. A gate electrode is over the zirconium-containing dielectric layer. Therefore, the oxide capacitance of the semiconductor element is increased and the gate leakage current is reduced.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] As integrated circuits (ICs) develop towards high density and low power consumption, the miniaturization of field effect transistors (FETs) has become a critical issue. In the miniaturization of FETs, reducing the channel length and gate oxide thickness results in low applied voltage and high off-state current. off In addition, in order to maintain the on-state current (I on ) and good gate control capability, shorter channel length and thinner gate oxide thickness are beneficial. However, when the gate oxide thickness is reduced to a certain extent, the gate leakage current will be too large to maintain gate control capability, especially for traditional transistors that only use silicon dioxide as a gate insulator.

[0003] Therefore, how to propose a semiconductor device and a manufacturing method thereof that can solve the above problems is one of the problems that the industry is eager to invest research and development resources to solve. Summary of the invention

[0004] In view of this, an object of the present disclosure is to provide a semiconductor device and a manufacturing method thereof that can solve the above-mentioned problems.

[0005] To achieve the above-mentioned object, according to some embodiments of the present disclosure, a semiconductor element includes a semiconductor substrate and a gate structure. The semiconductor substrate has a source / drain region and a channel region located between the source / drain region. The gate structure is located above the channel region of the semiconductor substrate. The gate structure includes an interface layer, a zirconium-containing dielectric layer, and a gate electrode. The zirconium-containing dielectric layer is located above the interface layer and is in a tetragonal phase. The gate electrode is located above the zirconium-containing dielectric layer.

[0006] In one or more embodiments of the present disclosure, the interface layer comprises titanium oxide.

[0007] In one or more embodiments of the present disclosure, the zirconium-containing dielectric layer is in contact with the interfacial layer.

[0008] In one or more embodiments of the present disclosure, the thickness of the interface layer is in the range between 5 angstroms and 3 nanometers.

[0009] In one or more embodiments of the present disclosure, the thickness of the interface layer is in the range between 1 angstrom and 50 nanometers.

[0010] In one or more embodiments of the present disclosure, the gate electrode includes titanium nitride or tantalum nitride.

[0011] In one or more embodiments of the present disclosure, the zirconium-containing dielectric layer is doped with nitrogen.

[0012] In one or more embodiments of the present disclosure, the zirconium-containing dielectric layer has a top portion and a bottom portion opposite to each other, the bottom portion is in contact with the interface layer, and the nitrogen atomic concentration of the top portion is higher than the nitrogen atomic concentration of the bottom portion.

[0013] In one or more embodiments of the present disclosure, the gate structure further comprises a diffusion barrier layer located between the gate electrode and the zirconium-containing dielectric layer. The diffusion barrier layer comprises aluminum oxide or titanium oxide.

[0014] In one or more embodiments of the present disclosure, the diffusion barrier layer comprises the same material as the interface layer.

[0015] In one or more embodiments of the present disclosure, the thickness of the zirconium-containing dielectric layer is in a range between 3 nm and 7 nm.

[0016] In one or more embodiments of the present disclosure, the thickness of the zirconium-containing dielectric layer is in a range between 1 angstrom and 50 nanometers.

[0017] In one or more embodiments of the present disclosure, the zirconium-containing dielectric layer includes titanium atoms.

[0018] In one or more embodiments of the present disclosure, the interface layer includes a first interface layer and a second interface layer. The first interface layer includes silicon oxide. The second interface layer includes titanium oxide.

[0019] According to other embodiments of the present disclosure, a method for manufacturing a semiconductor device includes forming a gate structure above a channel region of a semiconductor substrate. Forming the gate structure includes depositing an interface layer above the channel region. Forming the gate structure also includes depositing a zirconium-containing dielectric layer on the interface layer. The zirconium-containing dielectric layer is a tetragonal phase. Forming the gate structure also includes forming a gate electrode above the zirconium-containing dielectric layer. The manufacturing method also includes forming a source / drain region in the semiconductor substrate and on opposite sides of the channel region.

[0020] In one or more embodiments of the present disclosure, the manufacturing method further includes performing an annealing process after forming the gate electrode. The temperature of the annealing process is in the range of 400°C to 900°C.

[0021] In one or more embodiments of the present disclosure, the manufacturing method further includes performing an implantation process on the zirconium-containing dielectric layer using nitrogen gas.

[0022] In one or more embodiments of the present disclosure, the manufacturing method further comprises depositing a diffusion barrier layer on the zirconium-containing dielectric layer before forming the gate electrode. The diffusion barrier layer comprises aluminum oxide or titanium oxide.

[0023] In one or more embodiments of the present disclosure, the manufacturing method further includes performing an implantation process on the zirconium-containing dielectric layer using nitrogen. The manufacturing method further includes depositing a diffusion barrier layer on the zirconium-containing dielectric layer after performing the implantation process and before forming the gate electrode. The diffusion barrier layer includes aluminum oxide or titanium oxide.

[0024] In one or more embodiments of the present disclosure, depositing the interface layer includes depositing a first interface layer formed of silicon oxide and depositing a second interface layer formed of titanium oxide.

[0025] In summary, in the semiconductor device and the manufacturing method thereof disclosed in the present invention, by using a zirconium-containing dielectric layer as a gate insulator with antiferroelectric properties, the polarization induced by the electric field helps to attract more charges to accumulate in the channel region of the semiconductor device. In addition, the zirconium-containing dielectric layer has a high dielectric constant. This may increase the oxide capacitance of the semiconductor device and reduce the gate leakage current. Specifically, the zirconium-containing dielectric layer includes a tetragonal phase. In addition, by providing an interface layer containing titanium oxide between the zirconium-containing dielectric layer and the semiconductor substrate and / or performing an annealing process, the tetragonal phase of the zirconium-containing dielectric can be stabilized, thereby improving the reliability of the semiconductor device.

[0026] These and other aspects of the present disclosure will become apparent from the following description of preferred embodiments in conjunction with the accompanying drawings, but changes and modifications may be made therein without departing from the spirit and scope of the novel concepts of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings illustrate one or more embodiments of the present disclosure and together with the written description are used to explain the principles of the present disclosure. In all drawings, the same reference numerals are used as much as possible to refer to similar or identical elements of the embodiments, wherein:

[0028] Figure 1 The diagram is a schematic diagram illustrating a semiconductor device according to some embodiments of the present disclosure.

[0029] Figure 2 The diagram is a schematic diagram illustrating an intermediate stage of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0030] Figure 3 The diagram is a schematic diagram illustrating an intermediate stage of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0031] Figure 4The diagram is a schematic diagram illustrating an intermediate stage of a method for manufacturing a semiconductor device according to some other embodiments of the present disclosure.

[0032] Figure 5 The diagram is a schematic diagram illustrating an intermediate stage of a method for manufacturing a semiconductor device according to some other embodiments of the present disclosure.

[0033] Figure 6 Schematic diagrams illustrating semiconductor devices according to other embodiments of the present disclosure.

[0034] Figure 7 The diagram is a schematic diagram illustrating an intermediate stage of a manufacturing method according to yet other embodiments of the present disclosure.

[0035] Figure 8 Schematic diagrams illustrating semiconductor devices according to yet other embodiments of the present disclosure. DETAILED DESCRIPTION

[0036] The following will disclose the embodiments of the present disclosure with the accompanying drawings. For the purpose of clear description, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present disclosure. In other words, in some embodiments of the present disclosure, these practical details are not necessary. In addition, in order to simplify the drawings, some conventional structures and elements will be depicted in a simple schematic manner in the drawings.

[0037] By increasing the integration density of field effect transistors (FETs), more components can be fabricated on a single wafer, thus reducing the cost of each component. At the same time, circuit speed can be increased and power consumption can be reduced. However, in the process of miniaturization of field effect transistors, shrinking the channel length and gate oxide thickness results in low applied voltage and high off-state current (I off On the one hand, a low applied voltage is desirable because it increases the on-state current (I on ), thereby increasing circuit speed. On the other hand, the accompanying high off-state current leads to large gate leakage current and deteriorates gate control. Therefore, the off-state current should be kept as low as possible to minimize the static power consumption when the field effect transistor is in standby mode.

[0038] Take a field effect transistor that uses only silicon oxide (SiO2) as a gate insulator as an example. A thinner silicon oxide gate insulator has a larger oxide capacitance (C ox). This increases the on-current of the field effect transistor. However, as the thickness of the silicon dioxide gate insulator decreases, the leakage current rises rapidly. When the gate insulator shrinks to a certain thickness, the leakage current will be too large to maintain gate control.

[0039] Therefore, in some embodiments of the present disclosure, semiconductor devices incorporate novel oxide materials to enhance gate control while maintaining the same physical oxide thickness.

[0040] Please refer to Figure 1 , which is a schematic diagram of a semiconductor device 100 according to some embodiments of the present invention. Figure 1 As shown, the semiconductor device 100 includes a semiconductor substrate 110 and a gate structure 125. The gate structure 125 includes an interface layer 120, a zirconium-containing dielectric layer 150, and a gate electrode 160. The interface layer 120 is disposed on the semiconductor substrate 110. The interface layer 120 includes a first interface layer 130 and a second interface layer 140 located above the first interface layer 130. In detail, the first interface layer 130 is disposed on the semiconductor substrate 110. The second interface layer 140 is disposed on the first interface layer 130. The zirconium-containing dielectric layer 150 is disposed on the second interface layer 140. In addition, the bottom of the zirconium-containing dielectric layer 150 is in contact with the second interface layer 140. The gate electrode 160 is disposed on the zirconium-containing dielectric layer 150.

[0041] like Figure 1 As shown, the semiconductor substrate 110 has source / drain regions 115 on opposite sides of the gate structure 125. Here, the portion of the semiconductor substrate 110 covered by the gate structure 125 and located between the source / drain regions 115 can be referred to as a channel region. In this way, the first interface layer 130 is disposed above the channel region of the semiconductor substrate 110. In some embodiments, the semiconductor substrate 110 can include a dielectric material, such as silicon dioxide, silicon nitride (SiN), and combinations thereof.

[0042] In some embodiments, the zirconium-containing dielectric layer 150 includes undoped zirconium oxide (ZrO2), silicon-doped zirconium oxide, aluminum-doped zirconium oxide, lanthanum-doped zirconium oxide, hafnium zirconium oxide (HfZrO2, HZO), and combinations thereof. The zirconium-containing dielectric layer 150 is a tetragonal phase, such as tetragonal zirconium oxide. In some embodiments, the thickness of the zirconium-containing dielectric layer 150 is in the range of 1 angstrom and 50 nanometers. In some embodiments, the thickness of the zirconium-containing dielectric layer 150 is in the range of 3 nanometers and 7 nanometers.

[0043] In some embodiments, the gate electrode 160 includes a metal nitride or a metal carbide. In some embodiments, the gate electrode 160 includes at least one of titanium nitride (TiN) and tantalum nitride (TaN). In some embodiments, the gate electrode 160 includes tungsten nitride (WN).

[0044] In the semiconductor device 100, the zirconium-containing dielectric layer 150 is used as a gate insulator. The zirconium-containing dielectric layer 150 has a high dielectric constant (high-k) and provides a high dielectric constant. Compared with a conventional transistor using only a silicon dioxide gate insulator, the zirconium-containing dielectric layer 150 can have a larger oxide capacitance while maintaining the same physical oxide thickness, which will be beneficial to increase the on-current of the semiconductor device 100.

[0045] As described above, the zirconium-containing dielectric layer 150 may include a tetragonal phase. The zirconium-containing dielectric layer 150 of the tetragonal phase has antiferroelectric (AFE) properties. In antiferroelectric materials, spontaneous polarization dipoles are arranged in opposite directions in adjacent sublattices. Therefore, the polarization-electric field characteristics of the zirconium-containing dielectric layer 150 show double hysteresis loops with negligible residual polarization at zero bias. Such a zirconium-containing dielectric layer 150 can be applied to volatile memory elements. The polarization induced by the electric field helps to attract more charges to accumulate in the channel region. In some embodiments, one of the loops of the double hysteresis loop can be translated to be centered on an applied voltage of 0V. In this way, the polarization exists in the form of a built-in electric field. This allows the zirconium-containing dielectric layer 150 to be used as a gate insulator in a non-volatile memory.

[0046] In addition, the use of a tetragonal zirconium oxide gate insulator with antiferroelectric properties can reduce gate leakage current and suppress direct tunneling caused by insufficient gate insulator thickness in conventional transistors. This demonstrates the ability of zirconium oxide to further reduce the equivalent oxide thickness (EOT) of the gate insulator.

[0047] In some embodiments, the first interface layer 130 includes silicon oxide. In some embodiments, the thickness of the first interface layer 130 is in the range of 1 nanometer and 50 nanometers. In some embodiments, the thickness of the first interface layer 130 is in the range of 5 angstroms and 3 nanometers.

[0048] In some embodiments, the second interface layer 140 includes titanium oxide (TiO2). For example, the second interface layer 140 includes anatase or rutile. In these embodiments, the lattice constant (or unit cell size) of titanium oxide is different from the lattice constant of zirconium oxide. The lattice mismatch at the interface between titanium oxide and zirconium oxide can apply compressive strain to the lattice of zirconium oxide during the process of the semiconductor element 100 and cause the zirconium oxide to form a tetragonal phase. Since different parts of the zirconium-containing dielectric layer 150 are subjected to different strains, the proportion of tetragonal zirconium oxide in these parts will vary with their vertical distance from the interface between the second interface layer 140 and the zirconium-containing dielectric layer 150. For example, in some embodiments, the proportion of tetragonal zirconium oxide in the bottom of the zirconium-containing dielectric layer 150 can be higher than the proportion of tetragonal zirconium oxide in the top of the zirconium-containing dielectric layer 150.

[0049] In some embodiments, diffusion may occur at the interface between the second interface layer 140 and the zirconium-containing dielectric layer 150 , and thus the bottom of the zirconium-containing dielectric layer 150 may contain titanium atoms Ti. Figure 1 The possible distribution of titanium atoms Ti is indicated by a cross symbol. In some embodiments, the concentration of titanium atoms may gradually decrease from the bottom of the zirconium-containing dielectric layer 150 to the top of the zirconium-containing dielectric layer 150. The titanium atoms may exist in the form of titanium or titanium oxide. In some embodiments, a titanium oxide / zirconium oxide solid solution exists at the junction between the second interface layer 140 and the bottom of the zirconium-containing dielectric layer 150 to form a transition layer (not shown).

[0050] In some embodiments, the thickness of the second interface layer 140 is in the range of 1 nanometer to 50 nanometers. In some embodiments, the thickness of the second interface layer 140 is in the range of 5 angstroms to 3 nanometers.

[0051] Please refer to Figure 2 and Figure 3 , which is a schematic diagram of an intermediate stage of a method for manufacturing a semiconductor element 100 according to some embodiments of the present invention. The steps of the manufacturing method will be described below in conjunction with the accompanying drawings.

[0052] First, provide Figure 2 The semiconductor substrate 110 is shown in FIG. As described above, the semiconductor substrate 110 may include silicon oxide, silicon nitride, a combination thereof, and the like.

[0053] Next, a first interface layer 130, a second interface layer 140, a zirconium-containing dielectric layer 150, and a gate electrode 160 are formed. Figure 2As shown. In some embodiments, atomic layer deposition (ALD) is used to form these layers to facilitate fine-tuning and controlling the thickness of each layer. For example, plasma-enhanced atomic layer deposition (PEALD) or thermal atomic layer deposition (thermal atomic layer deposition) can be used. In some embodiments, the first interface layer 130 includes silicon oxide. In some embodiments, the second interface layer 140 includes titanium oxide.

[0054] As described above, in embodiments where the second interface layer 140 comprises titanium oxide and the zirconium-containing dielectric layer 150 comprises zirconium oxide, the difference in lattice constants between titanium oxide and zirconium oxide results in the formation of tetragonal zirconium oxide. More specifically, in some embodiments, the ALD process for depositing the zirconium-containing dielectric layer 150 is performed at a temperature between 200°C and 400°C.

[0055] Diffusion may occur at the interface between the formed zirconium oxide and the underlying titanium oxide. Therefore, the bottom of the zirconium-containing dielectric layer 150 in contact with the second interface layer 140 may include titanium atoms Ti. The distribution of titanium atoms Ti is as follows: Figure 2 The titanium atom may exist in the form of titanium or titanium oxide.

[0056] In some embodiments, to ensure the formation of tetragonal zirconium oxide, the thickness of the second interface layer 140 is in the range of 1 angstrom and 50 nanometers, and the thickness of the zirconium-containing dielectric layer 150 is in the range of 1 angstrom and 50 nanometers. In some embodiments, the thickness of the second interface layer 140 is in the range of 5 angstroms and 3 nanometers, and the thickness of the zirconium-containing dielectric layer 150 is in the range of 3 angstroms and 7 nanometers.

[0057] Next, if Figure 3 As shown in Figure 2 The intermediate structure is formed to form the gate structure 125. In some embodiments, the patterning process may include, for example, Figure 2 A mask is formed over the intermediate structure, an etching process is performed to remove the first interface layer 130, the second interface layer 140, the zirconium-containing dielectric layer 150, and the portion of the gate electrode 160 exposed by the mask, and then the mask is removed after the etching process is completed.

[0058] Then, source / drain regions 115 are formed in the exposed regions of the semiconductor substrate 110. In some embodiments, the source / drain regions 115 may be formed by a suitable implantation process. For example, for an n-type semiconductor device, n-type dopants may be implanted into the semiconductor substrate 110, and for a p-type semiconductor device, p-type dopants may be implanted into the semiconductor substrate 110.

[0059] Finally, in some embodiments, in order to stabilize the tetragonal zirconium oxide in the zirconium-containing dielectric layer 150 and improve the reliability of the semiconductor device 100, an annealing process may be performed by rapid thermal annealing. Figure 1 , which shows the final structure of the semiconductor device 100 .

[0060] As titanium atoms diffuse into the zirconium-containing dielectric layer 150, the stabilization temperature of the anneal may decrease. For example, Figure 1 The semiconductor device 100 is annealed at a temperature between 400° C. and 900° C. In some embodiments, the annealing process lasts for 10 seconds to 3 minutes. In some embodiments, the annealing process is performed in nitrogen.

[0061] As described above, the gate electrode 160 may include titanium nitride or tantalum nitride. However, diffusion may occur at the interface between the zirconium-containing dielectric layer 150 and the gate electrode 160. This may damage the grains of tetragonal zirconium oxide in the zirconium-containing dielectric layer 150. Therefore, in order to inhibit diffusion, some embodiments of the present disclosure passivate the zirconium-containing dielectric layer 150, while other embodiments form a diffusion barrier layer between the zirconium-containing dielectric layer 150 and the gate electrode 160. This will be described in detail in the following paragraphs.

[0062] Please refer to Figures 4 to 6 . Figure 4 and Figure 5 The diagram is a schematic diagram illustrating an intermediate stage of a method for manufacturing a semiconductor device according to some other embodiments of the present disclosure. Figure 6 Schematic diagram of a semiconductor device 200 according to some other embodiments of the present disclosure.

[0063] Please refer to Figure 4 In some embodiments, after depositing the zirconium-containing dielectric layer 150, an implantation process is performed on the zirconium-containing dielectric layer 150. Figure 4 As shown, the intermediate structure is doped with appropriate dopants, such as Figure 4 In some embodiments, the zirconium-containing dielectric layer 150 is doped with nitrogen atoms N (nitrogen), and this step is also called nitriding. Since the implantation process is performed on the top surface of the zirconium-containing dielectric layer 150, the nitrogen atom concentration at the top of the zirconium-containing dielectric layer 150 may be higher than the nitrogen atom concentration at the bottom of the zirconium-containing dielectric layer 150.

[0064] Please refer to Figure 5 Next, a gate electrode 160 is formed on the doped zirconium-containing dielectric layer 150 .

[0065] Please refer to Figure 6 The first interface layer 130, the second interface layer 140, the zirconium-containing dielectric layer 150 and the gate electrode 160 are patterned to form a gate structure 125. Then, the source / drain regions 115 are formed. In this way, the semiconductor device 200 is formed.

[0066] In order to further suppress diffusion, according to still other embodiments of the present disclosure, a diffusion barrier layer may be provided between the zirconium-containing dielectric layer 150 and the gate electrode 160, as described in the following paragraphs. Figure 7 and Figure 8 described.

[0067] Please refer to Figure 7 and Figure 8 . Figure 7 The diagram is a schematic diagram illustrating an intermediate stage of a manufacturing method according to yet other embodiments of the present disclosure. Figure 8 FIG. 1 is a schematic diagram illustrating a semiconductor device 300 formed by a manufacturing method according to some other embodiments of the present disclosure.

[0068] Please refer to Figure 7 In this embodiment, after forming the zirconium-containing dielectric layer 150 and before forming the gate electrode 160, a diffusion barrier layer 170 is formed, such as Figure 7 As shown. In some embodiments, the diffusion barrier layer 170 is in contact with the zirconium-containing dielectric layer 150. In some embodiments, the diffusion barrier layer 170 includes aluminum oxide (Al2O3) or titanium oxide. In some embodiments, the diffusion barrier layer 170 includes the same material as the second interface layer 140. For example, the diffusion barrier layer 170 and the second interface layer 140 both include titanium oxide. In such an embodiment, a lattice constant difference also exists at the interface between the zirconium-containing dielectric layer 150 and the diffusion barrier layer 170 including titanium oxide. Therefore, the proportion of tetragonal zirconium oxide in the bottom of the zirconium-containing dielectric layer 150 is substantially the same as the proportion of tetragonal zirconium oxide in the top of the zirconium-containing dielectric layer 150. In some embodiments, the thickness of the zirconium-containing dielectric layer 150 allows a monoclinic phase of zirconium oxide to form in regions between the top and bottom of the zirconium-containing dielectric layer 150 because these regions are farther from the interface between the zirconium-containing dielectric layer 150 and other layers containing titanium oxide and are less affected by strain caused by lattice mismatch.

[0069] In some embodiments, the diffusion barrier layer 170 includes a first layer having aluminum oxide and a second layer having titanium oxide. For example, the first layer having aluminum oxide is deposited on the zirconium-containing dielectric layer 150, and then the second layer having titanium oxide is deposited on the first layer. In some embodiments, the diffusion barrier layer 170 includes titanium atoms (not shown).

[0070] Please refer to Figure 8 Similarly, after forming the gate electrode 160, patterning, and forming the source / drain regions 115, the semiconductor device 300 is formed. Figure 6 Compared with the gate structure 125 of the semiconductor device 200, the gate structure 125 of the semiconductor device 300 further includes a diffusion barrier layer 170, such as Figure 8 The gate electrode 160 is in contact with the diffusion barrier layer 170. By providing the diffusion barrier layer 170 containing aluminum oxide and / or titanium oxide between the gate electrode 160 containing titanium nitride and / or tantalum nitride and the zirconium-containing dielectric layer 150 containing zirconium oxide, the diffusion of oxygen from zirconium oxide toward titanium nitride or tantalum nitride may be reduced, thereby suppressing the formation of interfacial oxides such as titanium oxynitride (TiON).

[0071] From the above detailed description of the specific embodiments of the present disclosure, it can be clearly seen that in the semiconductor device and the manufacturing method thereof disclosed in the present disclosure, by using a zirconium-containing dielectric layer as a gate insulator with antiferroelectric properties, the polarization induced by the electric field helps to attract more charges to accumulate in the channel region of the semiconductor device. In addition, the zirconium-containing dielectric layer has a high dielectric constant. This may increase the oxide capacitance of the semiconductor device and reduce the gate leakage current. Specifically, the zirconium-containing dielectric layer includes a tetragonal phase. In addition, by providing an interface layer containing titanium oxide between the zirconium-containing dielectric layer and the semiconductor substrate and / or performing an annealing process, the tetragonal phase of the zirconium-containing dielectric can be stabilized, thereby improving the reliability of the semiconductor device.

[0072] The foregoing description is provided only to illustrate and describe exemplary embodiments of the present disclosure and is not intended to be exhaustive or to limit the precise forms of the invention disclosed in the present disclosure. The above teachings may be modified or varied.

[0073] The embodiments selected and described are intended to explain the content of the present disclosure and their practical applications so as to inspire other persons skilled in the art to utilize the present disclosure and various embodiments, and to make various modifications to meet the specific intended use. Alternative embodiments will be apparent to those skilled in the art without departing from the spirit and scope of the present disclosure. Therefore, the scope of the present disclosure is determined according to the appended claims, rather than being limited by the foregoing specification and the exemplary embodiments described therein.

[0074]

Explanation of symbols

[0075] 100,200,300:Semiconductor components

[0076] 110:Semiconductor substrate

[0077] 115: Source / drain region

[0078] 120: Interface layer

[0079] 125: Gate structure

[0080] 130: first interface layer

[0081] 140: Second interface layer

[0082] 150: Zirconium-containing dielectric layer

[0083] 160: Gate electrode

[0084] 170: Diffusion barrier

[0085] N: Nitrogen atom

[0086] Ti: Titanium atom.

Claims

1. A semiconductor element, characterized in that: Include: A semiconductor substrate having a plurality of source / drain regions and a channel region between the plurality of source / drain regions; and A gate structure is located above the channel region of the semiconductor substrate, and the gate structure comprises: Interface layer; a zirconium-containing dielectric layer, located above the interface layer and in a tetragonal phase; and A gate electrode is located above the zirconium-containing dielectric layer.

2. The semiconductor device according to claim 1, characterized in that The interface layer includes titanium oxide.

3. The semiconductor device according to claim 2, characterized in that The zirconium-containing dielectric layer contacts the interface layer.

4. The semiconductor device according to claim 2, characterized in that The thickness of the interface layer is in the range between 5 angstroms and 3 nanometers.

5. The semiconductor device according to claim 2, characterized in that The thickness of the interface layer is in the range between 1 angstrom and 50 nanometers.

6. The semiconductor device according to claim 1, wherein: The gate electrode includes titanium nitride or tantalum nitride.

7. The semiconductor device according to claim 6, characterized in that The zirconium-containing dielectric layer is doped with nitrogen.

8. The semiconductor device according to claim 7, characterized in that The zirconium-containing dielectric layer has a top portion and a bottom portion opposite to each other, the bottom portion is in contact with the interface layer, and a nitrogen atomic concentration of the top portion is higher than a nitrogen atomic concentration of the bottom portion.

9. The semiconductor device according to claim 6, characterized in that The gate structure also includes a diffusion barrier layer between the gate electrode and the zirconium-containing dielectric layer, wherein the diffusion barrier layer includes aluminum oxide or titanium oxide.

10. The semiconductor device according to claim 9, characterized in that The diffusion barrier layer comprises the same material as the interface layer.

11. The semiconductor device according to claim 1, wherein: The zirconium-containing dielectric layer has a thickness in a range between 3 nanometers and 7 nanometers.

12. The semiconductor device according to claim 1, wherein: The zirconium-containing dielectric layer has a thickness in a range between 1 angstrom and 50 nanometers.

13. The semiconductor device according to claim 1, wherein: The zirconium-containing dielectric layer includes titanium atoms.

14. The semiconductor device according to claim 1, wherein: The interface layer includes a first interface layer and a second interface layer, wherein the first interface layer includes silicon oxide, and the second interface layer includes titanium oxide.

15. A method for manufacturing a semiconductor element, characterized in that: Include: A gate structure is formed above a channel region of a semiconductor substrate, wherein forming the gate structure comprises: depositing an interface layer above the channel region; Depositing a zirconium-containing dielectric layer on the interface layer, wherein the zirconium-containing dielectric layer is in a tetragonal phase; and forming a gate electrode over the zirconium-containing dielectric layer; and A plurality of source / drain regions are formed in the semiconductor substrate and on opposite sides of the channel region.

16. The manufacturing method according to claim 15, characterized in that: Also includes: After forming the gate electrode, an annealing process is performed, wherein a temperature of the annealing process is within a range between 400° C. and 900° C.

17. The manufacturing method according to claim 15, characterized in that: Also includes: An implantation process is performed on the zirconium-containing dielectric layer using nitrogen gas.

18. The manufacturing method according to claim 17, characterized in that: Also includes: Before forming the gate electrode, a diffusion barrier layer is deposited on the zirconium-containing dielectric layer, wherein the diffusion barrier layer comprises aluminum oxide or titanium oxide.

19. The manufacturing method according to claim 16, characterized in that: Also includes: performing an implantation process on the zirconium-containing dielectric layer using nitrogen; and After performing the implantation process and before forming the gate electrode, a diffusion barrier layer is deposited on the zirconium-containing dielectric layer, wherein the diffusion barrier layer comprises aluminum oxide or titanium oxide.

20. The manufacturing method according to claim 15, characterized in that: Depositing the interface layer comprises: depositing a first interfacial layer formed of silicon oxide; and A second interfacial layer formed of titanium oxide is deposited.

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