Nitride-based passivation layer at silicon germanium surfaces in nanoFETs

Abstract

The invention relates to a nitride-based passivation layer at a silicon germanium surface in a nanoFET. In a method of producing a nanoFET, source and drain first trenches are formed in a fin that includes a plurality of first nanostructures and a plurality of second nanostructures alternately formed over one another. A first semiconductor layer is deposited at a bottom portion of the source and drain first trenches and extends to the bottommost nanostructure. Sidewall passivation layers are formed over sidewalls of the plurality of first nanostructures in the source and drain first trenches, and internal spacers are formed on sidewalls of the plurality of second nanostructures. A second semiconductor layer is deposited in the source and drain first trenches over the first semiconductor layer to cover a sidewall passivation layer of the first nanostructure.

Description

Technical Field

[0001] The present disclosure relates to nitride-based passivation layers at silicon germanium surfaces in nanoFETs. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically made by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and elements thereon. The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise that should be addressed. Summary of the invention

[0003] According to one embodiment of the present disclosure, a method for forming a semiconductor device is provided, comprising: forming source and drain first trenches in a first fin, wherein the first fin includes a plurality of first nanostructures and a plurality of second nanostructures alternately formed on each other; forming internal spacers on the sidewalls of the plurality of second nanostructures; depositing a first semiconductor layer at the bottom portion of the source and drain first trenches, wherein the first semiconductor layer extends to the bottommost nanostructure; forming a sidewall passivation layer in the source and drain first trenches over the sidewalls of the plurality of first nanostructures; and depositing a second semiconductor layer in the source and drain first trenches over the first semiconductor layer, wherein the second semiconductor layer covers the sidewall passivation layer of the first nanostructure at the sidewalls of the source and drain first trenches.

[0004] According to one embodiment of the present disclosure, a method for forming a semiconductor device is provided, comprising: forming a source / drain trench in a semiconductor fin, wherein the semiconductor fin comprises a plurality of first nanostructures and a plurality of second nanostructures alternately formed on each other; depositing a first SiGe layer at a bottom portion of the source / drain trench, wherein the first SiGe layer extends to a bottommost nanostructure; forming a sidewall passivation layer in the source / drain trench over the sidewalls of the plurality of first nanostructures; and depositing a second SiGe layer in the source / drain trench over the first SiGe layer, wherein the second SiGe layer covers the sidewall passivation layer of one or more first nanostructures at the sidewalls of the source / drain trench.

[0005] According to one embodiment of the present disclosure, a semiconductor device is provided, comprising: a first semiconductor fin on a semiconductor substrate, wherein the first semiconductor fin comprises a plurality of first nanostructures; a gate electrode surrounding each of the plurality of first nanostructures; a source and a drain region in the first semiconductor fin, wherein each of the source and the drain region comprises: a first semiconductor layer, wherein the first semiconductor layer covers at least one of the plurality of first nanostructures; and a sidewall passivation layer on a sidewall of the at least one of the plurality of first nanostructures, wherein the sidewall passivation layer is between the first semiconductor layer and the at least one of the plurality of first nanostructures. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When with Figure 1 When read together, the various aspects of the present disclosure will be best understood from the following detailed description. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 An example of a nanostructured field effect transistor (nano-FET) in a three-dimensional view is illustrated according to some embodiments of the present disclosure.

[0008] Figure 2 , Figure 3 , Figure 4 and Figure 5 is an intermediate stage in manufacturing a nano FET according to some embodiments of the present disclosure Figure 1 Section AA' view shown in .

[0009] Fig. 6A and Figure 6B is an intermediate stage in manufacturing a nano FET according to some embodiments of the present disclosure Figure 1 Section BB' view shown in .

[0010] Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 11C , Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D , Fig.12E , Fig.12F , Figure 12G , Fig.13A , Fig. 13B , Fig. 13C , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Fig.18C , Fig.19A , Fig.19B , Fig.19C , Fig. 20A , Fig. 20B and Fig. 20C is a cross-sectional view of an intermediate stage in fabricating a nanoFET according to some embodiments of the present disclosure.

[0011] Fig.21A , Fig. 21B and Fig. 21C is a cross-sectional view of a nanoFET according to some embodiments of the present disclosure.

[0012] Fig.22A and Fig. 22B is a cross-sectional view of a nanoFET according to some embodiments of the present disclosure.

[0013] Fig.23A , Fig. 23B and Fig.23C Illustrated is a cross-sectional view of an intermediate stage in fabricating source / drain regions of two or more nanoFETs on a substrate, according to some embodiments of the present disclosure.

[0014] Fig.24A , Fig. 24B , Fig.25A , Fig.25B , Fig.26A , Fig.26B , Fig.27A and Fig.27B Illustrated is a cross-sectional view of a passivation layer in the source / drain region of a nanoFET according to some embodiments of the present disclosure.

[0015] Fig.28 A flow chart of a process for fabricating a nanoFET according to some embodiments of the present disclosure is illustrated. DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments, or examples, for implementing different features of the present invention. In order to simplify the present disclosure, specific examples of components and arrangements are described below. Of course, these are just examples and are not intended to be restrictive. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first and second features are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for simplicity and clarity, and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0017] Additionally, spatially relative terms, such as "below," "below," "lower," "above," "upper," and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the accompanying drawings. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. The device may be in other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0018] In various embodiments, in a nanoFET, a passivation layer generated between a source / drain region and one or more channels (e.g., nanosheets) can reduce the source-drain current of the nanoFET. At different locations of the substrate, different nanoFETs can be created, and different numbers of passivation layers can be generated between the source / drain region and the channel. Thus, at different locations of the substrate, the source-drain current of the nanoFET may be different.

[0019] Additionally, in the process of creating the source / drain regions, deposition and / or etching are used, source / drain region elements may migrate into the channel region during deposition, or etching may change the channel region dimensions, which may affect the critical dimension. Therefore, a passivation layer may be used between the source / drain regions and the channel region to prevent migration of elements between the source / drain regions and / or to prevent modification of the critical dimension.

[0020] The embodiments are described in the specific context of a die including nanoFETs. However, various embodiments may be applied to dies including other types of transistors (e.g., fin field-effect transistors (finFETs), planar transistors, etc.) in place of or in combination with nanoFETs.

[0021] Figure 1An example of a nanostructured field effect transistor (nano-FET) in a three-dimensional view is illustrated according to some embodiments of the present disclosure. Figure 1 Examples of nano-FETs (e.g., nanowire FETs, nano-sheet FETs (Nano-FETs), etc.) are shown in a three-dimensional view, with some features of the nano-FETs omitted for clarity of illustration. The nano-FETs may be nanosheet field-effect transistors (NSFETs), nanowire field-effect transistors (NWFETs), gate-all-around field-effect transistors (GAAFETs), etc.

[0022] The nanoFET includes a nanostructure 55 (e.g., a nanosheet, a nanowire, etc.) above a fin 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 55 acts as a channel region of the nanoFET. The nanostructure 55 may include a p-type nanostructure, an n-type nanostructure, or a combination thereof. An isolation region 68 is arranged between adjacent fins 66, and the fin 66 may protrude therefrom between adjacent isolation regions 68. Although the isolation region 68 is described / illustrated as being separated from the substrate 50, as used herein, the term "substrate" may refer only to a semiconductor substrate or to a combination of a semiconductor substrate and an isolation region. In addition, although the bottom portion of the fin 66 is illustrated as being a single continuous material together with the substrate 50, the bottom portion of the fin 66 and / or the substrate 50 may also include a single material or multiple materials. In this context, the fin 66 refers to the portion extending between adjacent isolation regions 68.

[0023] The gate dielectric layer 100 is over the top surface of the fin 66 and along the top surface, sidewalls, and bottom surface of the nanostructure 55. A gate electrode 102 (e.g., electrode) is over the gate dielectric layer 100 to create a gate structure. Epitaxial source / drain regions 92 are disposed on the fin 66 on opposite sides of the gate dielectric layer 100 and the gate electrode 102. The epitaxial source / drain regions 92 may be referred to as a source or a drain, individually or collectively, depending on the context.

[0024] Figure 1Reference cross sections used in subsequent figures are further illustrated. Cross section AA' is along the longitudinal axis of gate electrode 102 and in a direction perpendicular to the direction of current flow, e.g., between epitaxial source / drain regions 92 of the nanoFET. Cross section BB' is perpendicular to cross section AA' and parallel to the longitudinal axis of fin 66 of the nanoFET and in the direction of current flow, e.g., between epitaxial source / drain regions 92 of the nanoFET. Cross section CC' is parallel to cross section AA' and extends through epitaxial source / drain regions 82 of the nanoFET. For clarity, subsequent figures refer to these reference cross sections.

[0025] Some embodiments discussed herein are discussed in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Additionally, some embodiments contemplate aspects used in planar devices, such as planar FETs or fin field effect transistors (FinFETs).

[0026] Figure 2 , Figure 3 , Figure 4 and Figure 5 is an intermediate stage in manufacturing a nano FET according to some embodiments of the present disclosure Figure 1 The section A-A' view is shown in FIG. Figure 2 In the invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., doped with a p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. In general, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide; or a combination of these.

[0027] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, for example, an n-type nano FET, and the p-type region 50P can be used to form a p-type device, such as a PMOS transistor, for example, a p-type nano FET. The n-type region 50N can be physically separated from the p-type region 50P (as shown by the separator 20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be arranged between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0028] exist Figure 2 In the embodiment of the present invention, a multilayer stack 64 may also be formed over the substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A, 51B, and 51C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A, 53B, and 53C (collectively referred to as second semiconductor layers 53). For ease of illustration, as discussed in more detail below, the second semiconductor layer 53 will be removed and the first semiconductor layer 51 will be patterned to form a channel region of a nanoFET in the p-type region 50P. In addition, the first semiconductor layer 51 will be removed and the second semiconductor layer 53 will be patterned to form a channel region of a nanoFET in the n-type region 50N. However, in some embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of a nanoFET in the n-type region 50N, and the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of a nanoFET in the p-type region 50P.

[0029] In still other embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of a nanoFET in both the n-type region 50N and the p-type region 50P. In other embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of a nanoFET in both the n-type region 50N and the p-type region 50P. In such embodiments, the channel regions in both the n-type region 50N and the p-type region 50P may have the same material composition (e.g., silicon, or another semiconductor material) and be formed simultaneously.

[0030] For illustration, the multilayer stack 64 is illustrated as including three layers of each of the first semiconductor layer 51 and the second semiconductor layer 53. In some embodiments, the multilayer stack 64 may include any number of the first semiconductor layer 51 and the second semiconductor layer 53. Each layer of the multilayer stack 64 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE). In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material suitable for a p-type nano FET (e.g., silicon germanium or a similar material), and the second semiconductor layer 53 may be formed of a second semiconductor material suitable for an n-type nano FET (e.g., silicon, silicon carbide, or a similar material). For illustration, the multilayer stack 64 is illustrated as having a bottommost semiconductor layer suitable for a p-type nano FET. In some embodiments, the multilayer stack 64 may be formed so that the bottommost layer is a semiconductor layer suitable for an n-type nano FET.

[0031] The first semiconductor material and the second semiconductor material can be materials having high etching selectivity to each other. Therefore, the first semiconductor layer 51 of the first semiconductor material can be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material in the n-type region 50N, thereby allowing the second semiconductor layer 53 to be patterned to form the channel region of the n-type nanoFET. Similarly, the second semiconductor layer 53 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material in the p-type region 50P, thereby allowing the first semiconductor layer 51 to be patterned to form the channel region of the p-type nanoFET.

[0032] like Figure 3As shown, according to some embodiments, fins 66 are formed in substrate 50, and nanostructures 55 are formed in multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 can be formed in multilayer stack 64 and substrate 50, respectively, by etching grooves in multilayer stack 64 and substrate 50. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination of these. Etching can be anisotropic. Forming nanostructure 55 by etching multilayer stack 64 can further define first nanostructures 52A, 52B, and 52C (collectively referred to as first nanostructures 52) from first semiconductor layer 51, and define second nanostructures 54A, 54B, and 54C (collectively referred to as second nanostructures 54) from second semiconductor layer 53. The first nanostructure 52 and the second nanostructure 54 can be further collectively referred to as nanostructure 55.

[0033] The fins 66 and nanostructures 55 may be patterned by any suitable method. For example, the fins 55 and nanostructures 55 may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. In general, double patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing the created pattern to have, for example, a smaller pitch than would otherwise be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed above the substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 66.

[0034] Figure 3 The fins 66 in the n-type region 50N and the p-type region 50P are illustrated as having substantially equal widths for illustrative purposes. In some embodiments, the width of the fins 66 in the n-type region 50N may be greater or thinner than the fins 66 in the p-type region 50P. In addition, although each fin 66 and nanostructure 55 is always illustrated as having a uniform width, in other embodiments, the fins 66 and / or nanostructures 55 may have tapered sidewalls so that the width of each fin 66 and / or nanostructure 55 continues to increase in a direction toward the substrate 50. In such an embodiment, each nanostructure 55 may have a different width and be trapezoidal in shape.

[0035] exist Figure 4In the embodiment shown in the figure, a shallow trench isolation (STI) region 68 may be formed near the fin 66. The STI region 68 may be formed by depositing an insulating material over the substrate 50, the fin 66 and the nanostructure 55 and between adjacent fins 66. The insulating material may be an oxide, such as silicon oxide, nitride, or the like, or a combination of these, and may be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or the like, or a combination of these. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process may be performed. In one embodiment, the insulating material is formed so that excess insulating material covers the nanostructure 55. Although the insulating material is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown in the unit diagram) may first be formed along the surface of the substrate 50, the fin 66 and the nanostructure 55. Thereafter, a filling material such as those discussed above may be formed over the liner.

[0036] A removal process is then applied to the insulating material to remove excess insulating material above the nanostructures 55. In some embodiments, a planarization process may be utilized, such as chemical mechanical polishing (CMP), an etch-back process, a combination of these, etc. The planarization process exposes the nanostructures 55, so that after the planarization process is completed, the top surfaces of the nanostructures 55 and the insulating material are flush.

[0037] The insulating material is then recessed to form STI regions 68. The insulating material is recessed so that the upper portions of the fins 66 in the n-type region 50N and the p-type region 50P protrude from between adjacent STI regions 68. In addition, the top surface of the STI region 68 may have a flat surface, a convex surface, a concave surface (e.g., concave) as shown, or a combination of these. The top surface of the STI region 68 may be formed to be flat, convex, and / or concave by appropriate etching. The STI region 68 may be recessed using an acceptable etching process, such as an etch that is selective to the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than the material of the fin 66 and the nanostructure 55). For example, oxide removal may be used, wherein, for example, dilute hydrofluoric acid (dHF) is used.

[0038] The above article about Figures 2 to 4The described process is only one example of how the fin 66 and nanostructure 55 may be formed. In some embodiments, the fin 66 and / or nanostructure 55 may be formed using a mask and epitaxial growth process. For example, a dielectric layer may be formed above the top surface of the substrate 50, and a trench may be etched through the dielectric layer to expose the underlying substrate 50. The epitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed so that the epitaxial structure protrudes from the dielectric layer to form the fin 66 and / or nanostructure 55. The epitaxial structure may include alternating semiconductor materials discussed above, such as a first semiconductor material and a second semiconductor material. In some embodiments where the epitaxial structure is epitaxially grown, the epitaxially grown material may be doped in situ during growth, which may avoid prior and / or subsequent implants, although in situ and implant doping may be used together.

[0039] In addition, for illustrative purposes only, the first semiconductor layer 51 (and the nanostructure 52 generated thereby) and the second semiconductor layer 53 (and the nanostructure 54 generated thereby) are illustrated and discussed herein as including the same material in the p-type region 50P and the n-type region 50N. Therefore, in some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be different materials, or formed in a different order in the p-type region 50P and the n-type region 50N.

[0040] Further, in Figure 4 In the embodiment with different well types, a photoresist or other mask (not shown separately) can be used to implement different implantation steps for the n-type region 50N and the p-type region 50P. For example, a photoresist can be formed over the fin 66 and the STI region 68 in both the n-type region 50N and the p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist can be formed by using a spin coating technique, and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, n-type impurity implantation is performed in the p-type region 50P, and the photoresist can act as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50N. The n-type impurity can be phosphorus, arsenic, antimony, etc., implanted in this region to a concentration range of about 10 13 Atom / cm 3 to about 10 14 Atom / cm 3 After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0041] After or before implanting the p-type region 50P, a photoresist or other mask (not separately shown) is formed over the fins 66, nanostructures 55, and STI regions 68 in the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed by using a spin coating technique and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can act as a mask to substantially prevent the p-type impurity from being implanted into the p-type region 50P. The p-type impurity can be boron, boron fluoride, indium, etc., implanted in this region to a concentration range of about 10 13 Atom / cm 3 to about 10 14 Atom / cm 3 After implantation, the photoresist may be removed, for example, by an acceptable ashing process.

[0042] After implantation in the n-type region 50N and the p-type region 50P, an annealing process may be performed to repair implant damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fin may be doped in situ during growth, which may avoid implantation, although in situ and implantation doping may be used together. In some embodiments, initially, a dummy gate structure is created over the channel region to protect the channel region from being etched. Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A and Fig.18C The removal of the dummy gate structure and the generation of the gate structure are discussed. To generate the dummy gate structure, a dummy dielectric layer is patterned with a mask layer. Then, the dielectric layer and possible layers are retained over the channel area, and the mask layer and the dielectric layer are etched from other areas.

[0043] exist Figure 5 In the embodiment of the present invention, the mask layer 78 is patterned using an acceptable photolithography technique. The pattern of the mask layer 78 can then be transferred to the dummy gate layer 76 and the dummy dielectric layer 71 to form a dummy gate and a dummy gate dielectric, respectively. The dummy gate covers each channel region of the fin. The patterned mask layer 78 can be used to physically separate each dummy gate from an adjacent dummy gate. The dummy gate can also have a length direction that is substantially perpendicular to the length direction of each fin 66.

[0044] A dummy dielectric layer 71 may be formed on the fin 66 and / or the nanostructure 55. The dummy dielectric layer 71 may be, for example, silicon oxide, silicon nitride, a combination of these, and the like, and may be deposited or thermally grown according to an acceptable technique. A dummy gate layer 76 is formed above the dummy dielectric layer 71, and a mask layer 78 is formed above the dummy gate layer 76. The dummy gate layer 76 may be deposited above the dummy dielectric layer 71 and then flattened, for example, by CMP. The mask layer 78 may be deposited above the dummy gate layer 76. The dummy gate layer 76 may be a conductive or non-conductive material and may be selected from a group including: amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. The dummy gate layer 76 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing selected materials. The dummy gate layer 76 may be made of other materials that may have a high etch selectivity from the etching of the isolation region. The mask layer 78 may include, for example, silicon nitride, silicon oxide, etc. In this example, a single dummy gate layer 76 and a single mask layer 78 are formed on the n-type domain 50N and the p-type domain 50P. Note that the dummy dielectric layer 71 is shown as covering only the fin 66 and the nanostructure 55, which is only for illustration. In some embodiments, the dummy dielectric layer 71 may be deposited so that the dummy dielectric layer 71 covers the STI region 68, so that the dummy dielectric layer 71 extends between the dummy gate layer 76 and the STI region 68.

[0045] Fig. 6A and Figure 6B is an intermediate stage in manufacturing a nano FET according to some embodiments of the present disclosure Figure 1 The cross-sectional B-B' view shown in FIG. Fig. 6A As shown and as reference Figure 5 As described above, a dummy dielectric layer 71, a dummy gate layer 76, and a mask layer 78 are formed above the nanostructure 55 of the fin 66. Figure 6B As shown, after photolithography, the dummy dielectric layer 71 , the dummy gate electrode layer 76 , and the mask layer 78 remain only over the channel region, and are removed from other regions in both the n-type region 50N and the p-type region 50P.

[0046] Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 11C , Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D , Fig.12E , Fig.12F , Figure 12G , Fig.13A , Fig. 13B , Fig. 13C , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Fig.18C , Fig.19A , Fig.19B , Fig.19C , Fig. 20A , Fig. 20B and Fig. 20C is a cross-sectional view of an intermediate stage in fabricating a nanoFET according to some embodiments of the present disclosure. Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A , Fig.19A and Fig. 20A Picture shows Figure 1 Reference section AA' shown in . Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 11C , Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D , Fig.12E , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Figure 8B , Fig.19B and Fig. 20B Picture shows Figure 1 Reference section BB' shown in . Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A ,、 Fig.11A , Fig. 12A , Fig. 12C , Fig.12F , Figure 12G , Fig. 13C , Fig.18C , Fig.19C and Fig. 20C Picture shows Figure 1 Reference section CC' shown in . Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A , Fig. 12A , Fig. 12C , Fig.12F , Figure 12G , Fig. 13C , Fig.18C , Fig.19C and Fig. 20C The cross sections in both the n-type region 50N and the p-type region 50P are illustrated.

[0047] exist Fig. 7A and Figure 7B In the embodiment, the first spacer layer 80 and the second spacer layer 82 are formed respectively on Figure 5 and Fig. 6A or Figure 6B The first spacer layer 80 and the second spacer layer 82 will then be patterned to act as spacers for forming self-aligned source / drain regions. Fig. 7A and Figure 7B , a first spacer 80 is formed on the top surface of the STI region 68; the top surface and sidewalls of the fin 66, the nanostructure 55, and the mask layer 78; and the sidewalls of the dummy gate layer 76 and the dummy dielectric layer 71. A second spacer 82 is deposited over the first spacer 80. The first spacer 80 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like, using a technique such as thermal oxidation or deposition by CVD, ALD, or the like. The second spacer 82 may be formed of a material having a different etch rate than the material of the first spacer 80, such as silicon oxide, silicon nitride, silicon oxynitride, or the like, and may be deposited by CVD, ALD, or the like.

[0048] After forming the first spacer layer 80 and before forming the second spacer layer 82, implantation of lightly doped source / drain (LDD) regions (not shown separately) may be performed. Figure 4, a mask, such as a photoresist, may be formed over the n-type region 50N while exposing the p-type region 50P, and an appropriate type of impurity (e.g., p-type) may be implanted into the exposed fins 66 and nanostructures 55 in the p-type region 50P. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the p-type region 50P while exposing the n-type region 50N, and an appropriate type of impurity (e.g., n-type) may be implanted into the exposed fins 66 and nanostructures 55 in the n-type region 50N. The mask may then be removed. The n-type impurity may be any of the n-type impurities previously discussed, and the p-type impurity may be any of the p-type impurities previously discussed. The lightly doped source / drain regions may have a doping ratio from about 1x10 15 Atom / cm 3 To about 1x10 19 Atom / cm 3 Annealing can be used to repair implant damage and activate implanted impurities.

[0049] exist Fig. 8A and Figure 8B , the first spacer 80 and the second spacer 82 are etched to form the first spacer 81 and the second spacer 83. As will be discussed in more detail below, the first spacer 81 and the second spacer 83 function to self-align the subsequently formed source and drain regions and to protect the sidewalls of the fin 66 and / or the nanostructure 55 during subsequent processing. The first spacer 80 and the second spacer 82 can be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), and the like. In some embodiments, the material of the second spacer 82 has a different etching rate than the material of the first spacer 80, so that when the second spacer 82 is patterned, the first spacer 80 can act as an etching stop layer, and when the first spacer 80 is patterned, the second spacer 82 can act as a mask. For example, the second spacer 82 can be etched using an anisotropic etching process, wherein the first spacer 80 acts as an etching stop layer, and wherein the remaining portion of the second spacer 82 is formed as shown in FIG. Fig. 8A Thereafter, the second spacer 83 acts as a mask while etching the exposed portion of the first spacer layer 80, thereby forming a Fig. 8A The first spacer 81 shown in FIG.

[0050] like Fig. 8A As shown in FIG. 1 , the first spacer 81 and the second spacer 83 are arranged on the sidewalls of the fin 66 and / or the nanostructure 55. Figure 8BAs shown in FIG. 1 , in some embodiments, the second spacer layer 82 may be removed from over the first spacer layer 80 adjacent to the mask layer 78, the dummy gate layer 76, and the dummy dielectric layer 71, and the first spacer 81 is disposed on the sidewalls of the mask layer 78, the dummy gate layer 76, and the dummy dielectric layer 71. In other embodiments, a portion of the second spacer layer 82 may remain over the first spacer layer 80 adjacent to the mask layer 78, the dummy gate layer 76, and the dummy dielectric layer 71.

[0051] Note that the above disclosure generally describes processes for forming spacers and LDD regions. Other processes and sequences may also be used. For example, fewer or additional spacers may be used, a different sequence of steps may be used (e.g., the first spacer 81 may be patterned before the second spacer layer 82 is deposited), additional spacers may be formed and removed, etc.). Furthermore, different structures and steps may be used to form n-type and p-type devices.

[0052] exist Fig.9A and Fig. 9B In some embodiments, a trench 86 is formed in the fin 66, the nanostructure 55, and the substrate 50. The trench 86 may extend through the first nanostructure 52 and the second nanostructure 54 and into the substrate 50. Fig.9A As shown in , the top surface of the STI region 68 may be flush with the bottom surface of the trench 86. In various embodiments, the fin 66 may be etched so that the bottom surface of the trench 86 is disposed below the top surface of the STI region 68; and so on. The trench 86 may be formed by etching the fin 66, the nanostructure 55, and the substrate 50 using an anisotropic etching process such as RIE, NBE, and the like. During the etching process for forming the trench 86, the first spacer 81, the second spacer 83, and the mask layer 78 mask portions of the fin 66, the nanostructure 55, and the substrate 50. Each layer of the nanostructure 55 and / or the fin 66 may be etched using a single etching process or multiple etching processes. A timed etching process may be used to stop etching the trench 86 after the trench 86 reaches a desired depth.

[0053] exist Fig. 10A and 10B In the embodiment, the sidewall portions of the layers of the multilayer stack 64 formed of the first semiconductor material (e.g., the first nanostructure 52) exposed by the trench 86 are etched to form sidewall recesses 88 in the n-type region 50N, and the sidewall portions of the layers of the multilayer stack 64 formed of the second semiconductor material (e.g., the second nanostructure 54) exposed by the trench 86 are etched to form sidewall recesses 88 in the p-type region 50P. Fig. 10BThe sidewalls of the first nanostructure 52 and the second nanostructure 54 in the sidewall recess 88 are illustrated as straight, but the sidewalls may be concave or convex. The sidewalls may be etched using an isotropic etching process such as wet etching or the like. A mask (not shown) may be used to protect the p-type region 50P while the first nanostructure 52 is etched using an etchant selective to the first semiconductor material so that the second nanostructure 54 and the substrate 50 remain relatively unetched compared to the first nanostructure 52 in the n-type region 50N. Similarly, a mask (not shown) may be used to protect the n-type region 50N while the second nanostructure 54 is etched using an etchant selective to the second semiconductor material so that the first nanostructure 52 and the substrate 50 remain relatively unetched compared to the second nanostructure 54 in the p-type region 50P. In an embodiment where the first nanostructure 52 includes, for example, SiGe, and the second nanostructure 54 includes, for example, Si or SiC, a dry etching process with tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like may be used to etch the sidewalls of the first nanostructure 52 in the n-type region 50N, and a wet etching or dry etching process with hydrogen fluoride, another fluorine-based etchant, or the like may be used to etch the sidewalls of the second nanostructure 54 in the p-type region 50P.

[0054] exist Fig.11A , Fig. 11B and Fig. 11C In the embodiment, a first internal spacer 90 is formed in the sidewall recess 88. Fig. 10A and Fig. 10B An inner spacer layer (not separately shown) is deposited over the structure shown in to form a first inner spacer 90. The first inner spacer 90 acts as an isolation feature between the subsequently formed source / drain regions and the gate structure. As discussed in more detail below, the source / drain regions will be formed in the trenches 86, and the first nanostructures 52 in the n-type region 50N and the second nanostructures 54 in the p-type region 50P will be replaced by corresponding gate structures.

[0055] The inner spacer layer may be deposited by a conformal deposition process, such as CVD, ALD, etc. The inner spacer layer may include a material such as silicon nitride or silicon oxide, but any suitable material may be utilized, such as a low dielectric constant (low-k) material having a k value of less than about 3.5. The inner spacer layer may then be anisotropically etched to form a first inner spacer 90. Although the outer sidewalls of the first inner spacer 90 are illustrated as being flush with the sidewalls of the second nanostructure 54 in the n-type region 50N and flush with the sidewalls of the first nanostructure 52 in the p-type region 50P, the outer sidewalls of the first inner spacer 90 may extend beyond the sidewalls of the second nanostructure 54 and / or the first nanostructure 52, respectively, or be recessed relative to these sidewalls.

[0056] In addition, although Fig. 11B The outer side wall of the first inner partition 90 is shown as straight, but the outer side wall of the first inner partition 90 may be concave or convex. For example, Fig. 11C An embodiment is illustrated in which the sidewalls of the first nanostructure 52 are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer 90 is recessed relative to the sidewalls of the second nanostructure 54 in the n-type region 50N. An embodiment is also illustrated in which the sidewalls of the second nanostructure 54 are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer 90 is recessed relative to the sidewalls of the first nanostructure 52 in the p-type region 50P. The inner spacer layer can be etched by an anisotropic etching process such as RIE, NBE, etc. The first inner spacer 90 can be used to prevent subsequent etching processes (such as etching processes used to form gate structures) from etched to subsequently formed source / drain regions (such as epitaxial source / drain regions 92, which will be referred to below) Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D and Fig.12E discuss) causing damage.

[0057] exist Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D and Fig.12E 8, as shown, a bottom portion 230 (e.g., bottom layer) of trench 86 (source / drain recess or source / drain trench) is filled with a semiconductor material, and bottom portion 230 is filled up to the bottommost nanostructure 54 and the bottommost inner spacer 90 of nanostructure 54. In some embodiments, bottom portion 230 is a mesa or a portion of a mesa connecting two or more semiconductor fins 66, and is filled with a SiGe semiconductor material, such as Si 1-x Ge x , where x is between 0.1 and 0.4, such as 0.35. In some embodiments, the SiGe semiconductor material of the bottom portion 230 includes a dopant material. In some embodiments, the bottom portion 230 is filled up to the bottommost nanostructure, such as the bottommost nanostructure 52 in the n-type region 50N and the p-type region 50P. The inner spacer 90 has a concave, convex, or flat shape at the sidewall of the trench 86.

[0058] In some embodiments, in the n-type region 50N, the nanostructures 52 are subsequently removed and replaced by a gate structure wrapped around the nanostructures 54. In the p-type region 50P, the nanostructures 54 are subsequently removed and replaced by a gate structure wrapped around the nanostructures 52 (see Fig.19B As shown below, the nanostructures 54 disposed between adjacent pairs of epitaxial source / drain regions 92 act as channel regions (nanowires or nanosheets) or channels, and the gate structure wraps around the channel regions in the n-type region 50N. The nanostructures 52 may act as channel regions in the p-type region 50P.

[0059] exist Fig. 12B In the embodiment, the source / drain trench 86 is exposed to a plasma material 120, such as a directional plasma material or a plasma beam, thereby forming a passivation layer 232, such as a sidewall passivation layer, over the nanostructure 54 in the n-type region 50N and over the nanostructure 52 in the p-type region 50P. Another layer 234 is a passivation layer formed over the bottom portion 230. The passivation layer 232 prevents etching of the nanostructure 54 or 52, and prevents the migration of the bottom portion 230 material into the nanostructure 54 or 52, thereby maintaining the critical dimension (CD) of the nanoFET. In some embodiments, the plasma material 120 includes one of silicon, carbon, oxygen, nitrogen, or a combination of these, and may produce a passivation layer 232 such as silicon nitride, silicon dioxide, silicon carbide, amorphous silicon, polycrystalline silicon, or crystalline silicon. In some embodiments, the passivation layer 232 prevents the nanostructure 54 from acting as a channel region, thereby reducing the current of the nanoFET. In some embodiments, as Fig. 12B As shown, the plasma material 120 can be directional, and the direction can change from downward to tilted to the right or tilted to the left, so that the plasma material impacts the sidewall of the nanostructure or the top of the bottom portion 230. In some embodiments, the passivation layer 232 above the nanostructure 54 of the n-type region 50N or above the nanostructure 52 of the p-type region 50P is produced by atomic layer deposition of silicon, carbon, oxygen, nitrogen or a combination thereof, followed by thermal annealing at least 900 degrees Celsius. In addition, the layer 234 above the bottom portion 230 can also be produced by atomic layer deposition and then thermal annealing as described above. In some embodiments, the plasma is nitrogen, and the nitrogen diffuses into the nanostructure 54 and forms the passivation layer 232 together with the silicon of the nanostructure 54, which is a crystallized SiN barrier to prevent Ge from diffusing into the nanostructure 54. In addition, the SiN barrier can prevent etching of the nanostructure 54 and can maintain critical dimensions. In some embodiments where the plasma is nitrogen and the nitrogen diffuses into the nanostructures 54 , polycrystalline SiN and / or amorphous SiN may be produced in the passivation layer 232 .

[0060] like Fig. 12C As shown, a layer 234 is removed from above the bottom portion 230 material, and then another semiconductor layer 240 is deposited above the bottom portion 230. By removing the layer 234, the bottom portion 230 and the semiconductor layer 240 become electrically connected to each other. The semiconductor layer 240 may cover one or more, for example, one or two, of the nanostructures 54 of the n-type region 50N or the nanostructures 52 of the p-type region 50P. The semiconductor layer 240 also covers the passivation layer 232. The nanostructures 54 or 52 with the passivation layer 232 covered by the semiconductor layer 240 may not contribute to the current of the nanoFET, thereby reducing the current of the nanoFET. Therefore, depending on the current size required by the nanoFET, one or more of the nanostructures 54 or 52 with the passivation layer 232 may be covered by the semiconductor layer 240. In some embodiments, the nanostructures 54 or 52 may not have the passivation layer 232, or the nanostructures 54 or 52 may not be covered by the semiconductor layer 240. The passivation layer may be formed at a temperature between 300 degrees Celsius and 700 degrees Celsius. In some embodiments, the semiconductor layer 240 includes a SiGe semiconductor material, such as Si 1-x Ge x , where x is between 0.1 and 0.3, such as 0.25. In some embodiments, the SiGe semiconductor material of the semiconductor layer 240 includes a dopant material. In some embodiments, after removing the layer 234, a residual element (e.g., a nitrogen residue) remains on the top of the bottom portion 230. The bottom portion 230, the semiconductor layer 240, and the epitaxial source / drain region 92 may have an n-type (e.g., arsenic or phosphorus) dopant concentration or a p-type (e.g., boron) dopant concentration. In some embodiments, the dopant concentration of the epitaxial source / drain region 92 is between about 10 19 cm -3 and about 10 21 cm -3 and the dopant concentration of the bottom portion 230 and the semiconductor layer 240 is between about 10 14 cm -3 and about 10 16 cm -3 between.

[0061] like Fig.12D As shown, the passivation layer 232 not covered by the semiconductor layer 240 is removed by an etching process, such as wet etching or a dry etching process, such as anisotropic etching or directional dry etching. Fig.12EAs shown, after removing the passivation layer 232 not covered by the semiconductor layer 240, an epitaxial source / drain region 92 is grown in the source / drain trench 86 above the semiconductor layer 240. The epitaxial source / drain region 92 covers the remaining nanostructures 54 or 52 without the passivation layer 232 and becomes electrically in contact with the nanostructures 54 or 52. In some embodiments, the semiconductor fin 66 includes up to 10 nanostructures 54 or 52. Among the 10 nanostructures 54 or 52, there may be no, one, two, or up to 9 nanostructures 54 or 52 with the passivation layer 232 (closed channel) and may be covered by the semiconductor layer 240, and thus may not contribute to the current of the nanoFET. The remaining nanostructures 54 or 52 may not have the passivation layer 232 (open channel) and are in contact with the epitaxial source / drain region 92 and may contribute to the nanoFET current. Depending on the amount of current that may be required at a certain location in the semiconductor / integrated circuit, the number of open channels and closed channels of the nano FET may be determined. In some embodiments, the epitaxial source / drain region 92 comprises a SiGe semiconductor material, such as Si 1-x Ge x , where x is between 0.1 and 0.3, such as 0.2, and may include a dopant material.

[0062] like Fig.12E As shown, an epitaxial source / drain region 92 is formed in the trench 86. In some embodiments, the epitaxial source / drain region 92 can apply stress to the second nanostructure 54 in the n-type region 50N and the first nanostructure 52 in the p-type region 50P, thereby improving performance. Fig.12E As shown in , epitaxial source / drain regions 92 are formed in trenches 86 so that each dummy gate layer 76 is disposed between adjacent pairs of epitaxial source / drain regions 92. In some embodiments, first spacers 81 are used to separate epitaxial source / drain regions 92 from dummy gate layers 76, and first internal spacers 90 are used to separate epitaxial source / drain regions 92 from nanostructures 55 by an appropriate lateral distance so that epitaxial source / drain regions 92 do not short circuit with the gate of the resulting nanoFET formed subsequently.

[0063] The epitaxial source / drain region 92 in the n-type region 50N (e.g., NMOS region) can be formed by masking the p-type region 50P (e.g., PMOS region). Then, the epitaxial source / drain region 92 is epitaxially grown in the trench 86 in the n-type region 50N. The epitaxial source / drain region 92 may include any acceptable material suitable for n-type nanoFETs. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 82N may include a material that applies tensile stress on the second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, and the like. The epitaxial source / drain region 92 may have a surface elevated from each upper surface of the nanostructure 55, and may have a facet.

[0064] The epitaxial source / drain region 92 in the p-type region 50P (e.g., a PMOS region) can be formed by masking the n-type region 50N (e.g., an NMOS region). Then, the epitaxial source / drain region 92 is epitaxially grown in the trench 86 in the p-type region 50P. The epitaxial source / drain region 82P may include any acceptable material suitable for a p-type nano FET. For example, if the first nanostructure 52 is silicon germanium, the epitaxial source / drain region 92 may include a material that applies compressive stress on the first nanostructure 52, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, and the like. The epitaxial source / drain region 92 may also have a surface that is elevated from each surface of the multilayer stack 64, and may have a facet.

[0065] The epitaxial source / drain regions 92, the first nanostructures 52, the second nanostructures 54, and / or the substrate 50 may be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions, and then annealed. The source / drain regions may have a thickness of about 1x10 19 Atom / cm 3 To about 1x10 21 Atom / cm 3 The n-type and / or p-type impurities of the source / drain regions may be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 92 may be doped in situ during growth.

[0066] Due to the epitaxial process used to form epitaxial source / drain regions 92 in n-type region 50N and p-type region 50P, the upper surfaces of epitaxial source / drain regions 92 have facets that extend laterally outward beyond the sidewalls of nanostructure 55. In some embodiments, these facets may result in the merging of adjacent epitaxial source / drain regions 92 of the same two or more nanoFETs, such as Fig.12F In other embodiments, adjacent epitaxial source / drain regions 92 remain separated after the epitaxial process is completed, such as Figure 12GIn these embodiments, first spacer 81 may be formed to the top surface of STI region 68, thereby blocking epitaxial growth. In some other embodiments, first spacer 81 may cover some portion of the sidewalls of nanostructure 55, thereby further blocking epitaxial growth. In some other embodiments, the spacer etch used to form first spacer 81 may be adjusted to remove spacer material, thereby allowing the region of epitaxial growth to extend to the surface of STI region 68, such as Fig.12F and 12G As shown, these figures are at the cross section CC′ and also show the bottom portion 230 and the semiconductor layer 240 in the trench 86 .

[0067] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used for the epitaxial source / drain region 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of different semiconductor materials and may be doped to different doping concentrations. In some embodiments, the doping concentration of the first semiconductor material layer 92A may be less than that of the second semiconductor material layer 92B, and greater than that of the third semiconductor material layer 92C. In embodiments where the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited above the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited above the second semiconductor material layer 92B.

[0068] exist Fig.13A , Fig. 13B and Fig. 13C in Figure 5A first interlayer dielectric (ILD) 96 is deposited over the structure shown in FIG. The first ILD 96 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), and the like. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain regions 92, the mask layer 78, and the first spacer 81. The CESL 94 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, having a different etch rate than the material of the overlying first ILD 96 .

[0069] exist Fig.14A and Fig. 14B In the process, a planarization process, such as CMP, may be performed to make the top surface of the first ILD 96 flush with the top surface of the dummy gate layer 72 or the mask layer 76. The planarization process may also remove the mask layer 78 on the dummy gate layer 76, and some portions of the first spacer 81 along the sidewalls of the mask layer 78. After the planarization process, the top surfaces of the dummy gate layer 76, the first spacer 81, and the first ILD 96 are flush within the process variation range. Therefore, the top surface of the dummy gate layer 76 is exposed through the first ILD 96. In some embodiments, the mask layer 74 may remain, in which case the planarization process makes the top surface of the first ILD 96 flush with the top surfaces of the mask layer 74 and the first spacer 81.

[0070] exist Fig.15A and Fig. 15BIn one embodiment, the dummy gate layer 76 and the mask layer 78 (if present) are removed in one or more etching steps, thereby forming a recess 98. Portions of the dummy dielectric layer 71 in the recess 98 are also removed. In some embodiments, the dummy gate layer 76 and the dummy dielectric layer 71 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using (one or more) reactive gases that selectively etches the dummy gate layer 76 at a faster rate than the first ILD 96 or the first spacer 81. Each recess 98 exposes and / or covers some portions of the nanostructure 55 that serve as channel regions in the subsequently completed nanoFET. The portions of the nanostructure 55 that serve as channel regions are arranged between adjacent pairs of epitaxial source / drain regions 92. During removal, when the dummy gate layer 76 is etched, the dummy dielectric layer 71 may be used as an etch stop layer. After removing the dummy gate layer 76, the dummy dielectric layer 71 may then be removed.

[0071] exist Fig.16A and Fig. 16B , the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P are removed, extending the recess 98. The first nanostructure 52 may be removed by forming a mask (not shown) over the p-type region 50P and performing an isotropic etching process such as a wet etch or the like using an etchant selective to the material of the first nanostructure 52, while the second nanostructure 54, the substrate 50, and the STI region 68 remain relatively unetched compared to the first nanostructure 52. In embodiments where the first nanostructure 52 includes, for example, SiGe and the second nanostructures 54A, 54B, and 54C include, for example, Si or SiC, the first nanostructure 52 in the n-type region 50N may be removed using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like.

[0072] The second nanostructures 54 in the p-type region 50P may be removed by forming a mask (not shown) over the n-type region 50N and performing an isotropic etching process such as a wet etch or the like using an etchant that is selective to the material of the second nanostructures 54, while the first nanostructures 52, the substrate 50, and the STI regions 68 remain relatively unetched compared to the second nanostructures 54. In embodiments where the second nanostructures 54 include, for example, SiGe and the first nanostructures 52 include, for example, Si or SiC, the second nanostructures 54 in the p-type region 50P may be removed using hydrogen fluoride, another fluorine-based etchant, or the like.

[0073] In other embodiments, the channel regions in the n-type region 50N and the p-type region 50P may be formed simultaneously, for example by removing the first nanostructure 52 in both the n-type region 50N and the p-type region 50P or by removing the second nanostructure 54 in both the n-type region 50N and the p-type region 50P. In such embodiments, the channel regions of the n-type nanoFET and the p-type nanoFET may have the same material composition, for example, silicon, silicon germanium, etc. Fig.21A , Fig. 21B and Fig. 21C The structure resulting from such an embodiment is illustrated, wherein the channel regions in both the p-type region 50P and the n-type region 50N are provided by the second nanostructure 54 and comprise, for example, silicon.

[0074] Fig.17A and Fig. 17B A gate dielectric layer 100 and a gate electrode 102 that may be formed for a replacement gate are shown. The gate dielectric layer 100 is conformally deposited in the recess 98. In the n-type region 50N, the gate dielectric layer 100 may be formed on the top surface and sidewalls of the substrate 50 and the top surface, sidewalls, and bottom surface of the second nanostructure 54, while in the p-type region 50P, the gate dielectric layer 100 may be formed on the top surface and sidewalls of the substrate 50 and the top surface, sidewalls, and bottom surface of the first nanostructure 52. The gate dielectric layer 100 may also be deposited on the top surface of the first ILD 96, the CESL 94, the first spacer 81, and the STI region 68.

[0075] According to some embodiments, the gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, and the like, or a combination of these. For example, in some embodiments, the gate dielectric may include a silicon oxide layer and a metal oxide layer above the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 100 may have a k value greater than about 7.0 and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. In the n-type region 50N and the p-type region 50P, the structure of the gate dielectric layer 100 may be the same or different. The formation method of the gate dielectric layer 100 may include molecular beam deposition (MBD), ALD, PECVD, and the like.

[0076] The gate electrode 102 is deposited over the gate dielectric layer 100 and fills the remaining portion of the recess 98. The gate electrode 102 may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations of these, or multiple layers of such materials. Fig.17A and Fig. 17B, a single-layer gate electrode 102 is illustrated, but the gate electrode 102 may include any number of liner layers, any number of work function adjustment layers, and filler materials. Any combination of layers constituting the gate electrode 102 may be deposited in the n-type region 50N between adjacent second nanostructures 54 and between the second nanostructure 54A and the substrate 50, and may be deposited in the p-type region 50P between adjacent first nanostructures 52.

[0077] The formation of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P may occur simultaneously, so that the gate dielectric layer 100 in each region is formed of the same material, and the formation of the gate electrode 102 may occur simultaneously, so that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region may be formed by different processes, so that the gate dielectric layer 100 may be a different material and / or have a different number of layers, and / or the gate electrode 102 in each region may be formed by different processes, so that the gate electrode 102 may be a different material and / or have a different number of layers. When using different processes, various masking steps may be used to mask and expose appropriate regions.

[0078] After filling the recess 98, a planarization process, such as CMP, may be performed to remove excess portions of the gate dielectric layer 100 and the gate electrode 102 material that are above the top surface of the first ILD 96. The remaining portions of the gate electrode 102 and the gate dielectric layer 100 material thereby form a replacement gate structure for the resulting nanoFET. The gate electrode 102 and the gate dielectric layer 100 may be collectively referred to as a "gate structure". In some embodiments, the nanostructures 54 in the n-type region 50N are configured (e.g., formed or designed) to act as a channel for the nanoFET, and the nanostructures 52 in the p-type region 50P are configured (e.g., formed or designed) to act as a channel for the nanoFET. In addition, the nanostructures 52 in the n-type region 50N include the gate electrode 102, are electrically connected to each other, and are formed or designed to act as part of the gate structure. The nanostructures 54 in the p-type region 50P include the gate electrode 102, are electrically connected to each other, and are formed or designed to act as part of the gate structure.

[0079] Fig.18A , Fig.18B and Fig.18CThe gate structure (including the gate dielectric layer 100 and the corresponding overlying gate electrode 102) is shown to be recessed so that the recess is formed directly above the gate structure and between the opposing portions of the first spacer 81. A gate mask 104 including one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.) is filled in the recess, and then a planarization process is performed to remove excess portions of the dielectric material extending over the first ILD 96. A subsequently formed gate contact penetrates the gate mask 104 and contacts the top surface of the recessed gate electrode 102.

[0080] like Fig.18A , Fig.18B and Fig.18C As shown, the second ILD 106 is deposited over the first ILD 96 and over the gate mask 104. In some embodiments, the second ILD 106 is a flowable film formed by FCVD. In some embodiments, the second ILD 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method, such as CVD, PECVD, etc.

[0081] Fig.19A , Fig.19B and Fig.19C It is shown that the second ILD 106, the first ILD 96, the CESL 94, and the gate mask 104 can be etched to form a recess 108 that exposes the surface of the epitaxial source / drain region 92 and / or the gate structure. The recess 108 can be formed by etching using an anisotropic etching process such as RIE, NBE, etc. In some embodiments, the recess 108 can be etched through the second ILD 106 and the first ILD 96 using a first etching process; the recess 108 can be etched through the gate mask 104 using a second etching process; and then the recess 108 can be etched through the CESL 94 using a third etching process. A mask such as a photoresist can be formed and patterned over the second ILD 106 to mask portions of the second ILD 106 for the first etching process and the second etching process. In some embodiments, the etching process may be an over-etch so that the recess 108 extends into the epitaxial source / drain region 92 and / or the gate structure, and the bottom of the recess 108 may be flush with the epitaxial source / drain region 92 and / or the gate structure (e.g., at the same level, or at the same distance from the substrate), or lower than (lower than, for example, closer to the substrate) the epitaxial source / drain region 92 and / or the gate structure. Although Fig.19BThe recess 108 is illustrated as exposing the epitaxial source / drain region 92 and the gate structure in the same cross-section, but in various embodiments, the epitaxial source / drain region 92 and the gate structure may be exposed in different cross-sections to reduce the risk of shorting subsequently formed contacts. After forming the recess 108, a silicide region 110 is formed over the epitaxial source / drain region 92. In some embodiments, the silicide region 110 is formed by first depositing a metal (not shown) that is capable of reacting with the semiconductor material (e.g., silicon, silicon germanium, germanium) of the underlying epitaxial source / drain region 92 to form a silicide or germanide region, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof, over the exposed portion of the epitaxial source / drain region 92, and then performing a thermal annealing process to form the silicide region 110. The unreacted portion of the deposited metal is then removed, for example, by an etching process. Although the silicide region 110 is referred to as a silicide region, the silicide region 110 may also be a germanide region or a silicon-germanide region (e.g., a region including silicide and germanide). In one embodiment, the silicide region 110 includes TiSi and has a thickness in a range of about 2 nm to about 10 nm. Fig.19B As shown, in the n-type region 50N, the nanostructure 52 may be removed and replaced by a gate structure 195 wrapped around the nanostructure 54. In the p-type region 50P, the nanostructure 54 may be removed and replaced by a gate structure 195 wrapped around the nanostructure 52. Each gate structure 195 includes a gate electrode 102 in contact with a gate dielectric layer 100. In each nanoFET, the gate structures 195, such as the gate electrodes 102 of the gate structures 195, are in contact with each other. In the p-type region 50P, the gate structure 195 is in contact with the nanostructure 52, so that the gate electrode 102 is connected to the nanostructure 52 through the gate dielectric layer 100. In the n-type region 50N, the gate structure 195 is in contact with the nanostructure 54, so that the gate electrode 102 is connected to the nanostructure 54 through the gate dielectric layer 100.

[0082] Fig. 20A , Fig. 20B and Fig. 20CContacts 112 and 114 (also referred to as contact plugs) that may be formed in the recess 108 are shown. The contacts 112 and 114 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filling material. For example, in some embodiments, the contacts 112 and 114 each include a barrier layer and a conductive material, and are electrically coupled to underlying conductive features (e.g., the gate electrode 102 and / or the silicide region 110 in the illustrated embodiment). The contact 114 is electrically coupled to the gate electrode 102 and may be referred to as a gate contact, and the contact 112 is electrically coupled to the silicide region 110 and may be referred to as a source / drain contact. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, and the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, and the like. A planarization process, such as CMP, may be performed to remove excess material from the surface of the second ILD 106.

[0083] Fig.21A , Fig. 21B and Fig. 21C is a cross-sectional view of a nanoFET according to some embodiments of the present disclosure. Fig.21A Picture shows Figure 1 Reference section AA' shown in . Fig. 21B Picture shows Figure 1 Reference section BB' shown in . Fig. 21C Picture shows Figure 1 Reference section C-C' is shown in Fig.21A , Fig. 21B and Fig. 21C In the Fig. 20A , Fig. 20B and Fig. 20C Similar components are formed by similar processes. Figure 21A-Figure 21C In the embodiment, the channel regions in the n-type region 50N and the p-type region 50P include the same material. For example, the second nanostructure 54 including silicon provides channel regions for the p-type nanoFETs in the p-type region 50P and the n-type nanoFETs in the n-type region 50N. Fig.21A , 21B The structure of 21C can be formed by, for example, the following method: removing the first nanostructure 52 from both the p-type region 50P and the n-type region 50N at the same time; depositing the gate dielectric layer 100 and the gate electrode 102N (e.g., suitable for the gate electrode of the p-type nanoFET) around the second nanostructure 54 in the p-type region 50P; and depositing the gate dielectric layer 100 and the gate electrode 102N (e.g., suitable for the gate electrode of the n-type nanoFET) around the second nanostructure 54 in the n-type region 50N. In such an embodiment, as described above, the material of the epitaxial source / drain region 92 in the n-type region 50N may be different compared to the p-type region 50P. Fig. 21BAlso shown is a portion 225 of the source / drain trench 86. The portion 225 of the different passivation layers has been referenced to Fig.24A , Fig. 24B , Fig.25A , Fig.25B , Fig.26A , Fig.26B , Fig.27A and Fig.27B Described.

[0084] Fig.22A and Fig. 22B is a cross-sectional view of a nanoFET according to some embodiments of the present disclosure. Fig.22A and Fig. 20B The difference is that Fig.22A Two of the channels are closed, ie blocked, and only one channel is open. Fig. 22B and Fig. 20B The difference is that Fig. 22B No channel is closed; all channels are open and conductive.

[0085] Fig.23A , Fig. 23B and Fig.23C Illustrated is a cross-sectional view of an intermediate stage in fabricating source / drain regions of two or more nanoFETs 222 (eg, semiconductor devices) on a substrate, according to some embodiments of the present disclosure. Fig.23A , Fig. 23B and Fig.23C Two or more nano-FETs 222 are shown on substrate 50 at different locations of the semiconductor circuit. Fig.23A Shown is one nanoFET 222 having more open channels than closed channels, and another nanoFET 222 at another location having more closed channels than open channels. Fig. 23B Shown is one nanoFET 222 having no closed channels and all channels being open, and another nanoFET 222 at another location having one closed channel and two open channels. Fig.23C One nanoFET 222 is shown having one closed channel and two open channels, and another nanoFET 222 at another location having two closed channels and one open channel. Each nanoFET 222 is either in the n-type region 50N or in the p-type region 50P.

[0086] Fig.24A , Fig. 24B , Fig.25A , Fig.25B , Fig.26A , Fig.26B , Fig.27A and Fig.27B Illustrated is a cross-sectional view of a passivation layer in the source / drain region of a nanoFET according to some embodiments of the present disclosure. Fig.24A Shows Fig. 21B 225 of the semiconductor layer 240 and the bottom portion 230, the semiconductor layer 240 and the epitaxial source / drain regions 92 are shown. Fig.24A and Fig. 24B Also shown is a passivation layer 232 having a rectangular shape with a height 233 between 3 nm and 20 nm and a thickness 243 between 0.2 nm and 5 nm. Fig. 24B Shows Fig.24A 235. Bottom portion 230, semiconductor layer 240, and epitaxial source / drain region 92 have the same width 237 between 10 nm and 50 nm, and semiconductor layer 240 has a height 231 between 3 nm and 90 nm. Heights 239 and 241 of nanostructure 54 and internal spacer 90 are the same as the height of nanostructure 54, between 3 nm and 15 nm. A distance 249 between each bottom of upper internal spacer 90 and the bottom of epitaxial source / drain region 92 is between 5 nm and 10 nm. Relative to the bottom of lower internal spacer 90 as a reference line, a distance 247 between each bottom of lower internal spacer 90 and the bottom of semiconductor layer 240 is between 5 nm and -10 nm. An edge 2304 of passivation layer 232 is between 5 nm and -10 nm (e.g., recessed by 10 nm) relative to edge 2302 of semiconductor layer 240 (as a reference point). Additionally, angles 2306 and 2308 between the top surface of passivation layer 232 and the face of passivation layer 232 are between 80 and 110 degrees. Additionally, height 239 of nanostructures 54 is less than height 233 of passivation layer 232 , so that passivation layer 232 effectively covers nanostructures 54 .

[0087] Fig.25A and Fig.25B Shown with Fig.24A and Fig. 24B The same items, and thus the same item numbers, are used for the same features and have the same values ​​or value ranges, except that the passivation layer 232 has a pointed shape pointing toward the center of the semiconductor layer 240. Additionally, the angle 2308 is between 130 and 150 degrees, and the angle 2306 is between 40 and 60 degrees.

[0088] Fig.26A and Fig.26B Shown with Fig.24A and Fig. 24BThe same items, and thus the same item numbers, are used for the same features and have the same values ​​or value ranges, except that the passivation layer 232 has a lens shape. Additionally, the angle 2308 is between 70 and 90 degrees, and the angle 2306 is between 70 and 90 degrees. As shown, the angles 2306 and 2308 are calculated from the bottom surface of the epitaxial source / drain region 92 to the surface tangent to the lens shape.

[0089] Fig.27A and Fig.27B Shown with Fig.24A and Fig. 24B The same items, and thus the same item numbers, are used for the same features and have the same values ​​or value ranges, except that the passivation layer 232 has a disc shape. Additionally, the angle 2308 is between 90 degrees and 130 degrees, and the angle 2306 is between 50 degrees and 90 degrees. As shown, the angles 2306 and 2308 are calculated from the bottom surface of the epitaxial source / drain region 92 to the surface tangent to the lens shape.

[0090] Fig.28 A flow chart of a process 2800 for fabricating a nano FET according to some embodiments of the present disclosure is illustrated. The steps of the process are as follows: Fig.11A , Fig. 11B , Fig. 11C , Fig. 12A , Fig. 12B and Fig. 12C In step 2810, source and drain trenches are formed in the first fin. Fig.11A As shown, source and drain trenches 86 are formed in the semiconductor fin 66. In some embodiments, the first fin includes a plurality of first nanostructures 54 and a plurality of second nanostructures 52 that are alternately arranged on top of each other.

[0091] At step 2820, internal spacers are formed on the sidewalls of the plurality of second nanostructures. Fig. 11C As shown, the internal spacer 90 may be formed on the sidewalls of the plurality of second nanostructures 52 in the n-type region 50N, and the internal spacer 90 is not formed on the sidewalls of the plurality of first nanostructures 54 in the n-type region 50N. As described above, in the n-type region, the second nanostructures 52 may be removed and replaced with a gate structure 195 of a nanoFET. The first nanostructure 54 may serve as a channel of the nanoFET, and the gate structure 195 surrounds the channel.

[0092] At step 2830, a first semiconductor layer is deposited on the bottom portions of the source and drain trenches. Fig. 12A As shown, a first semiconductor layer is deposited on the bottom portions 230 of the source and drain trenches 86 .

[0093] At step 2840, a sidewall passivation layer is formed over the sidewalls of the plurality of first nanostructures in the source and drain trenches. Fig. 12B As shown, a passivation layer 232 is formed over the sidewalls of the plurality of first nanostructures 54 in the source and drain trenches 86 .

[0094] At step 2850, a second semiconductor layer is deposited over the first semiconductor layer in the source and drain trenches. Fig. 12C As shown, a semiconductor layer 240 is deposited over the bottom portion 230. The semiconductor layer 240 covers the first nanostructure 54 and one of the passivation layer 232. The uncovered passivation layer 232 is subsequently removed.

[0095] As described in the above embodiments, a passivation layer can be created between the source / drain region and the channel. The passivation layer can prevent current from passing through one or more channels, thereby reducing the source-drain current of the nanoFET. The passivation layer can also prevent elements from migrating between the channel and the source / drain region during deposition and etching, and can prevent the channel region from being etched, thereby maintaining critical dimensions.

[0096] According to an embodiment, a method includes forming source and drain first trenches in a first fin so that the first fin includes a plurality of first nanostructures and a plurality of second nanostructures alternately formed on top of each other. The method also includes forming internal spacers on the sidewalls of the plurality of second nanostructures, and depositing a first semiconductor layer at the bottom portion of the source and drain first trenches so that the first semiconductor layer extends to the bottommost nanostructure. The method also includes forming a sidewall passivation layer in the source and drain first trenches over the sidewalls of the plurality of first nanostructures, and depositing a second semiconductor layer in the source and drain first trenches over the first semiconductor layer so that the second semiconductor layer covers the sidewall passivation layer of the first nanostructure at the sidewalls of the source and drain first trenches.

[0097] In one embodiment, a top passivation layer is formed over the first semiconductor layer, the method further comprising: removing the top passivation layer from over the first semiconductor layer before depositing the second semiconductor layer. In one embodiment, a first fin is formed over a semiconductor substrate, the method further comprising: forming source and drain second trenches in a second fin formed over the semiconductor substrate, wherein the second fin comprises a plurality of first nanostructures and a plurality of second nanostructures alternately formed over each other, depositing a third semiconductor layer at a bottom portion of the source and drain second trenches, wherein the third semiconductor layer extends to the bottommost nanostructure, forming a sidewall passivation layer over the sidewalls of the plurality of first nanostructures in the source and drain second trenches, and depositing a fourth semiconductor layer in the source and drain second trenches over the third semiconductor layer, the fourth semiconductor layer covering the sidewall passivation layer of zero or more first nanostructures at the sidewalls of the source and drain second trenches. In one embodiment, the method further comprises directing a nitrogen plasma to the sidewalls of the plurality of nanostructures in the source and drain trenches to form a sidewall passivation layer comprising crystalline silicon nitride. The sidewall passivation layer has a rectangular shape covering at least the sidewalls of the plurality of first nanostructures and has a thickness between 1 nm and 3 nm. In one embodiment, the method further includes removing the sidewall passivation layer over the sidewalls of a group of the plurality of first nanostructures not covered by the second semiconductor layer, and epitaxially growing source and drain regions over the second semiconductor layer, wherein the source and drain regions are electrically connected to the first nanostructures not covered by the second semiconductor layer. In addition, the third semiconductor layer has a thickness of about 10 nm. 15 cm -3 The n-type doping concentration of the second semiconductor layer is about 10 16 cm -3 The n-type doping concentration of the source and drain regions is about 10 20 cm -3 In one embodiment, the second semiconductor layer covers the sidewall passivation layer of one or more additional first nanostructures, and the epitaxially grown source and drain regions are in electrical contact with the first nanostructures not covered by the second semiconductor layer. In one embodiment, the second semiconductor layer covers the sidewall passivation layer of two or more first nanostructures at the sidewalls of the source and drain trenches, and the source and drain regions are not electrically connected to the two or more first nanostructures covered by the second semiconductor layer.

[0098] According to an embodiment, a method includes forming a source / drain trench in a semiconductor fin, wherein the semiconductor fin includes a plurality of first nanostructures and a plurality of second nanostructures formed alternately on top of each other. The method also includes depositing a first SiGe layer at a bottom portion of the source / drain trench, wherein the first SiGe layer extends to a bottommost nanostructure and forms a sidewall passivation layer over sidewalls of the plurality of first nanostructures in the source / drain trench. The method also includes depositing a second SiGe layer in the source / drain trench over the first SiGe layer, wherein the second SiGe layer covers the sidewall passivation layer of one or more first nanostructures at the sidewalls of the source / drain trench.

[0099] In one embodiment, a semiconductor fin is formed above a semiconductor substrate, and a source / drain trench extends into the semiconductor substrate. In one embodiment, a top passivation layer is formed above a first SiGe layer, and the method further comprises: removing the top passivation layer from above the first SiGe layer before depositing the second SiGe layer. In one embodiment, before depositing the first SiGe layer, an internal spacer is formed on the sidewalls of a plurality of second nanostructures in the source / drain trench. In one embodiment, the method further comprises directing one of nitrogen plasma, silicon plasma, carbon plasma, or oxygen plasma to the sidewalls of a plurality of first nanostructures in the source / drain trench to form a sidewall passivation layer. The passivation layer is formed at a temperature between 300 degrees Celsius and 700 degrees Celsius. In one embodiment, the sidewall passivation layer covering the sidewalls of the plurality of first nanostructures is recessed by about 10 nm. In one embodiment, the first nanostructure is a gate channel, and the method further comprises epitaxially growing source and drain regions above the second SiGe layer in the source / drain trench, and replacing the second nanostructure with a gate structure.

[0100] According to an embodiment, a semiconductor device includes a first semiconductor fin above a semiconductor substrate, wherein the first semiconductor fin includes a plurality of first nanostructures. The semiconductor device also includes a gate electrode surrounding each of the plurality of first nanostructures and a source and drain region in the first semiconductor fin, wherein each of the source and drain regions includes: a first semiconductor layer, wherein the first semiconductor layer covers at least one of the plurality of first nanostructures and a sidewall passivation layer on a sidewall of the at least one of the plurality of first nanostructures. The sidewall passivation layer is between the first semiconductor layer and the at least one of the plurality of first nanostructures.

[0101] In one embodiment, each of the source and drain regions further comprises a terrace above the semiconductor substrate, wherein the first semiconductor fin is above the terrace and the terrace comprises SiGe. In one embodiment, the plurality of first nanostructures comprises up to 6 first nanostructures, wherein up to 2 first nanostructures comprise a sidewall passivation layer and are covered by the first semiconductor layer. In one embodiment, the first nanostructure comprises a semiconductor gate channel. In one embodiment, the sidewall passivation layer comprises one or more of silicon nitride, silicon dioxide, amorphous silicon, or silicon carbide. In one embodiment, the plurality of first nanostructures of the first semiconductor fin is an n-type semiconductor, and the semiconductor device further comprises: a second semiconductor fin comprising a plurality of second nanostructures as a p-type semiconductor, wherein none of the first nanostructures of the first semiconductor fin comprises a sidewall passivation layer, and at least one second nanostructure of the second semiconductor fin comprises a sidewall passivation layer.

[0102] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications to the present disclosure without departing from the spirit and scope of the present disclosure.

[0103] Example 1 is a method for forming a semiconductor device, comprising: forming source and drain first trenches in a first fin, wherein the first fin includes a plurality of first nanostructures and a plurality of second nanostructures alternately formed on each other; forming internal spacers on the sidewalls of the plurality of second nanostructures; depositing a first semiconductor layer at the bottom portion of the source and drain first trenches, wherein the first semiconductor layer extends to the bottommost nanostructure; forming a sidewall passivation layer in the source and drain first trenches over the sidewalls of the plurality of first nanostructures; and depositing a second semiconductor layer in the source and drain first trenches over the first semiconductor layer, wherein the second semiconductor layer covers the sidewall passivation layer of the first nanostructure at the sidewalls of the source and drain first trenches.

[0104] Example 2 is the method of Example 1, wherein a top passivation layer is formed over the first semiconductor layer, the method further comprising: before depositing the second semiconductor layer, removing the top passivation layer from over the first semiconductor layer.

[0105] Example 3 is the method described in Example 1, wherein the first fin is formed on a semiconductor substrate, and the method further includes: forming source and drain second trenches in a second fin formed on the semiconductor substrate, wherein the second fin includes a plurality of first nanostructures and a plurality of second nanostructures alternately formed on each other; depositing a third semiconductor layer on the bottom portion of the source and drain second trenches, wherein the third semiconductor layer extends to the bottommost nanostructure; forming a sidewall passivation layer on the sidewalls of the plurality of first nanostructures in the source and drain second trenches; and depositing a fourth semiconductor layer in the source and drain second trenches on the third semiconductor layer, wherein the fourth semiconductor layer covers the sidewall passivation layers of zero or more first nanostructures at the sidewalls of the source and drain second trenches.

[0106] Example 4 is the method described in Example 3, further comprising: removing a sidewall passivation layer on a sidewall of a group of the plurality of first nanostructures not covered by the second semiconductor layer; and epitaxially growing a source and a drain region on the second semiconductor layer, wherein the source and the drain region are electrically connected to the first nanostructures not covered by the second semiconductor layer, wherein: the third semiconductor layer has about 10 15 cm -3 The n-type doping concentration of the second semiconductor layer is about 10 16 cm -3 The n-type doping concentration of the source and drain regions has about 10 20 cm -3 The n-type doping concentration.

[0107] Example 5 is the method described in Example 1, further comprising: directing nitrogen plasma to the sidewalls of the multiple first nanostructures in the source and drain first trenches to form a sidewall passivation layer comprising crystalline silicon nitride, wherein the sidewall passivation layer has a rectangular shape that at least covers the sidewalls of the multiple first nanostructures and has a thickness between 1 nm and 3 nm.

[0108] Example 6 is the method of Example 5, wherein the second semiconductor layer covers the sidewall passivation layer of one or more additional first nanostructures, and wherein the epitaxially grown source and drain regions are in electrical contact with the first nanostructures not covered by the second semiconductor layer.

[0109] Example 7 is the method described in Example 6, wherein the second semiconductor layer covers a sidewall passivation layer of two or more first nanostructures at the sidewalls of the source and drain first grooves, and wherein the source and drain regions are not electrically connected to the two or more first nanostructures covered by the second semiconductor layer.

[0110] Example 8 is a method for forming a semiconductor device, comprising: forming a source / drain trench in a semiconductor fin, wherein the semiconductor fin includes a plurality of first nanostructures and a plurality of second nanostructures alternately formed on each other; depositing a first SiGe layer at a bottom portion of the source / drain trench, wherein the first SiGe layer extends to a bottommost nanostructure; forming a sidewall passivation layer in the source / drain trench over the sidewalls of the plurality of first nanostructures; and depositing a second SiGe layer in the source / drain trench over the first SiGe layer, wherein the second SiGe layer covers the sidewall passivation layer of one or more first nanostructures at the sidewalls of the source / drain trench.

[0111] Example 9 is the method of Example 8, wherein the semiconductor fin is formed over a semiconductor substrate, and wherein the source / drain trenches extend into the semiconductor substrate.

[0112] Example 10 is the method of Example 8, wherein a top passivation layer is formed over the first SiGe layer, the method further comprising: before depositing the second SiGe layer, removing the top passivation layer from over the first SiGe layer.

[0113] Example 11 is the method of Example 8, wherein internal spacers are formed on sidewalls of the plurality of second nanostructures in the source / drain trenches before depositing the first SiGe layer.

[0114] Example 12 is the method described in Example 8, further comprising: directing one of nitrogen plasma, silicon plasma, carbon plasma or oxygen plasma to the sidewalls of the multiple first nanostructures in the source / drain trenches to form the sidewall passivation layer, wherein the passivation layer is formed at a temperature between 300 degrees Celsius and 700 degrees Celsius.

[0115] Example 13 is the method of Example 8, wherein the sidewall passivation layer covering the sidewalls of the plurality of first nanostructures is recessed by about 10 nm.

[0116] Example 14 is the method described in Example 8, wherein the first nanostructure is a gate channel, and the method further includes: epitaxially growing source and drain regions above the second SiGe layer in the source / drain trench, and replacing the second nanostructure with a gate structure.

[0117] Example 15 is a semiconductor device comprising: a first semiconductor fin on a semiconductor substrate, wherein the first semiconductor fin includes a plurality of first nanostructures; a gate electrode surrounding each of the plurality of first nanostructures; source and drain regions in the first semiconductor fin, wherein each of the source and drain regions includes: a first semiconductor layer, wherein the first semiconductor layer covers at least one of the plurality of first nanostructures; and a sidewall passivation layer on a sidewall of the at least one of the plurality of first nanostructures, wherein the sidewall passivation layer is between the first semiconductor layer and the at least one of the plurality of first nanostructures.

[0118] Example 16 is the semiconductor device of Example 15, wherein each of the source and drain regions further includes: a terrace above the semiconductor substrate, wherein the first semiconductor fin is above the terrace, wherein the terrace includes SiGe.

[0119] Example 17 is the semiconductor device of Example 15, wherein the plurality of first nanostructures includes up to 6 first nanostructures, and wherein up to 2 first nanostructures include the sidewall passivation layer and are covered by the first semiconductor layer.

[0120] Example 18 is the semiconductor device of Example 15, wherein the first nanostructure includes a semiconductor gate channel.

[0121] Example 19 is the semiconductor device of Example 15, wherein the sidewall passivation layer includes one or more of silicon nitride, silicon dioxide, amorphous silicon, or silicon carbide.

[0122] Example 20 is the semiconductor device described in Example 15, wherein the multiple first nanostructures of the first semiconductor fin are n-type semiconductors, and the semiconductor device also includes: a second semiconductor fin, the second semiconductor fin including multiple second nanostructures that are p-type semiconductors, wherein none of the first nanostructures of the first semiconductor fin includes the sidewall passivation layer, and wherein at least one second nanostructure of the second semiconductor fin includes the sidewall passivation layer.

Claims

1. A method for forming a semiconductor device, comprising: forming source and drain first trenches in a first fin, wherein the first fin includes a plurality of first nanostructures and a plurality of second nanostructures alternately formed on top of each other; forming inner spacers on sidewalls of the plurality of second nanostructures; Depositing a first semiconductor layer at the bottom portion of the source and drain first trenches, wherein the first semiconductor layer extends to the bottommost nanostructure; forming a sidewall passivation layer on sidewalls of the plurality of first nanostructures in the source and drain first trenches; and A second semiconductor layer is deposited in the source and drain first trenches over the first semiconductor layer, wherein the second semiconductor layer covers the sidewall passivation layer of the first nanostructure at the sidewalls of the source and drain first trenches.

2. The method of claim 1, wherein: A top passivation layer is formed on the first semiconductor layer, the method further comprising: Prior to depositing the second semiconductor layer, the top passivation layer is removed from over the first semiconductor layer.

3. The method of claim 1, wherein: The first fin is formed on a semiconductor substrate, and the method further includes: forming source and drain second trenches in a second fin formed on the semiconductor substrate, wherein the second fin includes a plurality of first nanostructures and a plurality of second nanostructures alternately formed on each other; Depositing a third semiconductor layer at the bottom portion of the second trenches for the source and drain electrodes, wherein the third semiconductor layer extends to the bottommost nanostructure; forming a sidewall passivation layer on sidewalls of the plurality of first nanostructures in the source and drain second trenches; and A fourth semiconductor layer is deposited in the source and drain second trenches over the third semiconductor layer, wherein the fourth semiconductor layer covers zero or more first nanostructured sidewall passivation layers at sidewalls of the source and drain second trenches.

4. The method of claim 3, further comprising: removing a sidewall passivation layer on sidewalls of a group of the plurality of first nanostructures not covered by the second semiconductor layer; and A source and a drain region are epitaxially grown on the second semiconductor layer, wherein the source and the drain region are electrically connected to the first nanostructure not covered by the second semiconductor layer, wherein: the third semiconductor layer has 10 15 cm -3 The n-type doping concentration of the second semiconductor layer is 10 16 cm -3 The n-type doping concentration of the source and drain regions has 10 20 cm -3 The n-type doping concentration.

5. The method of claim 1, further comprising: Directing nitrogen plasma to sidewalls of the plurality of first nanostructures in the source and drain first trenches to form a sidewall passivation layer comprising crystalline silicon nitride, wherein the sidewall passivation layer has a rectangular shape covering at least the sidewalls of the plurality of first nanostructures and has a thickness between 1 nm and 3 nm.

6. The method of claim 5, wherein: The second semiconductor layer covers the sidewall passivation layer of one or more additional first nanostructures, and wherein the epitaxially grown source and drain regions are in electrical contact with the first nanostructures not covered by the second semiconductor layer.

7. The method of claim 6, wherein: The second semiconductor layer covers the sidewall passivation layer of the two or more first nanostructures at the sidewalls of the source and drain first trenches, and wherein the source and drain regions are not electrically connected to the two or more first nanostructures covered by the second semiconductor layer.

8. A method of forming a semiconductor device, comprising: forming source / drain trenches in a semiconductor fin, wherein the semiconductor fin comprises a plurality of first nanostructures and a plurality of second nanostructures alternately formed on top of each other; Depositing a first SiGe layer on a bottom portion of the source / drain trench, wherein the first SiGe layer extends to the bottommost nanostructure; forming a sidewall passivation layer in the source / drain trench over sidewalls of the plurality of first nanostructures; and A second SiGe layer is deposited in the source / drain trench over the first SiGe layer, wherein the second SiGe layer covers a sidewall passivation layer of one or more first nanostructures at a sidewall of the source / drain trench.

9. The method of claim 8, wherein: The semiconductor fin is formed over a semiconductor substrate, and wherein the source / drain trenches extend into the semiconductor substrate.

10. A semiconductor device comprising: A first semiconductor fin on the semiconductor substrate, wherein the first semiconductor fin comprises a plurality of first nanostructures; a gate electrode surrounding each of the plurality of first nanostructures; source and drain regions in the first semiconductor fin, wherein each of the source and drain regions comprises: A first semiconductor layer, wherein the first semiconductor layer covers at least one of the plurality of first nanostructures; and A sidewall passivation layer is formed on a sidewall of the at least one of the plurality of first nanostructures, wherein the sidewall passivation layer is between the first semiconductor layer and the at least one of the plurality of first nanostructures.

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