Preparation method of semiconductor structure and semiconductor structure

Abstract

The invention provides a preparation method of a semiconductor structure and the semiconductor structure, and the preparation method comprises the following steps: providing a substrate which comprises a substrate, a plurality of polycrystalline silicon grids on the substrate, and side walls located at the two sides of the polycrystalline silicon grids; etching the side walls on the two sides of the polycrystalline silicon gate so as to reduce the height and the thickness of the side walls on the two sides; and forming an interlayer dielectric layer covering the top of the polycrystalline silicon gate and the side wall. According to the preparation method of the semiconductor structure, before the interlayer dielectric layer is deposited, the thickness of the side walls of the adjacent polycrystalline silicon grids is reduced, so that the gap between the polycrystalline silicon grids is increased, the depth-to-width ratio of the gap is reduced, cavities formed in the subsequent interlayer dielectric layer deposition process are reduced or eliminated, and the performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the technical field related to semiconductor devices, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Art

[0002] As the critical dimension CD (Critical Dimension) of semiconductor devices continues to shrink, the density of polysilicon gates continues to increase. Voids are easily present between polysilicon gates after the inter-layer dielectric (ILD) process. When the contact hole CT is subsequently formed, Ti, TiN, and W will be connected through these voids, resulting in an increase in the leakage current of the semiconductor device, affecting the performance and reliability of the device. Usually, after the self-aligned silicide barrier (SAB) process, the metal silicide process is directly performed, and then the inter-layer dielectric layer ILD is further deposited. When the aspect ratio of the gap between the polysilicon gates reaches a certain level, voids will appear. How to improve the quality of the inter-layer dielectric layer of semiconductor devices and thus improve device performance has become a technical problem that needs to be solved urgently.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to those skilled in the art. Summary of the invention

[0004] In view of the problems in the prior art, the purpose of the present invention is to provide a method for preparing a semiconductor structure and a semiconductor structure. The preparation method increases the gap between polysilicon gates through an etching process before depositing an interlayer dielectric layer, thereby improving the quality of the interlayer dielectric layer filled in the gap and the performance of the semiconductor device.

[0005] Specifically, a first aspect of the present invention provides a method for preparing a semiconductor structure, the method comprising the following steps:

[0006] Providing a substrate, the substrate comprising a substrate, a plurality of polysilicon gates on the substrate, and sidewalls located on both sides of the polysilicon gates;

[0007] Etching the sidewalls on both sides of the polysilicon gate so as to reduce the height and thickness of the sidewalls on both sides;

[0008] An interlayer dielectric layer is formed to cover the top of the polysilicon gate and the sidewall.

[0009] According to the first aspect of the present invention, before the step of etching the sidewalls on both sides of the polysilicon gate, the preparation method further includes the following steps:

[0010] A metal silicide layer is formed on top of the polysilicon gate.

[0011] According to the first aspect of the present invention, after the step of etching the sidewalls on both sides of the polysilicon gate, the preparation method further comprises the following steps:

[0012] A metal silicide layer is formed on top of the polysilicon gate.

[0013] According to the first aspect of the present invention, the metal silicide layer is one or more layers of a nickel silicon compound layer, a titanium silicon compound layer and a platinum silicon compound layer.

[0014] According to the first aspect of the present invention, the sidewall spacer is a silicon nitride sidewall spacer;

[0015] Etching the sidewalls on both sides of the polysilicon gate using a wet etching process;

[0016] The etching solution used in the wet etching process is a phosphoric acid solution.

[0017] According to the first aspect of the present invention, the interlayer dielectric layer includes one or more dielectric layers.

[0018] According to the first aspect of the present invention, the interlayer dielectric layer is a silicon oxide layer or a silicon nitride layer.

[0019] According to the first aspect of the present invention, adjacent sidewalls of two adjacent polysilicon gates form a gap, and the aspect ratio of the gap is greater than or equal to 15.

[0020] According to the first aspect of the present invention, after the step of etching the side walls on both sides of the polysilicon gate to reduce the height and thickness of the side walls on both sides, the height difference between the top of the polysilicon gate and the side walls on both sides is h, and the height difference h is between 100 and 300 angstroms.

[0021] A second aspect of the present invention provides a semiconductor structure, which is obtained by using the semiconductor structure preparation method.

[0022] Compared with the prior art, in the method for preparing a semiconductor structure of the present invention, before depositing an interlayer dielectric layer, the thickness of the side walls of adjacent polysilicon gates is reduced, thereby increasing the gap between the polysilicon gates and reducing the aspect ratio of the gap, thereby reducing or eliminating the formation of voids during the subsequent deposition of the interlayer dielectric layer and improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. By reading the detailed description of the non-limiting embodiments with reference to the following drawings, other features, purposes and advantages of the present invention will become more apparent. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings without creative work. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same figure numbers in the figures represent the same or similar parts, and their repeated descriptions will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities.

[0024] Figure 1 A schematic structural diagram of a method for preparing a semiconductor structure according to an embodiment of the present invention;

[0025] Figures 2 to 6 A schematic diagram of the structure of the semiconductor structure after each step of the preparation method of the first embodiment of the present invention; and

[0026] Figures 7 and 8 It is a schematic structural diagram of a semiconductor structure after each step of the preparation method of the second embodiment of the present invention. DETAILED DESCRIPTION

[0027] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in the present invention. The present invention can also be implemented or applied through other different specific embodiments, and the details in the present invention can also be modified or changed according to different viewpoints and application systems without departing from the spirit of the present invention. It should be noted that the embodiments and features in the embodiments of the present invention can be combined with each other without conflict.

[0028] The following is a detailed description of the embodiments of the present invention with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. The present invention can be embodied in many different forms and is not limited to the embodiments described herein.

[0029] In the representation of the present invention, the reference terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" etc. mean that the specific features, structures, materials or characteristics represented in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. Moreover, the specific features, structures, materials or characteristics represented may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples represented in the present invention and the features of different embodiments or examples, unless they are contradictory.

[0030] In order to clearly describe the present invention, components not related to the description are omitted, and the same reference numerals are given to the same or similar components throughout the specification.

[0031] Throughout the specification, when a device is said to be "connected" to another device, this includes not only the case of "direct connection" but also the case of "indirect connection" by placing other elements therebetween. In addition, when a device is said to "include" a certain component, unless otherwise stated, it does not exclude other components, but means that other components may be included.

[0032] When a device is said to be "on" another device, it may be directly on the other device, but there may also be other devices between it. In contrast, when a device is said to be "directly" on another device, there are no other devices between it.

[0033] Although the terms first, second, etc. are used to represent various elements in some examples, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first interface and the second interface, etc. are represented. Moreover, as used in this article, the singular forms "one", "one" and "the" are intended to also include plural forms, unless there is an opposite indication in the context. It should be further understood that the terms "comprising" and "including" indicate the existence of features, steps, operations, elements, components, projects, kinds, and / or groups, but do not exclude the existence, occurrence or addition of one or more other features, steps, operations, elements, components, projects, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Only when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way, will there be an exception to this definition.

[0034] The technical terms used herein are only used to refer to specific embodiments and are not intended to limit the present invention. The singular form used herein also includes the plural form as long as the sentence does not clearly indicate the opposite meaning. The meaning of "including" used in the specification is to specify specific characteristics, regions, integers, steps, operations, elements and / or components, and does not exclude the existence or addition of other characteristics, regions, integers, steps, operations, elements and / or components.

[0035] Although not defined differently, all terms, including technical and scientific terms used herein, have the same meaning as those generally understood by those skilled in the art to which the present invention belongs. Terms defined in commonly used dictionaries are additionally interpreted as having meanings consistent with the content of relevant technical literature and current disclosures, and unless defined, shall not be overly interpreted as ideal or very formal meanings.

[0036] As the process node gradually decreases and the device size becomes smaller, the gap between the polysilicon gates also gradually decreases to produce a larger aspect ratio. As a result, the filling of the interlayer dielectric layer ILD becomes more difficult. The filling of the interlayer dielectric layer of different chemical vapor deposition CVD has its process limit. When the aspect ratio exceeds its limit, voids in the interlayer dielectric layer will be generated. In order to overcome the above technical problems, the present invention provides a method for preparing a semiconductor structure and a semiconductor structure, the preparation method comprising the following steps: providing a substrate, the substrate comprising a substrate, a plurality of polysilicon gates on the substrate, and side walls on both sides of the polysilicon gate, the side walls exposing the top of the polysilicon gate; etching the side walls on both sides of the polysilicon gate so that the top of the polysilicon gate is higher than the height of the side walls on both sides; forming an interlayer dielectric layer covering the top of the polysilicon gate and the side walls. In the method for preparing the semiconductor structure of the present invention, before depositing the interlayer dielectric layer, the thickness of the side walls of adjacent polysilicon gates is reduced, thereby increasing the gap between the polysilicon gates and reducing the aspect ratio of the gap, thereby reducing or eliminating the formation of voids during the subsequent deposition of the interlayer dielectric layer and improving the performance of the semiconductor structure.

[0037] The preparation method of the semiconductor structure and the semiconductor structure of the present invention are further described below in conjunction with the accompanying drawings and specific embodiments. It can be understood that the various specific embodiments are not intended to limit the protection scope of the present invention.

[0038] Figure 1 The structure diagram of a method for preparing a semiconductor structure according to an embodiment of the present invention is shown in FIG. 1 . Specifically, the method for preparing a semiconductor structure includes the following steps:

[0039] Step S100: Provide a substrate, the substrate comprising a substrate 1, a plurality of polysilicon gates 2 on the substrate 1, and sidewalls 3 located on both sides of the polysilicon gates 2. In some embodiments, an offset spacer 31 is further disposed between the polysilicon gates 2 and the sidewalls 3 on both sides, see Figure 2 . The substrate 1 can be made of semiconductor material, insulating material, conductive material or any combination of their material types. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for example, the substrate 1 can be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon on insulator (SOI) or a silicon germanium on insulator, etc.

[0040] Taking the substrate 1 as a silicon substrate as an example, an active region (not shown in the figure) is formed on one surface of the substrate 1, and the polysilicon gate 2 spans the active region. The active regions on both sides of the polysilicon gate 2 are doped to form source doping regions and drain doping regions, respectively. In some semiconductor structures, a silicon oxide / silicon nitride / silicon oxide (O / N / O) layer is formed on the substrate 1. The polysilicon gate is formed on the silicon oxide / silicon nitride / silicon oxide (O / N / O) layer. The source doping region, the drain doping region and the polysilicon gate can form a metal oxide semiconductor field effect transistor (MOSFET) semiconductor device.

[0041] The sidewalls 3 on both sides of the polysilicon gate 2 are insulating spacers between the polysilicon gates. In an embodiment, the sidewalls 3 may be silicon nitride sidewalls. The sidewalls 3 may be obtained by multiple deposition processes and subsequent patterned etching after obtaining the polysilicon gate 2. Generally, since the etching speed from the top to the bottom of the polysilicon gate 2 gradually decreases, during the etching process, the sidewalls present a tapered structure with a narrow top and a relatively wide bottom, and the adjacent sidewalls of the two adjacent polysilicon gates form a gap, such as Figure 1 As shown, at the same time, the sidewall 3 exposes the top of the polysilicon gate 2. The polysilicon gate has different functions in different semiconductor structures, and it can be a control gate or a storage gate of a memory, etc. Therefore, the structure of the polysilicon gate 2, such as the width and height of the polysilicon gate and the gap between adjacent polysilicon gates, can be set according to the target performance of the semiconductor structure, etc.

[0042] For example, the distance between two adjacent polysilicon gates of a semiconductor structure is ~105nm, the height of the polysilicon gate is ~700nm, the thickness of the sidewall of the polysilicon gate close to the substrate surface is between 25 and 35nm, and accordingly, the gap between the two adjacent sidewalls close to the substrate surface is 35 to 55nm, that is, the aspect ratio of the gap formed between the two adjacent sidewalls is 12 to 20. The existing high aspect ratio process (High Aspect Ratio Process, HARP) will still have the problem of voids in the gap filling interlayer dielectric layer of the above semiconductor structure. The preparation method disclosed in the present invention will reduce the aspect ratio of the gap between the two adjacent sidewalls of the above semiconductor structure in the subsequent steps, thereby improving the quality of filling the upper interlayer dielectric layer. That is, preferably, the preparation method disclosed in the present invention is more suitable for semiconductor structures in which the aspect ratio of the gap formed between the two adjacent sidewalls is greater than or equal to 15.

[0043] Step S200: etching the sidewalls 3 on both sides of the polysilicon gate 2 so as to reduce the height and thickness of the sidewalls 3A on both sides. Figure 3 , due to the reduction in the height of the sidewalls 3A on both sides, the top of the polysilicon gate 2 is higher than the height of the sidewalls 3A on both sides; usually, the sidewalls 3 are prepared after obtaining the semiconductor structure with the polysilicon gate 2. After obtaining the polysilicon gate structure with the sidewalls, different target semiconductor structures may also include other semiconductor processes, such as ion implantation to prepare the active area. The step S200 here refers to the step performed after the polysilicon gate structure with the sidewalls is obtained and the subsequent multiple processes are completed. The reason why the top of the polysilicon gate 2 is not directly obtained to be higher than the height of the sidewalls 3A on both sides when the sidewalls 3 are obtained by the etching process is that the above-mentioned subsequent processes will affect the performance of the top of the exposed polysilicon gate 2.

[0044] The etching process of step S200 can be a wet etching process. When the side wall 3 is a silicon nitride side wall, the etching solution used in the wet etching process is a phosphoric acid solution. Wet etching is to immerse the silicon nitride sample in a corrosive solution containing phosphoric acid, and by controlling the temperature, concentration and etching time of the etching solution, phosphoric acid and silicon nitride react to achieve the purpose of etching. The mass concentration of the phosphoric acid solution can be between 50% and 85%. When using a phosphoric acid solution for etching, the etching rate can be increased by increasing the acid content or raising the temperature of the etching solution, that is, the mass concentration of the phosphoric acid solution and other parameters of the etching process can be determined according to the etching rate to be obtained. Wet etching has the advantages of fast etching speed and uniform etching depth. Cleaning treatment is required after etching to avoid residues affecting subsequent processes.

[0045] Because the phosphoric acid etching solution is used to etch silicon nitride materials, during the wet etching of the sidewalls, a certain thickness of the surface of the tapered structure sidewalls with a narrower top and a relatively wider bottom is etched, and the height of the polysilicon gate 2 remains almost unchanged, so that the top of the polysilicon gate 2 is higher than the height of the sidewalls 3A on both sides. Preferably, the height difference between the top of the polysilicon gate 2 and the sidewalls 3A on both sides in step S200 is h, and h is between 100 angstroms and 300 angstroms. For example, the height difference h can be 100 angstroms, 150 angstroms, 200 angstroms, 250 angstroms or 300 angstroms, etc. Since the wet etching process has a uniform etching depth, that is, in step S200, the side walls 3A on both sides are etched for the entire surface in contact with the etching solution. Therefore, in the process of decreasing the height of the side walls 3A on both sides, the thickness of the side walls 3A also decreases. Correspondingly, the gap between the two adjacent side walls 3A near the substrate surface after step S200 increases by 200 to 600 angstroms. Still taking the height of the polysilicon gate as ~700nm and the gap between the two adjacent side walls near the substrate surface as 35 to 55nm, for example, the gap between the two adjacent side walls near the substrate surface after step S200 is between 55 and 175nm, that is, the depth-to-width ratio of the gap formed between the two adjacent side walls after step S200 is much smaller than that before step S200.

[0046] In order to reduce the square resistance of the polysilicon gate and the active area, metal silicide process technology has been developed and widely used in semiconductor process. In the actual process, before or after the step of etching the sidewalls on both sides of the polysilicon gate in step 200, the preparation method further includes the following steps:

[0047] S900: forming a metal silicide layer on the top of the polysilicon gate. In some embodiments, in order to reduce the series resistance and contact resistance of the active region, it is also necessary to form a metal silicide layer on the active region.

[0048] exist Figure 3 and Figure 4 In the embodiment, step S900 is performed after step S200, and the metal silicide layer 2A is formed on the top of the polysilicon gate 2 by using the Silicide process. This technology uses the metal (Ti, Co, Ni, Pt, etc.) deposited on the semiconductor device to react with the silicon of the active area or polysilicon gate 2 in direct contact to form the metal silicide layer 2A. The metal will not react with the dielectric materials such as SiO2, Si3N4 and SiON in contact, that is, Silicide can be well aligned with the active area and the polysilicon gate, and Silicide is formed on the active area and the polysilicon gate at the same time. The metal silicide layer can be one or more layers of a nickel silicon compound layer, a titanium silicon compound layer, and a platinum silicon compound layer. Through step S900, the conductivity of the polysilicon gate can be improved, and the performance of the device can be improved.

[0049] After executing step S200, step S300 is executed: forming an interlayer dielectric layer covering the top of the polysilicon gate 2 and the sidewall 3A. The interlayer dielectric layer includes one or more dielectric layers, and the interlayer dielectric layer is a silicon oxide layer or a silicon nitride layer. Figure 5 and Figure 6 In the implementation of the present invention, the interlayer dielectric layer includes a silicon nitride layer 51 and a silicon oxide layer 52 .

[0050] exist Figure 7 and Figure 8 In the embodiment, a metal silicide layer 2B is formed on the top of the polysilicon gate 2 in step S900 before etching the sidewalls 3 on both sides of the polysilicon gate 2 in step S200. Similarly, in step S900, a metal silicide layer can be formed in the active area and the polysilicon gate 2 through a Silicide process. In the subsequent step S200, a portion of the sidewall 3 is etched to form a sidewall 3B having a height and a thickness smaller than the sidewall 3, which will not be described in detail here.

[0051] The present invention also provides a semiconductor structure, which is obtained by the semiconductor structure preparation method. Since the gap between polysilicon gates is increased by an etching process before depositing the interlayer dielectric layer, the interlayer dielectric layer obtained thereafter has fewer voids and the performance of the semiconductor device is better.

[0052] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

[0053] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The preparation method comprises the following steps: Providing a substrate, the substrate comprising a substrate, a plurality of polysilicon gates on the substrate, and sidewalls located on both sides of the polysilicon gates; Etching the sidewalls on both sides of the polysilicon gate so as to reduce the height and thickness of the sidewalls on both sides; An interlayer dielectric layer is formed to cover the top of the polysilicon gate and the sidewall.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: Before the step of etching the sidewalls on both sides of the polysilicon gate, the preparation method further includes the following steps: A metal silicide layer is formed on top of the polysilicon gate.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that: After the step of etching the sidewalls on both sides of the polysilicon gate, the preparation method further comprises the following steps: A metal silicide layer is formed on top of the polysilicon gate.

4. The method for preparing a semiconductor structure according to claim 2 or 3, characterized in that: The metal silicide layer is one or more layers of a nickel silicon compound layer, a titanium silicon compound layer and a platinum silicon compound layer.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that: The sidewall is a silicon nitride sidewall; Etching the sidewalls on both sides of the polysilicon gate using a wet etching process; The etching solution used in the wet etching process is a phosphoric acid solution.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that: The interlayer dielectric layer includes one or more dielectric layers.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that: The interlayer dielectric layer is a silicon oxide layer or a silicon nitride layer.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that: Adjacent sidewalls of two adjacent polysilicon gates form a gap, and the aspect ratio of the gap is greater than or equal to 15.

9. The method for preparing a semiconductor structure according to claim 1, characterized in that: After the step of etching the side walls on both sides of the polysilicon gate to reduce the height and thickness of the side walls on both sides, the height difference between the top of the polysilicon gate and the side walls on both sides is h, and the height difference h is between 100 angstroms and 300 angstroms.

10. A semiconductor structure, characterized in that: The semiconductor structure is obtained by using the semiconductor structure preparation method described in any one of claims 1 to 9.

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