Semiconductor element

Abstract

The invention discloses a semiconductor element, which mainly comprises a substrate, a medium-voltage element and an OTP capacitor, wherein the substrate is provided with a medium-voltage region and an OTP capacitor region, the medium-voltage element is arranged in the medium-voltage region, and the OTP capacitor is arranged in the OTP capacitor region. Wherein the medium-voltage element comprises a first gate dielectric layer arranged on the substrate, a first gate electrode arranged on the first gate dielectric layer and a shallow trench isolation arranged on two sides of the first gate electrode; the OTP capacitor includes a fin structure disposed on the substrate, a doped region disposed in the fin structure, a second gate dielectric layer disposed on the doped region, and a second gate electrode disposed on the second gate dielectric layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor element, and more particularly to a semiconductor element integrating a medium voltage element and a one-time programmable (OTP) capacitor. Background Art

[0002] Semiconductor memory devices have been widely used in various electronic devices. For example, non-volatile memory is widely used in mobile phones, digital cameras, personal digital assistants, mobile computing devices, and other applications. Generally speaking, non-volatile memory mainly includes multi-time programmable (MTP) memory and one-time programmable (OTP) memory. Compared with rewritable memory, one-time programmable memory has the advantages of lower manufacturing cost and less loss of stored data. However, one-time programmable memory can only perform one-time data burning. Once the bits of specific storage cells in a specified storage block are rewritten through a one-time data writing program, those specific storage cells in the specified storage block cannot be burned again.

[0003] Since the existing one-time programmable memory devices still have disadvantages such as weak read current in read mode and long stress time in program mode, how to improve the existing one-time programmable memory device architecture to solve the above problems is an important issue nowadays. Summary of the invention

[0004] One embodiment of the present invention discloses a semiconductor device, which mainly includes a substrate having a medium voltage region and an OTP capacitor region, a medium voltage device disposed in the medium voltage region and an OTP capacitor disposed in the OTP capacitor region. The medium voltage device includes a first gate dielectric layer disposed on the substrate, a first gate electrode disposed on the first gate dielectric layer and a shallow trench isolation disposed on both sides of the first gate electrode. The OTP capacitor includes a fin structure disposed on the substrate, a doped region disposed in the fin structure, a second gate dielectric layer disposed on the doped region and a second gate electrode disposed on the second gate dielectric layer.

[0005] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a substrate having a medium voltage region, an OTP capacitor region and a core region, a medium voltage device disposed in the medium voltage region, an OTP capacitor disposed in the OTP capacitor region and a metal oxide semiconductor transistor disposed in the core region. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figures 1 to 11 A schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0007] Fig.12 FIG. 1 is an overall layout diagram of a semiconductor device according to an embodiment of the present invention.

[0008] Explanation of symbols

[0009] 12: Base

[0010] 14: High pressure area

[0011] 16: Medium pressure area

[0012] 18:I / O area

[0013] 20: Core Area

[0014] 22: OTP capacitor area

[0015] 24: Base

[0016] 26: Fin structure

[0017] 28: cushion layer

[0018] 30: Hard mask

[0019] 32: Shallow Trench Isolation

[0020] 34: Doping area

[0021] 36: Gate dielectric layer

[0022] 38: Lightly doped drain

[0023] 40: Gate dielectric layer

[0024] 42: P-type deep well region

[0025] 44: N-type deep well region

[0026] 46: Patterned Mask

[0027] 48: Ion implantation process

[0028] 50: Doping area

[0029] 52: Gate dielectric layer

[0030] 54: Gate structure

[0031] 56: Gate material layer

[0032] 58: Hard mask

[0033] 60: Gate electrode

[0034] 62: Gap wall

[0035] 64: Patterned mask

[0036] 68: Lower half

[0037] 70: Upper part

[0038] 72: Source / drain region

[0039] 74: Interlayer dielectric layer

[0040] 76: Patterned Mask

[0041] 78: Dielectric layer

[0042] 82: High dielectric constant dielectric layer

[0043] 84: Work function metal layer

[0044] 86: Low impedance metal layer

[0045] 88:Metal Gate

[0046] 92: Hard mask DETAILED DESCRIPTION

[0047] Please refer to Figures 1 to 11 , Figures 1 to 11 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 1 As shown, first, a substrate 12 is provided, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, and a high-voltage area 14, a medium-voltage area 16, an input / output (I / O) area 18, a core area 20 and an OTP capacitor area 22 are defined on the substrate 12, wherein the high-voltage area 14 and the medium-voltage area 16 are preferably used to prepare high-voltage components and medium-voltage components of metal oxide semiconductor transistors (MOSFETs) with planar structures in subsequent manufacturing processes, the I / O area 18 and the core area 20 are used to prepare low-voltage components such as fin field effect transistors (FinFETs) in subsequent manufacturing processes, and the OTP capacitor area 22 is used to prepare OTP capacitors.

[0048] In the present embodiment, the high voltage region 14, the medium voltage region 16, the I / O region 18, the core region 20 and the OTP capacitor region 22 may include transistor regions of the same conductivity type or different conductivity types, for example, each of which is a PMOS transistor region and / or an NMOS transistor region, and the five regions are respectively predetermined to be gate structures of the same or different threshold voltages to be subsequently manufactured. In the present embodiment, the P-type deep well region 42 may be first formed in the high voltage region 14 by an ion implantation process and the N-type deep well region 44 may be formed in the medium voltage region 16, the I / O region 18, the core region 20 and the OTP capacitor region 22, but the conductivity types of each region are not limited thereto.

[0049] Then, a base 24 is formed on the substrate 12 of the high voltage area 14 and the medium voltage area 16, and a plurality of fin structures 26 are formed on the substrate 12 of the I / O area 18, the core area 20 and the OTP capacitor area 22. According to a preferred embodiment of the present invention, the fin structure 26 is preferably obtained by sidewall image transfer (SIT) technology, and the procedure generally includes: providing a layout pattern to a computer system, and defining the corresponding pattern in a photomask through appropriate calculations. Subsequently, a plurality of equidistant and equal-width patterned sacrificial layers or mandrels can be formed on the substrate through photolithography and etching processes, so that their individual appearances are strip-shaped. Thereafter, deposition and etching processes are sequentially performed to form spacers on each sidewall of the patterned sacrificial layer. The patterned sacrificial layer is then removed and an etching process is performed under the coverage of the spacer, so that the pattern formed by the spacer is transferred to the substrate, and then a fin structure cutting process (fin cut) is performed to obtain the desired patterned structure, such as a strip-shaped patterned fin structure, and at least a plurality of relatively shallow grooves are relatively defined around each fin structure.

[0050] In addition, the formation method of the base 24 and the fin structure 26 may include first forming a patterned mask (not shown) on the substrate 12, and then performing an etching process to transfer the pattern of the patterned mask to the substrate 12 to form the fin structure 26. In addition, the formation method of the fin structure 26 may also include first forming a patterned hard mask layer (not shown) on the substrate 12, and using an epitaxial process to grow a semiconductor layer such as silicon germanium on the substrate 12 exposed from the patterned hard mask layer, and this semiconductor layer can serve as the corresponding fin structure 26. These embodiments of forming the fin structure 26 are all within the scope of the present invention.

[0051] In the present embodiment, each of the bases 24 and the top surface of the fin-shaped structure 26 may be provided with at least one liner layer 28 and a hard mask 30 on the substrate 12 during the patterning process, wherein the liner layer 28 may include silicon oxide and / or silicon nitride and the hard mask 30 preferably includes silicon oxide, but is not limited thereto. In addition, before forming the fin-shaped structure 26, the middle pressure area 16 may first use a pattern transfer process to remove part of the substrate 12 to form a groove, and then form the aforementioned fin-shaped structure 26. Therefore, the top surface of the base 24 in the middle pressure area 16 is preferably slightly lower than the top surface of the base 24 or the fin-shaped structure 26 in other areas.

[0052] After forming the fin structure 26, another photolithography and etching process may be performed to remove a portion of the substrate 12 in the high pressure area 14 and the medium pressure area 16 to form at least a plurality of deeper grooves (not shown). Figure 2As shown, a flowable chemical vapor deposition (FCVD) process is performed to simultaneously form an insulating layer composed of silicon oxide in all the grooves, and then a planarization process is performed, such as chemical mechanical polishing (CMP) to remove part of the insulating layer, part of the hard mask 30 and even the liner layer 28, so that the top surface of the remaining insulating layer is roughly aligned with the top surface of the substrate 12 in each region, so as to form a deeper shallow trench isolation 32 in the high voltage region 14 and the medium voltage region 16, and simultaneously form a shallower shallow trench isolation 32 in the I / O region 18, the core region 20 and the OTP capacitor region 22.

[0053] like Figure 3 As shown, the remaining hard mask 30 and the liner layer 28 of the medium voltage region 16 are then removed to expose the surface of the base 24, and an ion implantation process is performed to form a doped region 34 on both sides of the base 24 of the high voltage region 14 as a lightly doped drain of the subsequent high voltage element. Then, an oxide growth process or more specifically a rapid thermal oxidation (RTO) process is performed using a mask to form a gate dielectric layer 36 composed of silicon oxide on the base 24 of the high voltage region 14. Then, a lightly doped drain 38 is formed in the medium voltage region 16, and another oxide growth process is performed using a mask to form a gate dielectric layer 40 also composed of silicon oxide on the base 24 of the medium voltage region 16. It should be noted that in this stage, when removing the remaining hard mask 30 and the liner layer 28 of the medium voltage area 16, it is better to remove part of the shallow trench isolation 32 to form a groove. Therefore, the gate dielectric layer 40 formed subsequently not only grows on the surface of the substrate 12 but is also arranged in the groove of the shallow trench isolation 32.

[0054] like Figure 4 As shown, a patterned mask 46 is then formed, such as a patterned photoresist, on all areas outside the OTP capacitor area 22 to expose the substrate 12 or the surface of the fin structure 26 of the OTP capacitor area 22, and then an ion implantation process 48 or a heavy doping process is performed to implant dopants into the fin structure 26 of the OTP capacitor area 22 to form a doped region 50 so that the doping concentration of the substrate 12 in the high voltage area 14, the medium voltage area 16, the I / O area 18 and the core area 20 is less than the doping concentration of the fin structure 26 of the OTP capacitor area 22, wherein the doped region 50 is preferably used as the lower electrode of the OTP capacitor. In the present embodiment, the implanted dopant preferably includes arsenic, the energy of the ion implantation process is preferably between 5 and 20 KeV, and the dopant dosage is preferably between 1.0×10 15 atoms / cm2 to 1.0×10 16 atoms / cm2, and the doping concentration is between 1.0×1018 atoms / cm3 to 1.0×10 20 atoms / cubic centimeter.

[0055] like Figure 5 As shown, the patterned mask 46 may be removed first and an annealing process may be performed to drive the previously implanted dopants into the fin structure 26 of the OTP capacitor region 22, forming a patterned mask (not shown) such as a patterned photoresist in the high voltage region 14 and the medium voltage region 16, and then an etching process may be performed to remove a portion of the shallow trench isolation 32 in the I / O region 18, the core region 20 and the OTP capacitor region 22, so that the top surface of the remaining shallow trench isolation 32 is slightly lower than the top surface of the fin structure 26. Then, an oxide growth process such as a rapid thermal oxidation (RTO) process or an in-situ steam growth (ISSG) process may be performed to form a gate dielectric layer 52 composed of silicon oxide on the surface of the fin structure 18 where the shallow trench isolation 32 is exposed in the I / O region, the core region and the OTP capacitor region 16.

[0056] Then as Figure 6 As shown, a gate structure 54 can be formed on the base 24 and the fin structure 26 of the high voltage region 14, the medium voltage region 16, the I / O region 18, the core region 20 and the OTP capacitor region 22, respectively. The gate structures 54 of the high voltage region 14, the medium voltage region 16, the I / O region 18 and the core region 20 can be used as gate electrodes of each region. Meanwhile, the gate structure 54 formed in the OTP capacitor region 22 can be used as an upper electrode of the OTP capacitor. The gate structure 54 can be manufactured by a gate first manufacturing process, a gate last manufacturing process of a high-k first manufacturing process or a gate last manufacturing process of a high-k last manufacturing process according to the manufacturing process requirements.

[0057] Taking the post-high-k dielectric layer manufacturing process of the present embodiment as an example, a gate material layer 56 composed of polycrystalline silicon and a selective hard mask 58 can be sequentially formed on the substrate 12, and a patterned photoresist (not shown) is used as a mask to perform a pattern transfer manufacturing process, and a portion of the hard mask 58 and a portion of the gate material layer 56 and a portion of the gate dielectric layer 52 are removed by a single etching or successive etching steps, and then the patterned photoresist is stripped to form a gate structure 54 composed of a patterned gate material layer 56 and a patterned hard mask 58 in each area, wherein the patterned gate material layer 56 can be used as a gate electrode 60 of a high-voltage component, a medium-voltage component, an I / O component, and a core component, and an upper electrode of an OTP capacitor.

[0058] Then as Figure 7 As shown, at least one spacer 62 is formed on the sidewalls of the gate structure 54, and then a patterned mask 64, such as a patterned photoresist, is formed on the high voltage region 14, the I / O region 18, the core region 20, and the OTP capacitor region 22 to expose the gate dielectric layer 40 on both sides of the gate structure 54 in the medium voltage region 16. In this embodiment, the spacer 62 can be a single spacer or a composite spacer, for example, it can include an offset spacer and a main spacer in detail. The offset spacer and the main spacer can include the same or different materials, and both can be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride.

[0059] like Figure 8 As shown, an etching process is then performed using the patterned mask 64 as a mask to remove portions of the gate dielectric layer 40 on both sides of the gate structure 54 of the medium voltage region 16, so that the remaining gate dielectric layer 40 forms an inverted T shape. More specifically, the gate dielectric layer 40 of the medium voltage region 14 modified by etching at this stage preferably includes a lower half 68 disposed on both the substrate 12 and the shallow trench isolation 32 and an upper half 70 disposed on the lower half 68, wherein the width of the upper half 70 is smaller than the width of the lower half 68, and the top surface of the upper half 70 can be aligned with the top surface of the fin structure 26 of the core region 20 and the OTP capacitor region 22 and / or the top surface of the doped region 50 of the OTP capacitor region 22, and the sidewall of the upper half 70 is aligned with the sidewall of the spacer 62. In addition, the thickness of the lower half 68 is preferably smaller than the thickness of the upper half 70. For example, the thickness of the lower half 68 may be less than 90%, 80%, 70%, 60%, or even less than 50% of the thickness of the upper half 70. The top surface of the lower half 68 is preferably lower than the topmost surface of the shallow trench isolation 32 of the medium voltage area 16 but may be higher, flush, or lower than the top surface of the shallow trench isolation 32 of the I / O area 18, the core area 20, and the OTP capacitor area 22.

[0060] Then, a source / drain region 72 and / or an epitaxial layer (not shown) may be formed in the base 24 or the fin structure 26 on both sides of the spacer 62 in the high voltage region 14, the medium voltage region 16, the I / O region 18, and the core region 20, and a metal silicide (not shown) may be selectively formed on the surface of the source / drain region 72 and / or the epitaxial layer. The source / drain region 72 and the epitaxial layer may include different dopants or different materials according to the conductivity type of the transistor to be prepared. For example, the source / drain region 72 may include P-type dopants or N-type dopants, and the epitaxial layer may include silicon germanium, silicon carbide, or silicon phosphide depending on the characteristics of PMOS or NMOS. It should be noted that since the OTP capacitor area 22 is used to prepare a capacitor element, the present embodiment only forms a source / drain region 72 and / or an epitaxial layer in the substrate 12 on both sides of the gate structure 54 in the high voltage area 14, the medium voltage area 16, the I / O area 18 and the core area 20. However, it is worth noting that it is preferred not to form any source / drain region and / or epitaxial layer on the substrate 12 (fin structure 26) on both sides of the gate structure 54 (upper electrode) of the OTP capacitor area 22.

[0061] like Fig. 9 As shown, an interlayer dielectric layer 74 is then formed to cover the gate structure 54, and then a planarization process is performed, such as using chemical mechanical polishing (CMP) to remove part of the interlayer dielectric layer 74 and expose the hard mask 58, so that the upper surface of the hard mask 58 is flush with the upper surface of the interlayer dielectric layer 74. A metal gate replacement process is then performed to convert the gate material layer 56 composed of polysilicon material in the high voltage area 14, the medium voltage area 16, the I / O area 18, the core area 20 and the OTP capacitor area 22 into a metal gate. For example, a selective dry etching or wet etching process may be performed first, such as using an etching solution such as ammonium hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH) to remove the hard mask 58 and the gate material layer 56 of the high voltage area 14, the medium voltage area 16, the I / O area 18, the core area 20, and the OTP capacitor area 22, so as to form grooves in the interlayer dielectric layer 74 to expose the gate dielectric layers 36, 40, 52 of each area.

[0062] Then, a patterned mask 76 such as patterned photoresist is formed on the high voltage area 14, the medium voltage area 16 and the I / O area 18 to expose the gate dielectric layer 52 of the core area 20 and the OTP capacitor area 22. The patterned mask 76 is then used as a mask to etch away the gate dielectric layer 52 of the core area 20 and the OTP capacitor area 22 to expose the surface of the substrate 12 (fin structure 26).

[0063] Please continue to refer to Figure 10 to Figure 11 , Figure 10 to Figure 11 Continuation of an embodiment of the present invention Fig. 9The RMG manufacturing process is used to form metal gates in the high voltage area 14, the medium voltage area 16, the I / O area 18, the core area 20 and the OTP capacitor area 22, wherein Fig. 9 and Fig.10 The high voltage area 14, the medium voltage area 16, the I / O area 18, the core area 20 and the OTP capacitor area 22 are all cross-sectional schematic diagrams at the same angle. Fig.11 Only the high voltage area 14 and the medium voltage area 16 are cross-sectional diagrams at the same angle, while the I / O area 18, the core area 20 and the OTP capacitor area 22 are cross-sectional diagrams at different angles. Fig.10 It can be seen that the fin structure in the I / O area 18, the core area 20 and the OTP capacitor area 22 after the RMG manufacturing process is continued. Fig.11 In the middle, the source / drain regions 72 in the I / O region 18 and the core region 20 can be seen, but there is no source / drain region 72 in the OTP capacitor region 72 .

[0064] like Figure 10 to Figure 11 As shown, another dielectric layer 78 composed of silicon oxide is first formed on the surface of the substrate 12 in the core area 20 and the OTP capacitor area 22, and then the patterned mask 76 is removed to sequentially form a high-k dielectric layer 82, a work function metal layer 84, and a low-resistance metal layer 86 in the grooves of each region, and then a planarization process is performed, such as using CMP to remove part of the low-resistance metal layer 86, part of the work function metal layer 84, and part of the high-k dielectric layer 82 to form a metal gate 88. Taking the gate structure 54 manufactured by the post-high-k dielectric layer manufacturing process of this embodiment as an example, each metal gate 88 formed preferably includes a U-shaped high-k dielectric layer 82, a U-shaped work function metal layer 84, and a low-resistance metal layer 86.

[0065] It should be noted that, although the dielectric layer 78 formed in the core region 20 and the OTP capacitor region 22 and the gate dielectric layer 52 of the I / O region 18 are both made of silicon oxide at this stage, the thickness of the dielectric layer 78 is preferably slightly less than the thickness of the gate dielectric layer 52, or more specifically, the thickness of the dielectric layer 78 is preferably less than more than half of the thickness of the gate dielectric layer 52 of the I / O region 18. In addition, compared with the present embodiment in which the dielectric layer 78 of the same thickness is formed in the core region 20 and the OTP capacitor region 22 at the same time, according to another embodiment of the present invention, an additional oxidation process can be selected to form dielectric layers of the same thickness and different thicknesses in the core region 20 and the OTP capacitor region 22, wherein the thickness of the dielectric layer in the OTP capacitor region 22 is preferably less than the thickness of the dielectric layer in the core region 20, and the thickness of the dielectric layer in the core region 20 is preferably less than the thickness of the gate dielectric layer 52 of the I / O region 18. As a result, the I / O region 18 , the core region 20 , and the OTP capacitor region 22 have three dielectric layers or gate dielectric layer combinations with different thicknesses. This variation also falls within the scope of the present invention.

[0066] In the present embodiment, the high-k dielectric layer 82 includes a dielectric material with a dielectric constant greater than 4, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalum oxide (strontium bismuth tantalum oxide), and strontium tantalum oxide (strontium bismuth tantalum oxide). tantalate,SrBi2Ta2O9,SBT), lead zirconate titanate (leadzirconate titanate,PbZr x Ti 1-x O3, PZT), barium strontium titanate (Ba x Sr 1- x TiO3, BST), or a combination thereof.

[0067] The work function metal layer 84 is preferably used to adjust the work function of the metal gate so that it is suitable for an N-type transistor (NMOS) or a P-type transistor (PMOS). If the transistor is an N-type transistor, the work function metal layer 84 can be made of a metal material with a work function of 3.9 electron volts (eV) to 4.3 eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl) or TiAlC (titanium aluminum carbide), etc., but not limited thereto; if the transistor is a P-type transistor, the work function metal layer 84 can be made of a metal material with a work function of 4.8 eV to 5.2 eV, such as titanium nitride (TiN), tantalum nitride (TaN) or tantalum carbide (TaC), etc., but not limited thereto. Another barrier layer (not shown) may be included between the work function metal layer 84 and the low resistance metal layer 86, wherein the material of the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) and other materials. The low resistance metal layer 86 may be selected from low resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP) and other materials or combinations thereof. Since converting a dummy gate into a metal gate according to a metal gate replacement manufacturing process is a well-known technique in this field, it will not be further described here. Then, a portion of the high dielectric constant dielectric layer 82, a portion of the work function metal layer 84 and a portion of the low resistance metal layer 86 may be removed to form a groove (not shown), and then a hard mask 92 is filled in the groove and the hard mask 92 is flush with the surface of the interlayer dielectric layer 74, wherein the hard mask 92 may be selected from a group consisting of silicon oxide, silicon nitride, silicon oxynitride and silicon nitride carbide.

[0068] Afterwards, a pattern transfer process may be performed, for example, a pattern mask may be used to remove a portion of the interlayer dielectric layer 74 next to each metal gate 88 to form a plurality of contact holes (not shown) and expose the source / drain region 72. Then, the required metal material is filled into each contact hole, for example, a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials such as tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (cobalttungsten phosphide, CoWP), or a combination thereof. Afterwards, a planarization process is performed, for example, chemical mechanical polishing is used to remove a portion of the metal material to form contact plugs (not shown) in each contact hole to electrically connect the source / drain region 72. At this point, the fabrication of the semiconductor device of the preferred embodiment 1 of the present invention is completed.

[0069] Please refer to Fig.10 and Fig.11 , Fig.10 and Fig.11 The structural schematic diagrams of semiconductor components integrating high voltage components, medium voltage components, I / O components, core components and OTP capacitors are also disclosed in accordance with an embodiment of the present invention. Fig.10 and Fig.11 As shown, the semiconductor device mainly includes a high-voltage device disposed in the high-voltage region 14, a medium-voltage device disposed in the medium-voltage region 16, an I / O device disposed in the I / O region 18, a core device disposed in the core region 20, and an OTP capacitor disposed in the OTP capacitor region 22. The OTP capacitor includes a fin-shaped structure 26 disposed on the substrate 12, a doped region 50 disposed in the fin-shaped structure 26, at least one insulating layer such as a dielectric layer 78 and / or a high-k dielectric layer 82 is disposed on the fin-shaped structure 26, and a metal material such as a work function metal layer 84 and a low-resistance metal layer 86 is disposed on the high-k dielectric layer 82, wherein the fin-shaped structure 26 including the heavily doped region 50 is preferably used as the lower electrode of the OTP capacitor, the dielectric material such as the dielectric layer 78 and / or the high-k dielectric layer 82 is preferably used as the capacitor dielectric layer of the OTP capacitor, and the work function metal layer 84 and the low-resistance metal layer 86 are used as the upper electrode of the OTP capacitor.

[0070] Please continue to refer to Fig.12 , Fig.12 FIG. 1 is an overall layout diagram of a semiconductor device according to an embodiment of the present invention. Fig.12 As shown, the semiconductor element mainly includes various elements such as an OTP array, a row decoder, a column decoder, a sense amplifier, a control logic and analog block, and a medium voltage element. The OTP array preferably includes the OTP capacitor of the OTP capacitor area 22 in the aforementioned embodiment, and row and column decoders and sense amplifiers are arranged around the OTP array. In addition, a control logic and analog block is arranged between the OTP array and the medium voltage element, and the medium voltage element adjacent to the control logic and analog block preferably includes a circuit element for reading and writing each OTP element in the OTP array.

[0071] In summary, the present invention mainly discloses a manufacturing process and related structure for integrating high-voltage components, medium-voltage components, I / O components, core components and OTP capacitors. According to a preferred embodiment of the present invention, the high-voltage components and medium-voltage components are preferably manufactured according to a planar metal oxide semiconductor transistor manufacturing process, while the I / O components, core components and OTP capacitors are manufactured according to a non-planar or more specifically a fin-shaped field effect transistor (FinFET) manufacturing process. In order to make the medium-voltage components and their peripheral components more compatible, the present invention preferably uses an additional photolithography and etching manufacturing process to pattern the gate dielectric layer 40 of the medium-voltage components to form an inverted T shape before the RMG manufacturing process. In addition, in order to enhance the read and write capabilities of the OTP capacitor, the present invention preferably removes the gate material layer 56 composed of polysilicon and then removes the gate dielectric layer 52 of the core region and the OTP capacitor region, but retains the gate dielectric layer 52 of the I / O region, and then forms another dielectric layer 78 composed of silicon oxide on the surface of the substrate 12 of the core region 20 and the OTP capacitor region 22. Although the dielectric layer 78 formed by the core region 20 and the OTP capacitor region 22 and the gate dielectric layer 52 of the I / O region 18 are both made of silicon oxide, the overall thickness of the dielectric layer 78 is preferably slightly lower than the overall thickness of the gate dielectric layer 52. Based on the above adjustments in the manufacturing process, the present invention can achieve a more perfect combination of the components of the high voltage region, the medium voltage region, the I / O region, the core region and the OTP capacitor region.

[0072] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A semiconductor element, characterized in that: Include: A substrate, including a medium voltage area and an OTP capacitor area; A medium-voltage component is disposed in the medium-voltage area; and The OTP capacitor is disposed in the OTP capacitor area.

2. The semiconductor device as claimed in claim 1, wherein the medium voltage device comprises: A first gate dielectric layer is disposed on the substrate; A first gate electrode is disposed on the first gate dielectric layer; A spacer is disposed beside the first gate electrode; and Shallow trench isolation is arranged on both sides of the first gate electrode. The semiconductor device as claimed in claim 2 , wherein the first gate dielectric layer comprises an inverted T-shape.

4. The semiconductor device as claimed in claim 2, wherein the first gate dielectric layer comprises: A lower half is disposed on the shallow trench isolation and the substrate; and The upper part is arranged on the lower part. The semiconductor device as claimed in claim 4 , wherein the width of the upper portion is smaller than the width of the lower portion. The semiconductor device as claimed in claim 4 , wherein the upper sidewall is flush with the sidewall of the spacer.

7. The semiconductor device as claimed in claim 2, wherein the OTP capacitor comprises: A fin-shaped structure is disposed on the substrate; a doped region disposed within the fin structure; a dielectric layer disposed on the doped region; and The upper electrode is arranged on the dielectric layer. 8 . The semiconductor device as claimed in claim 7 , wherein a top surface of the first gate dielectric layer is flush with a top surface of the doped region.

9. A semiconductor element, characterized in that: Include: The substrate includes a medium voltage area, an OTP capacitor area, and a core area; A medium-voltage component is disposed in the medium-voltage area; An OTP capacitor is disposed in the OTP capacitor area; and The metal oxide semiconductor transistor is arranged in the core area.

10. The semiconductor device of claim 9, wherein the medium voltage device comprises: A first gate dielectric layer is disposed on the substrate; A first gate electrode is disposed on the first gate dielectric layer; A spacer is disposed beside the first gate electrode; and Shallow trench isolation is arranged on both sides of the first gate electrode. The semiconductor device as claimed in claim 10 , wherein the first gate dielectric layer comprises an inverted T-shape.

12. The semiconductor device of claim 10, wherein the first gate dielectric layer comprises: A lower half is disposed on the shallow trench isolation and the substrate; and The upper part is arranged on the lower part. The semiconductor device as claimed in claim 12 , wherein the width of the upper portion is smaller than the width of the lower portion. 14 . The semiconductor device as claimed in claim 12 , wherein the upper sidewall is flush with the sidewall of the spacer.

15. The semiconductor device as claimed in claim 10, wherein the OTP capacitor comprises: A first fin structure is disposed on the substrate; a doped region disposed in the first fin structure; A first dielectric layer is disposed on the doped region; and The upper electrode is arranged on the first dielectric layer. 16 . The semiconductor device as claimed in claim 10 , wherein a top surface of the first gate dielectric layer is flush with a top surface of the doped region.

17. The semiconductor device as claimed in claim 15, wherein the metal oxide semiconductor transistor comprises: A second fin structure is disposed on the substrate; A second dielectric layer is disposed on the second fin-shaped structure; A second gate electrode is disposed on the second dielectric layer; and The source / drain regions are arranged on both sides of the second gate electrode.

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