Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, the semiconductor structure comprises a substrate with a PMOS (P-channel Metal Oxide Semiconductor) region and an NMOS (N-channel Metal Oxide Semiconductor) region, and discrete fin parts are formed on the substrate; the gate structure is located on the substrate and stretches across the fin part, and the gate structure covers part of the top and part of the side wall of the fin part; the first isolation structure is located in the fin part between the adjacent gate structures to be isolated in the PMOS region; the second isolation structure is located in the NMOS region, the second isolation structure stretches across the fin part at the side part of the gate structure and is arranged in parallel with the gate structure, and the bottom of the second isolation structure extends into the fin part; the first source-drain doped layer is located in the fin parts on the two sides of the gate structure of the PMOS region; and the second source-drain doped layer is positioned in the fin parts on the two sides of the gate structure of the NMOS region. According to the invention, after the first isolation structure is formed, the response speed difference between the PMOS region and the NMOS region is reduced, so that the performance of the semiconductor structure is improved; and the area of the semiconductor structure can be saved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are moving towards higher component density and higher integration. Transistors, as one of the basic semiconductor devices, are currently being widely used. Therefore, with the increase in density and integration of semiconductor devices, the gate size of planar transistors is getting shorter and shorter. The control ability of traditional planar transistors over channel current becomes weaker, resulting in short channel effects, causing leakage current to increase, and ultimately affecting the electrical performance of semiconductor devices.

[0003] In order to better adapt to the reduction of feature size, semiconductor processes have gradually begun to transition from planar MOSFET to three-dimensional transistors with higher efficiency, such as fin field effect transistors (FinFET). In FinFET, the gate can control the ultra-thin body (fin) from at least two sides. Compared with planar MOSFET, the gate has stronger control over the channel and can effectively suppress the short channel effect; and FinFET has better compatibility with existing integrated circuit manufacturing than other devices.

[0004] In addition, in order to increase the operating speed of the chip and improve the performance of the transistor, the existing technology introduces a stress layer in the source and drain doping regions and introduces compressive stress or tensile stress in the channel region of the transistor to increase the mobility of carriers in the channel, thereby improving the performance of the transistor. Therefore, the stress layer in the current fin field effect transistor is located in the fins on both sides of the gate structure.

[0005] However, as the size of semiconductor devices decreases, the distance between adjacent fins also decreases. In order to prevent bridging between adjacent devices, a double diffusion break (DDB) structure is introduced. Along the extension direction of the fin, the distance between two adjacent transistors is one gate pitch. In order to further reduce the chip area, a single diffusion break (SDB) structure is introduced. After the SDB structure is introduced, along the extension direction of the fin, the distance between two adjacent transistors is only the width of one gate.

[0006] However, the performance of current semiconductor structures still needs to be improved. Summary of the invention

[0007] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.

[0008] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, the substrate including a PMOS region and an NMOS region, and discrete fins are formed on the substrate; a gate structure, located on the substrate and spanning the fins, the gate structure covering part of the top and part of the sidewalls of the fins; a first isolation structure, located in the PMOS region, and located in the fins between adjacent gate structures to be isolated; a second isolation structure, located in the NMOS region, the second isolation structure spans the fins on the sides of the gate structure and is arranged in parallel with the gate structure, and the bottom of the second isolation structure extends into the fins; a first source-drain doped layer, located in the fins on both sides of the gate structure in the PMOS region; a second source-drain doped layer, located in the fins on both sides of the gate structure in the NMOS region.

[0009] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a PMOS region and an NMOS region, and discrete fins are formed on the substrate; forming a gate structure spanning the fins on the substrate, the gate structure covering a portion of the top and a portion of the side walls of the fins; in the PMOS region, forming a first isolation structure in the fins between adjacent gate structures to be isolated; after forming the first isolation structure, forming a first source-drain doped layer in the fins on both sides of the gate structure in the PMOS region; forming a second source-drain doped layer in the fins on both sides of the gate structure in the NMOS region; in the NMOS region, forming a second isolation structure at the position of a portion of the gate structure, the second isolation structure extending into the fins.

[0010] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0011] The semiconductor structure provided in an embodiment of the present invention includes a first isolation structure located in the PMOS region and in the fin between adjacent gate structures to be isolated, a second isolation structure located in the NMOS region, the second isolation structure spans the fin on the side of the gate structure and is arranged parallel to the gate structure, and the bottom of the second isolation structure extends into the fin; a first source-drain doped layer in the fin on both sides of the gate structure in the PMOS region, and a second source-drain doped layer in the fin on both sides of the gate structure in the NMOS region. Since the carriers of the PMOS region are holes and the carriers of the NMOS region are electrons, the response speed of electrons is faster, so compared with the response speed of the PMOS region, the response speed of the NMOS region is faster; moreover, holes are more sensitive to changes in stress, that is, after losing stress of the same absolute value, the response speed of the PMOS region decreases more than the response speed of the NMOS region. A first isolation structure is formed in the fin portion between adjacent gate structures to be isolated in the PMOS region, thereby avoiding the removal of the gate structure of the PMOS region, reducing the stress loss caused by the formation of the first isolation structure to the first source and drain doping layer, and correspondingly reducing the response speed decrease of the PMOS region, thereby reducing the formation of the first isolation structure. After the structure is formed, the difference in response speed between the PMOS region and the NMOS region further improves the performance of the semiconductor structure; moreover, compared with the solution in which the first isolation structure is formed in both the PMOS region and the NMOS region, the embodiment of the present invention includes a first isolation structure located in the PMOS region and in the fin between adjacent gate structures to be isolated, and a second isolation structure located in the NMOS region, the second isolation structure spans the fin on the side of the gate structure and is arranged in parallel with the gate structure, and the bottom of the second isolation structure extends into the fin, that is, the second isolation structure extending into the fin is formed at the position of a part of the gate structure in the NMOS region, which is beneficial to saving the area of ​​the semiconductor structure.

[0012] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a first isolation structure is formed in the fin between adjacent gate structures to be isolated in the PMOS region. After the first isolation structure is formed, a first source-drain doping layer is formed in the fin on both sides of the gate structure in the PMOS region, and a second source-drain doping layer is formed in the fin on both sides of the gate structure in the NMOS region. In the NMOS region, a second isolation structure is formed at the position of a portion of the gate structure, and the second isolation structure extends into the fin. Since the carriers in the PMOS region are holes and the carriers in the NMOS region are electrons, the response speed of electrons is faster, so compared with the response speed of the PMOS region, the response speed of the NMOS region is faster; moreover, holes are more sensitive to changes in stress, that is, after losing stress of the same absolute value, the response speed of the PMOS region decreases by a greater margin than the response speed of the NMOS region. The first isolation structure is formed in the fin between adjacent gate structures to be isolated in the PMOS region, thereby avoiding the removal of the gate structure in the PMOS region, reducing the stress loss caused by the formation of the first isolation structure to the first source-drain doping layer, and correspondingly reducing the response speed of the PMOS region. The decrease rate reduces the difference in response speed between the PMOS region and the NMOS region after the first isolation structure is formed, thereby improving the performance of the semiconductor structure; moreover, compared with the solution in which the first isolation structure is formed in both the PMOS region and the NMOS region, the embodiment of the present invention forms a first isolation structure in the fin portion between adjacent gate structures to be isolated in the PMOS region, and in the NMOS region, a second isolation structure is formed at the position of a portion of the gate structure, and the second isolation structure extends into the fin portion, that is, a second isolation structure extending into the fin portion is formed at the position of a portion of the gate structure in the NMOS region, which is beneficial to saving the area of ​​the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figures 1 to 6 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0014] Figure 7 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0015] Figure 8 for Figure 7 A local enlarged view at position B;

[0016] Figures 9 to 27 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0017] At present, the performance of semiconductor structures still needs to be improved. Now, combined with a method for forming a semiconductor structure, the reasons why the performance of semiconductor structures needs to be improved are analyzed. Figures 1 to 6 The present invention is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.

[0018] Since the semiconductor structure of the NMOS region is similar to that of the PMOS region, in order to facilitate the display of the semiconductor structure, Figures 1 to 6 Only the PMOS region is shown.

[0019] refer to Figure 1 , providing a substrate 10, the substrate 10 including a PMOS region 21 and an NMOS region (not shown), a discrete fin 11 formed on the substrate 10, and a gate structure 12 across the fin 11 also formed on the substrate 10, the gate structure 12 covering a portion of the top and a portion of the sidewall of the fin 11,

[0020] refer to Figure 2 In the PMOS region 21 and the NMOS region, a patterned mask structure 13 is formed on the gate structure 12, and the mask structure 13 has an initial mask opening 14 located above the gate structure 12 to be removed in the PMOS region 21 and above the gate structure 12 to be removed in the NMOS region.

[0021] refer to Figure 3 , the mask structure 13 at the bottom of the initial mask opening 14 is removed along the initial mask opening 14 to form a mask opening 15 , wherein the mask opening 15 exposes the top of the gate structure 12 to be removed.

[0022] refer to Figure 4 , along the mask opening 15 , the gate structure 12 and the fin 11 at the bottom of the mask opening 15 are removed to form an initial isolation opening 16 .

[0023] refer to Figure 5 , along the initial isolation opening 16 , a portion of the thickness of the substrate 10 at the bottom of the initial isolation opening 16 is removed to form an isolation opening 17 ; after the isolation opening 17 is formed, the remaining mask structure 13 is removed.

[0024] refer to Figure 6 An isolation structure material layer (not shown) is filled in the isolation opening 17, and the isolation structure material layer is also formed on the remaining gate structure 12, wherein the isolation structure material layer in the isolation opening 17 located in the PMOS region 21 and the isolation structure material layer in the isolation opening 17 located in the NMOS region both serve as isolation structures 18.

[0025] According to research, since the carriers of the PMOS region are holes and the carriers of the NMOS region are electrons, the response speed of electrons is faster, so the response speed of the NMOS region is faster than that of the PMOS region. Therefore, after removing the PMOS region 21 and part of the gate structure of the NMOS region, the magnitude of the decrease in the response speed of the PMOS region is greater than the magnitude of the decrease in the response speed of the NMOS region, thereby further increasing the difference in the response speed between the PMOS region and the NMOS region, thereby affecting the performance of the semiconductor structure.

[0026] In order to solve the above technical problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, the substrate including a PMOS region and an NMOS region, and discrete fins are formed on the substrate; a gate structure, located on the substrate and spanning the fins, the gate structure covering part of the top and part of the side walls of the fins; a first isolation structure, located in the PMOS region, and located in the fins between adjacent gate structures to be isolated; a second isolation structure, located in the NMOS region, the second isolation structure spans the fins on the sides of the gate structure and is arranged parallel to the gate structure, and the bottom of the second isolation structure extends into the fins; a first source-drain doped layer, located in the fins on both sides of the gate structure in the PMOS region; a second source-drain doped layer, located in the fins on both sides of the gate structure in the NMOS region.

[0027] The semiconductor structure provided in an embodiment of the present invention includes a first isolation structure located in the PMOS region and in the fin between adjacent gate structures to be isolated, a second isolation structure located in the NMOS region, the second isolation structure spans the fin on the side of the gate structure and is arranged parallel to the gate structure, and the bottom of the second isolation structure extends into the fin; a first source-drain doped layer in the fin on both sides of the gate structure in the PMOS region, and a second source-drain doped layer in the fin on both sides of the gate structure in the NMOS region. Since the carriers of the PMOS region are holes and the carriers of the NMOS region are electrons, the response speed of electrons is faster, so compared with the response speed of the PMOS region, the response speed of the NMOS region is faster; moreover, holes are more sensitive to changes in stress, that is, after losing stress of the same absolute value, the response speed of the PMOS region decreases more than the response speed of the NMOS region. A first isolation structure is formed in the fin portion between adjacent gate structures to be isolated in the PMOS region, thereby avoiding the removal of the gate structure of the PMOS region, reducing the stress loss caused by the formation of the first isolation structure to the first source and drain doping layer, and correspondingly reducing the response speed decrease of the PMOS region, thereby reducing the formation of the first isolation structure. After the structure is formed, the difference in response speed between the PMOS region and the NMOS region further improves the performance of the semiconductor structure; moreover, compared with the solution in which the first isolation structure is formed in both the PMOS region and the NMOS region, the embodiment of the present invention includes a first isolation structure located in the PMOS region and in the fin between adjacent gate structures to be isolated, and a second isolation structure located in the NMOS region, the second isolation structure spans the fin on the side of the gate structure and is arranged in parallel with the gate structure, and the bottom of the second isolation structure extends into the fin, that is, the second isolation structure extending into the fin is formed at the position of a part of the gate structure in the NMOS region, which is beneficial to saving the area of ​​the semiconductor structure.

[0028] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0029] Figure 7 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0030] Figure 8 for Figure 7 A partial enlarged view at position B.

[0031] refer to Figures 7 and 8In this embodiment, the semiconductor structure includes: a substrate 100, the substrate 100 includes a PMOS region 101 and an NMOS region 102, and a discrete fin 110 is formed on the substrate 100; a gate structure 120, which is located on the substrate 100 and straddles the fin 110, and the gate structure 120 covers a portion of the top and a portion of the sidewall of the fin 110; a first isolation structure 150, which is located in the PMOS region 101 and in the fin 110 between adjacent gate structures 120 to be isolated; The second isolation structure 155 is located in the NMOS region 102. The second isolation structure 155 spans the fin 110 on the side of the gate structure 120 and is arranged parallel to the gate structure 120. The bottom of the second isolation structure 155 extends into the fin 110. The first source-drain doped layer 161 is located in the fin 110 on both sides of the gate structure 120 in the PMOS region 101. The second source-drain doped layer 162 is located in the fin 110 on both sides of the gate structure 120 in the NMOS region 102.

[0032] The substrate 100 is used to provide a process platform for forming a semiconductor structure.

[0033] In this embodiment, the substrate 100 is used to form a field effect transistor. As an example, the substrate 100 is used to form a fin field effect transistor.

[0034] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate material may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.

[0035] The fin 110 provides a process basis for forming an effective fin.

[0036] In this embodiment, the material of the fin 110 includes silicon. In other embodiments, the material of the fin may also include germanium, silicon germanium, III-V group semiconductor materials, single crystal silicon and other materials.

[0037] In this embodiment, the semiconductor structure further includes an isolation layer (not shown) located on the substrate 100 and surrounding the fin 110 . The isolation layer covers a portion of the sidewall of the fin 110 .

[0038] The isolation layer is used to isolate adjacent fins 110 and to isolate the substrate 100 from each semiconductor device. The fins 110 exposed by the isolation layer serve as active fins.

[0039] Specifically, the isolation layer is a shallow trench isolation (STI) structure. As an example, the material of the isolation layer is silicon oxide. In other embodiments, the material of the isolation layer may also be other insulating materials such as silicon nitride or silicon oxynitride.

[0040] The fin 110 covered by the gate structure 120 is used to provide a conductive channel when the semiconductor device is working.

[0041] Specifically, the effective fin covered by the gate structure 120 is used to provide a conductive channel when the semiconductor device is working.

[0042] In this embodiment, the gate structure 120 is a device gate structure 123 .

[0043] Specifically, the device gate structure 123 includes a gate dielectric layer (not shown) and a gate electrode layer (not shown) covering the gate dielectric layer.

[0044] The device gate structure 123 is used to form a field effect transistor with the conductive channel and the source-drain doped layer 163 .

[0045] The gate dielectric layer is used to isolate the gate electrode layer from the conductive channel.

[0046] The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3.

[0047] In this embodiment, the device gate structure 123 is a metal gate structure, and therefore, the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC. The gate electrode layer includes a work function layer and an electrode layer covering the work function layer, or may only include the work function layer.

[0048] Correspondingly, the gate dielectric layer includes a high-k gate dielectric layer. The material of the high-k gate dielectric layer is a high-k dielectric material, and the high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than the relative dielectric constant of silicon oxide. Specifically, the material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3. As an example, the material of the high-k gate dielectric layer is HfO2.

[0049] In other embodiments, the device gate structure may also be a polysilicon gate structure.

[0050] The first isolation structure 150 is a double diffusion break (DDB) isolation structure. The first isolation structure 150 is located between adjacent gate structures 120 to be isolated and is used to achieve electrical isolation between some adjacent gate structures 120 to prevent bridging between adjacent devices.

[0051] Since the carriers of the PMOS region 101 are holes and the carriers of the NMOS region 102 are electrons, the response speed of electrons is faster. Therefore, compared with the response speed of the PMOS region 101, the response speed of the NMOS region 102 is faster. Moreover, holes are more sensitive to changes in stress, that is, after losing stress of the same absolute value, the decrease in the response speed of the PMOS region 101 is greater than the decrease in the response speed of the NMOS region 102. A first isolation structure 150 is formed in the fin 110 between adjacent gate structures 120 to be isolated in the PMOS region 101, thereby avoiding the removal of the gate structure 120 of the PMOS region 101, reducing the stress loss caused by the formation of the first isolation structure 150 to the subsequently formed first source and drain doping layer, and correspondingly reducing the decrease in the response speed of the PMOS region 101, thereby reducing the difference in response speed between the PMOS region 101 and the NMOS region 102 after the first isolation structure 550 is formed, thereby improving the performance of the semiconductor structure.

[0052] The first isolation structure 150 is located in the fin between adjacent gate structures to be isolated in the PMOS region 101, and is used to achieve electrical isolation between some adjacent gate structures 120. It can be understood that the top of the first isolation structure 150 is higher than the top of the conductive channel, that is, the top of the first isolation structure 150 is higher than the top of the fin 110, and the bottom of the first isolation structure 150 is lower than the bottom of the fin 110, which makes it easy for the first isolation structure 150 to have a better isolation effect.

[0053] Since the bottom of the first isolation structure 150 is lower than the bottom of the fin 110 , that is, the bottom of the first isolation structure 150 is also lower than the bottom of the gate structure 120 .

[0054] Generally, before forming the first isolation structure 150, in the PMOS region, a first groove (not shown) is first formed in the fin 110 between the adjacent gate structures 120 to be isolated, and then the first isolation structure 150 is formed in the first groove. In the step of forming the first groove, when the bottom of the first groove is lower than the bottom of the fin 110 by 100 angstroms to 1000 angstroms along the normal direction of the top surface of the substrate 100, it is beneficial to ensure that the bottom of the first isolation structure 150 is lower than the bottom of the fin 110.

[0055] In this embodiment, the material of the first isolation structure 150 includes graphene.

[0056] Graphene material may have good insulation properties, so that the first isolation structure 150 can achieve better electrical isolation between adjacent gate structures 120. In other embodiments, the material of the first isolation structure may also include other dielectric materials, such as materials with a relative dielectric constant lower than 3.9.

[0057] The second isolation structure 155 is a single diffusion break (SDB) isolation structure. The second isolation structure 155 spans the fin 110 on the side of the gate structure 120 and is arranged parallel to the gate structure 120. The bottom of the second isolation structure 155 extends into the fin 110, which is used to achieve electrical isolation between partially adjacent second source and drain doping layers 162 to prevent bridging between adjacent devices.

[0058] Compared with the solution of forming the first isolation structure in both the PMOS region and the NMOS region, the embodiment of the present invention forms a first isolation structure 150 in the fin 110 between adjacent gate structures 120 to be isolated in the PMOS region 101, and in the NMOS region 102, a second isolation structure 155 is formed at the position of part of the gate structure 120, and the second isolation structure 155 extends into the fin 110, that is, the second isolation structure 155 extending into the fin 110 is formed at the position of part of the gate structure 120 in the NMOS region 102, which is beneficial to saving the area of ​​the semiconductor structure.

[0059] Specifically, in the NMOS region 102, the second isolation structure 155 spans the fin 110 on the side of the gate structure 120 and is arranged parallel to the gate structure 120. The bottom of the second isolation structure 155 extends into the fin 110 to achieve electrical isolation between partially adjacent second source and drain doping layers 162. It can be understood that the bottom of the second isolation structure 155 is lower than the bottom of the fin 110, which makes it easy for the second isolation structure 155 to have a better isolation effect.

[0060] In this embodiment, the material of the second isolation structure 155 is a dielectric material.

[0061] The first source-drain doped layer 161 is used as the source region and the drain region of the transistor in the PMOS region 101. When the device is working, the first source-drain doped layer 161 is used to provide carriers for the PMOS region 101.

[0062] In this embodiment, the first source-drain doping layer 161 is doped with P-type ions, and the P-type ions include B ions, Ga ions or In ions.

[0063] The second source-drain doped layer 162 is used as the source region and the drain region of the transistor in the NMOS region 102. When the device is working, the second source-drain doped layer 162 is used to provide carriers for the NMOS region 102.

[0064] Since the second isolation structure 155 spans the fin 110 on the side of the gate structure 120 and is arranged in parallel with the gate structure 120 , it can be understood that, correspondingly, the second source-drain doped layer 162 is also located on both sides of the second isolation structure 155 .

[0065] The second source-drain doping layer 162 and the first source-drain doping layer 161 constitute a source-drain doping layer 163 .

[0066] In this embodiment, the second source-drain doping layer 562 is doped with N-type ions, and the N-type ions include P ions, As ions or Sb ions.

[0067] In this embodiment, the semiconductor structure also includes: an interlayer dielectric layer 170, covering the top of the first source-drain doping layer 161 and the second source-drain doping layer 162, and the interlayer dielectric layer 170 also covers the side walls of the gate structure 120, the top of the first isolation structure 150, and the side walls of the second isolation structure 155.

[0068] The interlayer dielectric layer 170 is used to isolate adjacent devices. Usually, before forming the second isolation structure 155, an interlayer dielectric layer 170 covering the top of the source-drain doped layer 163 is formed, and the interlayer dielectric layer 170 also covers the sidewalls of the gate structure 120 and the top of the first isolation structure 150, so as to facilitate the formation of the second isolation structure 155 at the location of the partial gate structure 120 of the NMOS region 102.

[0069] It should be noted that the material of the interlayer dielectric layer 170 is an insulating material, for example, one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride. As an example, the material of the interlayer dielectric layer 170 is silicon oxide.

[0070] In this embodiment, the semiconductor structure also includes: a source-drain interconnection layer 165, which is located in the interlayer dielectric layer 170 on the top of the first source-drain doped layer 161 and the top of the second source-drain doped layer 162, and is electrically connected to the first source-drain doped layer 161 and the second source-drain doped layer 162 respectively; a first air sidewall 171, which is located between the source-drain interconnection layer 165 and the gate structure 120.

[0071] The source-drain interconnection layer 165 is electrically connected to the top of the first source-drain doped layer 161 and the second source-drain doped layer 162 , respectively, to achieve electrical connection between the source-drain doped layer 163 and an external circuit.

[0072] Since the dielectric constant of air is smaller than that of dielectric materials, the first air spacer 171 is helpful to reduce the parasitic capacitance between the gate structure 120 and the source-drain interconnection layer 165 , thereby improving the performance of the semiconductor structure.

[0073] The first air spacer 171 is located between the gate structure 120 and the source-drain interconnection layer 165 , that is, the first air spacer 171 exposes the sidewall of the source-drain interconnection layer 165 .

[0074] It should be noted that the thickness of the first air sidewall 171 should not be too small or too large. If the thickness of the first air sidewall 171 is too small, it is easy to increase the difficulty of forming the first air sidewall 171; if the thickness of the first air sidewall 171 is too large, it is easy to reduce the effect of subsequent film layers formed in the first air sidewall. Therefore, in this embodiment, the thickness of the first air sidewall 171 ranges from 10 angstroms to 30 angstroms.

[0075] In this embodiment, the semiconductor structure further includes: a spacer structure 130 located on the substrate 100 and spanning the fin 110 , the spacer structure 130 being arranged opposite to the sidewall of the gate structure 120 ; and a second air spacer 172 located between the gate structure 120 and the spacer structure 130 .

[0076] The spacer structure 130 is used to protect the sidewalls of the gate structure 120 , ie, the sidewalls of the device gate structure 123 .

[0077] The second air spacer 172 is beneficial to further reduce the parasitic capacitance between the gate structure 120 and the source-drain interconnection layer 165 , thereby improving the performance of the semiconductor structure.

[0078] It should be noted that an initial spacer structure (not shown) is usually formed first, and the initial spacer structure includes a first spacer layer (not shown) closest to the gate structure 120. After the source-drain interconnection layer 165 is formed, the first spacer layer is removed to form a second air spacer 172, and the remaining initial spacer structure serves as the spacer structure 130. It can be understood that the initial spacer structure is a stacked structure.

[0079] In a specific embodiment, the initial spacer structure includes a first spacer layer closest to the gate structure 120 , a second spacer layer (not shown) covering the first spacer layer, and a third spacer layer (not shown) covering the second spacer layer.

[0080] In other embodiments, the initial side wall structure may also be a single-layer structure, and accordingly, the second air side wall and the first air side wall are interconnected.

[0081] It should be noted that the material of the spacer structure 130 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride, boron carbonitride, and low-k dielectric materials. Among them, the low-k dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9.

[0082] As an example, the first spacer layer is made of a low-k dielectric material, the second spacer layer is made of silicon nitride, and the third spacer layer is made of silicon oxide.

[0083] In other embodiments, the first spacer layer may also be retained after the source-drain interconnection layer.

[0084] In this embodiment, the semiconductor structure further includes a contact etch stop layer (CESL) 136 located between the source / drain doped layer 163 and the interlayer dielectric layer 170 , on the top of the first isolation structure 150 , and on the sidewalls of the gate structure 120 .

[0085] The contact etch stop layer 136 is used to increase the stress of the source / drain doping layer 163 .

[0086] Moreover, the steps of forming the source-drain interconnection layer 165 generally include: forming a third groove (not shown) in the interlayer dielectric layer 170 on the top of the source-drain doped layer 163, the third groove exposing the source-drain doped layer; and forming the source-drain interconnection layer 165 in the third groove.

[0087] The contact etch stop layer 136 may be used as an initial stop position to first form an initial third groove, and then the contact etch stop layer 136 at the bottom of the initial third groove may be removed along the initial third groove to form a third groove.

[0088] In this embodiment, the semiconductor structure further includes a sealing layer 180 located on top of the first air spacer 171 and the second air spacer 172 .

[0089] It should be noted that the material of the sealing layer 180 includes a dielectric material. As an example, the material of the sealing layer 180 is silicon nitride.

[0090] Correspondingly, the present invention also provides a method for forming a semiconductor structure. Figures 9 to 27 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0091] refer to Fig. 9 , a substrate 500 is provided, the substrate includes a PMOS region 501 and an NMOS region 502 , and a discrete fin 510 is formed on the substrate 500 .

[0092] The substrate 500 is used to provide a process platform for subsequent process steps.

[0093] In this embodiment, the substrate 500 is used to form a field effect transistor. As an example, the substrate 500 is used to form a fin field effect transistor.

[0094] In this embodiment, the substrate 500 is a silicon substrate. In other embodiments, the substrate material may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.

[0095] The fin 510 provides a process basis for the subsequent formation of an effective fin, and occupies a space for the subsequent formation of a first isolation structure and a second isolation structure.

[0096] In this embodiment, the material of the fin 510 includes silicon. In other embodiments, the material of the fin may also include germanium, silicon germanium, III-V group semiconductor materials, single crystal silicon and other materials.

[0097] In this embodiment, after providing the substrate 500 and before forming the gate structure, the formation method further includes: forming an isolation layer (not shown) surrounding the fin 510 on the substrate 500 , wherein the isolation layer covers a portion of the sidewall of the fin 510 .

[0098] The isolation layer is used to isolate adjacent fins 510 and to isolate the substrate 500 from various semiconductor devices formed subsequently. The fins 510 exposed by the isolation layer serve as effective fins.

[0099] Specifically, the isolation layer is a shallow trench isolation structure. As an example, the material of the isolation layer is silicon oxide. In other embodiments, the material of the isolation layer can also be other insulating materials such as silicon nitride or silicon oxynitride.

[0100] Continue to refer Fig. 9 , a gate structure 520 is formed on the substrate 500 and crosses the fin 510 , and the gate structure 520 covers a portion of the top and a portion of the sidewall of the fin 510 .

[0101] The fin 510 covered by the gate structure 520 is used to provide a conductive channel when the semiconductor device is working.

[0102] Specifically, the effective fin covered by the gate structure 520 is used to provide a conductive channel when the semiconductor device is working.

[0103] In this embodiment, in the step of forming a gate structure 520 across the fin 510 on the substrate 500 , the gate structure 520 is a dummy gate structure 521 .

[0104] The dummy gate structure 521 is used to occupy a space for the subsequent formation of a device gate structure.

[0105] As an example, the material of the dummy gate structure 521 may be polysilicon, amorphous silicon, amorphous carbon, or the like.

[0106] refer to Fig.10 , and combined with reference Fig. 9 In this embodiment, after forming the gate structure 520 and before forming the first isolation structure, the formation method further includes: forming a sidewall structure 530 on the sidewall of the gate structure 520, and the sidewall structure 530 includes a first sidewall layer 531 closest to the gate structure 520.

[0107] in, Fig.10 for Fig. 9 A partial enlarged view of area A.

[0108] The spacer structure 530 is also used to protect the sidewalls of the dummy gate structure 521 and the subsequently formed device gate structure.

[0109] The first side wall layer occupies a space position for the subsequent formation of the second air side wall.

[0110] Specifically, the sidewall structure 530 is a stacked structure.

[0111] The sidewall structure 530 is a stacked structure. Accordingly, after the first sidewall layer 531 closest to the gate structure 520 is subsequently removed to form the second air sidewall, there is a remaining sidewall structure 530 between the first air sidewall and the second air sidewall, so that the lateral widths of the first air sidewall and the second air sidewall are not easy to be too large, thereby reducing the probability of subsequent film layers being formed in the first air sidewall or the second air sidewall.

[0112] The lateral width here refers to the width in a direction perpendicular to the sidewall of the gate structure 520 .

[0113] In other embodiments, the spacer structure may also be a single-layer structure. Accordingly, the spacer structure only includes a first spacer layer located on the sidewall of the gate structure.

[0114] More specifically, the spacer structure 530 includes a first spacer layer 531 closest to the gate structure 520 , a second spacer layer (not shown) covering the first spacer layer 531 , and a third spacer layer (not shown) covering the second spacer layer.

[0115] It should be noted that the material of the sidewall structure 530 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride, boron carbonitride, and low-k dielectric materials. Among them, the low-k dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9.

[0116] As an example, the material of the first spacer layer 531 is a low-k dielectric material, the material of the second spacer layer is silicon nitride, and the material of the third spacer layer is silicon oxide.

[0117] In this embodiment, the spacer structure 530 is also formed on the top and sidewalls of the fin 510 on both sides of the gate structure 520 .

[0118] refer to Figures 11 to 15 , and combined with reference Figures 9 and 10 , in the PMOS region 501 , a first isolation structure 550 is formed in the fin 510 between adjacent gate structures 520 to be isolated.

[0119] It should be noted that in order to make the structure of the semiconductor clear, Figures 11 to 15 Only the PMOS region is shown.

[0120] The first isolation structure 550 is a double diffusion isolation structure. The first isolation structure 550 is located between adjacent gate structures 520 to be isolated and is used to achieve electrical isolation between some adjacent gate structures 520 to prevent bridging between adjacent devices.

[0121] Since the carriers of the PMOS region 501 are holes and the carriers of the NMOS region 502 are electrons, the response speed of electrons is faster. Therefore, compared with the response speed of the PMOS region 501, the response speed of the NMOS region 502 is faster. Moreover, holes are more sensitive to changes in stress, that is, after losing stress of the same absolute value, the decrease in the response speed of the PMOS region 501 is greater than the decrease in the response speed of the NMOS region 502. A first isolation structure 550 is formed in the fin 510 between adjacent gate structures 520 to be isolated in the PMOS region 501, thereby avoiding the removal of the gate structure 520 of the PMOS region 501 and reducing the stress loss caused by the formation of the first isolation structure 550 to the subsequently formed first source and drain doping layer, and correspondingly reducing the decrease in the response speed of the PMOS region 501, thereby reducing the difference in response speed between the PMOS region 501 and the NMOS region 502 after the first isolation structure 550 is formed, thereby improving the performance of the semiconductor structure.

[0122] Specifically, the first isolation structure 550 is located in the fin 510 between the adjacent gate structures 520 to be isolated in the PMOS region 501, and is used to achieve electrical isolation between some adjacent gate structures 520. It can be understood that the top of the first isolation structure 550 is higher than the top of the conductive channel, that is, the top of the first isolation structure 550 is higher than the top of the fin 510, and the bottom of the first isolation structure 550 is lower than the bottom of the fin 510, which makes it easy for the first isolation structure 550 to have a better isolation effect.

[0123] Since the bottom of the first isolation structure 550 is lower than the bottom of the fin 510 , that is, the bottom of the first isolation structure 550 is also lower than the bottom of the gate structure 520 .

[0124] In this embodiment, the step of forming the first isolation structure 550 includes: forming a first groove 551 in the fin 510 between adjacent gate structures 520 to be isolated in the PMOS region 501 ; and forming the first isolation structure 550 in the first groove 551 .

[0125] Firstly, a first groove 551 is formed in the fin 510 between adjacent gate structures 520 to be isolated in the PMOS region 501 , and then a first isolation structure 550 is formed in the first groove 551 , which helps to reduce the difficulty of forming the first isolation structure 550 .

[0126] In this embodiment, before forming the first groove 551, the forming method further includes: Fig.11 As shown, source and drain grooves 560 are formed in the fins 510 on both sides of the gate structure 520 of the PMOS region 501; Figure 12 to Figure 13 As shown, the step of forming the first groove 551 includes: removing the fin 510 at the bottom of the source-drain groove 560 between the adjacent gate structures 520 to be isolated, so as to form the first groove 551 .

[0127] First, source-drain grooves 560 are formed in the fins 510 on both sides of the gate structure 520 of the PMOS region 501, and then the fins 510 at the bottom of the source-drain grooves 560 between the adjacent gate structures 520 to be isolated are removed to form a first groove 551, thereby reducing the thickness of the fins 510 that need to be removed, thereby reducing the process difficulty.

[0128] Specifically, after forming the sidewall structure 530 and before forming the first isolation structure 550, the formation method also includes: forming a patterned third mask structure 543 on the top and side walls of the gate structure 520, the third mask structure 543 being a PMOS silicon recess (PMOS Si Recess, PSR) mask structure, and exposing the top and side walls of the fins 510 on both sides of the gate structure 520; the step of forming the source-drain groove 560 includes: using the third mask structure 543 as a mask, removing a portion of the thickness of the fin 510, and forming the source-drain groove 560 in the fin 510 on both sides of the gate structure 520 in the PMOS region 501; after forming the source-drain groove 560, it also includes: removing the third mask structure 543.

[0129] It should be noted that the top of the first isolation structure 550 is higher than the top of the fin 510, and the bottom of the first isolation structure 550 is lower than the bottom of the fin 510; accordingly, in the process of removing the fin 510 at the bottom of the source-drain groove 560 between the adjacent gate structures 520 to be isolated, the first part of the thickness of the substrate is also removed.

[0130] It should also be noted that when the bottom of the first groove 551 is 100 angstroms to 1000 angstroms lower than the bottom of the fin 510 along the normal direction of the top surface of the substrate 500, it is helpful to ensure that the bottom of the first isolation structure 550 is lower than the bottom of the fin, thereby making it easier for the first isolation structure 550 to achieve better isolation effect.

[0131] In this embodiment, the step of forming the first groove 551 includes: forming a first mask structure 541 covering the fin 510 and the top of the gate structure 520, and forming a first mask opening 5411 in the first mask structure 541, and the first mask opening 5411 is located above the fin 510 between the adjacent gate structures 520 to be isolated (such as Fig.12 Along the first mask opening 5411, remove the first mask structure 541 at the bottom of the first mask opening 5411 and a portion of the thickness of the fin 510 to form a first groove 551 (as shown); Fig.13 As shown); the forming method further includes: removing the first mask structure 541.

[0132] A first mask structure 541 is formed to cover the fin 510 and the top of the gate structure 520. A first mask opening 5411 is formed in the first mask structure 541 above the fin 510 between adjacent gate structures 520 to be isolated. The first mask structure 541 is used as a mask to remove the first mask structure 541 at the bottom of the first mask opening 5411 and a portion of the thickness of the fin 510 to form a first groove 551. This is beneficial to reducing the probability of other film layers (for example, the sidewall structure 530, the gate structure 520, etc.) being damaged during the formation of the first groove 551, and is also beneficial to improving the size accuracy, position accuracy and morphology accuracy of the first groove 551.

[0133] It should be noted that the first isolation mask structure 541 includes a first mask layer 5412 covering the top of the fin 510 and the gate structure 520 , a second mask layer 5413 covering the first mask layer 5412 , and a third mask layer 5414 covering the second mask layer 5413 .

[0134] It should also be noted that the material of the first mask structure 541 includes an anti-reflective coating material, spin-on carbon (SOC), photoresist, etc. As an example, the material of the first mask layer 5412 includes spin-on carbon and an anti-reflective coating material, the material of the second mask layer 5413 includes a reflective coating material, and the material of the third mask layer 5414 includes a photoresist.

[0135] In this embodiment, in the step of forming the first isolation structure 550, the first isolation structure 550 (eg, Fig.14After forming the first isolation structure 550, the first mask structure 541 (as shown in Fig.15 shown).

[0136] The first isolation structure 550 is formed under the protection of the first mask structure 541 , which helps to reduce the probability of the material corresponding to the first isolation structure 550 being formed on other film layers (eg, the sidewall structure 530 , the gate structure 520 , etc.).

[0137] In this embodiment, the process of forming the first isolation structure 550 in the first groove 551 includes a dielectric-on-dielectric selective deposition process.

[0138] The first isolation structure 550 is formed in the first groove 551 by using a dielectric-on-dielectric selective deposition process, which is beneficial to simplify the process steps of forming the first isolation structure 550 and save process costs.

[0139] Specifically, after forming the first groove 551 and before forming the first isolation structure 550 , the forming method further includes: performing oxidation treatment on the surface of the first groove 551 ; after the oxidation treatment, forming the first isolation structure 550 in the first groove 551 .

[0140] Before forming the first isolation structure 550 , the surface of the first groove 551 is oxidized so that the surface of the first groove 551 is oxidized, which is beneficial to improving the efficiency of forming the first isolation structure 550 by using a dielectric-on-dielectric selective deposition process.

[0141] In this embodiment, the material of the first isolation structure 550 includes graphene.

[0142] Graphene material may have good insulation properties, so that the first isolation structure 550 can achieve better electrical isolation between adjacent gate structures 520. In other embodiments, the material of the first isolation structure may also include other dielectric materials, such as materials with a relative dielectric constant lower than 3.9.

[0143] refer to Fig.16 After forming the first isolation structure 550 , a first source-drain doped layer 561 is formed in the fins on both sides of the gate structure 520 of the PMOS region 501 .

[0144] The first source-drain doped layer 561 is used as the source region and the drain region of the transistor in the PMOS region 501. When the device is working, the first source-drain doped layer 561 is used to provide carriers for the PMOS region 501.

[0145] Specifically, the step of forming the first source-drain doped layer 561 includes: after forming the first isolation structure 550 , forming the first source-drain doped layer 561 in the remaining source-drain grooves 560 of the PMOS region 501 .

[0146] After the first isolation structure 550 is formed, a first source-drain doping layer 561 is formed in the remaining source-drain grooves 560 in the PMOS region 501. That is, when the first isolation structure 550 is formed, the first source-drain doping layer 561 has not yet been formed, thereby further reducing the impact of the formation of the first isolation structure 550 on the first source-drain doping layer 561.

[0147] It should be noted that the first source-drain doping layer 561 is doped with P-type ions, and the P-type ions include B ions, Ga ions or In ions.

[0148] refer to Figures 17 to 21 , a second source-drain doped layer 562 is formed in the fins 510 on both sides of the gate structure 520 of the NMOS region 502 .

[0149] in, Fig.17 for Fig.16 A schematic diagram of the structure after forming the second source-drain doping layer; Fig.18 for Fig.17 A local enlarged view of area A; Fig.19 for Fig.17 Schematic diagram of the structure after forming a sacrificial layer and a contact etch stop layer; Fig. 20 for Fig.19 A partial enlarged view of area A. Fig.21 for Fig. 20 Schematic diagram of the structure after forming the interlayer dielectric layer.

[0150] The second source-drain doped layer 562 is used as the source region and the drain region of the transistor in the NMOS region 502. When the device is working, the second source-drain doped layer 562 is used to provide carriers for the NMOS region 502.

[0151] It should be noted that the second source-drain doping layer 562 is doped with N-type ions, and the N-type ions include P ions, As ions or Sb ions.

[0152] In this embodiment, after forming the second source-drain doping layer 562, the second source-drain doping layer 562 and the first source-drain doping layer 561 constitute a source-drain doping layer 563, and before forming the second isolation structure, the forming method further includes: Fig.21 As shown, an interlayer dielectric layer 570 is formed to cover the top of the source-drain doped layer 563 . The interlayer dielectric layer 570 also covers the sidewalls of the gate structure 520 and the top of the first isolation structure 550 .

[0153] The interlayer dielectric layer 570 is used to isolate adjacent devices. Moreover, before forming the second isolation structure, an interlayer dielectric layer 570 covering the top of the source-drain doped layer 563 is formed, and the interlayer dielectric layer 570 also covers the sidewalls of the gate structure 520 and the top of the first isolation structure 550, so as to facilitate the subsequent formation of the second isolation structure at the location of the partial gate structure 520 of the NMOS region 502.

[0154] It should be noted that the material of the interlayer dielectric layer 570 is an insulating material, for example, one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride. As an example, the material of the interlayer dielectric layer 570 is silicon oxide.

[0155] In this embodiment, Figures 17 to 18 As shown, after forming the second source-drain doping layer 562 , the second source-drain doping layer 562 and the first source-drain doping layer 562 constitute a source-drain doping layer 563 , and before forming the interlayer dielectric layer 570 , the formation method further includes: forming a sacrificial layer 535 on the side wall of the gate structure 520 .

[0156] The sacrificial layer 535 is used to occupy a space position for the subsequent formation of the first air spacer, and is also used as a self-aligned spacer layer in the subsequent process of forming the source-drain interconnection layer.

[0157] Specifically, the process of forming the sacrificial layer 535 includes an atomic layer deposition process.

[0158] The use of an atomic layer deposition process to form the sacrificial layer 535 is beneficial to improving the thickness uniformity of the sacrificial layer 535 , thereby improving the thickness uniformity of the first air sidewalls formed subsequently.

[0159] It should be noted that the material of the sacrificial layer 535 includes one or more of amorphous silicon, amorphous carbon and silicon nitride. As an example, the material of the sacrificial layer 535 includes amorphous silicon.

[0160] Amorphous silicon is a commonly used material in deposition processes, and has the characteristics of simple process and low cost. At the same time, amorphous silicon has a stable structure and is not prone to deformation or stress, and its impact on the semiconductor structure is greatly reduced. In the subsequent process of removing the sacrificial layer 535, the higher etching selectivity between the material selected for the sacrificial layer 535 and the material selected for the interlayer dielectric layer 570 can be utilized to achieve the purpose of removing the sacrificial layer 535.

[0161] It should also be noted that after forming the second source-drain doping layer 562 and before forming the sacrificial layer 535, it also includes: forming a contact etch stop layer (CESL) 536 covering the top of the source-drain doping layer 563, and the contact etch stop layer 536 also covers the side walls and top of the gate structure 520, and the top of the first isolation structure 550.

[0162] The contact etch stop layer 536 is used to increase the stress of the source-drain doping layer 563 , and the contact etch stop layer 536 is also used as an initial etch stop position in the subsequent process of forming a source-drain interconnection layer.

[0163] It is also necessary to explain that the thickness of the sacrificial layer 535 should not be too small or too large. If the thickness of the sacrificial layer 535 is too small, it is easy to increase the difficulty of subsequently removing the sacrificial layer 535 and forming the first air sidewall; if the thickness of the sacrificial layer 535 is too large, it is easy to reduce the effect of subsequent film layers formed in the first air sidewall. Therefore, in this embodiment, the thickness of the sacrificial layer 535 ranges from 10 angstroms to 30 angstroms.

[0164] refer to Fig. 22 , and combined with reference Fig.21 In the NMOS region 502, a second isolation structure 555 is formed at a location of a portion of the gate structure 520, and the second isolation structure 555 extends into the fin 510 (eg, Fig. 22 shown).

[0165] It should be noted that in order to clearly show the semiconductor structure, Fig. 22 Only the NMOS region is shown in FIG.

[0166] The second isolation structure 555 is a single diffusion isolation structure. The second isolation structure 555 is located at a portion of the gate structure 520 and is used to achieve electrical isolation between adjacent portions of the second source-drain doping layers 562 to prevent bridging between adjacent devices.

[0167] Compared with the solution of forming the first isolation structure in both the PMOS region and the NMOS region, the embodiment of the present invention forms a first isolation structure 550 in the fin 510 between adjacent gate structures 520 to be isolated in the PMOS region 501, and in the NMOS region 502, a second isolation structure 555 is formed at the position of part of the gate structure 520, and the second isolation structure 555 extends into the fin 510, that is, the second isolation structure 555 extending into the fin 510 is formed at the position of part of the gate structure 520 in the NMOS region 502, which is beneficial to saving the area of ​​the semiconductor structure.

[0168] It is understandable that the second isolation structure 555 spans across the fin 510 on the side of the gate structure 520 and is arranged in parallel with the gate structure 520 . Accordingly, the second source-drain doped layer 562 is also located on both sides of the second isolation structure 555 .

[0169] Specifically, the steps of forming the second isolation structure 555 include: in the NMOS region 502, removing part of the gate structure 520 and part of the fin 510 at the bottom of the gate structure 520, forming a second groove (not shown) in the interlayer dielectric layer 570; and forming a second isolation structure 555 in the second groove.

[0170] Firstly forming the second groove in the interlayer dielectric layer 570 and then forming the second isolation structure 555 in the second groove is helpful to reduce the difficulty of forming the second isolation structure 555 .

[0171] It should be noted that in the NMOS region 502, a second isolation structure 555 is formed at the position of a portion of the gate structure 520, and the second isolation structure 555 extends into the fin 510 to achieve electrical isolation between adjacent second source-drain doping layers 562. It can be understood that the bottom of the second isolation structure 555 is lower than the bottom of the fin 510, which makes it easy for the second isolation structure 555 to have a better isolation effect.

[0172] Correspondingly, in the NMOS region 502 , in the process of removing a portion of the gate structure 520 and a portion of the fin 510 at the bottom of the gate structure 520 , the second portion of the thickness of the substrate 500 is also removed.

[0173] It should also be noted that the material of the second isolation structure 555 is a dielectric material.

[0174] In this embodiment, after forming the interlayer dielectric layer 570 and before forming the second groove, the forming method further includes: removing the dummy gate structure 521, and forming a device gate structure 523 at the position of the dummy gate structure 521 ( Fig.21 shown).

[0175] Specifically, the device gate structure 523 includes a gate dielectric layer (not shown) and a gate electrode layer (not shown) covering the gate dielectric layer.

[0176] The device gate structure 523 is used to form a field effect transistor with the conductive channel and the source-drain doped layer 563 .

[0177] The gate dielectric layer is used to isolate the gate electrode layer from the conductive channel.

[0178] The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3.

[0179] In this embodiment, the device gate structure 523 is a metal gate structure, and therefore, the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC. The gate electrode layer includes a work function layer and an electrode layer covering the work function layer, or may only include the work function layer.

[0180] Correspondingly, the gate dielectric layer includes a high-k gate dielectric layer. The material of the high-k gate dielectric layer is a high-k dielectric material, and the high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than the relative dielectric constant of silicon oxide. Specifically, the material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3. As an example, the material of the high-k gate dielectric layer is HfO2.

[0181] In other embodiments, the device gate structure may also be a polysilicon gate structure.

[0182] It should be noted that, in the process of removing the dummy gate structure 521 , the contact etching stop layer 536 on the top of the dummy gate structure 521 is correspondingly removed.

[0183] Accordingly, in this embodiment, in the step of forming the second groove, the device gate structure 523 at the location of a portion of the dummy gate structure 521 is removed.

[0184] refer to Figure 23 to Figure 26 In this embodiment, after forming the second isolation structure 555, the forming method further includes: forming a source-drain interconnection layer 565 electrically connected to the source-drain doping layer 563 in the interlayer dielectric layer 570 on the top of the source-drain doping layer 563, wherein the source-drain interconnection layer 565 covers the sidewall of the sacrificial layer 535; after forming the source-drain interconnection layer 565, removing the sacrificial layer 535 to form a first air sidewall 571 (such as Figure 25 to Figure 26 shown).

[0185] in, Fig.26 for Fig.25 A partial enlarged view of area B.

[0186] It should be noted that in order to clearly show the semiconductor structure, Figure 23 to Figure 25 Only the NMOS region is shown in FIG.

[0187] The source-drain interconnection layer 565 is electrically connected to the source-drain doping layer 563 to achieve electrical connection between the source-drain doping layer 563 and an external circuit.

[0188] Since the dielectric constant of air is smaller than that of dielectric materials, the first air spacer 571 is helpful to reduce the parasitic capacitance between the gate structure 520 and the source-drain interconnection layer 565 , thereby improving the performance of the semiconductor structure.

[0189] It can be understood that after the source-drain interconnection layer 565 is formed, the sacrificial layer 535 is removed to form a first air sidewall 571 located between the source-drain interconnection layer 565 and the gate structure 520, that is, after the sacrificial layer 535 is removed and the first air sidewall 571 is formed, the first air sidewall 571 exposes the sidewall of the source-drain interconnection layer 165.

[0190] Specifically, the step of forming the source-drain interconnection layer 565 includes: using the sacrificial layer 535 as a self-aligned sidewall, forming a third groove 566 in the interlayer dielectric layer 570 on the top of the source-drain doped layer 563, the third groove 566 exposing the source-drain doped layer 563 (such as Fig.23 565 (as shown); forming a source-drain interconnection layer 565 in the third groove 566 Fig.24 shown).

[0191] A third groove 566 is formed in the interlayer dielectric layer 570 at the top of the source-drain doped layer 563 with the sacrificial layer 535 as the self-aligned sidewall. This helps reduce the probability of other film layers (such as the device gate structure 523, the sidewall structure 530, etc.) being damaged during the formation of the third groove 566, and improves the position accuracy, size accuracy and morphology accuracy of the third groove 566, thereby improving the quality of the source-drain interconnection layer 565. Moreover, the third groove 566 is first formed in the interlayer dielectric layer 570 at the top of the source-drain doped layer 563, and then the source-drain interconnection layer 565 is formed in the third groove 566, which helps reduce the difficulty of forming the source-drain interconnection layer 565.

[0192] More specifically, the step of forming the third groove 566 in the interlayer dielectric layer 570 on top of the source-drain doped layer 563 includes: forming a patterned second mask structure 542 on the device gate structure 523 and the interlayer dielectric layer 570, the second mask structure 542 having a second mask opening 5421 located above the source-drain doped layer 563; removing the second mask structure 542, the interlayer dielectric layer 570, and the contact etch stop layer 536 at the bottom of the mask opening 5421 along the second mask opening 5421 to expose the source-drain doped layer 563 to form the third groove 566; after the third groove 566 is formed, removing the second mask structure 542.

[0193] The contact etch stop layer 536 may be used as the initial stop position to first form an initial third groove (not shown), and then the contact etch stop layer 536 at the bottom of the initial third groove may be removed along the initial third groove to form a third groove 566 .

[0194] In a specific embodiment, the second mask structure 542 includes a metal hard mask layer 5422. The sacrificial layer 535 is beneficial for reducing the probability of other film layers (such as the device gate structure 523) being damaged during the process of removing the metal hard mask layer 5422.

[0195] It should be noted that the third groove 566 is formed in the interlayer dielectric layer 570 on the top of the source / drain doped layer 563 by an anisotropic dry etching process with the sacrificial layer 535 as the self-aligned sidewall. As an example, the etching selectivity ratio of the sacrificial layer 535 to the interlayer dielectric layer 570 is greater than 8.

[0196] In other embodiments, in the step of removing the sacrificial layer and forming a first air spacer between the source-drain interconnect layer and the gate structure, the contact etch stop layer covering the sidewall of the gate structure is also removed.

[0197] In this embodiment, the process of removing the sacrificial layer 535 includes an anisotropic etching process.

[0198] The anisotropic etching characteristic has anisotropic characteristics, so the etching accuracy is high, the cross-section control is better, and it is beneficial to improve the quality of the first air sidewall 571. As an example, the anisotropic etching process includes an anisotropic dry etching process.

[0199] Specifically, the etching selectivity ratio between the sacrificial layer 535 and the interlayer dielectric layer 570 is greater than 8.

[0200] In this embodiment, after the source-drain interconnection layer 565 is formed, the first spacer layer 531 is removed to form a second air spacer 572 located between the gate structure 520 and the remaining spacer structure 530 .

[0201] The second air spacer 572 is beneficial to further reduce the parasitic capacitance between the gate structure 520 and the source-drain interconnection layer 565 , thereby improving the performance of the semiconductor structure.

[0202] In other embodiments, the sidewall structure may be a single-layer structure, and the sidewall structure only includes a first sidewall layer located on the sidewall of the gate structure; accordingly, after the source-drain interconnection layer is formed, the first sidewall layer is removed to form a first air sidewall and a second air sidewall that are interconnected. In other embodiments, after the source-drain interconnection layer is formed, the first sidewall layer may also be retained.

[0203] refer to Fig. 27 After the second air sidewall 572 is formed, a sealing layer 580 is formed on the top of the first air sidewall 571 and the second air sidewall 572 to seal the first air sidewall 571 and the second air sidewall 572 .

[0204] It should be noted that the process of forming the sealing layer 580 on the top of the first air sidewall 571 and the second air sidewall 572 includes plasma chemical vapor deposition (PCVD), and the gap filling performance of the plasma chemical deposition process is poor, and it is easy to seal the top of the first air sidewall 571 and the second air sidewall 572. In other embodiments, the process of forming the sealing layer on the top of the first air sidewall and the second air sidewall may also include other suitable chemical vapor deposition processes.

[0205] It should also be noted that the material of the sealing layer 580 includes a dielectric material. As an example, the material of the sealing layer 580 is silicon nitride.

[0206] It should be noted that the semiconductor structure can be formed by the formation method described in the above embodiment, or by other formation methods. For the specific description of the semiconductor structure described in this embodiment, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0207] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, the substrate comprising a PMOS region and an NMOS region, and having discrete fins formed thereon; A gate structure, located on the substrate and across the fin, the gate structure covering a portion of the top and a portion of the sidewall of the fin; A first isolation structure is located in the PMOS region and in a fin between adjacent gate structures to be isolated; A second isolation structure is located in the NMOS region, the second isolation structure spans the fin portion on the side of the gate structure and is arranged in parallel with the gate structure, and the bottom of the second isolation structure extends into the fin portion; A first source-drain doped layer is located in the fins on both sides of the gate structure of the PMOS region; The second source-drain doped layer is located in the fins on both sides of the gate structure of the NMOS region.

2. The semiconductor structure according to claim 1, wherein: The material of the first isolation structure includes graphene.

3. The semiconductor structure according to claim 1, wherein: The semiconductor structure further comprises: The interlayer dielectric layer covers the top of the first source-drain doped layer and the second source-drain doped layer, and the interlayer dielectric layer also covers the sidewall of the gate structure, the top of the first isolation structure, and the sidewall of the second isolation structure.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The gate structure is a device gate structure.

5. The semiconductor structure according to claim 3, wherein: The semiconductor structure further comprises: A source-drain interconnection layer, located in the interlayer dielectric layer on the top of the first source-drain doped layer and the top of the second source-drain doped layer, and electrically connected to the first source-drain doped layer and the second source-drain doped layer respectively; The first air sidewall is located between the source-drain interconnection layer and the gate structure.

6. The semiconductor structure according to claim 5, characterized in that The semiconductor structure further comprises: A sidewall structure, located on the substrate and spanning the fin, the sidewall structure being arranged opposite to a sidewall of the gate structure; The second air spacer is located between the gate structure and the spacer structure.

7. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a PMOS region and an NMOS region, and having discrete fins formed on the substrate; forming a gate structure across the fin on the substrate, wherein the gate structure covers a portion of the top and a portion of the sidewall of the fin; In the PMOS region, forming a first isolation structure in a fin portion between adjacent gate structures to be isolated; After forming the first isolation structure, forming a first source-drain doped layer in the fins on both sides of the gate structure of the PMOS region; forming a second source-drain doped layer in the fins on both sides of the gate structure of the NMOS region; In the NMOS region, a second isolation structure is formed at a location of a portion of the gate structure, and the second isolation structure extends into the fin.

8. The method for forming a semiconductor structure according to claim 7, wherein: The step of forming the first isolation structure comprises: In the PMOS region, forming a first groove in a fin portion between adjacent gate structures to be isolated; A first isolation structure is formed in the first groove.

9. The method for forming a semiconductor structure according to claim 8, wherein: Before forming the first groove, the forming method further includes: forming source and drain grooves in the fins on both sides of the gate structure of the PMOS region; The step of forming the first groove includes: removing the fin portion at the bottom of the source-drain groove between adjacent gate structures to be isolated to form the first groove.

10. The method for forming a semiconductor structure according to claim 8 or 9, characterized in that: The step of forming the first groove comprises: Forming a first mask structure covering the fin and the top of the gate structure, wherein a first mask opening is formed in the first mask structure, and the first mask opening is located above the fin between adjacent gate structures to be isolated; removing the first mask structure at the bottom of the first mask opening and a portion of the thickness of the fin along the first mask opening to form a first groove; The forming method further includes: removing the first mask structure.

11. The method for forming a semiconductor structure according to claim 10, wherein: In the step of forming the first isolation structure, the first isolation structure is formed under the protection of the first mask structure; After forming the first isolation structure, the first mask structure is removed.

12. The method for forming a semiconductor structure according to claim 9, wherein: The step of forming the first source-drain doped layer includes: after forming the first isolation structure, forming the first source-drain doped layer in the remaining source-drain grooves of the PMOS region.

13. The method for forming a semiconductor structure according to claim 8, wherein: The process of forming the first isolation structure in the first groove includes a dielectric-on-dielectric selective deposition process.

14. The method for forming a semiconductor structure according to claim 13, wherein: After forming the first groove and before forming the first isolation structure, the forming method further includes: performing oxidation treatment on the surface of the first groove; After the oxidation treatment, a first isolation structure is formed in the first groove.

15. The method for forming a semiconductor structure according to claim 7, wherein: After forming the second source-drain doped layer and before forming the second isolation structure, the forming method further includes: forming an interlayer dielectric layer covering the top of the source-drain doped layer, wherein the interlayer dielectric layer also covers the sidewall of the gate structure and the top of the first isolation structure; The step of forming the second isolation structure includes: in the NMOS region, removing part of the gate structure and the fin at the bottom of the part of the gate structure, forming a second groove in the interlayer dielectric layer; and forming a second isolation structure in the second groove.

16. The method for forming a semiconductor structure according to claim 15, wherein: In the step of forming a gate structure across the fin on the substrate, the gate structure is a dummy gate structure; After forming the interlayer dielectric layer and before forming the second groove, the forming method further comprises: removing the dummy gate structure and forming a device gate structure at the position of the dummy gate structure; In the step of forming the second groove, the device gate structure at the location of a portion of the dummy gate structure is removed.

17. The method for forming a semiconductor structure according to claim 7, wherein: After forming the second source-drain doped layer, the second source-drain doped layer and the first source-drain doped layer constitute a source-drain doped layer, and before forming the second isolation structure, the forming method further includes: forming an interlayer dielectric layer covering the top of the source-drain doped layer, the interlayer dielectric layer also covering the sidewall of the gate structure and the top of the first isolation structure; After forming the second source-drain doped layer, the second source-drain doped layer and the first source-drain doped layer constitute a source-drain doped layer, and before forming the interlayer dielectric layer, the forming method further includes: forming a sacrificial layer on the sidewall of the gate structure; After forming the second isolation structure, the formation method also includes: forming a source-drain interconnection layer electrically connected to the source-drain doped layer in the interlayer dielectric layer on top of the source-drain doped layer, the source-drain interconnection layer covering the side wall of the sacrificial layer; after forming the source-drain interconnection layer, removing the sacrificial layer to form a first air sidewall located between the source-drain interconnection layer and the gate structure.

18. The method for forming a semiconductor structure according to claim 17, wherein: The step of forming the source-drain interconnection layer comprises: Using the sacrificial layer as a self-aligned sidewall, a third groove is formed in the interlayer dielectric layer on top of the source-drain doped layer, wherein the third groove exposes the source-drain doped layer; A source-drain interconnection layer is formed in the third groove.

19. The method for forming a semiconductor structure according to claim 17 or 18, wherein: After forming the gate structure and before forming the first isolation structure, the forming method further comprises: forming a sidewall structure on the sidewall of the gate structure, wherein the sidewall structure comprises a first sidewall layer closest to the gate structure; After the source-drain interconnection layer is formed, the first spacer layer is removed to form a second air spacer between the gate structure and the remaining spacer structure.

20. The method for forming a semiconductor structure according to claim 17, wherein: The process of forming the sacrificial layer includes an atomic layer deposition process.

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