Array substrate and display panel

Abstract

The invention provides an array substrate and a display panel, and the array substrate comprises a groove, and the pattern corresponding to the longitudinal section of the groove is in a circular arc shape; the thin film transistor comprises an active pattern, the active pattern comprises a first connecting part, a middle part and a second connecting part, the middle part is connected between the first connecting part and the second connecting part, the middle part is arranged in the groove, and the pattern corresponding to the longitudinal section of the middle part is in a circular arc shape; the grid electrode is arranged corresponding to the middle part; and the source and drain electrode comprises a source electrode and a drain electrode, the source electrode is in contact with the first connecting part, and the drain electrode is in contact with the second connecting part. According to the invention, the middle part of the active pattern is arranged in the groove, and the pattern corresponding to the longitudinal section of the groove is arc-shaped, so that the size of the middle part of the active pattern is ensured, the performance of the thin film transistor is ensured, the area occupied by the thin film transistor is reduced, and the aperture ratio of the display panel is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] With the continuous development of the panel industry, higher and higher requirements are put forward for display panels to have narrow borders, high aperture ratio, high brightness, high resolution and other functions, resulting in new challenges in the manufacture of display panels. The display panel includes multiple thin film transistors, which include metals, and the metals reduce the aperture ratio of the display panel.

[0003] Therefore, it is necessary to propose a technical solution to solve the problem that the aperture ratio of the display panel is reduced due to the thin film transistor. Summary of the invention

[0004] The purpose of the present application is to provide an array substrate and a display panel, which can ensure the performance of thin film transistors on the array substrate while improving the resolution of the display panel.

[0005] To achieve the above purpose, the technical solution is as follows:

[0006] An array substrate, comprising:

[0007] A groove, wherein the shape corresponding to the longitudinal section of the groove is an arc shape; and

[0008] At least one thin film transistor, the thin film transistor comprising:

[0009] an active pattern, comprising a first connection portion, a middle portion and a second connection portion, wherein the middle portion is connected between the first connection portion and the second connection portion, the middle portion is disposed in the groove, and a longitudinal section of the middle portion corresponds to a circular arc shape;

[0010] a gate, arranged corresponding to the middle portion; and

[0011] The source-drain electrode comprises a source electrode and a drain electrode, wherein the source electrode contacts the first connection portion, and the drain electrode contacts the second connection portion.

[0012] In the above array substrate, the shape corresponding to the longitudinal section of the groove is a semicircular arc, and the shape corresponding to the cross section of the groove is a rectangle.

[0013] In the above array substrate, the radius corresponding to the arc shape is 2 micrometers to 10 micrometers.

[0014] In the above array substrate, the array substrate further includes:

[0015] substrate; and

[0016] A buffer layer is disposed on the substrate;

[0017] Wherein, at least one of the thin film transistors is disposed on a side of the buffer layer away from the substrate, and the groove is disposed on at least one of the substrate and the buffer layer.

[0018] In the above array substrate, the active pattern is arranged on a side of the buffer layer away from the substrate, the gate is arranged on a side of the active pattern away from the substrate, and the source-drain electrode is arranged on a side of the gate away from the active pattern. The array substrate further includes:

[0019] a gate insulating layer disposed between the active pattern and the gate and covering the buffer layer and the active pattern; and

[0020] An interlayer insulating layer, disposed between the gate and the source-drain electrode, and covering the gate insulating layer and the gate;

[0021] The source electrode contacts the first connection portion through a first contact hole penetrating the interlayer insulating layer and the gate insulating layer, and the drain electrode contacts the second connection portion through a second contact hole penetrating the interlayer insulating layer and the gate insulating layer.

[0022] In the above array substrate, the array substrate further includes:

[0023] a planarization layer, disposed on a side of the source / drain electrode away from the interlayer insulating layer, and covering the source / drain electrode and the interlayer insulating layer;

[0024] A first electrode is disposed on a side of the planarization layer away from the source and drain electrodes;

[0025] a passivation layer, disposed on a side of the first electrode away from the planarization layer; and

[0026] A second electrode is disposed on a side of the passivation layer away from the first electrode;

[0027] Wherein, one of the first electrode and the second electrode is electrically connected to the drain.

[0028] In the above array substrate, the thickness of the planarization layer is greater than or equal to 2.5 micrometers and less than or equal to 5 micrometers.

[0029] In the above array substrate, the planarization layer, the interlayer insulating layer and the gate insulating layer all include a recessed portion corresponding to the groove.

[0030] In the above array substrate, a dimension of the middle portion along a circumferential direction of the middle portion is larger than a dimension of the first connection portion and the second connection portion in a direction from the second connection portion to the first connection portion.

[0031] A display panel comprises the above array substrate.

[0032] Beneficial effects: The present application provides an array substrate and a display panel, wherein the middle portion of the active pattern is arranged in a groove, and the figure corresponding to the longitudinal section of the groove is an arc shape, and the figure corresponding to the longitudinal section of the middle portion is an arc shape, so as to ensure the size of the middle portion of the active pattern and thus the performance of the thin film transistor, while being conducive to reducing the area occupied by the thin film transistor, thereby improving the aperture ratio of the display panel. Moreover, the figure corresponding to the longitudinal section of the groove is an arc shape, which can maximize the size of the middle portion of the active pattern while reducing the size of the thin film transistor compared to grooves of other shapes. In addition, the figure corresponding to the longitudinal section of the groove is an arc shape, so that the stresses in various places of the middle portion are the same, reducing the risk of fracture of the middle portion of the active pattern. In addition, compared to the planar active layer, the projection area of ​​the middle portion of the present application is small, which is conducive to reducing the light intensity per unit area on the middle portion, and is conducive to omitting the design of the light shielding layer, thereby reducing the number of processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 This is a schematic diagram of an array substrate according to a first embodiment of the present application;

[0034] Figure 2 for Figure 1 A schematic diagram of a buffer layer in the array substrate shown;

[0035] Figure 3 for Figure 1 A schematic top view of an active pattern in the array substrate shown;

[0036] Figure 4 This is a schematic diagram of an array substrate according to a second embodiment of the present application;

[0037] Figure 5 A schematic diagram of an array substrate of a comparative example of the present application;

[0038] Figure 6 It is a schematic diagram of a display panel according to an embodiment of the present application. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0040] See also Figure 1 , which is a schematic diagram of an array substrate 10 according to a first embodiment of the present application. The array substrate 10 includes a substrate 101, a buffer layer 102, at least one thin film transistor T, a planarization layer 108, a first electrode 109, a passivation layer 110 and a second electrode 111.

[0041] In this embodiment, the substrate 101 is a glass substrate, and the thickness of the glass substrate is 0.3 mm-0.5 mm.

[0042] In this embodiment, the buffer layer 102 is used to prevent impurities in the substrate 101 from entering the thin film transistor T, so as to prevent the impurities from affecting the electrical properties of the thin film transistor T. The buffer layer 102 is disposed on the substrate 101, and the buffer layer 102 includes at least one groove 10a, the depth of the groove 10a is less than the thickness of the buffer layer 102, and the figure corresponding to the longitudinal section of the groove 10a is an arc shape, and the arc corresponding to the arc shape is greater than 90 degrees and less than or equal to 180 degrees, for example, 120 degrees, 150 degrees or 180 degrees. The thickness of the buffer layer 102 is 2 microns to 5 microns. The buffer layer 102 includes an organic insulating layer and an inorganic insulating layer, the thickness of the organic insulating layer is 1 micron to 3 microns, and the thickness of the inorganic insulating layer is 0.1 micron to 0.5 microns. The organic insulating layer is a polyimide layer. The preparation material of the inorganic insulating layer is selected from at least one of silicon nitride and silicon oxide layers.

[0043] Specifically, Figure 2 As shown, the buffer layer 102 includes a first inorganic insulating layer 1021, an organic layer 1022 and a second inorganic insulating layer 1023. The first inorganic insulating layer 1021 is disposed on the substrate 101, the organic layer 1022 is disposed on the first inorganic insulating layer 1021, and the second inorganic insulating layer 1023 is disposed on the organic layer 1022. The groove 10a runs through the second inorganic insulating layer 1023 and the organic layer 1022. The longitudinal section of the groove 10a corresponds to a semicircular arc shape, and the cross section of the groove 10a corresponds to a rectangular shape, that is, the three-dimensional configuration of the groove 10a is columnar.

[0044] In this embodiment, the radius corresponding to the arc shape is 2 microns to 10 microns, so as to provide sufficient space for setting the active pattern of the thin film transistor T, so that the channel size of the active pattern meets the basic performance requirements of the thin film transistor. When the figure corresponding to the longitudinal section of the groove 10a is a semicircular arc, the maximum depth of the groove 10a is equal to the radius corresponding to the arc shape. For example, the radius corresponding to the arc shape is 2 microns, 3 microns, 4 microns, 5 microns, 6 microns, 7 microns or 8 microns.

[0045] In this embodiment, at least one thin film transistor T is disposed on a side of the buffer layer 102 away from the substrate 101 , and each thin film transistor T includes an active pattern 103 , a gate 105 , source and drain electrodes, a gate insulating layer 104 and an interlayer insulating layer 106 .

[0046] In this embodiment, combined with Figure 1 and Figure 3 , the active pattern 103 is arranged on the side of the buffer layer 102 away from the substrate 101. The active pattern 103 includes a first connection portion 1034, an intermediate portion 103a and a second connection portion 1035. The intermediate portion 103a is connected between the first connection portion 1034 and the second connection portion 1035. The intermediate portion 103a is arranged in the groove 10a, and the figure corresponding to the longitudinal section of the intermediate portion 103a is an arc shape. The first connection portion 1034 and the second connection portion 1035 are arranged outside the groove 10a of the buffer layer 102. The orthographic projections of the intermediate portion 103a, the first connection portion 1034 and the second connection portion 1035 on the substrate are all rectangular. The size of the intermediate portion 103a along the circumferential direction of the intermediate portion 103a is greater than the size of the first connection portion 1034 and the second connection portion 1035 in the direction from the second connection portion 1035 to the first connection portion 1034. For example, along the circumferential direction of the middle portion 103a, the size of the middle portion 103a is 4 microns to 8 microns. In the direction from the second connection portion 1035 to the first connection portion 1034, the size of the first connection portion 1034 and the second connection portion 1035 is 2 microns to 4 microns. The active pattern 103 is made of low temperature polysilicon. It is understood that the active pattern 103 can also be made of metal oxide.

[0047] The middle portion 103a includes a first lightly doped portion 1032, a second lightly doped portion 1033 and a channel portion 1031, the channel portion 1031 is connected between the first lightly doped portion 1032 and the second lightly doped portion 1033, the first lightly doped portion 1032 is connected between the first connecting portion 1034 and the channel portion 1031, the second lightly doped portion 1033 is connected between the second connecting portion 1035 and the channel portion 1031, and the orthographic projections of the first lightly doped portion 1032, the second lightly doped portion 1033 and the channel portion 1031 on the substrate 101 are all rectangular. Along the circumferential direction of the middle portion 103a, the size of the channel portion 1031 is larger than the size of the first lightly doped portion 1032 and the size of the second lightly doped portion 1033. The doping concentration of the first connection portion 1034 and the second connection portion 1035 is greater than the doping concentration of the first lightly doped portion 1032 and the second lightly doped portion 1033 , so that the conductivity of the first connection portion 1034 and the second connection portion 1035 is stronger than the conductivity of the first lightly doped portion 1032 and the second lightly doped portion 1033 .

[0048] In this embodiment, the gate 105 is disposed on a side of the active pattern 103 away from the substrate 101, and the gate 105 is disposed corresponding to the middle portion 103a. The longitudinal section of the gate 105 is also arc-shaped, and the orthographic projection of the gate 105 on the substrate 101 is rectangular. The orthographic projection of the gate 105 on the substrate 101 completely overlaps with the orthographic projection of the middle portion 103a on the substrate 101. The material for preparing the gate 105 is selected from at least one of molybdenum, aluminum, titanium, copper, and silver.

[0049] In this embodiment, the gate insulating layer 104 is disposed between the active pattern 103 and the gate 105, and covers the buffer layer 102 and the active pattern 103. The thickness of the gate insulating layer 104 is 800 angstroms to 2500 angstroms. The gate insulating layer 104 is made of at least one of silicon nitride or silicon oxide. Since the gate insulating layer 104 is relatively thin and the depth of the groove 10a is relatively deep, the gate insulating layer 104 includes a first recessed portion corresponding to the groove 10a.

[0050] In this embodiment, the source-drain electrode is disposed on a side of the gate 105 away from the active pattern 103. The source-drain electrode includes a source electrode 1071 and a drain electrode 1072, the source electrode 1071 contacts the first connection portion 1034, and the drain electrode 1072 contacts the second connection portion 1035. The source-drain electrode is made of at least one of molybdenum, aluminum, titanium, copper, and silver.

[0051] In this embodiment, the interlayer insulating layer 106 is disposed between the gate 105 and the source-drain electrode, and covers the gate insulating layer 104 and the gate 105. The thickness of the interlayer insulating layer 106 is 3000 angstroms to 6000 angstroms. The preparation material of the insulating layer of the gate 105 is at least one of silicon nitride or silicon oxide. Since the thickness of the interlayer insulating layer 106 is relatively thin and the depth of the groove 10a is relatively deep, the interlayer insulating layer 106 includes a second recessed portion corresponding to the groove 10a.

[0052] In this embodiment, the source 1071 contacts the first connection portion 1034 through a first contact hole 10b penetrating the interlayer insulating layer 106 and the gate insulating layer 104 , and the drain 1072 contacts the second connection portion 1035 through a second contact hole 10c penetrating the interlayer insulating layer 106 and the gate insulating layer 104 .

[0053] In this embodiment, the planarization layer 108 is arranged on the side of the source-drain electrode away from the interlayer insulating layer 106, and covers the source-drain electrode and the interlayer insulating layer 106. The planarization layer 108 includes a third recessed portion for the groove 10a. Compared with the conventional technology, in order to make the groove 10a more flat, the thickness of the planarization layer 108 in this embodiment is increased, and the thickness of the planarization layer 108 is greater than or equal to 2.5 microns and less than or equal to 5 microns, so that the surface formed with at least one thin film transistor T is flat, which is conducive to the subsequent formation of the first electrode 109 and the second electrode 111. The first electrode 109 and the second electrode 111 can be formed on a flat surface to avoid affecting the direction of the electric field formed between the first electrode 109 and the second electrode 111. For example, the thickness of the planarization layer 108 is 3 microns, 4 microns or 5 microns. The material for preparing the planarization layer 108 is polyimide or acrylate.

[0054] In this embodiment, the first electrode 109 is disposed on a side of the planarization layer 108 away from the source and drain electrodes. The first electrode 109 is a common electrode, and the entire surface of the first electrode 109 is formed on the planarization layer 108. It can be understood that the first electrode 109 can also be a pixel electrode. The preparation material of the first electrode 109 is at least one of indium tin oxide or indium zinc oxide.

[0055] In this embodiment, the passivation layer 110 is disposed on a side of the first electrode 109 away from the planarization layer 108. The passivation layer 110 is an inorganic insulating layer. The passivation layer 110 is made of at least one of silicon nitride and silicon oxide.

[0056] In this embodiment, the second electrode 111 is disposed on a side of the passivation layer 110 away from the first electrode 109. The second electrode 111 is a pixel electrode, and the second electrode 111 contacts the drain electrode 1072 through a third contact hole 10d penetrating the passivation layer 110, the first electrode 109, and the planarization layer 108. The preparation material of the second electrode 111 is at least one of indium tin oxide or indium zinc oxide. If the first electrode 109 is a pixel electrode, the second electrode 111 is a common electrode, and the first electrode 109 contacts the drain electrode 1072 through a contact hole penetrating the planarization layer 108.

[0057] In this embodiment, the array substrate is arranged in a groove through the middle part of the active pattern. The figure corresponding to the longitudinal section of the groove is an arc shape, and the figure corresponding to the longitudinal section of the middle part is an arc shape. This ensures that the size of the middle part of the active pattern is large, thereby ensuring the performance of the thin film transistor, which is beneficial to reduce the area occupied by the thin film transistor, thereby improving the aperture ratio of the display panel.

[0058] See also Figure 4 , a schematic diagram of an array substrate according to a second embodiment of the present application. Figure 4 The array substrate 10 and Figure 1 The array substrate 10 shown is similar, except that the groove 10a is disposed on the substrate 101, and the buffer layer 102 includes a fourth recessed portion corresponding to the groove 10a. At this time, the thickness of the buffer layer 102 is 2500 angstroms-3000 angstroms.

[0059] Relative to Figure 1 The array substrate 10 shown, Figure 4 The array substrate 10 shown is provided with a groove 10 a on the substrate 101 , which is beneficial to thinning the thickness of the buffer layer 102 , thereby ensuring the thickness of the array substrate 10 .

[0060] It should be noted that, in addition to Figure 1 and Figure 4 In the array substrate 10 shown, the groove 10a can penetrate both the buffer layer 102 and the substrate 101. The groove 10a can be obtained by etching using a half-tone mask combined with a yellow light process, which will not be described in detail here.

[0061] like Figure 5 As shown, it is a schematic diagram of an array substrate of a comparative example of the present application. Figure 5 The array substrate 40 is Figure 1 The array substrate 10 shown is basically similar, except that the figure corresponding to the longitudinal section of the groove 40a is a broken line, which includes a first hypotenuse, a second hypotenuse and a bottom edge, the first hypotenuse and the second hypotenuse are two waist edges of an inverted isosceles trapezoid, and the bottom edge is the bottom edge of an inverted isosceles trapezoid.

[0062] In the comparative example, when the figure corresponding to the longitudinal section of the groove 40a is a broken line, when the middle part of the active pattern is formed in the groove 40a, the active pattern is easily broken at the corner of the groove 40a. The figure corresponding to the longitudinal section of the groove 10a of the present application is an arc shape, the curvature of the arc shape is equal everywhere and the bottom surface is smooth, so that the stress on each part of the middle part 103a is the same, reducing the risk of the middle part 103a of the active pattern 103 breaking. In addition, when the middle part of the active pattern has the same projected length on the substrate, when the figure corresponding to the longitudinal section of the groove 40a is a broken line, the length of the middle part set in the groove 40a is less than the size of the middle part set in the groove 10a when the figure corresponding to the longitudinal section of the groove 10a is a semicircular arc. Therefore, the figure corresponding to the longitudinal section of the groove 10a is a semicircular arc, which is more conducive to ensuring the size of the middle part of the active pattern while reducing the area occupied by the thin film transistor. In addition, compared to when the longitudinal section of the groove 40a is a broken line, the middle part of the active pattern is located on a plane, resulting in a greater light intensity received therein. The projection area of ​​the middle part 103a arranged in the groove 10a of the present application is small, which is beneficial to reducing the light intensity per unit area on the middle part 103a, and is beneficial to omitting the design of the shading layer, thereby reducing the number of processes.

[0063] like Figure 6 As shown, the present application also provides a display panel, the display panel 30 includes an array substrate 10 and a color filter substrate 20, the array substrate 10 and the color filter substrate 20 are arranged opposite to each other, and a liquid crystal layer is arranged between the array substrate 10 and the color filter substrate 20.

[0064] In the present embodiment, the array substrate of the display panel is arranged in a groove through the middle part of the active pattern. The figure corresponding to the longitudinal section of the groove is an arc shape, and the figure corresponding to the longitudinal section of the middle part is an arc shape. This ensures the size of the middle part of the active pattern and thus the performance of the thin film transistor, while helping to reduce the area occupied by the thin film transistor, thereby improving the aperture ratio and resolution of the display panel.

[0065] The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technical personnel in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate, characterized in that: include: substrate; A groove is located on the substrate, and a groove wall of the groove includes an arc surface; as well as At least one thin film transistor, located on the substrate, and comprising: an active pattern, comprising a first connecting portion, a middle portion and a second connecting portion, wherein the middle portion is connected between the first connecting portion and the second connecting portion, and the middle portion is disposed on the arc surface of the groove; and The gate is arranged corresponding to the middle portion.

2. The array substrate according to claim 1, characterized in that: The figure corresponding to the longitudinal section of the groove is a semicircular arc, the figure corresponding to the cross section of the groove is a rectangle, the longitudinal section of the groove is parallel to the direction in which the active pattern points to the substrate, and the cross section of the groove is perpendicular to the longitudinal section of the groove.

3. The array substrate according to claim 1, characterized in that: The radius of the arc surface is 2 micrometers to 10 micrometers.

4. The array substrate according to claim 1, characterized in that: The array substrate further includes: A buffer layer is located between the active pattern and the substrate; wherein the groove is located inside at least one of the substrate and the buffer layer.

5. The array substrate according to any one of claims 1 to 4, characterized in that: Also includes: The gate insulating layer is disposed between the active pattern and the gate and comprises a first recessed portion, wherein the first recessed portion overlaps the groove; wherein the gate is located in the first recessed portion.

6. The array substrate according to claim 5, characterized in that: Also includes: The interlayer insulating layer covers the gate insulating layer and the gate and includes a second recessed portion, wherein the second recessed portion overlaps the groove and the first recessed portion and protrudes toward the groove.

7. The array substrate according to claim 6, characterized in that: The thin film transistor further includes a source and a drain, wherein the source contacts the first connection portion, the drain contacts the second connection portion, and the source and the drain are located on a surface of the interlayer insulating layer away from the substrate and outside the second recessed portion.

8. The array substrate according to claim 7, characterized in that: The source electrode contacts the first connection portion through a first contact hole penetrating the interlayer insulating layer and the gate insulating layer, and the drain electrode contacts the second connection portion through a second contact hole penetrating the interlayer insulating layer and the gate insulating layer; wherein the first contact hole and the second contact hole are located outside the groove and the second recessed portion.

9. The array substrate according to any one of claims 1 to 4, characterized in that: The first connection portion and the second connection portion are both located outside the groove.

10. The array substrate according to any one of claims 1 to 4, characterized in that: Also includes: The planarization layer covers the thin film transistor and the substrate and includes a third recessed portion, wherein the third recessed portion overlaps with the groove and protrudes toward the groove.

11. The array substrate according to claim 10, characterized in that: Also includes: A first electrode is disposed on a side of the planarization layer away from the substrate; A passivation layer, disposed on a side of the first electrode away from the planarization layer; as well as The second electrode is disposed on a side of the passivation layer away from the first electrode; wherein one of the first electrode and the second electrode is electrically connected to the drain of the thin film transistor.

12. The array substrate according to claim 10, characterized in that: The thickness of the planarization layer is greater than or equal to 2.5 micrometers and less than or equal to 5 micrometers.

13. The array substrate according to claim 1, characterized in that: A dimension of the middle portion along a circumferential direction of the middle portion is larger than dimensions of the first connection portion and the second connection portion in a direction from the second connection portion to the first connection portion.

14. The array substrate according to claim 1, characterized in that: The material of the active pattern includes polysilicon; and / or, The middle portion includes a first lightly doped portion, a second lightly doped portion and a channel portion, the channel portion is connected between the first lightly doped portion and the second lightly doped portion, the first lightly doped portion is connected between the first connecting portion and the channel portion, and the second lightly doped portion is connected between the second connecting portion and the channel portion.

15. A display panel, characterized in that: The display panel comprises the array substrate according to any one of claims 1 to 14.

Images