Array substrate, preparation method thereof and display panel

Abstract

The invention discloses an array substrate, a preparation method thereof and a display panel, and belongs to the technical field of display. The array substrate comprises a first metal layer, a second metal layer and a third metal layer which are arranged in a stacked mode. Wherein an auxiliary metal layer is arranged between the second metal layer and the third metal layer; a first interlayer insulating layer is arranged between the auxiliary metal layer and the third metal layer, the first interlayer insulating layer is made of an inorganic material, and the thickness of the first interlayer insulating layer is smaller than or equal to # imgabs0 #. According to the array substrate and the manufacturing method thereof, it can be guaranteed that the thickness of the array substrate is low, and meanwhile the space utilization rate is increased.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, and a display panel. Background Art

[0002] Organic Light Emitting Display (OLED) and flat-panel display devices based on technologies such as Light Emitting Diode (LED) have been widely used in various consumer electronic products such as mobile phones, televisions, laptops and desktop computers due to their advantages of high image quality, power saving, thin body and wide application range, becoming the mainstream in display devices.

[0003] However, in current display panels, it is difficult to balance the thickness and space utilization of the array substrate. Summary of the invention

[0004] The present invention provides an array substrate and a preparation method thereof, and a display panel, so as to improve space utilization while ensuring that the thickness of the array substrate is relatively low.

[0005] In a first aspect, an embodiment of the present invention provides an array substrate, comprising: a first metal layer, a second metal layer, and a third metal layer stacked;

[0006] Among them, an auxiliary metal layer is arranged between the second metal layer and the third metal layer; a first interlayer insulating layer is arranged between the auxiliary metal layer and the third metal layer, the first interlayer insulating layer includes an inorganic material, and the thickness of the first interlayer insulating layer is less than or equal to

[0007] Optionally, the material of the third metal layer includes titanium aluminum titanium; the material of the auxiliary metal layer includes molybdenum;

[0008] The material of the first interlayer insulating layer includes: silicon oxide and / or silicon nitride;

[0009] Preferably, the thickness of the first interlayer insulating layer is greater than or equal to

[0010] Preferably, the thickness of the first interlayer insulating layer is in the range of

[0011] Preferably, the thickness of the first interlayer insulating layer is

[0012] Optionally, a second interlayer insulating layer is provided between the auxiliary metal layer and the second metal layer; the second interlayer insulating layer is made of inorganic material; and the thickness of the second interlayer insulating layer is less than or equal to

[0013] Preferably, the thickness of the second interlayer insulating layer is greater than or equal to

[0014] Preferably, the material of the second interlayer insulating layer includes: silicon oxide and / or silicon nitride;

[0015] Preferably, the second interlayer insulating layer includes at least one silicon nitride sublayer and at least one silicon oxide sublayer which are stacked.

[0016] Optionally, the array substrate further includes:

[0017] An active layer, disposed on a side of the first metal layer away from the second metal layer;

[0018] A gate insulating layer, disposed between the active layer and the first metal layer;

[0019] A capacitor insulating layer, disposed between the first metal layer and the second metal layer;

[0020] A plurality of via structures, wherein the via structures are used to realize electrical connection between any two different layers among the active layer, the first metal layer, the second metal layer, the auxiliary metal layer and the third metal layer;

[0021] Preferably, the third metal layer includes a data line and a power line;

[0022] Preferably, the auxiliary metal layer includes a capacitor plate for forming a storage capacitor in the pixel circuit.

[0023] Optionally, the via structure between the third metal layer and the first target layer includes:

[0024] a first via hole, penetrating the first interlayer insulating layer, and used to realize electrical connection between the third metal layer and the auxiliary metal layer;

[0025] a second via hole, penetrating all film layers between the auxiliary metal layer and the first target layer, for realizing electrical connection between the auxiliary metal layer and the first target layer; wherein the first target layer is the active layer, the first metal layer or the second metal layer;

[0026] A flying line disposed on the auxiliary metal layer, connecting the first via hole and the second via hole;

[0027] or,

[0028] The via structure between the third metal layer and the second target layer comprises:

[0029] A third via hole penetrates all film layers between the third metal layer and the second target layer, and is used to achieve electrical connection between the third metal layer and the second target layer; wherein the second target layer is the active layer, the first metal layer, the second metal layer or the auxiliary metal layer.

[0030] Optionally, the via structure between the auxiliary metal layer and the third target layer includes:

[0031] A fourth via hole penetrates all film layers between the auxiliary metal layer and the third target layer, and is used to achieve electrical connection between the auxiliary metal layer and the third target layer; wherein the third target layer is the active layer, the first metal layer or the second metal layer.

[0032] In a second aspect, an embodiment of the present invention further provides a method for preparing an array substrate, which is used to prepare the array substrate provided by any embodiment of the present invention; the method for preparing the array substrate comprises:

[0033] Prepare a first metal layer and a second metal layer which are stacked;

[0034] preparing an auxiliary metal layer on a side of the second metal layer away from the first metal layer;

[0035] A first interlayer insulating layer is prepared on the side of the auxiliary metal layer away from the second metal layer; wherein the first interlayer insulating layer is made of inorganic material, and the thickness of the first interlayer insulating layer is less than or equal to

[0036] A third metal layer is formed on a side of the first interlayer insulating layer away from the auxiliary metal layer.

[0037] Optionally, before preparing the first metal layer and the second metal layer stacked together, the method further includes:

[0038] providing a substrate;

[0039] An active layer and a gate insulating layer are sequentially stacked on one side of the substrate; wherein the first metal layer is arranged on a side of the gate insulating layer away from the substrate;

[0040] After the first metal layer and the second metal layer are stacked, the method further comprises:

[0041] A second interlayer insulating layer is prepared on a side of the second metal layer away from the substrate; wherein the auxiliary metal layer is arranged on a side of the second interlayer insulating layer away from the substrate.

[0042] Optionally, the auxiliary metal layer is connected to at least one of the active layer, the first metal layer and the second metal layer through a via; and a second interlayer insulating layer is prepared on a side of the second metal layer away from the substrate, comprising:

[0043] The second interlayer insulating layer is prepared by a mask process to form a via hole for connecting the auxiliary metal layer to at least one of the active layer, the first metal layer and the second metal layer;

[0044] and / or,

[0045] The third metal layer is connected to at least one of the active layer, the first metal layer, the second metal layer and the auxiliary metal layer through a via; and a first interlayer insulating layer is prepared on a side of the auxiliary metal layer away from the second metal layer, comprising:

[0046] The first interlayer insulating layer is prepared by a mask process to form a via hole for connecting the third metal layer to at least one of the active layer, the first metal layer, the second metal layer and the auxiliary metal layer.

[0047] In a third aspect, an embodiment of the present invention further provides a display panel, comprising the array substrate provided by any embodiment of the present invention.

[0048] In the array substrate provided by the embodiment of the present invention, by adding an auxiliary metal layer between the second metal layer and the third metal layer, it is equivalent to providing a structure of four metal layers, which can provide more flexibility for the wiring and via connection of the pixel circuit; and by increasing the number of metal layers vertically, the space utilization rate can be improved, providing space for widening the signal line and enlarging the capacitor plate, which is conducive to improving the performance of the pixel circuit and thus improving the display effect. In addition, the auxiliary metal layer and the third metal layer are provided with a thickness less than or equal to Compared with the use of an organic insulating layer, the first interlayer insulating layer can make the thickness of the array substrate smaller; at the same time, the depth of the connecting vias from the third metal layer to the metal layers below can be effectively reduced, the difficulty of via etching can be reduced, and the connection reliability can be improved; and the distance between the third metal layer and the metal layer below can be reduced, which can increase the feasibility of setting the plate of the capacitor in the pixel circuit on the third metal layer. Therefore, the embodiment of the present invention can improve the space utilization while ensuring the low thickness of the array substrate, which is conducive to improving the performance of the pixel circuit, and then improving the display effect of the display panel.

[0049] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0051] Figure 1 is a schematic diagram of a film layer structure of an array substrate provided by an embodiment of the present invention;

[0052] Figure 2 is a schematic diagram of a film layer structure of another array substrate provided by an embodiment of the present invention;

[0053] Figure 3 is a schematic diagram of a film layer structure of another array substrate provided by an embodiment of the present invention;

[0054] Figure 4 is a schematic diagram of a film layer structure of another array substrate provided by an embodiment of the present invention;

[0055] Figure 5 is a schematic diagram of a film layer structure of another array substrate provided by an embodiment of the present invention;

[0056] Figure 6 is a schematic diagram of a film layer structure of another array substrate provided by an embodiment of the present invention;

[0057] Figure 7 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0058] Figure 8 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0059] Fig. 9 is a schematic flow chart of a method for preparing an array substrate provided by an embodiment of the present invention;

[0060] Fig.10 yes Fig. 9 Schematic diagram of the structure in S110-S140;

[0061] Fig.11 is a flow chart of a nine-mask process provided by an embodiment of the present invention;

[0062] Fig.12 is a schematic flow chart of another method for preparing an array substrate provided by an embodiment of the present invention;

[0063] Fig.13 It is a flow chart of a ten-mask process provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0064] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0065] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0066] As mentioned in the background technology, it is difficult to balance the thickness and space utilization of the array substrate in the current display panel. In the related technology, with the diversification of the functions of the display panel, the structure of the pixel circuit is becoming more and more complicated. The traditional three-layer metal layer array substrate structure is increasingly unable to meet the wiring requirements of the pixel circuit. The area of ​​various electrodes in the pixel circuit and the line width of the related signal lines are greatly limited. In the array substrate with four metal layers, the third metal layer and the fourth metal layer are usually connected with a thicker organic glue, which makes the array substrate thicker and difficult to achieve an ultra-thin body. The distance between the fourth metal layer and the lower metal layer is larger, which makes it difficult to prepare the capacitor plate on the fourth metal layer, limiting the capacitance value of the capacitor.

[0067] In order to solve the above problems, an embodiment of the present invention provides an array substrate, which can realize a 4-metal layer structure while ensuring a low thickness of the array substrate, thereby improving the layout space utilization. Figure 1 Schematic diagram of a film structure of an array substrate provided by an embodiment of the present invention. Figure 1 The array substrate includes: a first metal layer M1, a second metal layer M2, and a third metal layer M3 which are stacked. An auxiliary metal layer M2_A is disposed between the second metal layer M2 and the third metal layer M3; a first interlayer insulating layer ILD_A is disposed between the auxiliary metal layer M2_A and the third metal layer M3, the first interlayer insulating layer ILD_A is made of an inorganic material, and the thickness d1 of the first interlayer insulating layer ILD_A is less than or equal to

[0068] Among them, the auxiliary metal layer M2_A is equivalent to a metal layer added on the basis of the original three metal layers of the array substrate. The auxiliary metal layer M2_A can be used to lay out the electrodes required for the pixel circuit, such as the plates of the capacitor in the pixel circuit, the gate, drain and source of the transistor, etc.; it can also be used to achieve connection between different electrodes. For example, two different electrodes arranged in the same metal layer, or two different electrodes arranged in different metal layers, can be electrically connected through vias and cross-wires located on the auxiliary metal layer M2_A.

[0069] Exemplarily, the first metal layer M1 can be used to lay out the gate of the transistor in the pixel circuit; the second metal layer M2 can be used to lay out the plate of the capacitor in the pixel circuit; the auxiliary metal layer M2_A can undertake most of the functions of the via connection, lay out the source and drain of the transistor in the pixel circuit, and lay out the plate of the capacitor in the pixel circuit; the third metal layer M3 can be mainly used to lay out the signal lines required in the pixel circuit, such as data lines and power lines. It can be understood that the signal lines required for the operation of the pixel circuit can be laid out in each metal layer according to the needs. An insulating layer can be set between each adjacent metal layer to achieve insulation between the two adjacent metal layers. Exemplarily, a capacitor insulating layer CI can be set between the first metal layer M1 and the second metal layer M2. A second interlayer insulating layer ILD_A can be set between the second metal layer M2 and the auxiliary metal layer M2_A.

[0070] The first interlayer insulating layer ILD_A is made of inorganic materials. The organic insulating layer can effectively reduce the thickness limit of the first interlayer insulating layer ILD_A, providing a film thickness less than or equal to A thinner insulating layer is formed, thereby reducing the total thickness of the array substrate as much as possible on the basis of adding a metal layer. Furthermore, the total thickness of the array substrate can be reduced by thinning the second interlayer insulating layer ILD; the amount of thinning of the second interlayer insulating layer ILD can be determined according to the thickness d1 of the added first interlayer insulating layer ILD_A, for example, the amount of thinning is equal to or close to the thickness d1 of the first interlayer insulating layer ILD_A, so that the sum of the thickness of the second interlayer insulating layer ILD and the first interlayer insulating layer ILD_A is basically consistent with the thickness of the second interlayer insulating layer ILD before the auxiliary metal layer M2_A is set. In other words, the thickness of the array substrate after the auxiliary metal layer M2_A is added is basically consistent with the thickness of the original array substrate with three metal layers.

[0071] In the array substrate provided by the embodiment of the present invention, by adding an auxiliary metal layer M2_A between the second metal layer M2 and the third metal layer M3, it is equivalent to providing a structure of 4 metal layers, which can provide more flexibility for the wiring and via connection of the pixel circuit; and by increasing the number of metal layers vertically, the space utilization rate can be improved, providing space for widening the signal line and enlarging the capacitor plate, which is conducive to improving the performance of the pixel circuit and thus improving the display effect. In addition, the auxiliary metal layer M2_A and the third metal layer M3 are provided with a thickness less than or equal to Compared with the use of an organic insulating layer, the first interlayer insulating layer ILD_A can make the thickness of the array substrate smaller; at the same time, the depth of the connection vias from the third metal layer M3 to the metal layers below can be effectively reduced, the difficulty of via etching can be reduced, and the connection reliability can be improved; and the distance between the third metal layer M3 and the metal layer below can be reduced, which can increase the feasibility of setting the plate of the capacitor in the pixel circuit on the third metal layer M3. Therefore, the embodiment of the present invention can improve the space utilization while ensuring the low thickness of the array substrate, which is conducive to improving the performance of the pixel circuit, and further improving the display effect of the display panel.

[0072] Based on the above embodiments, the material of the third metal layer M3 includes titanium aluminum titanium (TiAlTi). It can be understood that the structure of the titanium aluminum titanium material involved in the present invention is a titanium aluminum titanium stacked structure; the material of the auxiliary metal layer M2_A includes molybdenum. In this way, compared with the third metal layer M3 and the auxiliary metal layer M2_A being made of titanium aluminum titanium, the first interlayer insulating layer ILD_A can be easily made of inorganic materials without using organic glue (usually with a thickness of tens of thousands of Å). ). At the same time, the third metal layer M3 is made of titanium aluminum titanium to ensure that the square resistance of the third metal layer M3 is small. Using the third metal layer M3 to prepare the signal line can effectively reduce the IR Drop (voltage drop) on the signal line and improve the driving ability of the signal line. In addition, the auxiliary metal layer M2_A is made of molybdenum, which can make the thickness of the auxiliary metal layer M2_A itself thinner, so as to reduce the thickness of the array substrate.

[0073] Based on the above embodiments, optionally, the thickness d1 of the first interlayer insulating layer ILD_A is greater than or equal to This is to prevent the first interlayer insulating layer ILD_A from being etched through due to over-etching during the etching process of the third metal layer M3, thereby ensuring the reliability of the array substrate. The thickness of the first interlayer insulating layer ILD_A can be specifically set to or The specific settings can be made according to actual needs and are not limited here.

[0074] Based on the above embodiments, optionally, the material of the first interlayer insulating layer ILD_A includes silicon oxide (SiOx) and / or silicon nitride (SiNx). Exemplarily, the first interlayer insulating layer ILD_A may include a single layer of SiOx, or a single layer of SiNx, or a stacked structure including at least one layer of SiOx and at least one layer of SiNx.

[0075] On the basis of the above embodiments, optionally, a second interlayer insulating layer ILD is provided between the auxiliary metal layer M2_A and the second metal layer M2 to achieve insulation between the auxiliary metal layer M2_A and the second metal layer M2. The second interlayer insulating layer ILD is made of inorganic material; the thickness of the second interlayer insulating layer ILD is less than or equal to In this embodiment, the second interlayer insulating layer ILD is set to have a thickness less than or equal to Compared with the use of an organic insulating layer, the inorganic material layer of the array substrate can make the thickness of the array substrate smaller. Exemplarily, the thickness d2 of the second interlayer insulating layer ILD is greater than or equal to For example, or Exemplarily, the thickness d2 of the second interlayer insulating layer ILD is obtained by thinning the interlayer insulating layer between the second metal layer and the third metal layer in the array substrate having three metal layers in the related technology. The thinned thickness is, for example, equal to or close to the thickness d1 of the first interlayer insulating layer ILD_A, or equal to or close to the sum of the thicknesses of the first interlayer insulating layer ILD_A and the auxiliary metal layer M2_A.

[0076] The material of the second interlayer insulating layer ILD includes silicon oxide and / or silicon nitride. The second interlayer insulating layer ILD may be a single layer of SiOx or a single layer of SiNx; or the second interlayer insulating layer ILD includes at least one silicon nitride sublayer and at least one silicon oxide sublayer stacked. In a specific embodiment, the second interlayer insulating layer ILD includes, for example, a layer with a thickness of The silicon oxide sublayer and a layer of thickness of silicon nitride sublayer.

[0077] See also Figure 2-6On the basis of the above embodiments, optionally, the array substrate further comprises: an active layer PSI, a gate insulating layer GI and a capacitor insulating layer CI. The active layer PSI is arranged on the side of the first metal layer M1 away from the second metal layer M2; the gate insulating layer GI is arranged between the active layer PSI and the first metal layer M1; the capacitor insulating layer CI is arranged between the first metal layer M1 and the second metal layer M2. Exemplarily, the active layer PSI may be a polycrystalline silicon active layer; the material of the first metal layer M1 may include molybdenum; the material of the second metal layer M2 may include molybdenum; the gate insulating layer GI and the capacitor insulating layer CI may both be made of inorganic materials, such as silicon nitride and / or silicon oxide.

[0078] On this basis, the array substrate also includes multiple via structures K, which are used to achieve electrical connection between any two different layers among the active layer PSI, the first metal layer M1, the second metal layer M2, the auxiliary metal layer M2_A and the third metal layer M3; for example, they are used to achieve electrical connection between the third metal layer M3 and the other film layers mentioned above, or to achieve electrical connection between the auxiliary metal layer M2_A and the other film layers mentioned above.

[0079] Based on the above embodiments, the via structure K between different layers may optionally be arranged in a variety of ways, several of which are illustrated below, but are not intended to limit the present invention.

[0080] In one embodiment, optionally, see Figure 2 , the via structure K between the third metal layer M3 and the first target layer includes: a first via K1, a second via K2 and a crossover LK, that is, the third metal layer M3 is connected to the first target layer via a sleeve structure formed by the first via K1 and the second via K2 connected by the crossover LK. In this way, the connection reliability of the via structure K can be improved. Among them, the first target layer is the active layer PSI, the first metal layer M1 or the second metal layer M2, that is, at least one metal layer is spaced between the first target layer and the third metal layer M3, so that the crossover LK is set in the spaced metal layer.

[0081] Specifically, the first via K1 penetrates the first interlayer insulating layer ILD_A, and the first via K1 is used to realize the electrical connection between the third metal layer M3 and the auxiliary metal layer M2_A; the second via K2 penetrates all film layers between the auxiliary metal layer M2_A and the first target layer, and is used to realize the electrical connection between the auxiliary metal layer M2_A and the first target layer; wherein the crossover line LK is arranged in the auxiliary metal layer M2_A, and the crossover line LK respectively connects the first via K1 and the second via K2. Exemplarily, when the first target layer is the active layer PSI, the second via K2 penetrates the second interlayer insulating layer ILD, the capacitor insulating layer CI and the gate insulating layer G1 until the active layer PSI is exposed; when the first target layer is the first metal layer M1, the second via K2 penetrates the second interlayer insulating layer ILD and the capacitor insulating layer CI until the first metal layer M1 is exposed; when the first target layer is the second metal layer M2, the second via K2 penetrates the second interlayer insulating layer ILD until the second metal layer M2 is exposed. In this embodiment, by setting all the jump lines LK in the auxiliary metal layer M2_A, all the jump lines LK can be formed in the same mask process, that is, in the mask process for the auxiliary metal layer M2_A, thereby simplifying the manufacturing process.

[0082] In another embodiment, optionally, see Figure 3 , the via structure K between the third metal layer M3 and the second target layer includes: a third via K3; the third via K3 penetrates all film layers between the third metal layer M3 and the second target layer, and is used to realize electrical connection between the third metal layer M3 and the second target layer. The second target layer is the active layer PSI, the first metal layer M1, the second metal layer M2 or the auxiliary metal layer M2_A. Exemplarily, when the second target layer is the active layer PSI, the third via K3 penetrates the first interlayer insulating layer ILD_A, the second interlayer insulating layer ILD, the capacitor insulating layer CI and the gate insulating layer G1 until the active layer PSI is exposed; when the second target layer is the first metal layer M1, the third via K3 penetrates the first interlayer insulating layer ILD_A, the second interlayer insulating layer ILD and the capacitor insulating layer CI until the first metal layer M1 is exposed; when the second target layer is the second metal layer M2, the third via K3 penetrates the first interlayer insulating layer ILD_A and the second interlayer insulating layer ILD until the second metal layer M2 is exposed; when the second target layer is the auxiliary metal layer M2_A, the third via K3 penetrates the first interlayer insulating layer ILD_A until the auxiliary metal layer M2_A is exposed. In this embodiment, by setting the third metal layer M3 to be directly connected to the second target layer through a third via K3, the use of cross-over wires can be reduced and the preparation process can be simplified.

[0083] It is understandable that the connection method between the third metal layer M3 and the film layer below it can be selected according to actual needs, for example, by comprehensively considering the distance between the two film layers and the wiring space of the film layers between the two film layers, etc., to select the setting method of the via structure K. Among them, the above two via methods can be selected between the third metal layer M3 and different film layers as needed.

[0084] For example, see Figure 2 The third metal layer M3 can be connected to the auxiliary metal layer M2_A using a third via K3, and connected to other film layers using a sleeve hole structure of first via K1+second via K2+crossing line LK to ensure the reliability of electrical connection between the third metal layer M3 and each layer.

[0085] Alternatively, see Figure 3 , the third metal layer M3 and each film layer can be directly connected by a third via K3. In this way, since there is no need to set a via from the auxiliary metal layer M2_A downward, there is no need to pattern the second interlayer insulating layer ILD, and one mask process can be reduced, thereby simplifying the preparation process. Exemplarily, in this case, a mask process can be used to form the first interlayer insulating layer ILD_A. Specifically, an inorganic material for forming the first interlayer insulating layer ILD_A can be deposited on the side of the auxiliary metal layer M2_A away from the second metal layer M2 (i.e., above), for example, to form a SiOx insulating film and / or a SiNx insulating film, and then the entire deposited inorganic material is patterned by a process of photoresist coating-exposure-development-etching-photoresist stripping to form the first interlayer insulating layer ILD_A. It can be understood that the etching process includes four types of third via holes K3, namely, the third metal layer M3-active layer PSI, the third metal layer M3-first metal layer M1, the third metal layer M3-second metal layer M2, and the third metal layer M3-auxiliary metal layer M2_A. The size of the deep and shallow holes needs to be controlled during the etching process. Exemplarily, in this case, the first interlayer insulating layer ILD_A can be set thicker, for example, with a film thickness of about.

[0086] Alternatively, see Figure 4 and Figure 5 For a deeper via structure K, such as the via structure K between the third metal layer M3 and the active layer PSI, a sleeve hole structure of the first via K1+the second via K2+the cross-line LK can be used to ensure the reliability of the deep hole. For a shallower via structure K, such as the via structure K between the third metal layer M3 and the second metal layer M2, the third via K3 can be used for direct connection to simplify the preparation process, reduce the number of sleeve holes, and reduce the space occupied by the via structure K. For a via structure K with a moderate depth, such as the via structure K between the third metal layer M3 and the first metal layer M1, a sleeve hole structure (such as Figure 4) or directly connected structures (such as Figure 5 ).

[0087] Figure 6 FIG. 1 is a schematic diagram of a film layer structure of another array substrate provided by an embodiment of the present invention. Figure 6 , based on the above embodiments, optionally, the via structure K between the auxiliary metal layer M2_A and the third target layer includes: a fourth via K4; the fourth via K4 penetrates all film layers between the auxiliary metal layer M2_A and the third target layer, and is used to realize the electrical connection between the auxiliary metal layer M2_A and the third target layer. Wherein, the third target layer is the active layer PSI, the first metal layer M1 or the second metal layer M2. Exemplarily, when the third target layer is the active layer PSI, the fourth via K4 penetrates the second interlayer insulating layer ILD, the capacitor insulating layer CI and the gate insulating layer G1 until the active layer PSI is exposed; when the third target layer is the first metal layer M1, the fourth via K4 penetrates the second interlayer insulating layer ILD and the capacitor insulating layer CI until the first metal layer M1 is exposed; when the third target layer is the second metal layer M2, the fourth via K4 penetrates the second interlayer insulating layer ILD until the second metal layer M2 is exposed. In this embodiment, the manufacturing process can be simplified by directly connecting the auxiliary metal layer M2_A to the third target layer through a fourth via hole K4.

[0088] Continue to see Figure 6 On the basis of the above embodiments, optionally, the third metal layer M3 includes a data line LData and a power line LVDD. The third metal layer M3 is made of TiAlTi, which can effectively reduce the square resistance of various signal lines. Furthermore, the auxiliary metal layer M2_A is used to set the jump line, which is convenient for realizing the short-line connection in the pixel circuit. Since the jump line and other connecting lines are all arranged in the auxiliary metal layer M2_A, the third metal layer M3 can only be designed for the data line LData and the power line LVDD, which provides sufficient wiring space for the above signal lines. Then, the data line LData and the power line LVDD can be designed to be thickened to reduce IRDrop. Especially when there is a high brightness requirement, the power line can be designed to be very thick, thereby effectively reducing IR Drop, which is conducive to improving the color deviation problem; at the same time, there is no need to thicken the third metal layer M3, which does not affect the thickness of the array substrate and can reduce costs.

[0089] On the basis of the above-mentioned embodiments, optionally, the auxiliary metal layer M2_A may include a capacitor plate C for forming a storage capacitor in the pixel circuit; the area of ​​the capacitor plate C may be set according to actual needs. By setting the capacitor plate C in the auxiliary metal layer M2_A, on the one hand, since the auxiliary metal layer M2_A is a newly added film layer, it can share the wiring requirements of other film layers and improve space utilization; on the other hand, the capacitor plate C set in the auxiliary metal layer M2_A can be respectively opposite to the plates at corresponding positions of the upper and lower layers, which is beneficial to increase the capacitance of the storage capacitor by forming a parallel capacitor, thereby improving the performance of the pixel circuit.

[0090] The above embodiments mainly describe the film layer structure and via hole arrangement of the array substrate. The following briefly describes the exemplary layout of each film layer of the array substrate in combination with the pixel circuit, but it is not intended to limit the present invention.

[0091] Figure 7 is a schematic diagram of a pixel circuit provided by an embodiment of the present invention. Figure 7 Taking the pixel circuit of 7T1C structure as an example, the components in the pixel circuit may include: a first driving transistor M11, switch transistors M12-M17, a storage capacitor Cst and a light emitting device L. The signals required to drive the pixel circuit include: scanning signals S11-S13, a light emitting control signal EM, a data signal Vdata, an initialization signal Vref1-Vref2, a first power signal VDD and a second power signal VSS.

[0092] Exemplarily, the active layer PSI can be used to form the channel region, source region and drain region of each transistor in the pixel circuit; the first metal layer M1 can be used to form the gate of each transistor, and one plate of the storage capacitor Cst; the second metal layer M2 can be used to form another plate of the storage capacitor Cst; the third metal layer M3 can be used to lay out data lines (for transmitting data signals Vdata) and power lines (for transmitting the first power signal VDD); the auxiliary metal layer M2_A is mainly used to achieve cross-connection between different layers; signal lines for transmitting other signals can be distributed in each metal layer as needed.

[0093] In the pixel circuit, the threshold voltage of the first driving transistor M11 is compensated by using the switching transistor M13, wherein the data voltage associated with the threshold voltage is written into the storage capacitor Cst, and therefore, the threshold voltage information of the first driving transistor M11 is stored in the storage capacitor Cst. However, due to the short row scanning time corresponding to the switching transistor M13, the error of the threshold voltage information stored in the storage capacitor Cst increases, so that the threshold voltage of the first driving transistor M11 cannot be fully compensated. During the operation of the pixel circuit, the subthreshold swing of the first driving transistor M11 fluctuates, which will cause the driving current generated by different first driving transistors M11 under the same gray scale to be different, making the compensation effect unsatisfactory, and further resulting in poor brightness uniformity during display. The above problems can be alleviated by increasing the storage capacitor Cst. In this embodiment, by adding the auxiliary metal layer M2_A, it is equivalent to increasing the wiring space. On the basis of not increasing the area occupied by the pixel circuit, it can support making the plate of the storage capacitor Cst larger, and can also prepare a parallel capacitor structure through the auxiliary metal layer M2_A, thereby improving the voltage storage capacity of the storage capacitor Cst.

[0094] As the performance requirements for pixel circuits increase, the basic pixel circuit structure of 7T1C can no longer meet the functional requirements of pixel circuits. The performance improvement requirements can be met by adding transistors and / or capacitors. However, with the increase in PPI requirements and the increase in the demand for capacitor values, the layout space progress cannot meet the existing needs. In this embodiment, by adding an auxiliary metal layer M2_A, the wiring space of the pixel circuit can be more sufficient and the wiring method can be more flexible. The following is an exemplary description.

[0095] For example, see Figure 8, the pixel circuit is a 11T2C structure, specifically including a second driving transistor M21, switching transistors M22-M31, capacitors C1-C2, and a light-emitting device L. The signals required to drive the pixel circuit include: scanning signals S21-S24, a light-emitting control signal EM, a data signal Vdata, initialization signals Vrefn and Vrefp, a first power signal VDD, and a second power signal VSS. In the pixel circuit, by setting the switching transistors M28 and M30, the leakage of the gate of the second driving transistor M21 can be effectively reduced. Furthermore, by setting the capacitor C2, the voltage of the gate of the second driving transistor M21 can be further kept stable. The pixel circuit can be suitable for applications with low refresh rates such as an AOD. Exemplarily, for the pixel circuit, the active layer PSI can be used to form the channel region, source region and drain region of each transistor; the first metal layer M1 can be used to form the gate of each transistor; the plate of the capacitor C1 is, for example, separately arranged in the first metal layer M1 and the second metal layer M2; the plate of the capacitor C2 is, for example, separately arranged in the second metal layer M2 and the auxiliary metal layer M2_A; the third metal layer M3 can be used to lay out data lines (for transmitting data signals Vdata) and power lines (for transmitting the first power signal VDD), and the widened power lines can also be reused as the plates of capacitors C1 and C2; the auxiliary metal layer M2_A can also be used to achieve cross-connection between different layers; signal lines for transmitting other signals can be distributed in each metal layer as needed.

[0096] In summary, in the array substrate provided in the embodiment of the present invention, by adding an auxiliary metal layer M2_A and a thinner first interlayer insulating layer ILD_A, it can support new substrate layouts, via connections and routing selections, thereby significantly improving the layout space utilization. The array substrate structure provided in the embodiment of the present invention is conducive to widening the signal line on the basis of not thickening the third metal layer M3 to reduce IR Drop, improve the signal line driving capability, and meet high brightness requirements; at the same time, not thickening the third metal layer M3 can effectively control the substrate cost and provide better viewing angle performance (flatness). In addition, more wiring space supports increasing the capacitance of the capacitor in the pixel circuit, thereby supporting low-frequency displays such as AOD. In addition, the use of Figure 3-5 The via design in the circuit can effectively reduce the appearance of the hole and greatly reduce the occupied space within the pixel circuit.

[0097] An embodiment of the present invention further provides a method for preparing an array substrate, which can be used to prepare the array substrate provided by any embodiment of the present invention. Fig. 9 is a schematic flow chart of a method for preparing an array substrate provided by an embodiment of the present invention; Fig.10 yes Fig. 9 Schematic diagram of the structure in S110-S140.

[0098] Combination Fig. 9 and Fig.10 , the preparation method of the array substrate comprises:

[0099] S110, preparing a first metal layer and a second metal layer which are stacked.

[0100] Exemplarily, in the array substrate, a capacitor insulating layer C1 is disposed between the first metal layer M1 and the second metal layer M2. A stacked active layer PSI and a gate insulating layer GI are also disposed on the side of the first metal layer M1 away from the second metal layer M2 (ie, below).

[0101] Exemplarily, the material of the active layer PSI is polysilicon, and the material of the first metal layer M1 and the second metal layer M2 is a metal material such as aluminum, silver, titanium or molybdenum. The active layer PSI, the first metal layer M1 and the second metal layer M2 can all be prepared by a mask process. The process of preparing the target layer by a mask process can specifically be: firstly, the material of the target layer is laid in a whole layer by a process such as evaporation, sputtering or deposition, and then the target layer is obtained by patterning. The patterning process, for example, uses a process of mask plate + photolithography + dry etching / wet etching to remove part of the target layer material laid in a whole layer. The materials of the capacitor insulating layer C1 and the gate insulating layer GI can both be inorganic materials, for example, silicon oxide and / or silicon nitride. The capacitor insulating layer C1 and the gate insulating layer GI can both be laid in a whole layer.

[0102] S120, preparing an auxiliary metal layer on a side of the second metal layer away from the first metal layer.

[0103] For example, the second interlayer insulating layer ILD may be firstly formed on a side of the second metal layer M2 away from the first metal layer M1 (ie, on the upper side), and then the auxiliary metal layer M2_A may be formed on the second interlayer insulating layer ILD.

[0104] The material of the second interlayer insulating layer ILD may be an inorganic material, for example, silicon oxide and / or silicon nitride. The second interlayer insulating layer ILD may be laid as a whole layer (eg, Fig.10 The auxiliary metal layer M2_A may be prepared by a mask process. The material of the auxiliary metal layer M2_A is, for example, molybdenum. The auxiliary metal layer M2_A may be prepared by a mask process.

[0105] S130, preparing a first interlayer insulating layer on a side of the auxiliary metal layer away from the second metal layer; wherein the first interlayer insulating layer is made of an inorganic material, and the thickness of the first interlayer insulating layer is less than or equal to

[0106] The material of the first interlayer insulating layer ILD_A may specifically include silicon oxide and / or silicon nitride. The first interlayer insulating layer ILD_A may be prepared by a mask process.

[0107] S140 , preparing a third metal layer on a side of the first interlayer insulating layer away from the auxiliary metal layer.

[0108] The material of the third metal layer M3 may be titanium-aluminum-titanium. The third metal layer M3 may be prepared by using a mask process.

[0109] The embodiment of the present invention provides a method for preparing an array substrate based on S110-S140, and provides a structure of 4 metal layers, which can provide more flexibility for the wiring and via connection of the pixel circuit; and by increasing the number of metal layers vertically, the space utilization rate can be improved, providing space for widening the signal line and enlarging the capacitor plate, which is conducive to improving the performance of the pixel circuit and thus improving the display effect. In addition, the auxiliary metal layer M2_A and the third metal layer M3 are provided with a thickness less than or equal to Compared with the use of an organic insulating layer, the first interlayer insulating layer ILD_A can make the thickness of the array substrate smaller; at the same time, the depth of the connection vias from the third metal layer M3 to the metal layers below can be effectively reduced, the difficulty of via etching can be reduced, and the connection reliability can be improved; and the distance between the third metal layer M3 and the metal layer below can be reduced, which can increase the feasibility of setting the plate of the capacitor in the pixel circuit on the third metal layer M3. Therefore, the embodiment of the present invention can improve the space utilization while ensuring the low thickness of the array substrate, which is conducive to improving the performance of the pixel circuit, and further improving the display effect of the display panel.

[0110] Based on the above embodiments, optionally, before preparing the stacked first metal layer and the second metal layer, the method further includes:

[0111] 1) Provide a substrate.

[0112] The material of the substrate is, for example, an insulating material such as glass or polyimide, and the substrate is used to support other film layers in the array substrate.

[0113] 2) On one side of the substrate, a stacked active layer and a gate insulating layer are sequentially prepared; wherein the first metal layer is arranged on a side of the gate insulating layer away from the substrate.

[0114] And, after preparing the stacked first metal layer and the second metal layer, it also includes: preparing a second interlayer insulating layer on the side of the second metal layer away from the substrate; wherein the auxiliary metal layer is arranged on the side of the second interlayer insulating layer away from the substrate.

[0115] And, after preparing the third metal layer, the method further comprises:

[0116] 1) A planarization layer is prepared on a side of the third metal layer away from the substrate.

[0117] The material of the planarization layer may be an organic material and / or an inorganic material, and the planarization layer may be prepared by a mask process to prepare connection vias between the film layers on both sides of the planarization layer.

[0118] 2) An anode layer and a pixel definition layer are prepared on the side of the planarization layer away from the substrate.

[0119] The pixel definition layer may be made of insulating materials, such as organic materials and / or inorganic materials. The pixel definition layer may enclose a plurality of pixel openings. The material of the anode layer is a metal material such as aluminum, silver, titanium or molybdenum or its alloy material, or a metal oxide such as indium tin oxide, or other non-metallic materials with good electrical conductivity. The anode layer includes the anodes of the light-emitting devices in each pixel circuit. The anode layer may be prepared by a mask process, and each anode corresponding to each pixel opening is formed by patterning.

[0120] 3) A light-emitting layer and a cathode layer are sequentially prepared in each pixel opening.

[0121] The light-emitting layer may include the light-emitting material of the light-emitting device in each pixel circuit, and the cathode layer may include the cathode of the light-emitting device in each pixel circuit. The light-emitting layer may specifically include a stacked electron injection layer, an electron transport layer, a light-emitting material layer, a hole transport layer, and a hole injection layer. The light-emitting layer may be prepared by a mask process.

[0122] In one embodiment, optionally, the third metal layer is connected to at least one of the active layer, the first metal layer, the second metal layer, and the auxiliary metal layer through a via. Then, preparing a first interlayer insulating layer on a side of the auxiliary metal layer away from the second metal layer includes: preparing the first interlayer insulating layer using a mask process to form a via for connecting the third metal layer to at least one of the active layer, the first metal layer, the second metal layer, and the auxiliary metal layer.

[0123] For example Figure 3 As shown, when the third metal layer M3 is connected to other film layers using a directly connected via structure K, the number of mask processes in the manufacturing process can be effectively reduced. Fig.11 , select Figure 3 When the via structure K is shown, the preparation process of the array substrate includes nine mask processes for the active layer PSI, the first metal layer M1, the second metal layer M2, the auxiliary metal layer M2_A, the first interlayer insulating layer ILD_A, the third metal layer M3, the planarization layer PLA, the anode layer Anode and the light-emitting layer HTM.

[0124] In another embodiment, optionally, the auxiliary metal layer is connected to at least one of the active layer, the first metal layer and the second metal layer through a via. Then, preparing a second interlayer insulating layer on a side of the second metal layer away from the substrate includes: preparing the second interlayer insulating layer using a mask process to form a via for connecting the auxiliary metal layer to at least one of the active layer, the first metal layer and the second metal layer.

[0125] Specifically, see Fig.12 When there are downward via holes in the auxiliary metal layer M2_A and downward via holes in the third metal layer M3, the method for preparing the array substrate includes:

[0126] S210, preparing an active layer PSI, a gate insulating layer GI, a first metal layer M1, a capacitor insulating layer CI and a second metal layer M2 which are stacked.

[0127] S220 , using a mask process, preparing a second interlayer insulating layer ILD on a side of the second metal layer M2 away from the first metal layer M1 .

[0128] S230 , using a mask process, preparing an auxiliary metal layer M2_A on a side of the second interlayer insulating layer ILD away from the second metal layer M2 .

[0129] S240 , using a mask process to prepare a first interlayer insulating layer ILD_A on a side of the auxiliary metal layer M2_A away from the second metal layer M2 .

[0130] S250 , using a mask process, preparing a third metal layer M3 on a side of the first interlayer insulating layer ILD_A away from the auxiliary metal layer M2_A.

[0131] In this embodiment, the array substrate is prepared through S210-S250. The structure of the array substrate produced can be seen in Figure 2 , Figure 4 , Figure 5 and Figure 6 Specifically, see Fig.13 The preparation process of the array substrate includes ten mask processes for the active layer PSI, the first metal layer M1, the second metal layer M2, the second interlayer insulating layer ILD, the auxiliary metal layer M2_A, the first interlayer insulating layer ILD_A, the third metal layer M3, the planarization layer PLA, the anode layer Anode and the light-emitting layer HTM in sequence; compared with Fig.11 A mask process for the second interlayer insulating layer ILD is added.

[0132] On the basis of the above-mentioned embodiments, optionally, the array substrate can be applied to non-flexible products and flexible products. When the array substrate is applied to a flexible product, the array substrate is a flexible substrate and a flexible substrate can be used; and, a mask process for the non-display area of ​​the display panel can be added in the preparation process to achieve bending. Exemplarily, before preparing the third metal layer, a mask process can be added to pattern the portion of the first interlayer insulating layer located in the non-display area. After preparing the third metal layer, a third interlayer insulating layer can be prepared on the third metal layer by a mask process, and a passivation layer can be prepared above the third interlayer insulating layer by a mask process, and then a planarization layer can be prepared above the passivation layer by a mask process. It can be understood that the above process is only used as an exemplary description, but not as a limitation of the present invention.

[0133] In summary, the embodiments of the present invention provide a novel process and via structure, and a novel process route for preparing an array substrate, which can realize a four-metal layer structure without substantially affecting the thickness of the substrate.

[0134] The embodiment of the present invention further provides a display panel, comprising the array substrate provided by any embodiment of the present invention, and having corresponding beneficial effects. The array substrate can be prepared by the preparation method of the array substrate provided by any embodiment of the present invention.

[0135] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0136] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An array substrate, characterized in that: include: A first metal layer, a second metal layer and a third metal layer are stacked; Among them, an auxiliary metal layer is arranged between the second metal layer and the third metal layer; a first interlayer insulating layer is arranged between the auxiliary metal layer and the third metal layer, the material of the first interlayer insulating layer includes an inorganic material, and the thickness of the first interlayer insulating layer is less than or equal to 2. The array substrate according to claim 1, characterized in that: The material of the third metal layer includes titanium, aluminum and titanium; the material of the auxiliary metal layer includes molybdenum; The material of the first interlayer insulating layer includes: silicon oxide and / or silicon nitride; Preferably, the thickness of the first interlayer insulating layer is greater than or equal to Preferably, the thickness of the first interlayer insulating layer is in the range of Preferably, the thickness of the first interlayer insulating layer is 3. The array substrate according to claim 1, characterized in that: A second interlayer insulating layer is disposed between the auxiliary metal layer and the second metal layer; the material of the second interlayer insulating layer includes an inorganic material; the thickness of the second interlayer insulating layer is less than or equal to Preferably, the thickness of the second interlayer insulating layer is greater than or equal to Preferably, the material of the second interlayer insulating layer includes: silicon oxide and / or silicon nitride; Preferably, the second interlayer insulating layer includes at least one silicon nitride sublayer and at least one silicon oxide sublayer which are stacked.

4. The array substrate according to any one of claims 1 to 3, characterized in that: Also includes: An active layer, disposed on a side of the first metal layer away from the second metal layer; A gate insulating layer, disposed between the active layer and the first metal layer; A capacitor insulating layer, disposed between the first metal layer and the second metal layer; A plurality of via structures, wherein the via structures are used to realize electrical connection between any two different layers among the active layer, the first metal layer, the second metal layer, the auxiliary metal layer and the third metal layer; Preferably, the third metal layer includes a data line and a power line; Preferably, the auxiliary metal layer includes a capacitor plate for forming a storage capacitor in the pixel circuit.

5. The array substrate according to claim 4, characterized in that: The via structure between the third metal layer and the first target layer comprises: a first via hole, penetrating the first interlayer insulating layer, and used to realize electrical connection between the third metal layer and the auxiliary metal layer; a second via hole, penetrating all film layers between the auxiliary metal layer and the first target layer, for realizing electrical connection between the auxiliary metal layer and the first target layer; wherein the first target layer is the active layer, the first metal layer or the second metal layer; A flying line disposed on the auxiliary metal layer, connecting the first via hole and the second via hole; or, The via structure between the third metal layer and the second target layer comprises: A third via hole penetrates all film layers between the third metal layer and the second target layer, and is used to achieve electrical connection between the third metal layer and the second target layer; wherein the second target layer is the active layer, the first metal layer, the second metal layer or the auxiliary metal layer.

6. The array substrate according to claim 4, characterized in that: The via structure between the auxiliary metal layer and the third target layer comprises: A fourth via hole penetrates all film layers between the auxiliary metal layer and the third target layer, and is used to achieve electrical connection between the auxiliary metal layer and the third target layer; wherein the third target layer is the active layer, the first metal layer or the second metal layer.

7. A method for preparing an array substrate, characterized in that: include: Prepare a first metal layer and a second metal layer which are stacked; preparing an auxiliary metal layer on a side of the second metal layer away from the first metal layer; A first interlayer insulating layer is prepared on the side of the auxiliary metal layer away from the second metal layer; wherein the first interlayer insulating layer is made of inorganic material, and the thickness of the first interlayer insulating layer is less than or equal to A third metal layer is formed on a side of the first interlayer insulating layer away from the auxiliary metal layer.

8. The method for preparing an array substrate according to claim 7, characterized in that: Before preparing the first metal layer and the second metal layer stacked in layers, the method further includes: providing a substrate; An active layer and a gate insulating layer are sequentially stacked on one side of the substrate; wherein the first metal layer is arranged on a side of the gate insulating layer away from the substrate; After the first metal layer and the second metal layer are stacked, the method further comprises: A second interlayer insulating layer is prepared on a side of the second metal layer away from the substrate; wherein the auxiliary metal layer is arranged on a side of the second interlayer insulating layer away from the substrate.

9. The method for preparing an array substrate according to claim 8, characterized in that: The auxiliary metal layer is connected to at least one of the active layer, the first metal layer and the second metal layer through a via; The step of preparing a second interlayer insulating layer on a side of the second metal layer away from the substrate comprises: The second interlayer insulating layer is prepared by a mask process to form a via hole for connecting the auxiliary metal layer to at least one of the active layer, the first metal layer and the second metal layer; and / or, The third metal layer is connected to at least one of the active layer, the first metal layer, the second metal layer and the auxiliary metal layer through a via; and a first interlayer insulating layer is prepared on a side of the auxiliary metal layer away from the second metal layer, comprising: The first interlayer insulating layer is prepared by a mask process to form a via hole for connecting the third metal layer to at least one of the active layer, the first metal layer, the second metal layer and the auxiliary metal layer.

10. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 6.

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