Semiconductor device and method of manufacturing the same

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. The present disclosure relates to a semiconductor device manufacturing method including the steps of: forming a first layer including a first substrate, a first plug formed in the first substrate, a photodiode, and a first wiring layer; forming a second layer including a second substrate, a second plug formed in the second substrate, and a second wiring layer; forming a third layer including a third substrate and a third wiring layer; bonding the first wiring layer of the first layer to the second wiring layer of the second layer; and a third wiring layer bonding the second substrate of the second layer to the third layer.

Description

Technical Field

[0001] Various embodiments of the disclosed technology relate to semiconductor devices and methods of manufacturing the same. Background Art

[0002] As semiconductor devices are highly integrated, technology is being developed for a stacked semiconductor device that integrates required circuits or devices in two substrates of an upper substrate and a lower substrate, respectively, and then bonds the two substrates, thereby reducing the area of ​​a chip. Summary of the invention

[0003] Some implementations of the disclosed technology provide a semiconductor device and a method of manufacturing the same that are capable of minimizing thermal deformation such as warping or shrinkage when stacking a plurality of layers.

[0004] One embodiment is a method for manufacturing a semiconductor device. The manufacturing method includes the following steps: forming a first layer including a first substrate, a first plug formed in the first substrate, a photodiode, and a first wiring layer; forming a second layer including a second substrate, a second plug formed in the second substrate, and a second wiring layer; forming a third layer including a third substrate and a third wiring layer; bonding the first wiring layer of the first layer to the second wiring layer of the second layer; and bonding the second substrate of the second layer to the third wiring layer of the third layer.

[0005] The step of forming the first layer may include: forming a first substrate; forming a photodiode and a first plug in the first substrate; forming a first wiring layer on the first substrate; and forming a first bonding pad in a region of the first wiring layer.

[0006] The step of forming the second layer may include: forming a second substrate; forming a second plug in the second substrate; forming a second wiring layer on the second substrate; and forming a second bonding pad in a region of the second wiring layer.

[0007] The step of forming the third layer may include: forming a third substrate; forming a third wiring layer on the third substrate; and forming a third bonding pad in a region of the third wiring layer.

[0008] The step of bonding the first wiring layer of the first layer and the second wiring layer of the second layer may include bonding a first bonding pad of the first layer and a second bonding pad of the second layer.

[0009] The semiconductor device manufacturing method may also include: after bonding the first wiring layer of the first layer and the second wiring layer of the second layer, chemically mechanically polishing (CMP) the first substrate to a depth of a top of a first plug of the first layer; etching an upper portion of the first plug including the top of the first plug; forming a fourth bonding pad on the first plug; and forming a passivation layer on the first substrate.

[0010] The semiconductor device manufacturing method may further include: after forming the passivation layer, chemically mechanically polishing (CMP) the second substrate to a depth of a top of the second plug of the second layer; and etching an upper portion of the second plug including the top of the second plug.

[0011] The semiconductor device manufacturing method may further include forming a fifth bonding pad on the second plug after etching the top of the second plug.

[0012] The step of bonding the second substrate of the second layer and the third wiring layer of the third layer may include bonding a fifth bonding pad of the second layer and a third bonding pad of the third layer.

[0013] The semiconductor device manufacturing method may further include: after bonding the second substrate of the second layer and the third wiring layer of the third layer, removing the passivation layer of the first layer.

[0014] The semiconductor device manufacturing method may further include: forming a color filter over the photodiode of the first layer after removing the passivation layer of the first layer; and forming a microlens on the color filter.

[0015] Another embodiment is a semiconductor device, comprising: a first layer; a second layer, which is arranged below the first layer; and a third layer, which is arranged below the second layer, wherein the first layer comprises: a first wiring layer; a first substrate, which is bonded to the first wiring layer; a first plug, which is arranged in an area of ​​the first substrate; and a first bonding pad, which is arranged in an area of ​​the first wiring layer, wherein the second layer comprises: a second substrate; a second wiring layer, which is bonded to the second substrate; a second bonding pad, which is arranged in an area of ​​the second wiring layer and contacts the first bonding pad; and a second plug formed in an area of ​​the second substrate, and wherein the third layer comprises: a third substrate; a third wiring layer, which is arranged on the third substrate; and a third bonding pad, which is arranged in an area of ​​the third wiring layer.

[0016] The first layer may further include a fourth bonding pad disposed on the first plug.

[0017] The second layer may further include a fifth bonding pad disposed under the second plug and in contact with the third bonding pad.

[0018] The first layer may further include: a photodiode disposed in one region of the first substrate; a color filter disposed over the photodiode; and a microlens disposed on the color filter. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a block diagram of an image sensing device as a semiconductor device based on an implementation of the disclosed technology.

[0020] Figure 2 A semiconductor device including a first layer, a second layer, and a third layer based on some implementations of the disclosed technology is shown.

[0021] Figure 3 An example process of providing a first layer based on some implementations of the disclosed technology is illustrated.

[0022] Figure 4 An example process for providing a second layer based on some implementations of the disclosed technology is illustrated.

[0023] Figure 5 An example process for providing a third layer based on some implementations of the disclosed technology is illustrated.

[0024] Figure 6 An example process of bonding a first layer and a second layer based on some implementations of the disclosed technology is illustrated.

[0025] Figure 7 An example process of providing a fourth bonding pad and a passivation layer based on some implementations of the disclosed technology is illustrated.

[0026] Figure 8 An example process of etching the second substrate based on some implementations of the disclosed technology is illustrated.

[0027] Fig. 9 An example process of providing a fifth bonding pad based on some implementations of the disclosed technology is illustrated.

[0028] Fig.10 An example process of bonding the second layer and the third layer based on some implementations of the disclosed technology is illustrated.

[0029] Fig.11 An example process of removing a first layer of a passivation layer based on some implementations of the disclosed technology is illustrated.

[0030] Fig.12 An example process of forming color filters based on some implementations of the disclosed technology is illustrated. DETAILED DESCRIPTION

[0031] Features and certain advantages associated with particular embodiments of the disclosed technology disclosed in this patent document are described by way of example implementations with reference to the drawings.

[0032] It has been recognized that in a DRAM TSV process, when a subsequent heat treatment is performed, thermal deformation such as warping or shrinkage occurs.

[0033] In some implementations of the disclosed technology, a plug is formed before bonding an upper layer and a lower layer, so that thermal deformation such as warping or shrinkage caused by a subsequent heat treatment can be prevented.

[0034] Figure 1 is a block diagram of an image sensing device as a semiconductor device according to an embodiment of the present disclosure.

[0035] Reference Figure 1 , the image sensing device according to the embodiment includes a pixel array 1100, a row driver 1200, a correlated double sampler (CDS) 1300, an analog-to-digital converter (ADC) 1400, an output buffer 1500, a column driver 1600, a timing controller 1700, and a bias generator 1800. Here, each component of the image sensing device is merely an example, and at least some of the components may be added or omitted if necessary.

[0036] The pixel array 1100 may include a plurality of pixels arranged in a plurality of rows and columns. In an embodiment, a plurality of pixels may be arranged in a two-dimensional pixel array including rows and columns. In another embodiment, a plurality of unit image pixels may be arranged in a three-dimensional pixel array. A plurality of pixels may convert an optical signal into an electrical signal based on a pixel or based on a pixel group, and the pixels within the pixel group may share at least a specific internal circuit. The pixel array 1100 may receive a drive signal including a row selection signal, a pixel reset signal, and a transmission signal from a row driver 1200. The corresponding pixels of the pixel array 1100 may be activated by a drive signal to perform operations corresponding to the row selection signal, the pixel reset signal, and the transmission signal.

[0037] The row driver 1200 may activate the pixel array 1100 so that a specific operation is performed on the pixels included in the corresponding row based on the command and control signal provided by the timing controller 1700. In an embodiment, the row driver 1200 may select at least one pixel arranged in at least one row of the pixel array 1100. The row driver 1200 may generate a row selection signal to select at least one row among a plurality of rows. The row driver 1200 may sequentially enable a pixel reset signal and a transmission signal for pixels corresponding to at least one selected row. Therefore, the analog reference signal and the image signal generated from each pixel of the selected row may be sequentially sent to the correlated double sampler 1300. Here, the reference signal may be an electrical signal provided to the correlated double sampler 1300 when the sensing node (e.g., floating diffusion node) of the pixel is reset, and the image signal may be an electrical signal provided to the correlated double sampler 1300 when the photocharge generated by the pixel is accumulated in the sensing node. The reference signal indicating the reset noise specific to the pixel and the image signal indicating the intensity of the incident light may be collectively referred to as a pixel signal.

[0038] CMOS image sensors may use correlated double sampling to remove unwanted offset values ​​such as fixed pattern noise in pixels by sampling the pixel signal twice to remove the difference between the two samples. For example, through correlated double sampling, unwanted offset values ​​are removed by comparing the pixel output voltages obtained before and after the photocharges generated by the incident light are accumulated in the sensing node, so that the pixel output voltage based only on the incident light can be measured. In an embodiment, the correlated double sampler 1300 may sequentially sample and hold reference signals and image signals provided to each of the plurality of column lines from the pixel array 1100. That is, the correlated double sampler 1300 may sample and hold the levels of the reference signals and image signals corresponding to each column of the pixel array 1100.

[0039] The correlated double sampler 1300 may transmit the reference signal and the image signal of each column as a correlated double sampling signal to the ADC 1400 based on a control signal from the timing controller 1700 .

[0040] The ADC 1400 may convert and output the correlated double sampling signal of each column output from the correlated double sampler 1300 into a digital signal. In an embodiment, the ADC 1400 may be implemented as a ramp comparison type ADC. The ramp comparison type ADC may include a comparison circuit that compares a ramp signal that rises or falls over time with an analog pixel signal and a counter that performs a counting operation until the ramp signal matches the analog pixel signal. In an embodiment, the ADC 1400 may convert and output the correlated double sampling signal generated by the correlated double sampler 1300 for each column into a digital signal.

[0041] The ADC 1400 may include a plurality of column counters respectively corresponding to the columns of the pixel array 1100. The columns of the pixel array 1100 are respectively connected to the column counters, and image data may be generated by converting the correlated double sampling signals respectively corresponding to the columns into digital signals using the column counters. According to another embodiment, the ADC 1400 may include one global counter, and the correlated double sampling signals respectively corresponding to the columns may be converted into digital signals by using a global code provided by the global counter.

[0042] The output buffer 1500 may temporarily hold and output each image data provided from the ADC 1400 in a column unit. The output buffer 1500 may temporarily store the image data output from the ADC 1400 based on a control signal of the timing controller 1700. The output buffer 1500 may serve as an interface for compensating for a difference in transmission (or processing) speed between the image sensing device and another device connected to the output buffer.

[0043] The column driver 1600 may select a column of the output buffer 1500 based on a control signal of the timing controller 1700, and may control image data temporarily stored in the selected column of the output buffer 1500 to be sequentially output. In an embodiment, the column driver 1600 may receive an address signal from the timing controller 1700, and the column driver 1600 may generate a column selection signal based on the address signal and may select a column of the output buffer 1500, thereby controlling image data to be output from the selected column of the output buffer 1500 to the outside.

[0044] The timing controller 1700 may control at least one of the row driver 1200 , the correlated double sampler 1300 , the ADC 1400 , the output buffer 1500 , the column driver 1600 , and the bias generator 1800 .

[0045] The timing controller 1700 may provide a clock signal required for the operation of each component of the image sensing device, a control signal for timing control, an address signal for selecting a row or column, and a signal for controlling the level of a bias voltage applied to the pixel array 1100, etc. to at least one of the row driver 1200, the correlated double sampler 1300, the ADC 1400, the output buffer 1500, the column driver 1600, and the bias generator 1800. According to an embodiment, the timing controller 1700 may include a logic control circuit, a phase-locked loop (PLL) circuit, a timing control circuit, a communication interface circuit, and the like.

[0046] The bias generator 1800 may generate a bias voltage for suppressing a dark current generated in pixels of the pixel array 1100 , and may supply the bias voltage to the pixel array 1100 .

[0047] The bias voltage may be determined during a wafer probe test of the image sensing device and may be stored in a one-time programmable (OTP) memory. For example, the bias voltage has a value that can minimize unnecessary power consumption and maximize the effect of suppressing dark current without degrading the performance of the image sensing device. The value of the bias voltage may be determined experimentally.

[0048] The bias generator 1800 may generate a voltage corresponding to a bias voltage stored in the OTP memory. According to an embodiment, the OTP memory may be included in the image sensing device, and in particular, may be included in the bias generator 1800.

[0049] Depending on the implementation, the bias voltage may include multiple values.

[0050] For example, multiple values ​​may correspond to multiple operation modes of the image sensing device, respectively. Dark currents generated under low illumination and high illumination may be different from each other, and the bias voltage supplied by the bias generator 1800 to effectively suppress dark current in each environment may vary depending on the mode.

[0051] Alternatively, the plurality of values ​​may respectively correspond to the plurality of regions of the pixel array 1100. Dark currents generated according to the positions of pixels on the pixel array 1100 may be different from each other, and the bias voltage supplied by the bias generator 1800 in order to effectively suppress the dark current regardless of the position of the pixel may vary depending on the region.

[0052] In an example, the bias voltage may be a negative voltage having a negative sign. However, the bias voltage may have a different value (eg, a positive voltage) without being limited to a negative voltage.

[0053] Figures 2 to 12 The diagram illustrates a method for manufacturing a semiconductor device.

[0054] Reference Figures 2 to 12 , a method for manufacturing a semiconductor device according to an embodiment includes: forming a first layer 100 including a first substrate 110, a first plug 111 and a photodiode 112 formed in the first substrate 110, and a first wiring layer 120; forming a second layer 200 including a second substrate 210, a second plug 211 formed in the second substrate 210, and a second wiring layer 220; forming a third layer 300 including a third substrate 310 and a third wiring layer 320; bonding the first layer 100 and the second layer 200; and bonding the second layer 200 and the third layer 300. The photodiode 112 is described as an example of a photoelectric conversion element configured to convert incident light into electric charges. In some implementations, the photoelectric conversion element may be a phototransistor, a photogate, or a combination thereof, etc.

[0055] Figures 3 to 5 Processes of providing each of the first layer 100, the second layer 200, and the third layer 300 are illustrated separately. In an example, the first layer 100 may include a pixel array including pixels configured to provide electrical signals in response to incident light.

[0056] In an example, the second layer 200 may include logic circuits such as row drivers, correlated double samplers, analog-to-digital converters, output buffers, column drivers, timing controllers, and bias generators. The logic circuits are configured to provide various signals to pixels in the pixel array, such as referring to Figure 1 described.

[0057] The third layer 300 may include logic circuits such as an application processor (AP) and an artificial intelligence (AI) chip. For example, the third layer 300 may include at least one of an application processor or an AI chip. The application processor may process data from a pixel array, run an application, and / or control the operation of a semiconductor device. The AI ​​chip may be designed to perform AI tasks for various operations including, for example, object recognition, image segmentation, object tracking, etc. based on data from a pixel array.

[0058] Reference Figure 3 , forming the first layer 100 may include: forming a first substrate 110 , forming a photodiode 112 and a first plug 111 in the first substrate 110 , forming a first wiring layer 120 on the first substrate 110 , and forming a first bonding pad 121 in a region of the first wiring layer 120 .

[0059] The first substrate 110 may include a semiconductor substrate. The first substrate 110 may be in a single crystal state and may include a silicon-containing material.

[0060] The first substrate 110 may be thinned by a thinning process. For example, the first substrate 110 may be a bulk silicon substrate thinned by a thinning process. In an example, the first substrate 110 may include P-type impurities.

[0061] In an example, the first plug 111 may be formed by using doped polysilicon. In an example, the first plug 111 may be formed by removing polysilicon through wet etching to reduce resistance and then gap-filling by tungsten (W) or copper (Cu). In order to reduce resistance, a plurality of first plugs 111 may be formed.

[0062] The first wiring layer 120 may include a plurality of junction regions (not shown), a plurality of gate electrodes (not shown), a plurality of metal wirings (not shown), and a plurality of vias (not shown).

[0063] The junction region (not shown) may include one of an n-type region including n-type impurity ions such as phosphorus (P) or arsenic (As) or a p-type region including p-type impurity ions such as boron (B).

[0064] The gate electrode (not shown) may include a conductor such as metal or doped polysilicon.

[0065] A plurality of junction regions (not shown) may function as source electrodes and / or drain electrodes of the logic transistors.

[0066] The plurality of metal wirings (not shown) and the plurality of vias (not shown) may include a conductor such as a metal or doped polysilicon. For example, the plurality of metal wirings (not shown) and the plurality of vias (not shown) may include a metal such as tungsten (W), copper (Cu), aluminum (Al) or titanium (Ti), a metal compound such as titanium nitride (TiN), or a metal silicide such as tungsten silicide (WSi) or titanium silicide (TiSi).

[0067] Electrical signals may be routed between the vertical layers through a plurality of vias (not shown).

[0068] The first bonding pad 121 may include a metal or a metal compound such as copper (Cu), titanium (Ti), or titanium nitride (TiN). Figure 4 Forming the second layer 200 may include forming a second substrate 210 , forming a second plug 211 in the second substrate 210 , forming a second wiring layer 220 on the second substrate 210 , and forming a second bonding pad 221 in a region of the second wiring layer 220 .

[0069] The second substrate 210 may include a semiconductor substrate. The second substrate 210 may be in a single crystal state and may include a silicon-containing material.

[0070] The second substrate 210 may be thinned by a thinning process. For example, the second substrate 210 may be a bulk silicon substrate thinned by a thinning process. In an example, the second substrate 210 may include P-type impurities.

[0071] In an example, the second plug 211 may be formed by using doped polysilicon. For example, the second plug 211 may be formed by removing polysilicon by wet etching to reduce resistance and then gap-filling by tungsten (W) or copper (Cu). In order to reduce resistance, a plurality of second plugs 211 may be formed.

[0072] The second plug 211 is formed before bonding the second layer 200 and the third layer 300 so that thermal deformation such as warping or shrinkage caused by a subsequent heat treatment can be prevented.

[0073] The second wiring layer 220 may include a plurality of junction regions (not shown), a plurality of gate electrodes (not shown), a plurality of metal wirings (not shown), and a plurality of vias (not shown).

[0074] The junction region (not shown) may include one of an n-type region including n-type impurity ions such as phosphorus (P) or arsenic (As) or a p-type region including p-type impurity ions such as boron (B).

[0075] The gate electrode (not shown) may include a conductor such as metal or doped polysilicon.

[0076] A plurality of junction regions (not shown) may function as source electrodes and / or drain electrodes of the logic transistors.

[0077] Various logic transistors may be formed by a plurality of junction regions (not shown) and gate electrodes (not shown). A plurality of logic transistors may form various logic circuits.

[0078] The plurality of metal wirings (not shown) and the plurality of vias (not shown) may include a conductor such as a metal or doped polysilicon. In an example, the plurality of metal wirings (not shown) and the plurality of vias (not shown) may include a metal such as tungsten (W), copper (Cu), aluminum (Al), or titanium (Ti), a metal compound such as titanium nitride (TiN), or a metal silicide such as tungsten silicide (WSi) or titanium silicide (TiSi).

[0079] Electrical signals may be routed between the vertical layers through a plurality of vias (not shown).

[0080] The second bonding pad 221 may include a metal or a metal compound such as copper (Cu), titanium (Ti), or titanium nitride (TiN).

[0081] Reference Figure 5 Forming the third layer 300 may include forming a third substrate 310 , forming a third wiring layer 320 on the third substrate 310 , and forming a third bonding pad 321 in a region of the third wiring layer 320 .

[0082] The third substrate 310 may include a semiconductor substrate. The third substrate 310 may be in a single crystal state and may include a silicon-containing material.

[0083] The third substrate 310 may be thinned by a thinning process. In an example, the third substrate 310 may be a bulk silicon substrate thinned by a thinning process. For example, the third substrate 310 may include P-type impurities.

[0084] The third wiring layer 320 may include a plurality of junction regions (not shown), a plurality of gate electrodes (not shown), a plurality of metal wirings (not shown), and a plurality of vias (not shown).

[0085] The junction region (not shown) may include one of an n-type region including n-type impurity ions such as phosphorus (P) or arsenic (As) or a p-type region including p-type impurity ions such as boron (B).

[0086] The gate electrode (not shown) may include a conductor such as metal or doped polysilicon.

[0087] A plurality of junction regions (not shown) may function as source electrodes and / or drain electrodes of the logic transistors.

[0088] Various logic transistors may be formed by a plurality of junction regions (not shown) and gate electrodes (not shown). A plurality of logic transistors may form various logic circuits.

[0089] The plurality of metal wirings (not shown) and the plurality of vias (not shown) may include a conductor such as a metal or doped polysilicon. In an example, the plurality of metal wirings (not shown) and the plurality of vias (not shown) may include a metal such as tungsten (W), copper (Cu), aluminum (Al), or titanium (Ti), a metal compound such as titanium nitride (TiN), or a metal silicide such as tungsten silicide (WSi) or titanium silicide (TiSi).

[0090] Electrical signals may be routed between the vertical layers through a plurality of vias (not shown).

[0091] The third bonding pad 321 may include a metal or a metal compound such as copper (Cu), titanium (Ti), or titanium nitride (TiN).

[0092] Figure 6 An example process of bonding a first layer and a second layer based on an implementation of the disclosed technology is illustrated. Figure 6 In the bonding of the first layer 100 and the second layer 200, the first wiring layer 120 of the first layer 100 and the second wiring layer 220 of the second layer 200 can be bonded to contact each other, and the first bonding pad 121 of the first layer 100 and the second bonding pad 221 of the second layer 200 can be bonded to contact each other.

[0093] The first layer 100 and the second layer 200 may be bonded by a hybrid bonding technique.

[0094] Figure 7 An example process of providing a fourth bonding pad and a passivation layer based on some implementations of the disclosed technology is illustrated. Figure 7 , the semiconductor device manufacturing method may include: after bonding the first layer 100 and the second layer 200, chemically mechanically polishing (CMP) the first substrate 110 to a depth of a top of the first plug 111 of the first layer 100, etching the upper portion of the first plug 111 including the top of the first plug 111, forming a fourth bonding pad 130 on the first plug 111 by copper (Cu) deposition, and forming a passivation layer 140 on the first substrate 110. For example, after the upper portion of the first plug 111 is etched, the fourth bonding pad 130 may be formed on the remaining portion of the first plug 111. The fourth bonding pad 130 may have a bottom surface extending in a horizontal direction while contacting the remaining portion of the first plug 111 and a top surface flush with the surface of the first substrate 110.

[0095] After bonding the first layer 100 and the second layer 200 , the fourth bonding pad 130 may be formed by chemical mechanical polishing (CMP) to a depth of a top of the first plug 111 of the first layer 100 , etching an upper portion of the first plug 111 including a top of the first plug 111 , and copper (Cu) deposition.

[0096] After forming the fourth bonding pad 130 , a passivation layer 140 may be formed on the photodiode 112 and the fourth bonding pad 130 .

[0097] Reference Figure 8 and Fig. 9 , the semiconductor device manufacturing method may include: after forming the passivation layer 140, chemically mechanically polishing (CMP) the second substrate 210 to a depth of the top of the second plug 211 of the second layer 200, etching the upper portion of the second plug 211 including the top of the second plug 211, and forming the fifth bonding pad 230 on the second plug 211 by copper (Cu) deposition. For example, after the upper portion of the second plug 211 is etched, the fifth bonding pad 230 may be formed on the remaining portion of the second plug 211. The fifth bonding pad 230 may have a bottom surface extending in a horizontal direction while contacting the remaining portion of the second plug 211 and a top surface flush with the surface of the second substrate 210.

[0098] After forming the passivation layer 140 , the fifth bonding pad 230 may be formed by chemical mechanical polishing (CMP) to a depth of the top of the second plug 211 of the second layer 200 , etching the upper portion of the second plug 211 including the top of the second plug 211 , and copper (Cu) deposition.

[0099] Reference Fig.10 The semiconductor device manufacturing method may include: after forming the fifth bonding pad 230 , bonding the second layer 200 and the third layer 300 .

[0100] In the bonding of the second layer 200 and the third layer 300 , the second substrate 210 of the second layer 200 and the third wiring layer 320 of the third layer 300 may be bonded to contact each other, and the fifth bonding pad 230 of the second layer 200 and the third bonding pad 321 of the third layer 300 may be bonded to contact each other.

[0101] The second layer 200 and the third layer 300 may be bonded by a hybrid bonding technique.

[0102] Fig.11 An example process of removing the first passivation layer based on some implementations of the disclosed technology is illustrated. Fig.11The semiconductor device manufacturing method may include: after bonding the second layer 200 and the third layer 300 , removing the passivation layer 140 of the first layer 100 .

[0103] After the second layer 200 and the third layer 300 are bonded, the passivation layer 140 may be removed by chemical mechanical polishing (CMP).

[0104] Fig.12 An example process for forming a color filter based on some implementations of the disclosed technology is illustrated. Fig.12 The semiconductor device manufacturing method may include: after removing the passivation layer 140 , forming a color filter 150 over the photodiode 112 of the first layer 100 , and forming a microlens 160 on the color filter 150 .

[0105] After the passivation layer 140 is removed, a pixel array including the color filter 150 and the micro lens 160 may be formed.

[0106] After the first plug 111 is pre-formed in the first layer 100 where the pixel region is formed, the first plug 111 is exposed by chemical mechanical polishing (CMP) during a backside illumination (BSI) process. Then, tungsten-polysilicon (W-Poly Si) bonding can be used to achieve signal transmission between the upper and lower layers.

[0107] Reference Figure 2 and Fig.12 , a semiconductor device according to an embodiment includes a first layer 100 , a second layer 200 bonded under the first layer 100 , and a third layer 300 bonded under the second layer 200 .

[0108] The first layer 100 may include a first wiring layer 120 , a first substrate 110 formed on the first wiring layer 120 , a first plug 111 formed in a region of the first substrate 110 , a first bonding pad 121 formed in a region of the first wiring layer 120 , and a fourth bonding pad 130 formed on the first plug 111 .

[0109] The first layer 100 may include a photodiode 112 formed in one region of the first substrate 110 , a color filter 150 formed over the photodiode 112 , and a microlens 160 formed on the color filter 150 .

[0110] The second layer 200 may include: a second substrate 210, a second wiring layer 220 formed on the second substrate 210, a second bonding pad 221 formed in a region of the second wiring layer 220 and bonded to the first bonding pad 121, a second plug 211 formed in a region of the second substrate 210, and a fifth bonding pad 230 formed under the second plug 211 and bonded to the third bonding pad 321.

[0111] The third layer 300 includes a third substrate 310 , a third wiring layer 320 formed on the third substrate 310 , and a third bonding pad 321 formed in one region of the third wiring layer 320 .

[0112] Since components of the first layer 100 , the second layer 200 , and the third layer 300 are the same as those described above, a detailed description thereof will be omitted.

[0113] Although this patent document contains many details, these details should not be interpreted as limitations on the scope of any subject matter or content that can be claimed, but rather as descriptions of features that can be specific to a particular embodiment of a particular technology. Certain features described in the context of a separate embodiment in this patent document may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations and even initially claimed as such, in some cases, one or more features from the claimed combination may be removed from the combination, and the claimed combination may point to a variant of a sub-combination or a sub-combination.

[0114] Only some implementations and examples of the disclosed technology are described, and other implementations, enhancements, and variations may be made based on what is described and illustrated in this patent document.

[0115] Priority claim and cross reference to related applications

[0116] This patent document claims priority to and the benefit of Korean Patent Application No. 10-2023-0142173, filed on October 23, 2023, which is incorporated by reference in its entirety as a part of the disclosure of this patent document.

Claims

1. A method for manufacturing a semiconductor device, comprising the following steps: forming a first layer including a first substrate, a first plug formed in the first substrate, a photodiode, and a first wiring layer; forming a second layer including a second substrate, a second plug formed in the second substrate, and a second wiring layer; forming a third layer, the third layer comprising a third substrate and a third wiring layer; bonding the first wiring layer of the first layer to the second wiring layer of the second layer; as well as The second substrate of the second layer is bonded to the third wiring layer of the third layer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The steps of forming the first layer include: forming the first substrate; forming the photodiode and the first plug in the first substrate; forming the first wiring layer on the first substrate; and A first bonding pad is formed in a region of the first wiring layer.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The step of forming the second layer comprises: forming the second substrate; forming the second plug on the second substrate; forming the second wiring layer on the second substrate; and A second bonding pad is formed in a region of the second wiring layer.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: The step of forming the third layer comprises: forming the third substrate; forming the third wiring layer on the third substrate; and A third bonding pad is formed in a region of the third wiring layer.

5. The method for manufacturing a semiconductor device according to claim 4, wherein: The step of bonding the first wiring layer of the first layer and the second wiring layer of the second layer includes bonding the first bonding pad of the first layer and the second bonding pad of the second layer.

6. The method for manufacturing a semiconductor device according to claim 5, further comprising: After bonding the first wiring layer of the first layer and the second wiring layer of the second layer, Chemically mechanically polishing (CMP) the first substrate to a depth equal to the top of the first plug of the first layer; etching an upper portion of the first plug including a top portion of the first plug; forming a fourth bonding pad on the first plug; as well as A passivation layer is formed on the first substrate.

7. The method for manufacturing a semiconductor device according to claim 6, further comprising: After forming the passivation layer, Chemically mechanically polishing (CMP) the second substrate to a depth equal to the top of the second plug of the second layer; as well as An upper portion of the second plug including a top portion of the second plug is etched.

8. The method for manufacturing a semiconductor device according to claim 7, further comprising: After etching the top of the second plug, a fifth bonding pad is formed on the second plug.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: The step of bonding the second substrate of the second layer and the third wiring layer of the third layer includes bonding the fifth bonding pad of the second layer and the third bonding pad of the third layer.

10. The method for manufacturing a semiconductor device according to claim 9, further comprising: After bonding the second substrate of the second layer and the third wiring layer of the third layer, the passivation layer of the first layer is removed.

11. The method for manufacturing a semiconductor device according to claim 10, further comprising: After removing the passivation layer of the first layer, forming a color filter over the photodiode of the first layer; as well as Micro lenses are formed on the color filters.

12. A semiconductor device, comprising: First floor; a second layer, the second layer being disposed below the first layer; as well as a third layer, the third layer being disposed below the second layer, Wherein, the first layer includes: A first wiring layer; a first substrate bonded to the first wiring layer; a first plug disposed in a region of the first substrate; and A first bonding pad is disposed in a region of the first wiring layer, wherein the second layer comprises: a second substrate; a second wiring layer bonded to the second substrate; a second bonding pad provided in one region of the second wiring layer and in contact with the first bonding pad; and a second plug formed in a region of the second substrate, and Wherein, the third layer includes: a third substrate; a third wiring layer, the third wiring layer being provided on the third substrate; and A third bonding pad is provided in a region of the third wiring layer.

13. The semiconductor device according to claim 12, wherein: The first layer also includes a fourth bonding pad disposed on the first plug.

14. The semiconductor device according to claim 13, wherein: The second layer also includes a fifth bonding pad disposed under the second plug and contacting the third bonding pad.

15. The semiconductor device according to claim 14, wherein: The first layer also includes: a photodiode disposed in a region of the first substrate; a color filter disposed above the photodiode; and A microlens is disposed on the color filter.

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