Bipolar ion gated transistor based on MoS2 and preparation method thereof

Abstract

The invention discloses a bipolar ion gated transistor based on MoS2 and a preparation method thereof, and belongs to the field of semiconductor design. The transistor comprises a conductive substrate, an insulating dielectric layer arranged on the conductive substrate, a gate electrode, a source electrode and a drain electrode which are arranged on the insulating dielectric layer, a two-dimensional material layer arranged on the source electrode and the drain electrode, and ionic liquid arranged on the two-dimensional material layer, the source electrode, the drain electrode and the gate electrode. Wherein the two-dimensional material layer is made of MoS2. Molybdenum disulfide is used as a semiconductor channel layer, ionic liquid is used as a dielectric layer, an upper layer of the ionic liquid generally plays a role of a top gate, a double-electrode layer with nanoscale thickness can be conveniently formed under low external voltage, and great gate capacitance can be shown, so that the working gate voltage can be obviously reduced.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor design, and specifically relates to a method based on MoS 2 A bipolar ion-gated transistor and a method for preparing the same. Background Art

[0002] In the research of modern artificial synaptic transistors, most synaptic transistors exhibit single polarity synaptic plasticity because the semiconductor channel material is n-type or p-type material, and need to switch voltages of opposite polarity when simulating the excitatory and inhibitory behaviors of biological synapses. In the process of conductivity modulation, a topological inverter is required to generate voltages of opposite polarity, making the peripheral circuit structure more complicated.

[0003] The recently proposed unipolar voltage-regulated device uses a positive or negative voltage as the voltage polarity when regulating the device performance. Traditional transistor devices require the application of positive and negative bidirectional voltages to achieve switching operations, thereby realizing write / erase or excitation / inhibition functions. However, unipolar synaptic transistors only require a voltage of a single polarity, and use the voltage amplitude (i.e., unipolar SVDP) to show inhibition under small voltage stimulation conditions and enhancement under large voltage stimulation conditions. Unipolar voltage regulation can accurately regulate the increase or decrease of the device conductance value under unidirectional voltage, that is, it can simulate the excitation and inhibition behavior of biological synapses under voltages of the same polarity. Therefore, in terms of simulating the function of biological synapses, synaptic transistors that can achieve unipolarity play a huge role. Unipolar regulation not only has advantages in simulating biological synapses, but also has broad application prospects in neuromorphic computing and intelligence.

[0004] However, except for a few materials such as graphene that can realize the conduction of both electrons and holes as majority carriers, most other semiconductor materials can only realize the carriers of either electrons or holes for charge transfer when used in devices, that is, there is a difference between n-type and p-type. Based on this, when the field effect transistor structure device is used in artificial neural synapse simulation, it can only achieve the inhibition and enhancement effect in one direction according to the carrier type of its semiconductor material, and the external gate pulse also needs to be set accordingly, which may face design limitations in large-scale integration. Based on this, someone proposed a bipolar thin film transistor, which overcomes the problem that the field effect transistor can only achieve the inhibition and enhancement effect in one direction when simulating the synaptic function by changing the amplitude of the gate voltage. In actual circuit integration, a smaller working voltage is often used, and the enhancement and inhibition in one direction are modulated in a variety of ways under the same polarity, which can adjust the working state of the transistor from more dimensions (gate voltage, source-drain voltage). For example, in some amplifier circuits that require fine current adjustment, not only can the source-drain current be controlled by the gate voltage, but the magnitude of the output current can also be further adjusted by adjusting the source-drain voltage, thereby more accurately amplifying or suppressing the signal.

[0005] In the face of the above situation, there is an urgent need for a simple and effective artificial synaptic transistor that can use a variety of methods to achieve the excitation and inhibition of biological synapses using unipolar voltage regulation under positive and negative voltages. Summary of the invention

[0006] In view of the shortcomings of the prior art, the present invention aims to provide a MoS 2 The bipolar ion-gated transistor and its preparation method solve the problems in the prior art.

[0007] The purpose of the present invention can be achieved through the following technical solutions:

[0008] A MoS-based 2 Bipolar ion-gated transistors, including:

[0009] Conductive substrate;

[0010] An insulating dielectric layer disposed on the conductive substrate;

[0011] A gate electrode, a source electrode and a drain electrode are arranged on the insulating dielectric layer;

[0012] A two-dimensional material layer disposed on the source electrode and the drain electrode;

[0013] An ionic liquid disposed on the two-dimensional material layer, the source electrode, the drain electrode, and the gate electrode;

[0014] The two-dimensional material layer is made of MoS2 .

[0015] Furthermore, the conductive substrate is made of silicon.

[0016] Furthermore, the material of the insulating dielectric layer is SiO 2 .

[0017] Furthermore, the gate electrode, the source electrode and the drain electrode are all made of platinum.

[0018] Furthermore, the ionic liquid uses DEMETFSI as the electrolyte layer.

[0019] Furthermore, the thickness of the insulating dielectric layer is 300 nm; the thickness of the two-dimensional material layer is 8.3 nm.

[0020] The above one is based on MoS 2 The method for preparing a bipolar ion-gated transistor comprises the following steps:

[0021] S1, after cleaning the conductive substrate, put it into a quartz boat, send it into the chamber of a high-temperature furnace, first introduce nitrogen to expel the air, then introduce oxygen and heat it, and perform dry oxygen oxidation and wet oxygen oxidation in sequence to obtain an insulating dielectric layer;

[0022] S2, spin-coating a positive photoresist onto the insulating dielectric layer, forming an electrode pattern mask on the insulating dielectric layer by photolithography and development, then evaporating Pt by an electron beam evaporation device, and finally washing with acetone to remove the photoresist and the metal layer outside the electrode area to obtain a gate electrode, a source electrode, and a drain electrode;

[0023] S3, MoS was transferred by dry transfer method 2 Transferring to the source and drain electrodes to obtain a two-dimensional material layer;

[0024] S4, use a cotton swab to dip DEME TFSI ionic liquid and cover it on the two-dimensional material layer, source electrode, drain electrode and gate electrode to obtain MoS based 2 Bipolar ion-gated transistor.

[0025] Furthermore, in S2, the spin coating time is 60 seconds, the spin coating speed is 4000 revolutions per minute; the developer is tetramethylammonium hydroxide, and the developing time is 15 seconds.

[0026] Further, in S3, the step of preparing the two-dimensional material layer is:

[0027] Use tape to glue MoS 2 Materials from MoS 2 The blocks were peeled off in layers and then bonded to PDMS;

[0028] Tear off the PDMS from the tape surface to peel off the MoS 2 Material;

[0029] Under a microscope, the MoS 2 The material PDMS is attached to the target positions on the source electrode and the drain electrode and subjected to heat treatment;

[0030] Tear off the PDMS, MoS 2 The material remains at the target location, completing the MoS 2 transfer.

[0031] Furthermore, the heating temperature of the heating treatment is 130° C. and the heating time is 10 min.

[0032] Beneficial effects of the present invention:

[0033] 1. The transistor of the present invention uses molybdenum disulfide as a semiconductor channel layer and DEME TFSI ionic liquid as a dielectric layer. The upper layer of the ionic liquid usually acts as a top gate, and a double electric layer with a nanometer thickness can be easily formed under a low applied voltage. This double electric layer can exhibit a very large gate capacitance, so the working gate voltage can be significantly reduced. The double electric layer can also induce bipolar carrier transport and accumulate extremely high density carriers in the conduction band and valence band of the TMD. This is of great significance for reducing the operating voltage of the transistor and improving its on / off current ratio.

[0034] 2. The present invention selects Pt as the metal electrode. The inert metal can avoid reacting with the ionic liquid, thereby improving the stability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0036] Figure 1 It is a schematic diagram of the overall structure of the bipolar ion-gated transistor based on MoS2 of the present invention;

[0037] Figure 2 is an optical schematic diagram of a bipolar ion-gated transistor based on MoS2 of the present invention;

[0038] Figure 3 is a transfer characteristic diagram of a bipolar ion-gated transistor of MoS2 of the present invention;

[0039] Figure 4 It is a diagram showing enhancement and suppression achieved by regulating the transistor of the present invention under positive voltage;

[0040] Figure 5 It is a diagram showing enhancement and suppression achieved by regulating the transistor of the present invention under negative voltage. DETAILED DESCRIPTION

[0041] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0042] Example 1

[0043] like Figure 1 As shown, a MoS-based 2 Bipolar ion-gated transistors, including:

[0044] Conductive substrate;

[0045] An insulating dielectric layer disposed on the conductive substrate;

[0046] A gate electrode, a source electrode and a drain electrode are arranged on the insulating dielectric layer;

[0047] A two-dimensional material layer disposed on the source electrode and the drain electrode;

[0048] An ionic liquid disposed on the two-dimensional material layer, the source electrode, the drain electrode, and the gate electrode;

[0049] In this embodiment, SiO 2 The insulating dielectric layer is 300nm thick. The gate electrode, drain electrode, and source electrode are made of platinum, with an electrode width of 10um. The two-dimensional material layer is made of MoS2 with a thickness of 8.3nm. The ionic liquid is DEMETFSI, which is used as the electrolyte layer. The conductive substrate is made of silicon.

[0050] Example 2

[0051] In this embodiment, a method based on MoS in Embodiment 1 is disclosed. 2 The method for preparing a bipolar ion-gated transistor comprises the following steps:

[0052] S1, preparing an insulating dielectric layer on the upper end of a conductive substrate (silicon);

[0053] First, the silicon wafer was ultrasonically cleaned with acetone and ethanol for 15 minutes each to remove oil and organic matter on the surface of the silicon wafer. The ultrasonic frequency was 40kHz and the power was 100W.

[0054] Then put the cleaned silicon wafer into a quartz boat and push it into the constant temperature zone of the high-temperature furnace. Close the air inlet and outlet of the high-temperature furnace, first introduce nitrogen with a flow rate of 500sccm and keep it for 15 minutes to remove the air in the reaction chamber. Then turn off the nitrogen, introduce oxygen with a flow rate of 300sccm, and start the dry oxygen oxidation process. After the dry oxygen oxidation is carried out for 1 hour, start the wet oxygen oxidation process. Water vapor is generated by deionized water heated to 95°C, and the water vapor is mixed with oxygen and introduced into the reaction chamber. The oxygen flow rate is maintained at 300sccm, and the water vapor flow rate is controlled at 100sccm by adjusting the temperature and pressure of the water vapor generator. The high-temperature furnace is heated from room temperature to 1050°C at a rate of 10°C / minute. At a temperature of 1050°C, dry oxygen oxidation and wet oxygen oxidation are carried out for a total of 2 hours and 15 minutes. Among them, dry oxygen oxidation is 1 hour and wet oxygen oxidation is 1 hour and 15 minutes. After such an oxidation process, a silicon dioxide layer about 300nm thick can be grown on the surface of the silicon wafer.

[0055] S2, preparing a gate electrode, a source electrode and a drain electrode on the insulating dielectric layer;

[0056] First, a positive photoresist is spin-coated onto the insulating dielectric layer, with a spin-coating time of 60 s and a spin-coating speed of 4000 rpm.

[0057] Then, an electrode pattern mask is formed on the insulating dielectric layer through photolithography and development, wherein the developer used is tetramethylammonium hydroxide and the development time is 15 seconds.

[0058] Finally, Pt with a thickness of 50 nm was sequentially deposited using an electron beam evaporation device, and then washed with acetone to remove the photoresist and the metal layer outside the electrode area to obtain the gate electrode, source electrode, and drain electrode.

[0059] S3, preparing a two-dimensional material layer on the source electrode and the drain electrode using a dry transfer method;

[0060] Use tape to glue MoS 2 Materials from MoS 2 The blocks were peeled off in layers and then bonded to PDMS;

[0061] Tear off the PDMS from the tape surface to peel off the MoS 2 Material;

[0062] Under a microscope, the MoS 2 The material PDMS is attached to the target position on the source electrode and the drain electrode and heated at a temperature of 130°C for 10 minutes.

[0063] Tear off the PDMS, MoS 2 The material remains at the target location, completing the MoS 2 transfer.

[0064] S4, using a sharpened cotton swab to dip a trace amount of DEME TFSI ionic liquid, and covering it on the two-dimensional material layer, source electrode, drain electrode and gate electrode to obtain a MoS-based 2 Bipolar ion-gated transistor;

[0065] The optical microscope image of the transistor is shown in Figure 2 As shown in the figure, it can be seen that: two electrodes in contact with molybdenum disulfide are selected as source electrodes and drain electrodes, and the ionic liquid covers the source electrode, the drain electrode and the gate electrode on the right side of the array.

[0066] Experimental testing

[0067] The transistor prepared in Example 2 is subjected to the following performance tests:

[0068] 1) Test transistor transfer characteristics;

[0069] The test steps are as follows: Fixed V DS =0.5V, the gate voltage scans from 0V to 3V, and then scans back from 3V to 0V, then the gate voltage scans from 0V to -3V, and then scans back from -3V to 0V.

[0070] Test results such as Figure 3 As shown in the figure, it can be seen that when V g When it is positive, the source-drain current I Ds As the applied gate voltage increases, it increases, showing the electronic conductivity characteristics of n-type semiconductor materials. g Up to 3V, I Ds No saturation was observed, indicating high performance transistor operation. g When it is negative, the source-drain current I Ds It increases with the applied gate voltage, showing the hole conduction characteristics of the p-type semiconductor material, indicating that the device is a bipolar transistor with a high switching ratio for both electrons and holes.

[0071] 2) The transistor is regulated under positive voltage to achieve enhancement and inhibition;

[0072] Figure 4 The experimental parameters corresponding to (a) are: fixed V DS =0.5V, apply 20 gate voltage pulses with a pulse width of 2.5V, a pulse duration of 50ms, and a pulse interval of 30ms; fix V DS =0.5V, apply 20 gate voltage pulses with a pulse width of 1.9V, a pulse duration of 50ms, and a pulse interval of 30ms.

[0073] Figure 4The experimental parameters corresponding to (b) are: fixed V DS =0.5V, apply 20 gate voltage pulses with a pulse width of 2.5V, a pulse duration of 50ms, and a pulse interval of 30ms; fix V DS =1.5V, apply 20 gate voltage pulses with a pulse width of 2.5V, a pulse duration of 50ms, and a pulse interval of 30ms.

[0074] from Figure 4 As can be seen from (a) in the figure: when V is fixed DS =0.5V, by applying a larger pulse voltage (2.5V), as the number of pulses increases, the output drain-source current I DS As it increases, at a fixed V DS =0.5V, by applying a smaller pulse voltage (1.9), as the number of pulses increases, the output drain-source current Ids decreases accordingly. It can be concluded that enhancement and suppression can be achieved by adjusting the amplitude of the pulse voltage under the same polarity.

[0075] from Figure 4 It can be seen from (b) that under the same gate voltage pulse conditions (50 gate voltage pulses with a pulse width of 2.5V, a pulse duration of 50ms, and a pulse interval of 30ms), applying a smaller V DS (0.5V), as the number of pulses increases, the output drain-source current I DS Applying a larger V DS (1.5V), as the number of pulses increases, the output drain-source current I DS It can be concluded that under the same polarity, by changing V DS The amplitude is enhanced and suppressed.

[0076] 3) Transistor regulation under negative voltage to achieve enhancement and suppression

[0077] Figure 5 The experimental parameters corresponding to (a) are: fixed V DS = -1.5V, apply 20 gate voltage pulses with a pulse width of -1.7V, a pulse duration of 50ms, and a pulse interval of 30ms. Fixed V DS =-1.5V, apply 20 gate voltage pulses with a pulse width of -1V, a pulse duration of 50ms, and a pulse interval of 30ms.

[0078] Figure 5 The experimental parameters corresponding to (b) are: fixed V DS= -0.5V, apply 20 gate voltage pulses with a pulse width of -1V, a pulse duration of 50ms, and a pulse interval of 30ms. Fixed V DS = -1V, apply 20 gate voltage pulses with a pulse width of -1V, a pulse duration of 50ms, and a pulse interval of 30ms. Fixed V DS = -1.5V, apply 20 gate voltage pulses with a pulse width of -1V, a pulse duration of 50ms, and a pulse interval of 30ms. Fixed V DS = -1.8V, apply 20 gate voltage pulses with a pulse width of -1V, a pulse duration of 50ms, and a pulse interval of 30ms. Fixed V DS =-2V, apply 20 gate voltage pulses with a pulse width of -1V, a pulse duration of 50ms, and a pulse interval of 30ms.

[0079] Figure 5 As can be seen from (a) in the figure: when V is fixed DS = -1.5V, by applying a larger pulse voltage (-1.7V), as the number of pulses increases, the output drain-source current I DS As it increases, at a fixed V DS = -1.5V, by applying a smaller pulse voltage (-1V), as the number of pulses increases, the output drain-source current I DS It decreases accordingly, which shows that enhancement and suppression can be achieved by adjusting the amplitude of the pulse voltage at the same polarity.

[0080] Figure 5 It can be seen from (b) that under the same gate voltage pulse conditions (20 gate voltage pulses with a pulse width of -1V, a pulse duration of 50ms, and a pulse interval of 30ms), applying a smaller V DS (-1.5V), as the number of pulses increases, the output drain-source current I DS Applying a larger V DS (-2V), as the number of pulses increases, the output drain-source current I DS It can be concluded that under the same polarity, by changing V DS The amplitude is enhanced and suppressed.

[0081] In the description of this specification, the description with reference to the terms "one embodiment", "example", "specific example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0082] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments, and the above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, and these changes and improvements all fall within the scope of the present invention to be protected.

Claims

1. A bipolar ion-gated transistor based on MoS2, characterized in that: include: Conductive substrate; An insulating dielectric layer disposed on the conductive substrate; A gate electrode, a source electrode and a drain electrode are arranged on the insulating dielectric layer; A two-dimensional material layer disposed on the source electrode and the drain electrode; An ionic liquid disposed on the two-dimensional material layer, the source electrode, the drain electrode, and the gate electrode; The two-dimensional material layer is made of MoS2.

2. A bipolar ion-gated transistor based on MoS2 according to claim 1, characterized in that: The conductive substrate is made of silicon.

3. A bipolar ion-gated transistor based on MoS2 according to claim 1, characterized in that: The insulating dielectric layer is made of SiO2.

4. The bipolar ion-gated transistor based on MoS2 according to claim 1, characterized in that: The gate electrode, source electrode and drain electrode are all made of platinum.

5. The bipolar ion-gated transistor based on MoS2 according to claim 1, characterized in that: The ionic liquid uses DEMETFSI as the electrolyte layer.

6. The bipolar ion-gated transistor based on MoS2 according to claim 1, characterized in that: The thickness of the insulating medium layer is 300 nm; the thickness of the two-dimensional material layer is 8.3 nm.

7. A method for preparing a bipolar ion-gated transistor based on MoS2 according to any one of claims 1 to 6, characterized in that: The following steps are involved: S1, after cleaning the conductive substrate, put it into a quartz boat, send it into the chamber of a high-temperature furnace, first introduce nitrogen to expel the air, then introduce oxygen and heat it, and perform dry oxygen oxidation and wet oxygen oxidation in sequence to obtain an insulating dielectric layer; S2, spin-coating a positive photoresist onto the insulating dielectric layer, forming an electrode pattern mask on the insulating dielectric layer by photolithography and development, then evaporating Pt by an electron beam evaporation device, and finally washing with acetone to remove the photoresist and the metal layer outside the electrode area to obtain a gate electrode, a source electrode, and a drain electrode; S3, using a dry transfer method to transfer MoS2 onto the source electrode and the drain electrode to obtain a two-dimensional material layer; S4, use a cotton swab to dip DEME TFSI ionic liquid and cover it on the two-dimensional material layer, source electrode, drain electrode and gate electrode to obtain a MoS2-based bipolar ion-gated transistor.

8. The method for preparing a bipolar ion-gated transistor based on MoS2 according to claim 7, characterized in that: In S2, the spin coating time is 60 seconds, the spin coating speed is 4000 revolutions per minute; the developer is tetramethylammonium hydroxide, and the developing time is 15 seconds.

9. The method for preparing a bipolar ion-gated transistor based on MoS2 according to claim 7, characterized in that: In S3, the steps of preparing the two-dimensional material layer are: Use tape to peel the MoS2 material off from the MoS2 block in layers, and then bond it to PDMS; Tear off the PDMS from the tape surface to allow the PDMS to peel off the MoS2 material; Under a microscope, PDMS with MoS2 material is attached to the target positions on the source electrode and the drain electrode and heated; The PDMS is peeled off, and the MoS2 material remains at the target location, completing the transfer of MoS2.

10. The method for preparing a bipolar ion-gated transistor based on MoS2 according to claim 9, characterized in that: The heating temperature of the heating treatment is 130° C. and the heating time is 10 min.

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