Electrostatic clamp with structured electrode structured by bonding

Abstract

Embodiments relating to an electrostatic wafer holder and methods for forming and modifying an electrode structure of an electrostatic wafer holder are disclosed herein. The wafer clamp includes an electrode structure having a plurality of tabs in a dielectric layer interconnected via a ground line. By modifying the electrode structure in the vicinity of the ground wire by post-bonding structuring or the like, the electric field can be reduced, resulting in lower cyclic inductive charging.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. application No. 63 / 378,892, filed on October 10, 2022, and the entire contents of that U.S. application are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to electrostatic wafer chucks and methods for forming and modifying electrode structures of electrostatic wafer chucks. Background Art

[0004] A lithographic apparatus is a machine that applies a desired pattern to a substrate or wafer, typically to a target portion of a wafer. A lithographic apparatus may be used, for example, in the manufacture of integrated circuits (ICs). In that case, a pattern forming device, interchangeably referred to as a mask or reticle, may be used to produce a circuit pattern to be formed on a single layer of the IC being formed. This pattern may be transferred to a target portion (e.g., a portion including a die, a die, or several dies) on a wafer (e.g., a silicon wafer). The transfer of the pattern is typically performed via imaging onto a layer of radiation-sensitive material (e.g., a resist) disposed on the wafer. Typically, a single wafer will include a network of adjacent target portions that are patterned in succession. Conventional lithographic apparatus include: a so-called stepper, in which each target portion is irradiated by exposing the entire pattern to the target portion at once; and a so-called scanner, in which each target portion is irradiated by scanning the pattern via a radiation beam in a given direction (the "scanning" direction) while simultaneously scanning the target portion parallel or antiparallel to such a scanning direction. It is also possible to transfer the pattern from the patterning device to the wafer by imprinting the pattern onto the wafer.

[0005] As semiconductor manufacturing processes continue to advance, the size of circuit elements has been continuously reduced for decades, while the amount of functional elements such as transistors per device has been steadily increasing, following a trend often referred to as "Moore's Law". In order to keep up with Moore's Law, the semiconductor industry is chasing technologies that enable the production of smaller and smaller features. In order to project a pattern onto a wafer, a lithography apparatus can use electromagnetic radiation. The wavelength of this radiation determines the minimum size of the features patterned on the wafer. Typical wavelengths currently in use are: 365 nm (i-line), 248 nm, and 193 nm in deep ultraviolet (DUV) radiation systems; and 13.5 nm in extreme ultraviolet (EUV) radiation systems. EUV radiation, such as electromagnetic radiation having a wavelength of about 50 nanometers (nm) or less (sometimes also referred to as soft x-rays) and including light at a wavelength of about 13.5 nm, can be used in or with a lithography apparatus to produce very small features in or on a wafer such as a silicon wafer. For example, a lithography apparatus using EUV radiation having a wavelength in the range of 4 nm to 20 nm (eg, 6.7 nm or 13.5 nm) can be used to form smaller features on a wafer than a lithography apparatus using radiation having a wavelength of 193 nm.

[0006] A wafer chuck is typically used to hold a wafer (i.e., a substrate) on a wafer stage. The wafer chuck may be, for example, a vacuum chuck for use in a DUV radiation system or an electrostatic chuck for use in an EUV radiation system. It is desirable to specify and maintain the friction properties (e.g., friction, hardness, wear, etc.) on the surface of the wafer stage. The wafer stage, or a wafer chuck attached to the wafer stage, has a surface level tolerance that may be difficult to meet due to the precision requirements of the lithography and measurement processes. A wafer that is relatively thin (e.g., thickness <1.0 millimeter (mm)) compared to the width of its surface area (e.g., width>100.0 mm) is particularly sensitive to the non-uniformity of the wafer stage. Because the ultra-smooth surfaces in contact may become stuck together, the problem persists when the wafer must be disengaged from the wafer stage. In order to reduce the smoothness of the surface interfacing with the wafer, the surface of the wafer stage or wafer chuck may include, for example, a protrusion formed by patterning and etching the wafer. However, the wafer may sag in the region between the burls due to a combination of forces applied to the wafer by the burls, electrostatic clamping, backfill gas pressure, wafer hardness, and / or gravity.There is a need for an improved wafer clamp. Summary of the invention

[0007] Various embodiments of electrostatic wafer chucks and methods for forming and modifying electrode structures of electrostatic wafer chucks are disclosed herein.

[0008] Some embodiments are directed to a support structure for positioning an exchangeable object in a lithographic device. In some embodiments, the support structure may form a clamping mechanism and include a plurality of burls extending from a top surface of the clamping mechanism, wherein the clamping mechanism includes a dielectric layer. In some embodiments, a plurality of ground wires may be coated on the top surface. In some embodiments, at least one of the plurality of ground wires may be configured to interconnect with at least one of the plurality of burls. In some embodiments, an electrode layer may be embedded in the dielectric layer below the top surface. In some embodiments, the electrode layer may include an insulating material in the electrode layer. In some embodiments, a portion of the insulating material may be shaped to correspond to an outer contour of the plurality of ground wires so that an inner contour of the insulating material may be aligned with the outer contour of the plurality of ground wires.

[0009] In some embodiments, shaping a portion of the insulating material may enhance the effect of charging near the plurality of ground lines.

[0010] In some embodiments, the shaping may be accomplished by post-bonding structuring.

[0011] In some embodiments, the post-bonding structuring is performed using a laser beam.

[0012] In some embodiments, the plurality of burls may include a conductive coating.

[0013] In some embodiments, the plurality of ground lines may be configured to couple the plurality of burls to a ground potential.

[0014] In some embodiments, embedding the electrode layer may include embedding using a chromium layer.

[0015] In some embodiments, the electrode layer may be formed with a contact hole.

[0016] In some embodiments, the electrode layer may be patterned.

[0017] In some embodiments, the exchangeable object and the dielectric layer may be positioned about 10 microns apart.

[0018] In some embodiments, a vacuum may be formed between the exchangeable object and the dielectric layer.

[0019] The following describes in detail the additional features of the present disclosure and the structure and operation of each embodiment with reference to the accompanying drawings. It should be noted that the present disclosure is not limited to the specific embodiments described herein. These embodiments are presented herein only for illustrative purposes. Based on the teachings included herein, those skilled in the relevant art will understand additional embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings, which are incorporated herein and form a part of this specification, illustrate the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable one skilled in the relevant art to make and use the embodiments described herein.

[0021] Figure 1A Schematic diagram showing a reflective lithography apparatus according to some embodiments.

[0022] Figure 1B Schematic diagram showing a transmissive lithography apparatus according to some embodiments.

[0023] Figure 2 A more detailed schematic diagram showing a reflective lithography apparatus according to some embodiments.

[0024] Figure 3 A schematic diagram illustrating a lithography cell according to some embodiments is shown.

[0025] Figure 4A and Figure 4B Schematic diagram showing a lithographic apparatus according to some embodiments.

[0026] Figure 5 A cross section of an electrostatic wafer chuck at the top side of a dielectric layer is shown in accordance with some embodiments.

[0027] Figure 6 A cross section of an electrostatic wafer chuck is shown in accordance with some embodiments.

[0028] Figure 7 Another cross section of an electrostatic wafer chuck is shown in accordance with some embodiments.

[0029] Fig. 8A , Figure 8B and Figure 8C A top view of the electrode plane and a close-up of the electrode plane and the MH line are shown, respectively, according to some embodiments.

[0030] Fig. 9 Depicted is the electric field strength in the z-direction for an electrostatic wafer chuck according to some embodiments.

[0031] Fig.10 is a flow chart illustrating a process for forming and modifying an electrode structure of an electrostatic wafer chuck according to some embodiments.

[0032] Features of the present disclosure will become more apparent from the detailed description set forth below in conjunction with the accompanying drawings, in which the same reference symbols identify corresponding elements throughout the entire text. In the accompanying drawings, the same element numbers generally indicate identical, functionally similar, and / or structurally similar elements. In addition, generally, the leftmost digit of a reference number identifies the drawing in which the reference number first appears. Unless otherwise indicated, the drawings provided throughout the present disclosure should not be construed as being to scale. DETAILED DESCRIPTION

[0033] This specification discloses one or more embodiments having features of the present disclosure. The disclosed one or more embodiments are provided as examples. The scope of the present disclosure is not limited to the disclosed one or more embodiments. The claimed features are defined by the claims attached hereto.

[0034] The described embodiments and references in this specification to "one embodiment," "an embodiment," "an example embodiment," etc. indicate that the described embodiments may include certain features, structures, or characteristics, but every embodiment may not necessarily include the certain features, structures, or characteristics. Moreover, these phrases do not necessarily refer to the same embodiment. Furthermore, when a certain feature, structure, or characteristic is described in conjunction with an embodiment, it should be understood that it is within the purview of those skilled in the art to implement such feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described.

[0035] For ease of description, spatially relative terms (such as "below," "below," "lower," "above," "upper," etc.) may be used herein to describe the relationship of one element or feature illustrated in the figures to another element or feature. Spatially relative terms are also intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0036] As used herein, the term "about" indicates a value of a given quantity that may vary based on a particular technology. Based on a particular technology, the term "about" may indicate, for example, a value of a given quantity that varies within plus or minus 10% to 30% of a value (e.g., ±10%, ±20%, or ±30% of a value).

[0037] Embodiments of the present disclosure may be implemented in hardware, firmware, software, or any combination thereof. Embodiments of the present disclosure may also be implemented as instructions stored on a machine-readable medium, which may be read and executed by one or more processors. A machine-readable medium may include any mechanism for storing or transmitting information in a form that can be read by a machine (e.g., a computing device). For example, a machine-readable medium may include: a read-only memory (ROM); a random access memory (RAM); a disk storage medium; an optical storage medium; a flash memory device; an electrical, optical, acoustic, or other form of propagation signal (e.g., a carrier wave, an infrared signal, a digital signal, etc.), etc. In addition, firmware, software, routines, and / or instructions may be described herein as performing specific actions. However, it should be understood that these descriptions are merely for convenience, and that these actions are actually caused by a computing device, a processor, a controller, or other devices that execute firmware, software, routines, instructions, etc.

[0038] However, before describing such embodiments in further detail, it is instructive to present an example environment that can be used to implement embodiments of the present disclosure.

[0039] An example lithography system will now be described.

[0040] Figure 1A and Figure 1B Schematic illustrations of a lithographic apparatus 100 and a lithographic apparatus 100', respectively, which can be used to implement embodiments of the present disclosure are shown. The lithographic apparatus 100 and the lithographic apparatus 100' each include the following: an illumination system (illuminator) IL, which is configured to condition a radiation beam B (e.g., deep ultraviolet or extreme ultraviolet radiation); a support structure (e.g., a mask stage) MT, which is configured to support a pattern forming device (e.g., a mask, a reticle, or a dynamic pattern forming device) MA and is connected to a first positioner PM configured to accurately position the pattern forming device MA; and a wafer stage (e.g., a substrate stage) WT, which is configured to hold a wafer (e.g., a wafer coated with a resist) W and is connected to a second positioner PW configured to accurately position the wafer W. The lithographic apparatus 100 and 100' also have a projection system PS, which is configured to project a pattern imparted to the radiation beam B by the pattern forming device MA onto a target portion (e.g., including one or more tube cores) C of the wafer W. In lithographic apparatus 100, patterning device MA and projection system PS are reflective. In lithographic apparatus 100', patterning device MA and projection system PS are transmissive.

[0041] The illumination system IL may include various types of optical components for directing, shaping or controlling the radiation beam B, such as refractive, reflective, catadioptric, magnetic, electromagnetic, electrostatic or other types of optical components, or any combination thereof.

[0042] The support structure MT holds the patterning device MA in a manner that depends on the orientation of the patterning device MA relative to the reference frame, the design of at least one of the lithographic apparatuses 100 and 100', and other conditions, such as whether the patterning device MA is held in a vacuum environment. The support structure MT may use mechanical, vacuum, electrostatic or other clamping techniques to hold the patterning device MA. For example, the support structure may be a frame or a stage, which may be fixed or movable as desired. By using sensors, the support structure MT may ensure that the patterning device MA is in a desired position, for example relative to the projection system PS.

[0043] The term “patterning device” MA should be broadly interpreted as referring to any device that can be used to impart a radiation beam B with a pattern in its cross-section so as to create a pattern in a target portion C of the wafer W. The pattern imparted to the radiation beam B may correspond to a specific functional layer in a device created in the target portion C to form an integrated circuit.

[0044] The terms "inspection equipment", "metrology system" and the like may be used herein to refer to, for example, a device or system used to measure properties of a structure (e.g., overlay error, critical dimension parameters) or used in a lithography apparatus to check the alignment of a wafer (e.g., alignment equipment).

[0045] The pattern forming device MA may be a transmissive type (e.g. Figure 1B lithographic apparatus 100') or a reflective type (such as in Figure 1A 100). Examples of patterning devices MA include reticles, masks, programmable mirror arrays, or programmable LCD panels. Masks are well known in lithography and include mask types such as binary, alternating phase shift, or attenuated phase shift, as well as various hybrid mask types. Examples of programmable mirror arrays use a matrix arrangement of small mirrors, each of which can be individually tilted to reflect an incident radiation beam in different directions. The tilted mirrors impart a pattern in a radiation beam B that is reflected by the matrix of small mirrors.

[0046] The term "projection system" PS may encompass any type of projection system suitable for the exposure radiation being used or for other factors such as the use of an immersion liquid on the wafer W or the use of a vacuum, including refractive, reflective, catadioptric, magnetic, electromagnetic and electrostatic optical systems, or any combination thereof. A vacuum environment may be used for EUV or electron beam radiation, since other gases may absorb excess radiation or electrons. Therefore, a vacuum environment may be provided to the entire beam path by means of vacuum walls and a vacuum pump.

[0047] The lithographic apparatus 100 and / or lithographic apparatus 100' may be of a type having two (dual stage) or more wafer tables WT (and / or two or more mask tables). In these "multi-stage" machines, the additional wafer tables WT may be used in parallel, or preparatory steps may be performed on one or more tables while one or more other wafer tables WT are being used for exposure. In some cases, the additional tables may not be wafer tables WT.

[0048] The lithographic apparatus may also be of a type in which at least a portion of the wafer may be covered by a liquid having a relatively high refractive index, such as water, so as to fill the space between the projection system and the wafer. Immersion liquid may also be applied to other spaces in the lithographic apparatus, for example, the space between the mask and the projection system. Immersion techniques are well known in the art for increasing the numerical aperture of the projection system. The term "immersion" as used herein does not mean that structures such as the wafer are necessarily immersed in the liquid, but only means that the liquid is located between the projection system and the wafer during exposure.

[0049] refer to Figure 1A and Figure 1B , the illuminator IL receives a radiation beam from a radiation source SO. For example, when the source SO is an excimer laser, the source SO and the lithographic apparatus 100, 100' may be separate physical entities. In such a case, the source SO is not considered to form part of the lithographic apparatus 100 or 100', and the radiation beam B is delivered to the lithographic apparatus 100 or 100' by means of a beam delivery system BD (in the case of a beam delivery system BD) comprising, for example, suitable directional mirrors and / or a beam expander. Figure 1B In other cases, for example, when the source SO is a mercury lamp, the source SO may be an integral part of the lithographic apparatus 100, 100'. The source SO and the illuminator IL together with the beam delivery system BD may be referred to as a radiation system where necessary.

[0050] The illuminator IL may comprise an adjuster AD (at Figure 1B In general, at least the outer radial extent and / or the inner radial extent (commonly referred to as "σ-outer" and "σ-inner", respectively) of the intensity distribution in a pupil plane of the illuminator can be adjusted. In addition, the illuminator IL may include various other components (in Figure 1B The illuminator IL may be used to condition the radiation beam B to have a desired uniformity and intensity distribution in its cross-section.

[0051] refer to Figure 1A, the radiation beam B is incident on a patterning device (e.g., a mask) MA held on a support structure (e.g., a mask table) MT and is patterned by the patterning device MA. In the lithographic apparatus 100, the radiation beam B is reflected from the patterning device (e.g., a mask) MA. After reflection from the patterning device (e.g., a mask) MA, the radiation beam B passes through a projection system PS, which focuses the radiation beam B onto a target portion C of a wafer W. With the aid of a second positioner PW and a position sensor IF2 (e.g., an interferometric device, a linear encoder, or a capacitive sensor), the wafer table WT can be accurately moved (e.g., in order to position a different target portion C in the path of the radiation beam B). Similarly, a first positioner PM and a further position sensor IF1 can be used to accurately position the patterning device (e.g., a mask) MA relative to the path of the radiation beam B. The patterning device (e.g., a mask) MA and the wafer W can be aligned using mask alignment marks M1, M2 and wafer alignment marks P1, P2.

[0052] refer to Figure 1B , the radiation beam B is incident on a patterning device (e.g., mask MA) held on a support structure (e.g., mask table MT) and is patterned by the patterning device. Having traversed the mask MA, the radiation beam B passes through a projection system PS which focuses the beam onto a target portion C of the wafer W. The projection system has a pupil conjugate PPU to the illumination system pupil IPU. Portions of the radiation diverge from the intensity distribution at the illumination system pupil IPU and traverse the mask pattern without being affected by diffraction at the mask pattern, and produce an image of the intensity distribution at the illumination system pupil IPU.

[0053] The projection system PS projects an image of a mask pattern MP onto a resist layer coated on a wafer W, wherein the image is formed by a diffraction beam generated from the marking pattern MP by radiation from the intensity distribution. For example, the mask pattern MP may include an array of lines and spaces. Diffraction of radiation at the array and other than the zero-order diffraction generates a steered diffraction beam having a change of direction in a direction perpendicular to the lines. The non-diffracted beam (i.e., the so-called zero-order diffraction beam) traverses the pattern without any change in the propagation direction. The zero-order diffraction beam traverses the upper lens or upper lens group of the projection system PS upstream of the pupil conjugate PPU of the projection system PS to reach the pupil conjugate PPU. The portion of the intensity distribution in the plane of the pupil conjugate PPU and associated with the zero-order diffraction beam is an image of the intensity distribution in the illumination system pupil IPU of the illumination system IL. The aperture device PD is, for example, arranged at or approximately at a plane including the pupil conjugate PPU of the projection system PS.

[0054] The projection system PS is arranged to capture not only the zero-order diffraction beam, but also the first-order, or first-order and higher-order diffraction beams (not shown) by means of a lens or lens group L. In some embodiments, dipole illumination for imaging a line pattern extending in a direction perpendicular to the line can be used to exploit the resolution enhancement effect of dipole illumination. For example, the first-order diffraction beam interferes with the corresponding zero-order diffraction beam at the level of the wafer W, and an image of the line pattern MP is produced with the highest possible resolution and process window (i.e., the available focal depth combined with the allowable exposure dose deviation). In some embodiments, astigmatism aberrations can be reduced by providing radiation poles (not shown) in the opposite quadrants of the illumination system pupil IPU. In addition, in some embodiments, astigmatism aberrations can be reduced by blocking the zero-order beam associated with the radiation poles in the opposite quadrant in the conjugate pupil PPU of the projection system. This situation is described in more detail in US 7,511,799 B2 issued on March 31, 2009, which is incorporated herein by reference in its entirety.

[0055] With the aid of a second positioner PW and a position sensor IFD (e.g. an interferometric device, a linear encoder or a capacitive sensor), the wafer table WT can be accurately moved (e.g. to position a different target portion C in the path of the radiation beam B). Similarly, the first positioner PM and another position sensor ( Figure 1B ) can be used to accurately position the mask MA relative to the path of the radiation beam B (for example after mechanical retrieval from a mask library or during scanning).

[0056] Typically, movement of the mask table MT may be achieved with the aid of a long-stroke module (coarse positioning) and a short-stroke module (fine positioning) forming part of the first positioner PM. Similarly, movement of the wafer table WT may be achieved using a long-stroke module and a short-stroke module forming part of the second positioner PW. In the case of a stepper (as opposed to a scanner), the mask table MT may be connected only to a short-stroke actuator, or may be fixed. Mask MA and wafer W may be aligned using mask alignment marks M1, M2 and wafer alignment marks P1, P2. Although the wafer alignment marks (as illustrated) occupy dedicated target portions, the marks may be located in the spaces between target portions (these marks are referred to as scribe alignment marks). Similarly, in the case where more than one die is provided on the mask MA, the mask alignment marks may be located between the dies.

[0057] The mask table MT and the patterning device MA may be in a vacuum chamber V, wherein an in-vacuum robot IVR may be used to move the patterning device, such as a mask, into and out of the vacuum chamber. Alternatively, when the mask table MT and the patterning device MA are outside the vacuum chamber, an out-of-vacuum robot may be used for various transfer operations similar to the in-vacuum robot IVR. Both the in-vacuum robot and the out-of-vacuum robot need to be calibrated for smooth transfer of any payload (e.g., mask) to the fixed kinematic mount of the transfer station.

[0058] The lithographic apparatus 100 and 100' may be used in at least one of the following modes:

[0059] 1. In step mode, the support structure (e.g. mask table) MT and wafer table WT are kept substantially stationary while the entire pattern imparted to the radiation beam B is projected onto a target portion C at one time (i.e. a single static exposure). Next, the wafer table WT is shifted in the X and / or Y direction so that a different target portion C can be exposed.

[0060] 2. In scan mode, the support structure (e.g. mask table) MT and wafer table WT are scanned synchronously while a pattern imparted to radiation beam B is projected onto a target portion C (i.e. a single dynamic exposure). The speed and direction of the wafer table WT relative to the support structure (e.g. mask table) MT may be determined by the (de-)magnification and image reversal characteristics of the projection system PS.

[0061] 3. In another mode, the support structure (e.g., mask table) MT is kept substantially stationary, holding the programmable patterning device, and the wafer table WT is moved or scanned while a pattern imparted to the radiation beam B is projected onto a target portion C. A pulsed radiation source SO may be used, and the programmable patterning device updated as required after each movement of the wafer table WT or between successive radiation pulses during a scan. This mode of operation may be readily applicable to maskless lithography utilizing a programmable patterning device, such as a programmable mirror array.

[0062] Combinations and / or variations on the described modes of use or entirely different modes of use may also be used.

[0063] In further embodiments, the lithographic apparatus 100 includes an extreme ultraviolet (EUV) source configured to generate an EUV radiation beam for EUV lithography. Typically, the EUV source is configured in a radiation system, and a corresponding illumination system is configured to condition the EUV radiation beam of the EUV source.

[0064] Figure 2The lithographic apparatus 100 is shown in more detail and includes a source collector apparatus SO, an illumination system IL, and a projection system PS. The source collector apparatus SO is constructed and arranged so that a vacuum environment can be maintained in an enclosure 220 of the source collector apparatus SO. The EUV radiation emitting plasma 210 can be formed by a discharge generating a plasma source. EUV radiation can be generated by a gas or vapor (e.g., Xe gas, Li vapor, or Sn vapor), wherein a very hot plasma 210 is generated to emit radiation in the EUV range of the electromagnetic spectrum. For example, the very hot plasma 210 is generated by a discharge that generates an at least partially ionized plasma. In order to efficiently generate radiation, a partial pressure of, for example, 10 Pa of Xe, Li, Sn vapor, or any other suitable gas or vapor may be required. In some embodiments, a plasma of excited tin (Sn) is provided to generate EUV radiation.

[0065] The radiation emitted by the hot plasma 210 is transferred from the source chamber 211 to the collector chamber 212 via an optional gas barrier or contaminant trap 230 (also referred to as a contaminant barrier or fin trap in some cases) positioned in or behind an opening in the source chamber 211. The contaminant trap 230 may include a channel structure. The contaminant trap 230 may also include a gas barrier, or a combination of a gas barrier and a channel structure. The contaminant trap or contaminant barrier 230 further indicated herein includes at least a channel structure.

[0066] The collector chamber 212 may include a radiation collector CO, which may be a so-called grazing incidence collector. The radiation collector CO has an upstream radiation collector side 251 and a downstream radiation collector side 252. Radiation traversing the collector CO may be reflected from the grating spectral filter 240 to be focused in a virtual source point INTF. The virtual source point INTF is often referred to as an intermediate focus, and the source collector device is arranged so that the intermediate focus INTF is located at or near an opening 219 in the enclosure structure 220. The virtual source point INTF is an image of the radiation emitting plasma 210. The grating spectral filter 240 is used, in particular, to suppress infrared (IR) radiation.

[0067] The radiation then traverses an illumination system IL which may include a faceted field mirror arrangement 222 and a faceted pupil mirror arrangement 224 arranged to provide a desired angular distribution of the radiation beam 221 at the patterning device MA, and a desired uniformity of radiation intensity at the patterning device MA. After reflection of the radiation beam 221 at the patterning device MA held by the support structure MT, a patterned beam 226 is formed and is imaged by the projection system PS via reflective elements 228, 229 onto a wafer W held by a wafer stage or wafer table WT.

[0068] In general, there may be more elements than shown in the illumination optics unit IL and the projection system PS. Depending on the type of lithographic apparatus, a grating spectral filter 240 may optionally be present. In addition, there may be more than Figure 2 More mirrors than the one shown in FIG. 1 may be present in the projection system PS. Figure 2 The reflective elements shown in FIG. 5 may include up to six additional reflective elements.

[0069] like Figure 2 The collector optics CO illustrated in FIG. 1 is depicted as a nested collector with grazing incidence reflectors 253, 254 and 255, merely as an example of a collector (or collector mirror). The grazing incidence reflectors 253, 254 and 255 are arranged axially symmetrically around the optical axis O, and this type of collector optics CO is preferably used in combination with a discharge produced plasma source (often referred to as a DPP source).

[0070] An exemplary lithography cell will now be described.

[0071] Figure 3A lithography unit 300 according to some embodiments is shown, which is sometimes also referred to as a lithography cell or cluster. The lithography apparatus 100 or 100' may form part of the lithography unit 300. The lithography unit 300 may also include one or more devices to perform pre-exposure processes and post-exposure processes in pairs of wafers. In some examples, these include a spin coater SC for depositing a resist layer, a developer DE for developing the exposed resist, a chill plate CH, and a baking plate BK. A wafer conveyor or robot RO picks up wafers from input / output ports I / O1, I / O2, moves wafers between different process devices, and transfers wafers to a feed station LB of the lithography apparatus 100 or 100'. These devices, which are often collectively referred to as track or coating and developing systems, are under the control of a track or coating and developing system control unit TCU, which itself is controlled by a management control system SCS, which also controls the lithography apparatus via a lithography control unit LACU. Therefore, different devices can be operated to maximize production volume and processing efficiency.

[0072] An exemplary inspection apparatus will now be described.

[0073] In order to control the lithography process to accurately place the device features on the wafer, alignment marks are usually set on the wafer, and the lithography equipment includes one or more inspection devices for accurately positioning the marks on the wafer. These alignment devices are actually position measurement devices. Different types of marks and different types of alignment devices and / or systems are known from different times and different manufacturers. The type of system widely used in current lithography equipment is based on a self-reference interferometer as described in U.S. Patent No. 6,961,116 (den Boef et al.). Typically, the marks are measured separately to obtain the X position and the Y position. However, the technology described in U.S. Publication No. 2009 / 195768 A (Bijnen et al.) can be used to perform a combined X measurement and Y measurement. The entire contents of these two disclosures are incorporated herein by reference.

[0074] Figure 4A Schematic diagram showing a cross-sectional view of an inspection apparatus 400 that may be implemented as part of a lithographic apparatus 100 or 100' according to some embodiments. In some embodiments, the inspection apparatus 400 may be configured to align a wafer (e.g., wafer W) relative to a patterning device (e.g., patterning device MA). The inspection apparatus 400 may also be configured to detect positions of alignment marks on the wafer and use the detected positions of the alignment marks to align the wafer relative to the patterning device or other components of the lithographic apparatus 100 or 100'. Such alignment of the wafer may ensure accurate exposure of one or more patterns on the wafer.

[0075] In some embodiments, the inspection device 400 may include an illumination system 412, a beam splitter 414, an interferometer 426, a detector 428, a beam analyzer 430, and an overlap calculation processor 432. The illumination system 412 may be configured to provide an electromagnetic narrowband radiation beam 413 having one or more passbands. In an example, the one or more passbands may be within a spectrum of wavelengths between about 500 nm and about 900 nm. In another example, the one or more passbands may be discrete narrow passbands within a spectrum of wavelengths between about 500 nm and about 900 nm. The illumination system 412 may also be configured to provide one or more passbands having a substantially constant center wavelength (CWL) value over a long period of time (e.g., over the lifetime of the illumination system 412). Such a configuration of the illumination system 412 may help prevent the actual CWL value from shifting from the desired CWL value as discussed above in the current alignment system. And as a result, the use of a constant CWL value may improve the long-term stability and accuracy of an alignment system (eg, inspection apparatus 400 ) compared to current alignment apparatuses.

[0076] In some embodiments, beam splitter 414 can be configured to receive radiation beam 413 and split radiation beam 413 into at least two radiation sub-beams. For example, radiation beam 413 can be split into radiation sub-beams 415 and 417. Figure 4A. The beam splitter 414 may also be configured to direct the radiation sub-beam 415 onto a wafer 420 placed on a platform 422. In one example, the platform 422 may be moved along a direction 424. The radiation sub-beam 415 may be configured to illuminate an alignment mark or target 418 located on the wafer 420. The alignment mark or target 418 may be coated with a radiation sensitive film. In some embodiments, the alignment mark or target 418 may have a one hundred and eighty degree (i.e., 180°) symmetry. That is, when the alignment mark or target 418 is rotated 180° around an axis of symmetry perpendicular to the plane of the alignment mark or target 418, the rotated alignment mark or target 418 may be substantially the same as the unrotated alignment mark or target 418. The target 418 on the wafer 420 can be: (a) a resist layer grating including strips formed by solid resist lines, or (b) a product layer grating, or (c) a composite grating stack including a resist grating superimposed or interleaved on a product layer grating in an overlay target structure. The strips can alternatively be etched into the wafer. Such patterns are sensitive to chromatic aberrations in the lithographic projection equipment (particularly the projection system PL), and the illumination symmetry and the presence of these aberrations will manifest themselves as variations in the printed grating. One in-line method used in device manufacturing to measure line width, pitch and critical dimensions utilizes a technique known as "scatterometry". The method of scatterometry is described in Raymond et al., "Multiparameter Grating Metrology Using Optical Scatterometry" (J. Vac. Sci. Tech. B, Vol. 15, No. 2, pp. 361-368 (1997)) and Niu et al., "Specular Spectroscopic Scatterometry in DUV Lithography" (SPIE, Vol. 3677 (1999)), both of which are incorporated herein by reference. In scatterometry, light is reflected by a periodic structure in the target and the resulting reflection spectrum at a given angle is detected. The structure that produces the reflection spectrum is reconstructed, for example using rigorous coupled wave analysis (RCWA) or by comparison with a library of patterns derived by simulation. Therefore, the scatterometry data of the printed grating is used to reconstruct the grating. Based on knowledge or understanding of the printing steps and / or other scatterometry processes, the parameters of the grating (such as line width and shape) can be input to the reconstruction process performed by the processing unit PU.

[0077] In some embodiments, the beam splitter 414 may also be configured to receive the diffracted radiation beam 419 and split the diffracted radiation beam 419 into at least two radiation sub-beams, according to an embodiment. The diffracted radiation beam 419 may be split into diffracted radiation sub-beams 429 and 439, as shown in FIG. Figure 4A Shown in.

[0078] It should be noted that although beam splitter 414 is shown as directing radiation sub-beam 415 toward alignment mark or target 418 and directing diffracted radiation sub-beam 429 toward interferometer 426, the present disclosure is not limited thereto. It will be apparent to one skilled in the relevant art that other optical arrangements may be used to obtain similar results of illuminating alignment mark or target 418 on wafer 420 and detecting an image of alignment mark or target 418.

[0079] like Figure 4A , the interferometer 426 may be configured to receive the radiation sub-beam 417 and the diffracted radiation sub-beam 429 via the beam splitter 414. In an example embodiment, the diffracted radiation sub-beam 429 may be at least a portion of the radiation sub-beam 415 that may be reflected from the alignment mark or target 418. In an example of such an embodiment, the interferometer 426 includes any suitable set of optical elements, such as a prismatic combination that may be configured to form two images of the alignment mark or target 418 based on the received diffracted radiation sub-beam 429. It should be understood that it is not necessary to form a good quality image, but the features of the alignment mark 418 should be resolved. The interferometer 426 may also be configured to rotate one of the two images by 180° relative to the other of the two images and interferometrically recombining the rotated image and the unrotated image.

[0080] In some embodiments, the detector 428 may be configured to receive the recombined image via the interferometer signal 427 and detect interference caused by the recombined image when the alignment axis 421 of the inspection device 400 passes through the center of symmetry (not shown) of the alignment mark or target 418. According to an example embodiment, such interference may be due to the alignment mark or target 418 being 180° symmetrical and the recombined images interfering constructively or destructively. Based on the detected interference, the detector 428 may also be configured to determine the position of the center of symmetry of the alignment mark or target 418 and thus detect the position of the wafer 420. According to an example, the alignment axis 421 may be aligned with a beam perpendicular to the wafer 420 and passing through the center of the image rotation interferometer 426. The detector 428 may also be configured to estimate the position of the alignment mark or target 418 by implementing sensor characteristics and interacting with wafer marking process variations.

[0081] In further embodiments, the detector 428 determines the location of the center of symmetry of the alignment mark or target 418 by performing one or more of the following measurements:

[0082] 1. Measuring the position change for various wavelengths (position shift between multiple colors);

[0083] 2. Measuring the position change for each order (position shift between multiple diffraction orders); and

[0084] 3. Measure the position change for each polarization (position shift between multiple polarizations).

[0085] Such data may be obtained, for example, using any type of alignment sensor, such as a SMASH-type alignment sensor hybrid (SMASH) sensor as described in U.S. Pat. No. 6,961,116, which employs a self-referencing interferometer with a single detector and four different wavelengths and extracts the alignment signal in software, or an Advanced Technology using High order Enhancement of Alignment (Athena) as described in U.S. Pat. No. 6,297,876, which directs each of the seven diffraction orders to a dedicated detector, both of which are incorporated herein by reference in their entirety.

[0086] In some embodiments, the beam analyzer 430 may be configured to receive the diffracted radiation sub-beam 439 and determine the optical state of the diffracted radiation sub-beam 439. The optical state may be a measure of the beam wavelength, polarization, or beam profile. The beam analyzer 430 may also be configured to determine the position of the platform 422 and to relate the position of the platform 422 to the position of the center of symmetry of the alignment mark or target 418. In this way, the position of the alignment mark or target 418 and therefore the position of the wafer 420 may be accurately known with reference to the platform 422. Alternatively, the beam analyzer 430 may be configured to determine the position of the inspection device 400 or any other reference element so that the center of symmetry of the alignment mark or target 418 relative to the inspection device 400 or any other reference element may be known. The beam analyzer 430 may be a point or imaging polarimeter with some form of wavelength band selectivity. In some embodiments, the beam analyzer 430 may be directly integrated into the inspection device 400 or connected via several types of optical fibers, such as polarization-maintaining single-mode, multimode, or imaging fibers, according to other embodiments.

[0087] In some embodiments, the beam analyzer 430 may also be configured to determine overlap data between two patterns on the wafer 420. One of the patterns may be a reference pattern on a reference layer. Another pattern may be an exposed pattern on an exposure layer. The reference layer may be an etch layer already present on the wafer 420. The reference layer may be generated by a reference pattern exposed on the wafer by the lithography apparatus 100 and / or 100'. The exposure layer may be a resist layer exposed adjacent to the reference layer. The exposure layer may be generated by an exposure pattern exposed on the wafer 420 by the lithography apparatus 100 or 100'. The exposure pattern on the wafer 420 may correspond to the movement of the wafer 420 by the platform 422. In some embodiments, the measured overlap data may also indicate an offset between the reference pattern and the exposure pattern. The measured overlap data may be used as calibration data to calibrate the exposure pattern exposed by the lithography apparatus 100 or 100' so that after calibration, the offset between the exposure layer and the reference layer may be minimized.

[0088] In some embodiments, the beam analyzer 430 may also be configured to determine a model of the product stack profile of the wafer 420, and may be configured to measure the overlay, critical dimension, and focus of the target 418 in a single measurement. The product stack profile includes information about the stack product such as alignment marks, the target 418, or the wafer 420, and may include optical identification mark measurements caused by changes in the marking process that vary with changes in illumination. The product stack profile may also include product grating profiles, mark stack profiles, and mark asymmetry information. An example of a beam analyzer 430 is the Yieldstar manufactured by ASML of Veldhoven, The Netherlands, as described in U.S. Patent No. 8,706,442. TM , which is incorporated herein by reference in its entirety. The beam analyzer 430 may also be configured to process information related to specific properties of the exposed pattern in the layer. For example, the beam analyzer 430 may process overlay parameters of the depicted image in the layer (an indication of the accuracy of positioning of the layer relative to the previous layer on the wafer or the accuracy of positioning of the first layer relative to a mark on the wafer), focus parameters, and / or critical dimension parameters (e.g., line width and its variation). Other parameters are image parameters related to the quality of the depicted image of the exposed pattern.

[0089] In some embodiments, an array of detectors (not shown) can be connected to the beam analyzer 430 and allow the possibility of accurate stack profile detection, as discussed below. For example, the detector 428 can be an array of detectors. For arrays of detectors, a number of options are possible: multimode fiber bundles; discrete pin detectors per channel; or CCD or CMOS (linear) arrays. The use of multimode fiber bundles enables any dissipative elements to be remotely located for stability reasons. Discrete pin detectors provide a large dynamic range, but each requires a separate preamplifier. The number of elements is therefore limited. CCD linear arrays provide many elements that can be read out at high speed and are particularly concerned when phase-stepping detection is used.

[0090] In some embodiments, the second beam analyzer 430' may be configured to receive the diffracted radiation sub-beam 429 and determine an optical state of the diffracted radiation sub-beam 429, such as Figure 4B . The optical state may be a measure of the beam wavelength, polarization, or beam profile. The second beam analyzer 430' may be identical to the beam analyzer 430. Alternatively, the second beam analyzer 430' may be configured to perform at least all of the functions of the beam analyzer 430, such as determining the position of the platform 422, and correlating the position of the platform 422 with the position of the center of symmetry of the alignment mark or target 418. In this way, the position of the alignment mark or target 418 and therefore the position of the wafer 420 may be accurately known relative to the platform 422. The second beam analyzer 430' may also be configured to determine the position of the inspection device 400 or any other reference element, so that the center of symmetry of the alignment mark or target 418 may be known relative to the inspection device 400 or any other reference element. The second beam analyzer 430' may also be configured to determine overlap data between two patterns and a model of the product stack profile of the wafer 420. The second beam analyzer 430' may also be configured to measure the overlap, critical dimension, and focus of the target 418 in a single measurement.

[0091] In some embodiments, the second beam analyzer 430' may be directly integrated into the inspection device 400, or it may be connected via several types of optical fibers: polarization maintaining single mode, multimode or imaging fibers, according to other embodiments. Alternatively, the second beam analyzer 430' and the beam analyzer 430 may be combined to form a single analyzer (not shown) configured to receive both diffracted radiation sub-beams 429 and 439 and to determine the optical state of both diffracted radiation sub-beams 429 and 439.

[0092] In some embodiments, the processor 432 receives information from the detector 428 and the beam analyzer 430. For example, the processor 432 can be an overlap calculation processor. The information may include a model of the product stack profile constructed by the beam analyzer 430. Alternatively, the processor 432 can use the received information about the product mark to construct a model of the product mark profile. In either case, the processor 432 uses or merges the model of the product mark profile to construct a model of the stacked product and the overlap mark profile. The stack model is then used to determine the overlap offset and minimize the spectral effect on the overlap offset measurement. The processor 432 can generate a basic correction algorithm based on the information received from the detector 428 and the beam analyzer 430, the information including but not limited to the optical state of the illumination beam, the alignment signal, the associated position estimate, and the optical state in the pupil plane, the image plane, and the additional plane. The pupil plane is a plane in which the radial position of the radiation defines the angle of incidence and the angular position defines the azimuth of the radiation. The processor 432 can use the basic correction algorithm to characterize the inspection device 400 relative to the wafer mark and / or alignment mark 418.

[0093] In some embodiments, the processor 432 may also be configured to determine the printed pattern position offset error relative to the sensor estimate of each mark based on information received from the detector 428 and the beam analyzer 430. The information includes, but is not limited to, the overlap of each alignment mark or target 418 on the wafer 420, the measured values ​​of critical dimensions and focus, and the product stack profile. The processor 432 may group the marks into sets of similar constant offset errors using a clustering algorithm and generate an alignment error offset correction table based on the information. The clustering algorithm may be based on the overlap measurements, the position estimates, and additional optical stacking process information associated with each set of offset errors. Overlap is calculated for a plurality of different marks, such as overlap targets with positive and negative offsets around the programmed overlap offset. The target measuring the minimum overlap is considered a reference (because it is measured with optimal accuracy). Based on this measured smaller overlap and the known programmed overlap of its corresponding target, the overlap error may be derived. Table 1 illustrates how this derivation may be performed. The minimum measured overlap in the example shown is -1 nm. However, this is associated with a target with a programmed overlap of -30 nm. The process may have introduced an overlay error of 29 nm.

[0094]

[0095] The minimum value can be considered as a reference point, and relative to this minimum value, the offset between the measured overlap and the expected overlap due to the programmed overlap can be calculated. This offset determines the overlap error of each mark or a set of marks with similar offsets. Therefore, in the example of Table 1, at the target position with a programmed overlap of 30 nm, the minimum measured overlap is -1nm. The difference between the expected overlap and the measured overlap at other targets is compared with this reference value. Tables such as Table 1 can also be obtained from the marks and targets 418 under different illumination settings, and the illumination settings that lead to the minimum overlap error and their corresponding calibration factors can be determined and selected. After this, the processor 432 can group the marks into sets with similar overlap errors. The criteria for grouping the marks can be adjusted based on different process controls, such as different error tolerances for different processes.

[0096] In some embodiments, the processor 432 may confirm that all or most members of a group have similar offset errors and apply individual offset corrections from a clustering algorithm to each mark based on additional optical stack measurements thereof. The processor 432 may determine the correction for each mark and feed the correction back to the lithographic apparatus 100 or 100' for correcting the error in the stack, for example by feeding the correction into the inspection apparatus 400.

[0097] Exemplary embodiments of electrostatic wafer chucks and methods for forming and modifying electrode structures included in electrostatic wafer chucks will now be described. The described embodiments and methods may also be applied to reticles (also referred to as patterning devices) and reticle chucks. Wafers, substrates, reticles, patterning devices, and any related structures may be referred to as objects or interchangeable objects. These exemplary embodiments may be used in the lithographic apparatus of FIGS. 1 to 4.

[0098] Most electrostatic wafer clamps in lithographic equipment include two continuous electrodes, which can be located (e.g., embedded) in a dielectric material. Multiple burls can be set on the top of the wafer clamp to support the wafer and can be covered by a conductive coating as described in more detail below. The multiple burls and dielectric layer can form a clamping mechanism using the wafer clamp. The burls can also be interconnected by a series of Manhattan (MH) lines that can also be set on the top of the wafer clamp. In some embodiments, the MH lines are not electrically or physically connected to the wafer or burls. The main purpose of the MH lines in this article is to ground the burls.

[0099] Electrostatic chucks work on the principle of parallel plate capacitance. They work by creating a very high electric field in a vacuum gap. The vacuum gap is created between the wafer and the wafer chuck. The MH line can be positioned in the electric field to ground the spurs. The MH line can be a source of electric field amplification at triple intersection corners, spurs, and / or debris particles. The term "triple intersection" refers to any location where a dielectric material and a metal are adjacent in a vacuum.

[0100] MH lines can be a source of electric field amplification because they can act as cathodes, causing the emission of electrons, which is highly undesirable. Immediately following the MH lines, quasi-uniform charging of the dielectric surface can occur when the wafer is cycled on and off the wafer holder / stage. Quasi-uniform charging can be referred to as the cyclic inductive charging (CIC) problem. Non-uniform charging can occur when debris particles become attached to MH lines located at critical locations. For example, critical locations can include triple intersections, top corners of MH lines, or at salient points along the sidewalls of MH lines.

[0101] Figure 5 An enlarged cross-section of an electrostatic wafer chuck 500 at the top side of a dielectric layer 540 is shown according to some embodiments. Although only one view is shown, the electrostatic wafer chuck 500 may include multiple layers. In particular, an MH line 530 is disposed on the dielectric layer 540 (e.g., on top thereof). The MH line 530 may contact the burl 520, but may also be interconnected with the burl 520. The MH line 530 may contact both the burl 520 and the dielectric layer 540. The MH line 530 may be used to ground the burl 520. For example, both the burl 520 and the dielectric layer 540 may be made of glass. The burl 520 may be made of glass or a similar dielectric, and the MH line 530 may be a conductor.

[0102] The protuberance 520 may also include a conductive coating (not depicted). The conductive layer may be formed to be between about 300 mm and about 1500 mm thick. The wafer 510 is on top of the clamping mechanism together with the electrostatic wafer clamp 500 under vacuum pressure. A backfill gas may be applied after clamping the wafer 510. An adhesive (not depicted) may be provided between any of the multiple layers described herein to serve as an intermediate adhesive. For example, such an added adhesive layer may include benzocyclobutene (BCB). The dielectric layer 540 may be made of glass, such as Eagle XG® borosilicate glass manufactured by Corning Incorporated, Corning New York.

[0103] An example triple intersection 550 is illustrated at the junction where dielectric layer 540, MH line 530, and vacuum (not shown) intersect. At triple intersection 550, the electric field strength is stronger, as illustrated by the logarithmic scale of the electric field strength. For example, the distance between the bottom of wafer 510 and dielectric layer 540 can be at most about 10 μm, but can be between about 6 μm and about 12 μm.

[0104] Figure 6 A cross section of an electrostatic wafer chuck 500 is shown in accordance with some embodiments. A dielectric layer 540 is shown having an embedded electrode 545. For example, the embedded electrode 545 may be formed of chromium.

[0105] To overcome quasi-uniform charging, according to some embodiments, the electrode 545 embedded in the dielectric layer 540 is modified. Although the MH line 530 can remain unchanged, a small portion of the electrode 545 adjacent to the MH line 530 can be converted into an insulating material using a post-bonding structure (PBS) process. In addition, it is permissible to remove a portion of the electrode 545 below the MH line 530. For example, such removal can be performed using photolithography. The removal of a segment need not be limited to PBS, and other suitable processes, such as patterning the electrode via a photolithography process, can be utilized. The removed segment can be a continuous strip along the MH line 530 and can extend up to about 50 μm away from the MH line 530 on both sides. Such a PBS process, etc., converts a segment of the electrode 545 into an insulating material.

[0106] The removed segments may be shaped to correspond to the shape of the MH line 530 so that the insulating material is aligned with the MH line 530 above it. In an embodiment, not all of the electrode 545 is removed so that a portion of the electrode 545 remains. Shaping a portion of the insulating material may correspond to the outer contour of the MH line 530. By aligning the inner contour of the insulating material to the outer contour of the MH line 530, charging issues may be reduced. For example, charging effects near the MH line 530 may be reduced.

[0107] The modification of the electrode 545 results in a reduced electric field strength at the sidewalls of the MH line 530 across the clamp. This modification reduces charging effects due to processing and defectivity on and near the MH line 530. In addition, the nominal clamping force between the burls 520 does not need to be changed. The total clamping force can be reduced by having a smaller effective electrode area under the wafer 510. In some embodiments, the area under the MH line 530 does not contribute to the clamping force, but this can be compensated by having a slightly higher clamping voltage, which is possible due to the reduced charging issues in this article. A clamping voltage of about 3.2 kV can be used, but this clamping voltage can vary depending on the clamping pressure.

[0108] In some embodiments, PBS of electrode 545 can be performed at several stages in the fixture manufacturing process, but can also be performed on the finished fixture or the fixture used. MH line 530 can be used as a guide to manipulate the PBS laser beam, which can be applied through transparent dielectric layer 540. This manipulation can allow the finished fixture to be trimmed. In addition, PBS can be performed at a certain angle relative to the surface instead of perpendicular to the surface to remove a portion of the electrode layer under MH line 530.

[0109] In some embodiments, the PBS process can melt and or vaporize the portion of the electrode 545 to be removed. The section surrounding the removed area can be changed into an insulating material, also referred to as an insulator. In some embodiments, the thin conductive layer of the electrode is converted into an insulating layer.

[0110] Figure 7 Another cross section of an electrostatic wafer chuck 500 is shown in accordance with some embodiments. A dielectric layer 540 is shown having MH lines 530 and burls 520.

[0111] Fig. 8A , Figure 8B and Figure 8C A top view of the electrode plane and a close-up of the electrode plane and the MH line are shown, respectively, according to some embodiments.

[0112] Fig. 8A The top-mounted electrode plane of structured electrode 800 is shown. Electrode 845 is shown, with various electrode cutouts 840 and 860 of different (or alternatively similar) sizes. Electrode cutouts 840 and 860 are removed below the MH line and a structured electrode is produced. Here, for test purposes, the density of electrode cutouts 840 and 860 is illustrated as width changes from left to right. In practice, for operable electrodes, the density of electrode cutouts 840 and 860 can be uniform. Contact hole 850 is shown, and electrode 845 is at the bottom of the hole. For example, the contact hole 850 can connect electrode 845 to an external power supply, i.e., an external power supply.

[0113] Figure 8B A close-up of electrode cutout 840 and electrode cutout 860 is shown below the MH line and the burl (both not depicted here). For example, electrode cutout 860 may extend up to about 50 μm on either side.

[0114] Figure 8C A top view of both electrode 845 and MH wire 830 is shown. MH wire 830 may surround burl 820. burl 820 may also be contacted or partially contacted by MH wire 830. Electrode cutout 840 shows an area of ​​electrode 845 that has been removed. Electrode cutout 860 shows an area of ​​electrode 845 that has been removed in a circular manner.

[0115] Fig. 9 Depicts the electric field in the z-direction of an electrostatic wafer chuck according to some embodiments. MH lines 930 and electrode cutout regions 960 extend in the vertical direction together with the MH lines 930. The electric field strength in the lower left quadrant decreases in the region surrounding the MH lines 930. In such quadrants, the MH lines 930 have structured electrodes (not depicted) of varying widths. Here, structured electrodes mean that a portion of the electrode has been removed and shaped, such as in conjunction with Figure 6 However, the upper right quadrant does not have a structured electrode (not depicted) and does not have the reduced electric field strength along MH line 930. As the electric field strength is locally reduced, the field emission current density may also be reduced.

[0116] In the case where a portion of the electrode is cut away to produce a structured electrode, cyclic inductive charging (CIC) is completely absent in the cutout region. However, CIC is strongly observed in other sections where a standard electrode layout (i.e., no cutouts) occurs. Fig. 9 In the upper right quadrant of FIG. 1 , no structured electrodes are used and significant charging near the MH line occurs (not shown). The electric field strength is stronger there than in the lower left quadrant next to the MH line.

[0117] Fig.10 1 is a flow chart illustrating a process 1000 for forming and modifying an electrode structure for an electrostatic wafer chuck. In step 1002, a chuck mechanism may be provided. Specifically, the chuck mechanism includes a plurality of burls that may extend from a top surface of the chuck mechanism. The chuck mechanism may include a dielectric layer.

[0118] A plurality of ground wires, also referred to as MH wires, may be coated on the top surface of the clamp mechanism in step 1004. At least one ground wire of the plurality of ground wires may be interconnected with at least one burl of the plurality of burls.

[0119] In step 1006, an electrode layer may be disposed in a dielectric layer below the top surface of the clamp mechanism. The electrode layer may include an insulating material in an electrode layer.

[0120] In step 1008, a portion of the insulating material may be shaped to correspond to an outer contour of the plurality of ground lines. An inner contour of the insulating material may be aligned with an outer contour of the plurality of ground lines.

[0121] The structured electrode below the MH line can avoid CIC and can reduce the risk of charging caused by defects located on or near the MH line. In addition, the manufacturing cost can be reduced because this structured electrode technology can be used on an already existing fixture. The existing fixture can be trimmed using PBS to reduce surface charging problems. The fixture can be operated with a structured electrode at a voltage greater than 3.2 kV. This achieves high clamping force without increasing charging problems. Therefore, the structured electrode disclosed herein and formed by PBS or a similar process helps to reduce undesirable surface charging.

[0122] Although specific reference may be made herein to the use of lithographic apparatus in IC manufacturing, it should be understood that the lithographic apparatus described herein may have other applications, such as manufacturing integrated optical systems, guide and detection patterns for magnetic domain memories, flat panel displays, liquid crystal displays (LCDs), thin film magnetic heads, etc. It should be understood by those skilled in the art that in the context of these alternative applications, any use of the term "wafer" or "die" herein may be considered as a specific example of the more general term "substrate" or "target portion", respectively. The wafers referred to herein may be processed in, for example, a track or coating development system (a tool that typically applies a resist layer to a wafer and develops the exposed resist) and / or a metrology unit before or after exposure. Where applicable, the disclosure herein may be applied to such and other wafer processing tools. In addition, a wafer may be processed more than once, for example, to produce a multi-layer IC, so that the term wafer used herein may also refer to a wafer that has included multiple processing layers.

[0123] Although the above may have specifically referred to the use of embodiments of the present disclosure in the context of optical lithography, it should be understood that the present disclosure may be used in other applications (e.g., imprint lithography) and is not limited to optical lithography where the context permits. In imprint lithography, the topography in the patterning device defines the pattern produced on the wafer. The topography of the patterning device may be pressed into a layer of resist supplied to the wafer, after which the resist is cured by applying electromagnetic radiation, heat, pressure, or a combination thereof. After the resist is cured, the patterning device is removed from the resist, leaving a pattern therein.

[0124] It is to be understood that the phraseology or terminology herein is for the purpose of description rather than limitation, so that the phraseology or terminology of the present disclosure is to be interpreted by those skilled in the relevant art in accordance with the teachings herein.

[0125] As used herein, the terms "radiation", "radiation beam", and the like may encompass various types of electromagnetic radiation, for example, ultraviolet (UV) radiation (e.g., having a wavelength λ of 365 nm, 248 nm, 193 nm, 157 nm, or 126 nm), extreme ultraviolet (EUV or soft X-ray) radiation (e.g., having a wavelength in the range of 5 nm to 20 nm, such as 13.5 nm), or hard X-rays that function at less than 5 nm, and matter beams, such as ion beams or electron beams. The terms "light", "irradiation", and the like may refer to non-periodic radiation (e.g., photons, UV, X-rays, etc.). Typically, radiation having a wavelength between about 400 nm and about 700 nm is considered visible radiation; typically, radiation having a wavelength between about 780 nm and 3000 nm (or greater) is considered IR radiation. UV refers to radiation having a wavelength of approximately 100 nm to 400 nm. Within lithography, the term "UV" also applies to wavelengths that may be produced by mercury discharge lamps: G-line 436 nm; H-line 405 nm; and / or I-line 365 nm. Vacuum UV or VUV (i.e., UV absorbed by a gas) refers to radiation having a wavelength of approximately 100 nm to 200 nm. Deep UV (DUV) generally refers to radiation having a wavelength in the range of 126 nm to 428 nm, and in some embodiments, an excimer laser may produce DUV radiation for use within a lithographic apparatus. It will be appreciated that radiation having a wavelength in the range of, for example, 5 nm to 20 nm refers to radiation having a wavelength band, at least a portion of which is in the range of 5 nm to 20 nm.

[0126] Aspects of the present disclosure may be further described using the following aspects:

[0127] 1. A method of manufacturing a support structure for positioning an exchangeable object in a lithographic apparatus, comprising:

[0128] A clamp mechanism is provided, the clamp mechanism comprising a plurality of burls extending from a top surface of the clamp mechanism, wherein the clamp mechanism comprises a dielectric layer

[0129] applying a plurality of ground wires on the top surface of the clamp mechanism, wherein the ground wires are positioned to electrically interconnect the plurality of burls;

[0130] disposing an electrode layer in the dielectric layer below the top surface of the clamp mechanism, wherein the electrode layer includes an insulating material in the electrode layer; and

[0131] A portion of the insulating material is shaped to correspond to an outer contour of the plurality of ground lines such that an inner contour of the insulating material is aligned with the outer contour of the plurality of ground lines.

[0132] 2. The method of aspect 1, further comprising shaping a portion of the insulating material to reduce charging effects near the plurality of ground lines.

[0133] 3. A method according to aspect 1, wherein the forming includes post-bonding structuring.

[0134] 4. The method according to clause 3, wherein the post-bonding structuring comprises using a laser beam.

[0135] 5. The method of aspect 1, further comprising disposing a conductive coating on the plurality of burls.

[0136] 6. The method of aspect 1, further comprising coupling the plurality of ground lines and the plurality of burls to a ground potential.

[0137] 7. The method according to aspect 1, wherein providing the electrode layer comprises embedding a chromium layer.

[0138] 8. The method according to aspect 1 further comprises forming the electrode layer having a contact hole.

[0139] 9. The method according to aspect 1 also includes patterning the electrode layer.

[0140] 10. The method of clause 1, further comprising positioning the exchangeable object and the dielectric layer approximately 10 microns apart.

[0141] 11. The method of clause 10, further comprising forming a vacuum between the exchangeable object and the dielectric layer by the clamping mechanism.

[0142] 12. A support structure for positioning an exchangeable object in a lithographic apparatus, comprising:

[0143] a clamp mechanism comprising a plurality of burls extending from a top surface of the clamp mechanism, wherein the clamp mechanism comprises a dielectric layer;

[0144] a plurality of ground lines located on the top surface, wherein the ground lines electrically interconnect the plurality of burls; and

[0145] an electrode layer located in the dielectric layer below the top surface, wherein the electrode layer includes an insulating material in the electrode layer,

[0146] The insulating material includes an inner contour shaped to correspond to an outer contour of the plurality of ground lines such that the inner contour of the insulating material is aligned with the outer contour of the plurality of ground lines.

[0147] 13. A support structure according to aspect 12, wherein the outer profile of the insulating material is configured to reduce charging effects near the plurality of ground lines.

[0148] 14. The support structure of aspect 12, wherein the plurality of burls comprise a conductive coating.

[0149] 15. The support structure of aspect 12, wherein the plurality of ground lines electrically couple the plurality of burls to a ground potential.

[0150] 16. A support structure according to aspect 12, wherein the electrode layer comprises chromium.

[0151] 17. A support structure according to aspect 12, wherein the electrode layer includes contact holes.

[0152] 18. A support structure according to aspect 12, wherein the electrode layer is patterned.

[0153] 19. A support structure according to aspect 12, wherein the exchangeable object and the dielectric layer are separated by about 10 microns.

[0154] 20. A support structure according to aspect 19, wherein a vacuum is formed between the exchangeable object and the dielectric layer by the clamping mechanism.

[0155] It should be understood that the detailed description section, rather than the summary and abstract sections, is intended to be used to interpret the claims. The summary and abstract sections may set forth one or more, but not all, exemplary embodiments of the present disclosure as contemplated by the inventors, and therefore, are not intended to limit the present disclosure and the appended claims in any way.

[0156] The present disclosure has been described above with the aid of functional building blocks that illustrate the implementation of specific functions and relationships of the functions. For ease of description, the present disclosure has arbitrarily defined the boundaries of these functional building blocks. Alternative boundaries may be defined as long as the specified functions and their relationships are appropriately performed.

[0157] Although specific embodiments of the present disclosure have been described above, it will be appreciated that embodiments of the present disclosure may be practiced in other ways than those described. The description is intended to be illustrative, not restrictive. Thus, it will be appreciated by those skilled in the art that the present disclosure may be modified as described without departing from the scope of the claims set forth below.

[0158] The foregoing description of specific embodiments will fully reveal the general nature of the present disclosure so that others can easily modify and / or adapt such specific embodiments for various applications by applying the knowledge understood by those skilled in the art without undue experimentation without departing from the general concept of the present disclosure. Therefore, based on the teaching content and guidance presented herein, it is expected that such adaptations and modifications fall within the meaning and range of equivalents of the disclosed embodiments.

[0159] The breadth and scope of the protected subject matter should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A method of manufacturing a support structure for positioning an exchangeable object in a lithographic apparatus, comprising: providing a clamp mechanism comprising a plurality of burls extending from a top surface of the clamp mechanism, wherein the clamp mechanism comprises a dielectric layer; applying a plurality of ground wires on the top surface of the clamp mechanism, wherein the ground wires are positioned to electrically interconnect the plurality of burls; disposing an electrode layer in the dielectric layer below the top surface of the clamp mechanism, wherein the electrode layer includes an insulating material in the electrode layer; as well as A portion of the insulating material is shaped to correspond to an outer contour of the plurality of ground lines such that an inner contour of the insulating material is aligned with the outer contour of the plurality of ground lines. 2 . The method of claim 1 , further comprising shaping a portion of the insulating material to reduce charging effects near the plurality of ground lines.

3. The method according to claim 1, wherein: The shaping includes post-bonding structuring, and Wherein, the post-bonding structuring comprises using a laser beam.

4. The method according to claim 1, further comprising: disposing a conductive coating on the plurality of burls; and The plurality of ground lines and the plurality of burls are coupled to a ground potential.

5. The method according to claim 1, wherein: Providing the electrode layer includes embedding a chromium layer.

6. The method according to claim 1, further comprising: forming the electrode layer having a contact hole; and The electrode layer is patterned.

7. The method according to claim 1, further comprising: positioning the exchangeable object and the dielectric layer about 10 microns apart; and A vacuum is formed between the exchangeable object and the dielectric layer by the clamping mechanism.

8. A support structure for positioning an exchangeable object in a lithographic apparatus, comprising: a clamp mechanism comprising a plurality of burls extending from a top surface of the clamp mechanism, wherein the clamp mechanism comprises a dielectric layer; a plurality of ground lines located on the top surface, wherein the ground lines electrically interconnect the plurality of burls; as well as an electrode layer located in the dielectric layer below the top surface, wherein the electrode layer includes an insulating material in the electrode layer, The insulating material includes an inner contour shaped to correspond to an outer contour of the plurality of ground lines such that the inner contour of the insulating material is aligned with the outer contour of the plurality of ground lines.

9. The support structure according to claim 8, wherein: The outer profile of the insulating material is configured to reduce charging effects near the plurality of ground lines.

10. The support structure according to claim 8, wherein: The plurality of burls include a conductive coating.

11. The support structure according to claim 8, wherein: The plurality of ground lines electrically couple the plurality of burls to a ground potential.

12. The support structure according to claim 8, wherein: The electrode layer includes chromium.

13. The support structure according to claim 8, wherein: The electrode layer includes a contact hole.

14. The support structure according to claim 8, wherein: The electrode layer is patterned.

15. The support structure according to claim 8, wherein: The exchangeable object and the dielectric layer are separated by about 10 microns; and Wherein, a vacuum is formed between the exchangeable object and the dielectric layer by the clamping mechanism.

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