Semiconductor device and method of manufacturing the same

Abstract

This semiconductor device is provided with: a silicon carbide layer that has an element region and a terminal region surrounding the element region, and that has a first semiconductor part of a first conductivity type having a first portion in the element region, and a second semiconductor part of a second conductivity type having a second portion in the element region; a second semiconductor portion provided on the first semiconductor portion in a first direction and adjacent to the first portion in a second direction orthogonal to the first direction; a gate electrode facing the second semiconductor part in the element region; a first insulating film provided between the gate electrode and the silicon carbide layer; and a second insulating film provided on the first portion of the first semiconductor portion and thicker than the first insulating film.

Description

Technical Field

[0001] Embodiments relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] In a semiconductor device using silicon carbide (SiC), there is a problem that carbon is removed and vacancies are generated due to high-temperature heat treatment for activating a region into which an impurity imparting conductivity is introduced.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2015-176992

[0006] Non-patent literature

[0007] Non-patent document 1: Koutarou Kawahara; Jun Suda; Tsunenobu Kimoto, “Analytical model for reduction of deep levels in SiC by thermal oxidation”, Journal of Applied Physics 111, 053710 (2012); doi: 10.1063 / 1.3692766 Summary of the invention

[0008] Problems to be solved by the invention

[0009] Embodiments provide a semiconductor device capable of reducing carbon vacancies in a silicon carbide layer and a method of manufacturing the same.

[0010] Means for solving problems

[0011] According to an embodiment, a semiconductor device comprises: a silicon carbide layer having an element region and an end region surrounding the element region, and having a first semiconductor portion and a second semiconductor portion, the first semiconductor portion being of a first conductivity type and having a first portion in the element region, the second semiconductor portion being arranged on the first semiconductor portion in a first direction and being adjacent to the first portion in a second direction orthogonal to the first direction; a gate electrode opposing the second semiconductor portion of the element region; a first insulating film arranged between the gate electrode and the silicon carbide layer; and a second insulating film arranged on the first portion of the first semiconductor portion and being thicker than the first insulating film. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1It is a schematic cross-sectional view of the semiconductor device according to the first embodiment.

[0013] Figure 2 yes Figure 1 FIG. 1 is a schematic top view of a silicon carbide layer in a semiconductor device shown in FIG.

[0014] Figure 3 (a) and (b) are schematic cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment.

[0015] Figure 4 (a) and (b) are schematic cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment.

[0016] Figure 5 (a) and (b) are schematic cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment.

[0017] Figure 6 It is a schematic cross-sectional view of a semiconductor device according to a second embodiment. DETAILED DESCRIPTION

[0018] The following describes the embodiments with reference to the accompanying drawings. In each of the drawings, the same reference numerals are used for the same structure. In the following embodiments, the first conductivity type is set to n-type and the second conductivity type is set to p-type for description, but the first conductivity type may be set to p-type and the second conductivity type may be set to n-type.

[0019] [First embodiment]

[0020] like Figure 1 As shown, the semiconductor device 1 of the first embodiment includes a silicon carbide layer 10. The silicon carbide layer 10 has a first surface 10A and a second surface 10B located on the opposite side of the first surface 10A in a first direction Z. The first direction Z is a direction connecting the first surface 10A and the second surface 10B at the shortest distance. Two directions orthogonal to the first direction Z are set as a second direction X and a third direction Y. The second direction X and the third direction Y are orthogonal to each other.

[0021] like Figure 2 As shown, the silicon carbide layer 10 has a device region R1 and an end region R2. In a plan view, the end region R2 continuously surrounds the device region R1. The area of ​​the device region R1 is larger than the area of ​​the end region R2.

[0022] The silicon carbide layer 10 includes an n-type first semiconductor portion 11 and a p-type second semiconductor portion 12 disposed on the first semiconductor portion 11 in a first direction Z. The silicon carbide layer 10 also includes an n-type third semiconductor portion 13, a p-type fourth semiconductor portion 14, and a p-type fifth semiconductor portion 15. The third semiconductor portion 13 and the fifth semiconductor portion 15 are disposed on the surface of the second semiconductor portion 12. The fourth semiconductor portion 14 is a SiC substrate on which the first semiconductor portion 11 is epitaxially grown. The n-type impurity concentration of the third semiconductor portion 13 is higher than the n-type impurity concentration of the first semiconductor portion 11. The p-type impurity concentration of the fourth semiconductor portion 14 and the p-type impurity concentration of the fifth semiconductor portion 15 are higher than the p-type impurity concentration of the second semiconductor portion 12.

[0023] Figure 1 2 is a cross-sectional view of the device region R1 . At least the first semiconductor portion 11 and the fourth semiconductor portion 14 are continuously provided in the device region R1 and the terminal region R2 .

[0024] The semiconductor device 1 further includes an upper electrode 21 provided on the first surface 10A and a lower electrode 22 provided on the second surface 10B. The lower electrode 22 is in contact with the lower surface of the fourth semiconductor portion 14 and is electrically connected to the fourth semiconductor portion 14. The upper electrode 21 is in contact with the third semiconductor portion 13 and is electrically connected to the third semiconductor portion 13. In addition, the upper electrode 21 is in contact with the fifth semiconductor portion 15, and the second semiconductor portion 12 is electrically connected to the upper electrode 21 via the fifth semiconductor portion 15.

[0025] The semiconductor device 1 of the first embodiment is a bipolar element, for example, having an IGBT (Insulated Gate Bipolar Transistor) structure. The lower electrode 22 is a collector electrode, the fourth semiconductor portion 14 is a collector layer, the first semiconductor portion 11 is a drift layer, the second semiconductor portion 12 is a base layer, the third semiconductor portion 13 is an emitter layer, the upper electrode 21 is an emitter electrode, and the fifth semiconductor portion 15 is a base contact layer.

[0026] The first semiconductor portion 11 of the element region R1 is in contact with the bottom surface of the second semiconductor portion 12 in the first direction Z. In addition, the first semiconductor portion 11 of the element region R1 has a first portion 11a located on the first surface 10A side and adjacent to the side surface of the second semiconductor portion 12 in the second direction X. Furthermore, the first semiconductor portion 11 of the element region R1 has a second portion 11b located on the first surface 10A side and adjacent to the side surface of the second semiconductor portion 12 in the second direction X.

[0027] The semiconductor device 1 further includes a gate electrode 30. Figure 1In the example shown, a planar gate structure is shown. The gate electrode 30 is provided on the first surface 10A of the element region R1 of the silicon carbide layer 10. The second semiconductor portion 12 has a portion 12a located between the second portion 11b and the third semiconductor portion 13 in the second direction X. The gate electrode 30 is at least opposite to the portion 12a of the second semiconductor portion 12. In addition, the gate electrode 30 is also located on the second portion 11b. In addition, the semiconductor device 1 is not limited to a planar gate structure, and may also have a trench gate structure.

[0028] The semiconductor device 1 further includes a first insulating film 41 provided between the gate electrode 30 and the silicon carbide layer 10. The first insulating film 41 is provided between the portion 12a of the second semiconductor portion 12 and the gate electrode 30 and between the second portion 11b and the gate electrode 30. As the first insulating film 41, for example, a silicon oxide film can be used.

[0029] The semiconductor device 1 includes a second insulating film 42 provided on the first portion 11a of the first semiconductor portion 11 in the element region R1. The thickness of the second insulating film 42 in the first direction Z is thicker than the thickness of the first insulating film 41 in the first direction Z. A portion of the second insulating film 42 is also provided on the second semiconductor portion 12 adjacent to the first portion 11a and on the third semiconductor portion 13. As the second insulating film 42, for example, a silicon oxide film can be used.

[0030] The semiconductor device 1 further includes an interlayer insulating film 43 provided between the gate electrode 30 and the upper electrode 21. As the interlayer insulating film 43, for example, a silicon oxide film can be used.

[0031] When the semiconductor device 1 is turned on, a potential higher than the threshold value is given to the gate electrode 30, and an inversion layer (n-type channel) is formed in the portion 12a of the second semiconductor portion 12 that faces the gate electrode 30. A potential lower than that of the lower electrode 22 is given to the upper electrode 21, and a potential higher than that of the lower electrode 22 is given to the lower electrode 22. In this state, a current flows between the lower electrode 22 and the upper electrode 21 in the element region R1 through the fourth semiconductor portion 14, the second portion 11b of the first semiconductor portion 11, the n-type channel, and the third semiconductor portion 13.

[0032] According to the present embodiment, by providing the first portion 11a in the first semiconductor portion 11 of the element region R1, carbon is diffused into the first semiconductor portion 11 of the element region R1 through the first portion 11a as described later, thereby reducing carbon vacancies. Thus, when the semiconductor device 1 performs a bipolar operation in the on state, recombination of holes and electrons at carbon vacancies can be reduced, and degradation of the operating characteristics of the semiconductor device 1 can be suppressed.

[0033] Carbon diffuses from the first portion 11a to the bottom of the first portion 11a, and then diffuses in the first semiconductor portion 11 along the second direction X and the third direction Y. Therefore, the carbon density in the first semiconductor portion 11 below the first portion 11a is higher than the carbon density in the first semiconductor portion 11 below the gate electrode 30 (below the second portion 11b). In addition, the carbon density in the first semiconductor portion 11 on the first surface 10A side is higher than the carbon density in the first semiconductor portion 11 on the second surface 10B side.

[0034] If the potential of the gate electrode 30 becomes a potential lower than the threshold, the n-type channel is cut off and the semiconductor device 1 becomes a cut-off state. In this cut-off state, the depletion layer expands from the pn junction of the n-type first semiconductor portion 11 and the p-type second semiconductor portion 12 in the first semiconductor portion 11, and the withstand voltage of the semiconductor device 1 is maintained. Since the second insulating film 42 is provided between the first portion 11a and the upper electrode 21, the leakage current passing through the first portion 11a can be suppressed, and the withstand voltage can be maintained. The thickness of the first insulating film 41 that functions as a gate insulating film is preferably tens of nanometers, and in order to maintain the withstand voltage, the thickness of the second insulating film 42 is preferably 100nm or more.

[0035] A plurality of first portions 11 a may be provided in the device region R1 . The planar pattern of the first portion 11 a may be, for example, concentric circles, stripes, a grid, or dots.

[0036] Next, refer to Figure 3 (a)~ Figure 5 (b) The method for manufacturing the semiconductor device according to the first embodiment is described. Figure 3 (a)~ Figure 5 The cross section shown in (b) is Figure 1 The illustrated cross section corresponds to a cross section of a portion where the first portion 11 a of the first semiconductor portion 11 is provided.

[0037] like Figure 3 As shown in (a), a first region r1 into which impurities are injected and a second region r2 into which impurities are not injected are formed on the upper part of the silicon carbide layer 10. The first region r1 is a region into which impurities are injected by ion implantation. The first region r1 includes a p-type second semiconductor portion 12 and an n-type third semiconductor portion 13. After injecting p-type impurities from the first surface 10A into the upper part of the n-type first semiconductor portion 11, n-type impurities are injected. For example, as p-type impurities, Al (aluminum), B (boron), and Ga (gallium) can be used, and as n-type impurities, N (nitrogen) and P (phosphorus) can be used. Impurities are not injected into the second region r2. The second region r2 is a part of the first semiconductor portion 11. The second region r2 is adjacent to the first region r1 in the second direction X. The first surface 10A of the silicon carbide layer 10 includes the upper surface of the first region r1 and the upper surface of the second region r2.

[0038] After the above-mentioned ion implantation, a first heat treatment process is performed. Through the first heat treatment process, the first region r1 into which the impurities are implanted is activated. The temperature of the first heat treatment process is, for example, above 1600°C. Due to the high-temperature heat treatment in the first heat treatment process, carbon (C) in the silicon carbide layer 10 may be separated, resulting in vacancies. According to the present embodiment, in order to fill the vacancies generated in the first heat treatment process with carbon, a second heat treatment process is performed after the first heat treatment process.

[0039] Furthermore, it is preferable to cover the upper surface of the first region r1 with a protective film after the first heat treatment step and before the second heat treatment step. Figure 3 As shown in (b), after the protective film 40 is formed so as to cover the entire surface of the first surface 10A of the silicon carbide layer 10 including the upper surface of the first region r1 and the upper surface of the second region r2, as shown in Figure 4 As shown in (a), an opening 40a is formed in the protective film 40. The upper surface of the second region r2 is exposed from the protective film 40 at the opening 40a. The upper surface of the first region r1 is covered with the protective film 40. As the protective film 40, for example, a silicon nitride film can be used.

[0040] In the second heat treatment step, the second region r2 is thermally oxidized at a lower temperature than in the first heat treatment step. In the second heat treatment step, heat treatment is performed in an oxygen-containing atmosphere at a temperature of, for example, about 1300° C. Thus, a thermal oxidation reaction is performed from the upper surface of the second region r2 exposed in the opening 40a, and a portion (upper portion) of the second region r2 is converted into Figure 4 The thermal oxidation portion 50 shown in (b) of FIG. 1 is shown. The upper surface of the first region r1 is covered by the protective film 40 and is therefore not thermally oxidized. In addition, the upper surface of the region adjacent to the second region r2 in the second semiconductor portion 12 is covered by the protective film 40, but there is also a case where thermal oxidation is performed from the lateral direction (second direction X), and a thermal oxidation portion 50 is also formed in the region adjacent to the second region r2 in the second semiconductor portion 12.

[0041] In the second heat treatment step, the carbon in the silicon carbide layer 10 bonded with oxygen is released as CO or CO2 gas, and the carbon not bonded with oxygen is released as Figure 4 As schematically indicated by the black circle in (b), carbon diffuses from the second region r2 downward in the silicon carbide layer 10 and in the second direction X and the third direction Y. Thus, the vacancies generated in the first heat treatment step can be filled with carbon.

[0042] The second region r2 is a region where ion implantation of impurities has not been performed and has no defects caused by ion implantation. Therefore, carbon can diffuse from the second region r2 into the silicon carbide layer 10 without being hindered by the defects caused by ion implantation.

[0043] In addition, as a comparative example, a method of filling vacancies by ion implanting carbon from the first surface 10A of the silicon carbide layer 10 after the first heat treatment step can be considered. However, in this case, defects caused by ion implantation of carbon occur at the pn junction interface between the second semiconductor portion 12 and the first semiconductor portion 11, which may cause leakage current.

[0044] According to the present embodiment, since carbon is diffused by thermal oxidation treatment, defects due to carbon ion implantation are not generated.

[0045] After the second heat treatment process, the thermal oxidation portion 50 is removed. For example, hydrofluoric acid, dilute hydrofluoric acid, buffered hydrofluoric acid, etc. may be used to remove the thermal oxidation portion 50. Figure 5 As shown in (a), a recess 10C is formed above the second region r2. The second region r2 below the recess 10C becomes the first portion 11a of the first semiconductor portion 11 described above. Then, the protective film 40 is removed. For example, the protective film 40 can be removed using high-temperature phosphoric acid. Thus, as shown in FIG. Figure 5 As shown in (b), the upper surface of the first region r1, the upper surface of the second region r2, and the recess 10C are exposed.

[0046] After removing the protective film 40, a Figure 1 The second insulating film 42 shown in FIG. 4 can be formed by, for example, a CVD (Chemical Vapor Deposition) method or a PVD (physical vapor deposition) method. The second insulating film 42 is provided at least on the first portion 11 a of the first semiconductor portion 11 .

[0047] Furthermore, in the step of removing the protective film 40 , when the protective film 40 is removed under the condition that the thermally oxidized portion 50 is not removed, the thermally oxidized portion 50 may be left as the second insulating film 42 without being removed.

[0048] [Second embodiment]

[0049] Figure 6 It is a schematic cross-sectional view of a semiconductor device 2 according to the second embodiment.

[0050] The semiconductor device 2 of the second embodiment includes a silicon carbide layer 110. The silicon carbide layer 110 has a first surface 110A and a second surface 110B located opposite to the first surface 110A in the first direction Z. Similar to the first embodiment, the silicon carbide layer 110 of the second embodiment also has a device region and a terminal region. Figure 6 is a cross-sectional view of the device region R1.

[0051] The silicon carbide layer 110 includes an n-type first semiconductor portion 111 and a p-type second semiconductor portion 112 provided on the first semiconductor portion 111 in the first direction Z. The silicon carbide layer 110 further includes an n-type third semiconductor portion 114. At least the first semiconductor portion 111 and the third semiconductor portion 114 are continuously provided in the element region and the terminal region.

[0052] The third semiconductor portion 114 is a SiC substrate on which the first semiconductor portion 111 is epitaxially grown. The n-type impurity concentration of the third semiconductor portion 114 is higher than the n-type impurity concentration of the first semiconductor portion 111 .

[0053] The semiconductor device 2 further includes an upper electrode 121 provided on the first surface 110A and a lower electrode 122 provided on the second surface 110B. The lower electrode 122 is in contact with the lower surface of the third semiconductor portion 114 and is electrically connected to the third semiconductor portion 114. The upper electrode 121 is in contact with the second semiconductor portion 112 and is electrically connected to the second semiconductor portion 112.

[0054] The semiconductor device 2 of the second embodiment is also a bipolar element, for example, having a PIN diode structure. The upper electrode 121 is an anode electrode, the second semiconductor portion 112 is an anode layer, the first semiconductor portion 111 is a drift layer, the third semiconductor portion 114 is a cathode layer, and the lower electrode 122 is a cathode electrode.

[0055] The first semiconductor portion 111 of the element region R1 is in contact with the bottom surface of the second semiconductor portion 112 in the first direction Z. The first semiconductor portion 111 of the element region R1 has a first portion 111 a located on the first surface 110A side and adjacent to the side surface of the second semiconductor portion 112 in the second direction X.

[0056] The semiconductor device 2 includes an insulating film 142 provided on the first portion 111a of the first semiconductor portion 111 in the element region R1. A portion of the insulating film 142 is also provided on a portion of the second semiconductor portion 112 adjacent to the first portion 111a. As the insulating film 142, for example, a silicon oxide film can be used.

[0057] When the semiconductor device 2 is turned on, a higher potential is given to the upper electrode 121 than to the lower electrode 122, and a lower potential is given to the lower electrode 122 than to the upper electrode 121. In this state, current flows between the upper electrode 121 and the lower electrode 122 in the element region R1 through the second semiconductor portion 112, the first semiconductor portion 111, and the third semiconductor portion 114.

[0058] The manufacturing method of the semiconductor device 2 of the second embodiment is the same as that of the aforementioned first embodiment, and comprises: a process of forming a first region injected with impurities (a region where the second semiconductor portion 112 is provided) and a second region not injected with impurities (a region where the first portion 111a is provided) on the upper portion of the silicon carbide layer 110; a first heat treatment process for activating the first region; and a second heat treatment process for thermally oxidizing the second region at a temperature lower than that of the first heat treatment process after the first heat treatment process.

[0059] Furthermore, in the second heat treatment step, similarly to the first embodiment, carbon is diffused into the first semiconductor portion 111 of the element region R1 through the first portion 111a, thereby reducing carbon vacancies. Thus, when the semiconductor device 2 performs bipolar operation in the on state, recombination of holes and electrons at carbon vacancies can be reduced, thereby suppressing degradation of the operating characteristics of the semiconductor device 2.

[0060] Carbon diffuses from the first portion 111a to the lower portion of the first portion 111a, and further diffuses in the first semiconductor portion 111 along the second direction X and the third direction Y. Therefore, the carbon density in the first semiconductor portion 111 below the first portion 111a is higher than the carbon density in the first semiconductor portion 111 below the connection portion between the second semiconductor portion 112 and the upper electrode 121. In addition, the carbon density in the first semiconductor portion 111 on the first surface 110A side is higher than the carbon density in the first semiconductor portion 111 on the second surface 110B side.

[0061] When a reverse voltage is applied to the pn junction of the second semiconductor portion 112 and the first semiconductor portion 111, a depletion layer expands from the pn junction in the first semiconductor portion 111, and the withstand voltage of the semiconductor device 2 is maintained. Since the insulating film 142 is provided between the first portion 111a of the first semiconductor portion 111 and the upper electrode 121, leakage current passing through the first portion 111a can be suppressed, and the withstand voltage can be maintained. In order to maintain the withstand voltage, the thickness of the insulating film 142 is preferably 100 nm or more.

[0062] A plurality of first portions 111 a may be provided in the device region R1 . The planar pattern of the first portion 111 a may be, for example, concentric circles, stripes, a grid, dots, or the like.

[0063] Several embodiments of the present invention have been described, but these embodiments are provided for example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are also included in the invention described in the claims and their equivalents.

[0064] Description of Reference Numerals

[0065] 1, 2…semiconductor device; 10, 110…silicon carbide layer; 10A, 110A…first surface; 10B, 110B…second surface; 11, 111…first semiconductor portion; 11a, 111a…first part; 11b…second part; 12, 112…second semiconductor portion; 13, 114…third semiconductor portion; 14…fourth semiconductor portion; 15…fifth semiconductor portion; 21, 121…upper electrode; 22, 122…lower electrode; 30…gate electrode; 40…protective film; 41…first insulating film; 42…second insulating film; 43…interlayer insulating film; 50…thermally oxidized portion; 142…insulating film; R1…element region; R2…terminal region; r1…first region; r2…second region.

Claims

1. A semiconductor device, characterized in that: have: A silicon carbide layer having an element region and an end region surrounding the element region, and having a first semiconductor portion and a second semiconductor portion, wherein the first semiconductor portion is of a first conductivity type and has a first portion in the element region, and the second semiconductor portion is disposed on the first semiconductor portion in a first direction and is adjacent to the first portion in a second direction orthogonal to the first direction; a gate electrode facing the second semiconductor portion of the element region; a first insulating film disposed between the gate electrode and the silicon carbide layer; as well as A second insulating film is provided on the first portion of the first semiconductor portion and is thicker than the first insulating film.

2. The semiconductor device according to claim 1, wherein: A carbon density in the first semiconductor portion below the first part is higher than a carbon density in the first semiconductor portion below the gate electrode.

3. The semiconductor device according to claim 1 or 2, characterized in that: The second insulating film has a thickness of 100 nm or more.

4. A semiconductor device, characterized in that: have: A silicon carbide layer having an element region and an end region surrounding the element region, and having a first semiconductor portion and a second semiconductor portion, wherein the first semiconductor portion is of a first conductivity type and has a first portion in the element region, and the second semiconductor portion is disposed on the first semiconductor portion in a first direction and is adjacent to the first portion in a second direction orthogonal to the first direction; an upper electrode disposed on the second semiconductor portion of the element region and electrically connected to the second semiconductor portion; as well as An insulating film is provided on the first portion of the first semiconductor portion.

5. The semiconductor device according to claim 4, wherein: The carbon density in the first semiconductor portion below the first portion is higher than the carbon density in the first semiconductor portion below the connection portion between the second semiconductor portion and the upper electrode.

6. The semiconductor device according to claim 4 or 5, characterized in that: The thickness of the insulating film is greater than 100 nm.

7. A method for manufacturing a semiconductor device, characterized in that: have: A step of forming a first region into which impurities are implanted and a second region into which impurities are not implanted on an upper portion of the silicon carbide layer; A first heat treatment step for activating the first region; as well as After the first heat treatment step, a second heat treatment step is performed to thermally oxidize the second region at a temperature lower than that of the first heat treatment step.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The method for manufacturing a semiconductor device further includes a step of covering an upper surface of the first region with a protective film before the second heat treatment step.

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