Semiconductor device

Abstract

A semiconductor device (1) is provided with a semiconductor layer (40), and a first vertical MOS transistor (10) and a second vertical MOS transistor (20) which are formed on the semiconductor layer (40), and in a plan view of the semiconductor layer (40), the entire length of one side of the outer periphery of a first gate electrode region (G1) and the entire length of one side of the outer periphery of a first resistive element region (R1) are smaller than the entire length of the other side of the outer periphery of a second resistive element region (R2). The first gate pad (119) and the second gate pad (119) coincide with a portion of a side of the outer periphery of the semiconductor layer (40) that is orthogonal to the boundary line (90) and has the shortest distance from the first gate pad (119). The outer periphery of the first resistive element region (R1) includes only one corner section among four corner sections of the outer periphery of the first gate electrode region (G1), the corner section having the shortest distance from the boundary line (90) and the shortest distance from a side of the outer periphery of the semiconductor layer (40) orthogonal to the boundary line (90).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and more particularly to a chip size package type semiconductor device. Background Art

[0002] A dual-structure vertical MOS transistor capable of controlling bidirectional conduction with a single chip requires a reduction in on-resistance and miniaturization. A dual-structure vertical MOS transistor has been disclosed that has a 4-pad structure having only the minimum number of pads required.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2008-53623A Summary of the invention

[0006] Problems to be solved by the invention

[0007] In a semiconductor device having a vertical MOS transistor, a resistor is sometimes provided in the semiconductor device in order to improve the resistance to ESD (Electro Static Discharge). However, by providing the resistor, the area of ​​the region contributing to the conduction of the vertical MOS transistor is reduced, and thus it becomes difficult to reduce the on-resistance.

[0008] Means for solving problems

[0009] In order to solve the above-mentioned problems, a semiconductor device of a technical solution of the present disclosure is a chip-size package type semiconductor device that can be mounted face-down, and comprises: a semiconductor layer, including a semiconductor substrate; a first vertical MOS transistor, which is formed as a whole in a first region of the semiconductor layer on the upper surface side of the semiconductor layer; a second vertical MOS transistor, which is formed as a whole in a second region adjacent to the first region in a plan view of the semiconductor layer; and a metal layer, which is formed on the lower surface side of the semiconductor layer and is in contact with and connected to the semiconductor substrate; the semiconductor substrate is a common drain region of the first vertical MOS transistor and the second vertical MOS transistor; in the plan view, the semiconductor layer is a square; in the plan view, the first region and the second region are arranged in a first direction; in the plan view, the boundary line between the first region and the second region is orthogonal to the first direction and is a straight line that divides the semiconductor layer into two equal parts in area and passes through the center of the semiconductor layer; in the plan view, the pads provided in the first region are only a first source pad connected to the first source electrode of the first vertical MOS transistor and a first source pad connected to the first vertical MOS transistor. a first gate pad connected to a first gate electrode of the transistor; the first vertical MOS transistor comprises: a first gate resistor connected to the first gate electrode; a first gate electrode region, which is a rectangular region that includes the first gate pad in the plan view and is the largest region in a range that does not include the first source electrode or the first gate resistor; and a first resistor region, which is a rectangular region that includes the first gate resistor in the plan view and is the largest region in a range that does not include the first source electrode or the first gate electrode region. the area with the largest area surrounded by the first gate electrode region; in the above-mentioned plan view, the full length of one side in the outer periphery of the first gate electrode region and the full length of one side in the outer periphery of the first resistor element region are consistent with a part of the side in the outer periphery of the semiconductor layer that is orthogonal to the above-mentioned boundary line and has the shortest distance to the first gate pad; in the above-mentioned plan view, the outer periphery of the first resistor element region only includes one corner of the four corners of the outer periphery of the first gate electrode region that has the shortest distance to the above-mentioned boundary line and has the shortest distance to the side in the outer periphery of the semiconductor layer that is orthogonal to the above-mentioned boundary line.

[0010] Effects of the Invention

[0011] According to a semiconductor device of one aspect of the present disclosure, it is possible to improve ESD tolerance and reduce on-resistance using a compact dual-structure vertical MOS transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a schematic cross-sectional view showing an example of the structure of the semiconductor device according to the embodiment.

[0013] Figure 2 It is a schematic plan view showing an example of arrangement of pads of the semiconductor device according to the embodiment.

[0014] Figure 3 It is a schematic plan view showing an example of the shape and arrangement of components of the semiconductor device according to the embodiment.

[0015] Figure 4 is a circuit diagram showing an equivalent circuit of a semiconductor device according to an embodiment.

[0016] Figure 5A FIG. 1 is a schematic plan view showing a rough unit structure of a first transistor according to an embodiment.

[0017] Figure 5B FIG. 1 is a schematic perspective view showing a rough unit structure of a first transistor according to an embodiment.

[0018] Figure 6 It is a plan view showing an example of the shape and arrangement of components of the semiconductor device according to the embodiment.

[0019] Fig. 7A It is a schematic plan view showing the shapes and arrangements of components of the semiconductor device of Comparative Example 1.

[0020] Figure 7B It is a schematic plan view showing the shapes and arrangements of components of the semiconductor device of Comparative Example 1.

[0021] Figure 8 It is a schematic plan view showing an example of the shape and arrangement of components of the semiconductor device according to the embodiment.

[0022] Fig. 9A It is a schematic plan view showing the arrangement of components of a semiconductor device according to Comparative Example 2.

[0023] Fig. 9B It is a schematic plan view showing the arrangement of components of a semiconductor device according to Comparative Example 3.

[0024] Fig. 9C It is a schematic plan view showing the arrangement of components of a semiconductor device according to Comparative Example 4.

[0025] Fig.9D It is a schematic plan view showing the arrangement of components of a semiconductor device according to Comparative Example 5.

[0026] Fig.9E It is a schematic plan view showing the arrangement of components of a semiconductor device according to Comparative Example 6.

[0027] Fig.10 It is a schematic plan view showing an example of the shape and arrangement of components of the semiconductor device according to the embodiment.

[0028] Fig.11 It is a schematic plan view showing an example of the shape and arrangement of components of the semiconductor device according to the embodiment.

[0029] Fig.12 It is a schematic plan view showing an example of the shape and arrangement of components of the semiconductor device according to the embodiment.

[0030] Fig.13 It is a schematic plan view showing an example of the shape and arrangement of components of the semiconductor device according to the embodiment.

[0031] Fig.14 It is a schematic plan view showing an example of the shape and arrangement of components of the semiconductor device according to the embodiment. DETAILED DESCRIPTION

[0032] The embodiments described below are all used to represent a specific example of the present disclosure. The numerical values, shapes, materials, components, configuration positions of components, and connection forms shown in the following embodiments are examples and are not intended to limit the present disclosure.

[0033] In the present disclosure, “A and B are electrically connected” includes the case where A and B are directly connected via wiring, the case where A and B are directly connected without wiring, and the case where A and B are indirectly connected via a resistance component (resistance element, resistance wiring).

[0034] (Implementation Method)

[0035] [1. Structure of semiconductor device]

[0036] Hereinafter, the structure of the semiconductor device according to the embodiment will be described.

[0037] The semiconductor device of the embodiment is a chip size package (CSP) type semiconductor device that can be mounted face-down and has two vertical MOS (Metal Oxide Semiconductor) transistors formed on a semiconductor substrate. The two vertical MOS transistors are power transistors and are so-called trench MOS FETs (Field Effect Transistors).

[0038] Figure 1 It is a schematic cross-sectional view showing an example of the structure of the semiconductor device 1 according to the embodiment. Figure 2It is a schematic plan view showing an example of the arrangement of pads of the semiconductor device 1 . Figure 1 yes Figure 2 The cross section at I-I.

[0039] like Figure 1 and Figure 2 As shown, the semiconductor device 1 has a semiconductor layer 40, a metal layer 30, a first vertical MOS transistor 10 (hereinafter also referred to as transistor 10) formed as a whole in a first area A1 of the semiconductor layer 40, and a second vertical MOS transistor 20 (hereinafter also referred to as transistor 20) formed as a whole in a second area A2 of the semiconductor layer 40.

[0040] The transistor 10 formed entirely within the first region A1 means that all elements constituting the transistor 10 are contained within the first region A1 in a plan view and are not contained within the second region A2. Similarly, the transistor 20 formed entirely within the second region A2 means that all elements constituting the transistor 20 are contained within the second region A2 in a plan view and are not contained within the first region A1.

[0041] In the present disclosure, the semiconductor substrate 32 and the low-concentration impurity layer 33 are collectively referred to as the semiconductor layer 40. The semiconductor substrate 32 is disposed on the lower surface side (also referred to as the back surface side) of the semiconductor layer 40 and is composed of silicon containing first conductivity type impurities.

[0042] The low-concentration impurity layer 33 is disposed on the upper surface side (also referred to as the surface side) of the semiconductor layer 40, is formed in contact with the semiconductor substrate 32, and is a first conductivity type impurity layer containing first conductivity type impurities having a concentration lower than the concentration of first conductivity type impurities of the semiconductor substrate 32. The low-concentration impurity layer 33 can be formed on the semiconductor substrate 32 by, for example, epitaxial growth.

[0043] The metal layer 30 is formed in contact with and connected to the back side of the semiconductor layer 40, that is, the back side of the semiconductor substrate 32, and is composed of silver (Ag) or copper (Cu). In addition, the metal layer 30 may contain a trace amount of elements other than metals mixed as impurities in the manufacturing process of the metal material. In addition, the metal layer 30 may not be formed on the entire back side of the semiconductor layer 40.

[0044] like Figure 1 As shown, a second conductivity type first body region 18 containing impurities of a second conductivity type different from the first conductivity type is formed in the first region A1 of the low concentration impurity layer 33. A first conductivity type first source region 14 containing impurities of the first conductivity type is formed in the first body region 18.

[0045] In addition, in the first region A1, a plurality of first gate trenches 17 are formed to penetrate the first source region 14 and the first body region 18 from the upper surface of the semiconductor layer 40 and to a depth reaching a portion of the low-concentration impurity layer 33, and further, the first gate conductor 15 is formed on the first gate insulating film 16 inside the first gate trench 17. The first gate conductor 15 is a buried gate electrode buried inside the semiconductor layer 40 and is electrically connected to the first gate pad 119.

[0046] The first source electrode 11 includes a portion 12 and a portion 13 , and the portion 12 is connected to the first source region 14 and the first body region 18 via the portion 13 .

[0047] The portion 12 of the first source electrode 11 is a layer that is bonded to the solder during reflow in face-down mounting, and can be made of a metal material including one or more of nickel, titanium, tungsten, and palladium as a non-limiting example. The surface of the portion 12 can be plated with gold or the like.

[0048] The portion 13 of the first source electrode 11 is a layer connecting the portion 12 and the semiconductor layer 40 , and may be made of a metal material including one or more of aluminum, copper, gold, and silver as a non-limiting example.

[0049] A second conductive type second body region 28 containing second conductive type impurities is formed in the second region A2 of the low-concentration impurity layer 33. A first conductive type second source region 24 containing first conductive type impurities is formed in the second body region 28.

[0050] In addition, in the second region A2, a plurality of second gate trenches 27 are formed to penetrate the second source region 24 and the second body region 28 from the upper surface of the semiconductor layer 40 and to a depth up to a portion of the low-concentration impurity layer 33, and further, the second gate conductor 25 is formed on the second gate insulating film 26 inside the second gate trench 27. The second gate conductor 25 is a buried gate electrode buried inside the semiconductor layer 40 and is electrically connected to the second gate pad 129.

[0051] The second source electrode 21 includes a portion 22 and a portion 23 , and the portion 22 is connected to the second source region 24 and the second body region 28 via the portion 23 .

[0052] The portion 22 of the second source electrode 21 is a layer that is bonded to the solder during reflow in face-down mounting, and can be made of a metal material including one or more of nickel, titanium, tungsten, and palladium as a non-limiting example. The surface of the portion 22 can be plated with gold or the like.

[0053] The portion 23 of the second source electrode 21 is a layer connecting the portion 22 and the semiconductor layer 40 , and may be made of a metal material including one or more of aluminum, copper, gold, and silver as a non-limiting example.

[0054] With the above structures of the transistors 10 and 20, the semiconductor substrate 32 and the area immediately above the semiconductor substrate 32 in the low-concentration impurity layer 33 are the common drain region that makes common the first drain region of the transistor 10 and the second drain region of the transistor 20. Furthermore, the metal layer 30 is the common drain electrode that makes common the first drain electrode of the transistor 10 and the second drain electrode of the transistor 20.

[0055] like Figure 1 As shown, the first body region 18 is covered by an interlayer insulating layer 34 having an opening, and a portion 13 of the first source electrode 11 connected to the first source region 14 is provided through the opening of the interlayer insulating layer 34. The interlayer insulating layer 34 and the portion 13 of the first source electrode 11 are covered by a passivation layer 35 having an opening, and a portion 12 connected to the portion 13 of the first source electrode 11 is provided through the opening of the passivation layer 35.

[0056] The second body region 28 is covered by an interlayer insulating layer 34 having an opening, and a portion 23 of the second source electrode 21 connected to the second source region 24 is provided through the opening of the interlayer insulating layer 34. The interlayer insulating layer 34 and the portion 23 of the second source electrode 21 are covered by a passivation layer 35 having an opening, and a portion 22 connected to the portion 23 of the second source electrode 21 is provided through the opening of the passivation layer 35.

[0057] Therefore, the first source pad 111 and the second source pad 121 refer to the regions where the first source electrode 11 and the second source electrode 21 are partially exposed on the surface of the semiconductor device 1, so-called terminal portions. Similarly, the first gate pad 119 and the second gate pad 129 refer to the first gate electrode 19 (at Figure 1 , Figure 2 ) and the second gate electrode 29 (not shown in the figure) Figure 1 , Figure 2 An area partially exposed on the surface of the semiconductor device 1 (not shown), a so-called terminal portion.

[0058] The material constituting the first gate electrode 19 and the second gate electrode 29 may be the same as the material constituting the first source electrode 11 and the second source electrode 21 .

[0059] Regarding the thickness of each structure in the semiconductor device 1 , as an example, the thickness of the semiconductor layer 40 is 10-90 μm, the thickness of the metal layer 30 is 10-90 μm, and the sum of the thicknesses of the interlayer insulating layer 34 and the passivation layer 35 is 3-13 μm.

[0060] like Figure 1 and Figure 2 As shown, the transistor 10 has a first source pad 111 and a first gate pad 119 on the surface of the semiconductor layer 40, which are bonded to the mounting substrate via a bonding member when the transistor 10 is mounted face down. In addition, the transistor 20 has a second source pad 121 and a second gate pad 129 on the surface of the semiconductor layer 40, which are bonded to the mounting substrate via a bonding member when the transistor 20 is mounted face down.

[0061] like Figure 2 As shown, the semiconductor layer 40 is square in plan view.

[0062] exist Figure 2 In the figure, an imaginary boundary line 90 that distinguishes the first area A1 and the second area A2 of the semiconductor layer 40 is indicated by a dotted line. The boundary line 90 between the first area A1 and the second area A2 can also be understood as an imaginary line along the center position of the interval between the portion 13 of the first source electrode 11 and the portion 23 of the second source electrode 21. In addition, although it has a limited width, it can also be understood as the interval itself. Even in the case of this interval, it can be recognized as a line in the naked eye or in a low-magnification appearance.

[0063] In plan view, the boundary line 90 is a straight imaginary line that is orthogonal to the first direction, divides the area of ​​the semiconductor layer 40 into two equal parts in the first direction, and passes through the center of the semiconductor layer 40. The center of the semiconductor layer 40 is the intersection of two diagonal lines of the semiconductor layer 40 in plan view.

[0064] The first direction is a direction in which the first area A1 and the second area A2 are arranged in a direction parallel to the outer periphery of the semiconductor device 1 in a plan view.

[0065] like Figure 2 As shown, in the plan view, the first area A1 and the second area A2 are adjacent to each other and are rectangular areas that divide the area of ​​the semiconductor layer 40 into two equal parts. In the plan view, there is no semiconductor layer 40 that is neither the first area A1 nor the second area A2.

[0066] The outer periphery is the side that forms the outline of the shape, and in the case of a square like the semiconductor layer 40 or a rectangle like the first area A1, it is the four sides that form the respective shapes. In the case of a shape other than a rectangle, it is the multiple sides that form the outer periphery of the shape.

[0067] like Figure 2As shown, in the present disclosure, in a plan view, of the two sides parallel to the boundary line 90 in the outer periphery of the semiconductor layer 40, the side with the shortest distance to the first gate pad 119 is set as the first side S1, and the other side with the shortest distance to the second gate pad 129 and opposite to the first side S1 is set as the second side S2.

[0068] Similarly, in the plan view, of the two sides orthogonal to the boundary line 90 in the outer periphery of the semiconductor layer 40, the side with the shortest distance to the first gate pad 119 is set as the third side S3, and the other side with the shortest distance to the first source pad 111 and opposite to the third side S3 is set as the fourth side S4.

[0069] In addition, since the semiconductor layer 40 is a square in a plan view, the length of the first side S1 , the length of the second side S2 , the length of the third side S3 , and the length of the fourth side S4 are the same.

[0070] The number of the first source pads 111 of the transistor 10 and the number of the second source pads 121 of the transistor 20 are respectively as follows: Figure 2 In addition, the number of the first gate pads 119 of the transistor 10 and the number of the second gate pads 129 of the transistor 20 are respectively as shown in FIG. Figure 2 As shown, there is 1.

[0071] That is, the semiconductor device 1 in the present disclosure is a dual-structure vertical MOS transistor having a common drain electrode and in which two vertical MOS transistors are arranged in one semiconductor device, and is a semiconductor device with a four-pad structure in which the source electrode and the gate electrode of each vertical MOS transistor each have a corresponding pad.

[0072] Figure 2 The shape, size, and configuration of the pads in the plan view shown are only examples, and the shapes and sizes of the four pads (first source pad 111, first gate pad 119, second source pad 121, and second gate pad 129) are preferably uniform, and more preferably circular with the same diameter.

[0073] Figure 3 It is a schematic plan view showing an example of the shape and arrangement of components of the semiconductor device 1 in a plan view. Figure 3 In order to easily understand the structure of the upper surface of the semiconductor layer 40 which is actually not recognizable, the passivation layer 35 and the interlayer insulating layer 34 are omitted and shown as if they are transparent. Figure 2 The corresponding relationship is shown.

[0074] like Figure 3As shown, in the plan view, the shape and configuration of the components provided in the first area A1 and the shape and configuration of the components provided in the second area A2 corresponding to the components in a 1:1 manner are arranged to be in a line-symmetric relationship with the boundary line 90 as the axis of symmetry. The components corresponding in a 1:1 manner are, for example, the first gate electrode 19 and the second gate electrode 29, the first source pad 111 and the second source pad 121, the first gate resistor element 41 and the second gate resistor element 51 described later, etc. The same is true for the first control area C1 and the second control area C2 described later. They are arranged in a line-symmetric relationship with the boundary line 90 as the axis of symmetry in the plan view.

[0075] like Figure 3 As shown, a first gate resistor 41 connected to the first gate electrode 19 is formed in the first region A1 of the semiconductor device 1 , and a second gate resistor 51 connected to the second gate electrode 29 is formed in the second region A2 of the semiconductor device 1 .

[0076] As a non-limiting example, the first gate resistor 41 and the second gate resistor 51 are made of polysilicon implanted with first conductivity type or second conductivity type impurities, and each gate resistor is made of a material having a larger resistance value than a metal material constituting a source electrode or the like.

[0077] The first gate resistor 41 and the second gate resistor 51 are provided to prevent the transistor 10 and the transistor 20 from being damaged when an excessive voltage is applied to the gate electrode or a surge current flows. That is, the first gate resistor 41 and the second gate resistor 51 are provided to improve the ESD resistance of the semiconductor device 1.

[0078] In addition, if Figure 3 As shown, in the first region A1 of the semiconductor device 1, a first gate wiring 42 is provided which is connected to the first gate electrode 19 via a first gate resistor element 41 and is provided so as to surround the first source electrode 11. Similarly, in the second region A2 of the semiconductor device 1, a second gate wiring 52 is provided which is connected to the second gate electrode 29 via a second gate resistor element 51 and is provided so as to surround the second source electrode 21.

[0079] The first gate wiring 42 and the second gate wiring 52 are formed, as a non-limiting example, of polysilicon injected with impurities of the first conductivity type or the second conductivity type or a metal of the same type as the first gate electrode 19 and the second gate electrode 29, and are connected to the first gate conductor 15 and the second gate conductor 25, respectively.

[0080] In addition, if Figure 3As shown, in a plan view, a first Zener diode 43 connected to the first source electrode 11 and the first gate electrode 19 and arranged around the first gate electrode 19 is provided in the first region A1. Similarly, a second Zener diode 53 connected to the second source electrode 21 and the second gate electrode 29 and arranged around the second gate electrode 29 is provided in the second region A2.

[0081] As a non-limiting example, the first Zener diode 43 and the second Zener diode 53 may be bidirectional Zener diodes made of polysilicon implanted with first conductivity type or second conductivity type impurities and having one or more PN junctions.

[0082] The first Zener diode 43 and the second Zener diode 53 are provided to prevent the transistor 10 and the transistor 20 from being damaged when an excessive voltage is applied to the gate electrode or the source electrode or a surge current flows. That is, the first Zener diode 43 and the second Zener diode 53 are elements provided to improve the ESD resistance of the semiconductor device 1.

[0083] also, Figure 3 Although not shown in the figure, the first region A1 includes a first connection region where the first Zener diode 43 is connected to the first source electrode 11, and the second region A2 includes a second connection region where the second Zener diode 53 is connected to the second source electrode 21 (see Fig.14 ).

[0084] Furthermore, the first connection region and the second connection region are made of the same metal as the portion 13 of the first source electrode 11 and the portion 23 of the second source electrode 21 , and the first gate trench 17 and the second gate trench 27 are not provided directly thereunder in plan view.

[0085] In addition, if Figure 3 As shown, in the plan view, a first EQR (EQui potential ring) 44 electrically connected to the semiconductor substrate 32 as a common drain region may be provided at the periphery of the first region A1. Similarly, in the plan view, a second EQR 54 electrically connected to the semiconductor substrate 32 as a common drain region may be provided at the periphery of the second region A2. In the plan view, the first EQR 44 and the second EQR 54 may be shared in a portion where the transistor 10 and the transistor 20 are adjacent and opposed.

[0086] In addition, the portion where the first EQR 44 and the second EQR 54 are common and is perpendicular to the first direction may be understood as the boundary line 90 .

[0087] In the transistor 10 , the first EQR 44 is provided to prevent leakage current from flowing between the outside and the first body region 18 . In the transistor 20 , the second EQR 54 is provided to prevent leakage current from flowing between the outside and the second body region 28 .

[0088] As a non-limiting example, the first EQR 44 and the second EQR 54 may be made of a metal material including one or more of aluminum, copper, gold, and silver. In addition, the first EQR 44 and the second EQR 54 may be electrically connected to the metal layer 30 via the semiconductor substrate 32 as a common drain region.

[0089] like Figure 3 As shown, in the plan view, in the first region A1, a rectangular region having the largest area in a range including the first gate pad 119 inside and excluding neither the first source electrode 11 nor the first gate resistance element 41 is referred to as a first gate electrode region G1.

[0090] Likewise, if Figure 3 As shown, in the plan view, in the second region A2, a rectangular region having the largest area in a range including the second gate pad 129 and excluding the second source electrode 21 and the second gate resistor 51 is referred to as a second gate electrode region G2.

[0091] In addition, if Figure 3 As shown, in the plan view, in the first region A1, a rectangular region having the largest area including the first gate resistor 41 therein and excluding neither the first source electrode 11 nor the first gate electrode region G1 is referred to as a first resistor region R1.

[0092] Likewise, if Figure 3 As shown, in the plan view, in the second region A2, a rectangular region having the largest area including the second gate resistor 51 therein and excluding neither the second source electrode 21 nor the second gate electrode region G2 is referred to as a second resistor region R2.

[0093] In plan view, the first gate electrode region G1 and the first resistor region R1 do not overlap due to the definition of the range of each region. However, in plan view, the outer peripheries of the regions may coincide with each other.

[0094] Similarly, in plan view, the second gate electrode region G2 and the second resistor region R2 do not overlap due to the definition of the range of each region. However, in plan view, the outer peripheries of the regions may coincide with each other.

[0095] Furthermore, in the present disclosure, when the outer periphery of a certain area is shown to be consistent with the outer periphery of another area in a plan view, it can be understood that the respective outer peripheries are overlapped or common.

[0096] like Figure 3 As shown, in a plan view, at least one side of the outer periphery of the first gate electrode region G1 and at least one side of the outer periphery of the first resistor region R1 coincide with a portion of the third side S3 of the semiconductor layer 40 .

[0097] Likewise, if Figure 3 As shown, in a plan view, at least one side of the outer periphery of the second gate electrode region G2 and at least one side of the outer periphery of the second resistor region R2 coincide with a portion of the third side S3 of the semiconductor layer 40 .

[0098] In addition, if Figure 3 As shown, in the plan view, the outer periphery of the first resistor element region R1 includes only one corner (also called the first corner P1) among the four corners of the outer periphery of the first gate electrode region G1, which has the shortest distance to the boundary line 90 and the shortest distance to the third side S3 of the semiconductor layer 40, and does not include other corners.

[0099] Likewise, if Figure 3 As shown, in the plan view, the outer periphery of the second resistor element region R2 includes only one corner (also called the second corner P2) among the four corners of the outer periphery of the second gate electrode region G2, which has the shortest distance to the boundary line 90 and the shortest distance to the third side S3 of the semiconductor layer 40, and does not include other corners.

[0100] like Figure 3 As shown, in the plan view, in the first area A1, the area obtained by adding the first gate electrode area G1 and the first resistor element area R1 is called the first control area C1. Similarly, in the plan view, in the second area A2, the area obtained by adding the second gate electrode area G2 and the second resistor element area R2 is called the second control area C2.

[0101] like Figure 3 As shown, with respect to the semiconductor device 1, in a plan view, at least one side of the outer periphery of the first control region C1 and at least one side of the outer periphery of the second control region C2 are consistent with a portion of the third side S3 of the semiconductor layer 40, and the outer periphery of the first control region C1 and the outer periphery of the second control region C2 do not have a portion that is consistent with the fourth side S4 of the semiconductor layer 40.

[0102] In addition, if Figure 3As shown, in plan view, the length of the portion where the outer periphery of the first control region C1 coincides with the outer periphery of the semiconductor layer 40 is the longest where the outer periphery of the first control region C1 coincides with the third side S3 of the semiconductor layer 40 .

[0103] Likewise, if Figure 3 As shown, in the plan view, the length of the portion where the outer periphery of the second control region C2 coincides with the outer periphery of the semiconductor layer 40 is the longest where the outer periphery of the second control region C2 coincides with the third side S3 of the semiconductor layer 40 .

[0104] exist Figure 3 , an example is shown in which the outer periphery of the first control region C1 and the outer periphery of the second control region C2 in a plan view are respectively consistent with a portion of the first side S1 and a portion of the second side S2 of the semiconductor layer 40. However, the semiconductor device 1 of the present embodiment may also have a portion in which the outer periphery of the first control region C1 and the outer periphery of the second control region C2 in a plan view do not respectively have portions that are consistent with a portion of the first side S1 and a portion of the second side S2 of the semiconductor layer 40.

[0105] In addition, Figure 3 2 shows an example in which the outer periphery of the first control region C1 and the outer periphery of the second control region C2 in a plan view are respectively consistent with a portion of the boundary line 90. However, the semiconductor device 1 of the present embodiment may also have a portion in which the outer periphery of the first control region C1 and the outer periphery of the second control region C2 in a plan view do not have a portion consistent with a portion of the boundary line 90.

[0106] Figure 4 : is a circuit diagram showing an equivalent circuit of the semiconductor device 1 according to the present embodiment.

[0107] like Figure 4 As shown, in the transistor 10 , the first gate resistance element 41 and the first Zener diode 43 are connected in parallel between the first gate pad 119 and the first source pad 111 , respectively.

[0108] Among them, due to the function of the first Zener diode 43, when an excessive voltage is applied to the first gate pad 119 or the first source pad 111 or a surge current flows, a path for current to flow between the first gate pad 119 and the first source pad 111 through the first Zener diode 43 is opened.

[0109] Generally, as a damage mode of a vertical MOS transistor caused by the application of an excessive voltage or the flow of a surge current, there is damage to the gate insulating film. By providing the first Zener diode 43 in the transistor 10 to shunt the surge current, the load acting on the first gate insulating film 16 can be reduced. Thus, the damage to the first gate insulating film 16 can be prevented, so the ESD resistance of the transistor 10 can be improved.

[0110] Furthermore, by providing the first gate resistance element 41 in parallel with the first Zener diode 43 , the surge current flowing through the first gate insulating film 16 can be further reduced, so that the ESD resistance of the transistor 10 can be further improved.

[0111] In the above description, an example is given in which an excessive voltage is applied to the first gate pad 119 or the first source pad 111 of the transistor 10 or a surge current flows. This is also the case when an excessive voltage is applied to the second gate pad 129 or the second source pad 121 of the transistor 20 or a surge current flows. By providing the second Zener diode 53 and the second gate resistor 51 in the transistor 20, the damage of the second gate insulating film 26 can be prevented, so the ESD resistance of the transistor 20 can be improved.

[0112] [2. Operation of semiconductor device]

[0113] Figure 5A and Figure 5B The schematic diagrams are respectively a plan view and a three-dimensional view of a rough unit structure of the transistor 10 or the transistor 20 repeatedly formed in the X direction and the Y direction of the semiconductor device 1. Figure 5A and Figure 5B In the figure, the semiconductor substrate 32, the metal layer 30, the passivation layer 35, the first source electrode 11 or the second source electrode 21, and the interlayer insulating layer 34 are not shown for easy understanding.

[0114] In addition, the Y direction is parallel to the upper surface of the semiconductor layer 40 and is the direction in which the first gate trench 17 extends. In addition, the X direction is parallel to the upper surface of the semiconductor layer 40 and is orthogonal to the Y direction. The Z direction is a direction that is orthogonal to both the X direction and the Y direction and indicates the height direction of the semiconductor device 1.

[0115] like Figure 5A and Figure 5BAs shown, in the transistor 10, a first connection portion 18a electrically connecting the first body region 18 and the first source electrode 11 is provided. The first connection portion 18a is a region of the first body region 18 where the first source region 14 is not formed, and contains the same second conductivity type impurities as the first body region 18. The first source region 14 and the first connection portion 18a are alternately and periodically arranged repeatedly along the Y direction. The transistor 20 is the same.

[0116] In the semiconductor device 1, for example, the first conductivity type may be set to N type, the second conductivity type may be set to P type, the first source region 14, the second source region 24, the semiconductor substrate 32 and the low-concentration impurity layer 33 may be N type semiconductors, and the first body region 18, the first connecting portion 18a, the second body region 28 and the second connecting portion 28a may be P type semiconductors.

[0117] In addition, in the semiconductor device 1, for example, the first conductivity type may be set to P type, the second conductivity type may be set to N type, the first source region 14, the second source region 24, the semiconductor substrate 32 and the low-concentration impurity layer 33 may be P type semiconductors, and the first body region 18, the first connecting portion 18a, the second body region 28 and the second connecting portion 28a may be N type semiconductors.

[0118] In the following description, it is assumed that the transistor 10 and the transistor 20 are so-called N-channel transistors having an N-type first conductivity type and a P-type second conductivity type, and the bidirectional conduction path of the semiconductor device 1 is described.

[0119] In the semiconductor device 1, when a high voltage is applied to the first source electrode 11 and a low voltage is applied to the second source electrode 21, and a voltage higher than a threshold value is applied to the second gate electrode 29 (second gate conductor 25) with reference to the second source electrode 21, a conduction channel is formed near the second gate insulating film 26 in the second body region 28. As a result, a current flows through a path of the first source electrode 11-first connecting portion 18a-first body region 18-low-concentration impurity layer 33-semiconductor substrate 32-metal layer 30-semiconductor substrate 32-low-concentration impurity layer 33-conduction channel formed in the second body region 28-second source region 24-second source electrode 21, and the semiconductor device 1 is turned on. A PN junction exists at the contact surface between the first body region 18 and the low-concentration impurity layer 33 in this conduction path, and functions as a body diode.

[0120] Similarly, in the semiconductor device 1, when a high voltage is applied to the second source electrode 21 and a low voltage is applied to the first source electrode 11, and a voltage higher than a threshold value is applied to the first gate electrode 19 (first gate conductor 15) with reference to the first source electrode 11, a conduction channel is formed near the first gate insulating film 16 in the first body region 18. As a result, a current flows through the path of the second source electrode 21-second connecting portion 28a-second body region 28-low-concentration impurity layer 33-semiconductor substrate 32-metal layer 30-semiconductor substrate 32-low-concentration impurity layer 33-conduction channel formed in the first body region 18-first source region 14-first source electrode 11, and the semiconductor device 1 is turned on. A PN junction exists at the contact surface between the second body region 28 and the low-concentration impurity layer 33 in this conduction path, and functions as a body diode.

[0121] Furthermore, in the semiconductor device 1, a voltage above the threshold is applied to the first gate electrode 19 to form a conduction channel near the first gate insulating film 16 in the first body region 18, and a voltage above the threshold is applied to the second gate electrode 29 to form a conduction channel near the second gate insulating film 26 in the second body region 28. As a result, the semiconductor device 1 can be turned on by flowing a current in the path of the first source electrode 11-first source region 14-conduction channel formed in the first body region 18-low-concentration impurity layer 33-semiconductor substrate 32-metal layer 30-semiconductor substrate 32-low-concentration impurity layer 33-conductivity channel formed in the second body region 28-second source region 24-second source electrode 21 or in the opposite path.

[0122] Figure 6 1 is a schematic plan view showing an example of the shapes and arrangements of the first body region 18 and the second body region 28 and the first active region 112 and the second active region 122 in a plan view, among the components of the semiconductor device 1. Figure 6 In order to make the structure of the upper surface of the semiconductor layer 40, which is actually not recognizable, easier to understand, the passivation layer 35, the first source electrode 11, the first gate electrode 19, the second source electrode 21, the second gate electrode 29, and the interlayer insulating layer 34 are omitted and shown as if they are transparent. In addition, the first source region 14 and the second source region 24 are also omitted. The pads shown by the dotted lines are for the purpose of Figure 2 and Figure 3 The corresponding relationship is easy to understand.

[0123] The first active region 112 is a minimum range that includes all of the portions where a conduction channel is formed when a voltage above a threshold value is applied to the first gate electrode 19 (first gate conductor 15) of the transistor 10. The portion where a conduction channel is formed is a portion where the plurality of first gate trenches 17 are adjacent to the first source region 14. Figure 6 As shown, in a plan view of the semiconductor layer 40 , the first active region 112 is contained within the first body region 18 .

[0124] The second active region 122 is a minimum range that includes all of the portions where a conduction channel is formed when a voltage above a threshold value is applied to the second gate electrode 29 (second gate conductor 25) of the transistor 20. The portion where a conduction channel is formed is a portion where the plurality of second gate trenches 27 are adjacent to the second source region 24. Figure 6 As shown, in a plan view of the semiconductor layer 40 , the second active region 122 is contained within the second body region 28 .

[0125] To reduce the on-resistance of semiconductor device 1, it is required to ensure as large an area as possible for first active region 112 and second active region 122. If the area of ​​first active region 112 and second active region 122 is large, the conduction path of semiconductor device 1 is expanded, and the on-resistance of semiconductor device 1 is reduced.

[0126] Figure 3 The first control region C1 and the second control region C2 shown in the figure are regions where the first active region 112 and the second active region 122 are not formed, and are regions that do not contribute to the conduction of the semiconductor device 1. That is, the first control region C1 and the second control region C2 are regions necessary for the semiconductor device 1 to function, and on the other hand, the first control region C1 and the second control region C2 are regions that are desired to be as small as possible in order to reduce the on-resistance of the semiconductor device 1 within a limited device area.

[0127] [3. Investigation]

[0128] The features of the semiconductor device 1 in the present disclosure described above are as follows.

[0129] A semiconductor device 1 of a technical solution disclosed in the present invention is a chip-size package type semiconductor device 1 that can be mounted face-down, and comprises: a semiconductor layer 40, including a semiconductor substrate 32; a first vertical MOS transistor 10, which is formed as a whole in a first region A1 of the semiconductor layer 40 on the upper surface side of the semiconductor layer 40; a second vertical MOS transistor 20, which is formed as a whole in a second region A2 adjacent to the first region A1 in a plan view of the semiconductor layer 40; and a metal layer 30, which is formed on the lower surface side of the semiconductor layer 40 and is in contact with and connected to the semiconductor substrate 32; the semiconductor substrate 32 is the first vertical MOS transistor 10 and The common drain region of the second vertical MOS transistor 20, in the plan view, the semiconductor layer 40 is a square, in the plan view, the first region A1 and the second region A2 are arranged in the first direction, in the plan view, the boundary line 90 between the first region A1 and the second region A2 is orthogonal to the first direction, and is a straight line that divides the semiconductor layer 40 into two equal parts in area and passes through the center of the semiconductor layer 40, in the plan view, the pads provided in the first region A1 are only a first source pad 111 connected to the first source electrode 11 of the first vertical MOS transistor 10 and a first gate pad 112 connected to the first vertical MOS transistor 10. The first vertical MOS transistor 10 comprises: a first gate pad 119 connected to the first gate electrode 19; a first gate resistor 41 connected to the first gate electrode 19; a first gate electrode region G1, which is a rectangular region that includes the first gate pad 119 in a plan view and is the largest region in a range that does not include the first source electrode 11 or the first gate resistor 41; and a first resistor region R1, which is a rectangular region that includes the first gate resistor 41 in a plan view and is a range that does not include the first source electrode 11 or the first gate electrode region G1. The area with the largest area; in the plan view, the full length of one side in the outer periphery of the first gate electrode region G1 and the full length of one side in the outer periphery of the first resistor element region R1 are consistent with a portion of the side in the outer periphery of the semiconductor layer 40 that is orthogonal to the boundary line 90 and has the shortest distance to the first gate pad 119. In the plan view, the outer periphery of the first resistor element region R1 only includes one corner (first corner P1) among the four corners of the outer periphery of the first gate electrode region G1 that has the shortest distance to the boundary line 90 and the shortest distance to the side in the outer periphery of the semiconductor layer 40 that is orthogonal to the boundary line 90.

[0130] Figure 8 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.141 is a schematic plan view showing an example of the shape and arrangement of components of the semiconductor device 1 according to the present embodiment that satisfies the above-mentioned conditions.

[0131] Figure 8 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 In order to facilitate understanding of the structure of the upper surface of the semiconductor layer 40 which is actually not recognizable, the passivation layer 35 and the interlayer insulating layer 34 are omitted and shown as if they are transparent. The pads shown by the dotted lines would not be visible if the passivation layer 35 is omitted, but are shown as they remain for easy understanding.

[0132] In the description Figure 8 Before the features and effects of the shapes and arrangements of the components shown below, first use Fig. 7A , Figure 7B A semiconductor device 2 of comparative example 1 of the present embodiment will be described. Regarding the semiconductor device 2 of comparative example 1, the same components as those of the semiconductor device 1 of the present embodiment are considered to have been described and are assigned the same reference numerals, and their detailed description is omitted, and the description will focus on the differences from the semiconductor device 1.

[0133] It is described that the ESD resistance of a semiconductor device can be improved by providing a gate resistance element in the semiconductor device. However, in a planar view of the semiconductor layer, depending on the positions of the gate electrode and the gate resistance element, there are cases where the contribution to conduction is low despite being an active region. This is described using the semiconductor device 2 of Comparative Example 1.

[0134] Fig. 7A It is a schematic plan view showing the shapes and arrangements of components of the semiconductor device 2 in a plan view of the semiconductor layer 40 . Fig. 7A In order to facilitate understanding of the structure of the upper surface of the semiconductor layer 40 which is actually not recognizable, the passivation layer 35 and the interlayer insulating layer 34 are omitted and shown as if they are transparent. The pads shown by the dotted lines would not be visible if the passivation layer 35 is omitted, but are left to be shown for easy understanding.

[0135] Figure 7B It is a schematic plan view showing the shapes and arrangements of the first body region 18 and the second body region 28 and the first active region 112 and the second active region 122 in a plan view among the components of the semiconductor device 2 . Figure 7B In addition to Fig. 7AIn addition to the omission in FIG. 1 , the first source electrode 11 , the first gate electrode 19 , the second source electrode 21 , and the second gate electrode 29 are omitted from the illustration. In addition, the illustration of the first source region 14 and the second source region 24 is also omitted.

[0136] The semiconductor layer 40 of the semiconductor device 2 of Comparative Example 1 has the same shape and the same area as those of the semiconductor layer 40 of the semiconductor device 1 of the embodiment in plan view.

[0137] like Fig. 7A As shown, in the plan view, in the first region A1 of the semiconductor device 2, a first control region C1 is formed by adding the first gate electrode region G1 and the first resistor region R1 together. In addition, in the second region A2, a second control region C2 is formed by adding the second gate electrode region G2 and the second resistor region R2 together. In the plan view, the semiconductor device 1 of the embodiment and the semiconductor device 2 of the comparative example 1 are the same in terms of the area of ​​the first control region C1 and the area of ​​the second control region C2 (see FIG. Figure 3 ).

[0138] like Fig. 7A As shown, in the plan view, one side of the outer periphery of the first resistor element region R1 coincides with a portion of the third side S3 of the semiconductor layer 40. However, the outer periphery of the first gate electrode region G1 does not have a portion that coincides with the outer periphery of the semiconductor layer 40. In addition, the outer periphery of the first resistor element region R1 does not include the first corner P1 of the four corners of the outer periphery of the first gate electrode region G1. In addition, the so-called first corner P1 is the same as the definition in the semiconductor device 1 of the embodiment, and is the corner of the four corners of the outer periphery of the first gate electrode region G1 in the plan view that has the shortest distance to the boundary line 90 and the shortest distance to the side of the outer periphery of the semiconductor layer 40 that is orthogonal to the boundary line 90.

[0139] Similarly, in the plan view, one side of the outer periphery of the second resistor element region R2 coincides with a portion of the third side S3 of the semiconductor layer 40. However, the outer periphery of the second gate electrode region G2 does not have a portion that coincides with the outer periphery of the semiconductor layer 40. In addition, the outer periphery of the second resistor element region R2 does not include the second corner P2 of the four corners of the outer periphery of the second gate electrode region G2. In addition, the so-called second corner P2 is the same as the definition in the semiconductor device 1 of the embodiment, and is the corner of the four corners of the outer periphery of the second gate electrode region G2 in the plan view that has the shortest distance to the boundary line 90 and the shortest distance to the side of the outer periphery of the semiconductor layer 40 that is orthogonal to the boundary line 90.

[0140] Figure 7BThe area of ​​the first active region 112 and the area of ​​the second active region 122 in the plan view of the semiconductor device 2 shown in the figure are respectively the same as the area of ​​the first active region 112 and the area of ​​the second active region 122 in the plan view of the semiconductor device 1 of the embodiment (see FIG. Figure 6 ).

[0141] However, if Figure 7B As shown, in the plan view, in the first active region 112 of the semiconductor device 2, a relatively narrow region is generated in the region between the first gate electrode region G1 and the boundary line 90, or in the region between the first gate electrode region G1 and the first side S1 of the semiconductor layer 40. The relatively narrow region between the first gate electrode region G1 and the boundary line 90, or between the first gate electrode region G1 and the first side S1 of the semiconductor layer 40 is referred to as a first narrow (narrow passage) region N1.

[0142] Similarly, in the plan view, in the second active region 122 of the semiconductor device 2, a relatively narrow region is generated in the region between the second gate electrode region G2 and the boundary line 90, or in the region between the second gate electrode region G2 and the second side S2 of the semiconductor layer 40. The relatively narrow region between the second gate electrode region G2 and the boundary line 90, or between the second gate electrode region G2 and the second side S2 of the semiconductor layer 40 is referred to as a second narrow (narrow path) region N2.

[0143] In addition, if Figure 7B As shown, in a plan view, in the first active region 112 of the semiconductor device 2, there is a region that cannot be reached from the first source pad 111 without passing through the first narrow region N1. This is called a first dead end region D1.

[0144] Likewise, in the plan view, in the second active region 122 of the semiconductor device 2, there is a region that cannot be reached from the second source pad 121 without passing through the second narrow region N2. This region is referred to as a second dead-end region D2.

[0145] When current flows from first source pad 111 , the portion of first source electrode 11 formed near first source pad 111 is sufficiently large and has low on-resistance, and is a region that can be effectively used for conduction.

[0146] In this regard, from the perspective of the first source pad 111, the current cannot reach the portion of the first source electrode 11 formed in the first non-path region D1 without passing through the first narrow region N1. However, the portion of the first source electrode 11 formed in the first narrow region N1 has a relatively high on-resistance when the current passes therethrough because the width is narrow in a plan view. Therefore, it is difficult for the current to flow in the portion of the first source electrode 11 formed in the first narrow region N1, and further, it is also difficult for the current to reach the portion of the first source electrode 11 formed in the first non-path region D1 in front of the first narrow region N1.

[0147] That is, although the first narrow region N1 and the first non-path region D1 both have a mechanism that can contribute to conduction as part of the first active region 112, the current density is not increased and they are only regions that are relatively difficult to contribute to conduction. The same is true for the second narrow region N2 and the second non-path region D2.

[0148] Therefore, the semiconductor device 2 of Comparative Example 1 is not a configuration that can fully and effectively utilize the remaining limited area after the first control region C1 and the second control region C2 are provided in a plan view in order to reduce the on-resistance. In order to reduce the on-resistance, it is preferable to configure the first narrow region N1 and the second narrow region N2 and the first non-path region D1 and the second non-path region D2 so as to minimize the generation of the first narrow region N1 and the second narrow region N2 that relatively reduce the contribution to conduction.

[0149] like Figure 3 As shown, in the semiconductor device 1 disclosed in the present invention, in a plan view, the first gate electrode region G1 and the first resistor element region R1 are respectively configured so that the entire length of one side in the outer periphery of the first gate electrode region G1 and the first resistor element region R1 is consistent with a portion of the third side S3 of the semiconductor layer 40, so that the first non-path region D1 is not generated.

[0150] Similarly, in the semiconductor device 1 disclosed herein, in a plan view, the second gate electrode region G2 and the second resistor element region R2 are respectively configured so that the entire length of one side in the outer periphery of the second gate electrode region G2 and the second resistor element region R2 is consistent with a portion of the third side S3 of the semiconductor layer 40, so that a second non-path region D2 is not generated.

[0151] Therefore, in semiconductor device 1, although the area of ​​the active region is the same, the area that contributes relatively more to conduction can be expanded compared to semiconductor device 2 of Comparative Example 1. That is, it is a configuration that can effectively utilize the limited area of ​​semiconductor device 1 and reduce on-resistance.

[0152] Furthermore, when the semiconductor device 1 is mounted face down on the mounting substrate, if the distance between the pads of the semiconductor device 1 is short in a plan view, the solders joining the semiconductor device 1 to the mounting substrate may come into contact with each other. Therefore, a certain distance must be maintained between the pads of the semiconductor device 1. As a non-limiting example, the certain distance is the same as the diameter of the pads of the semiconductor device 1.

[0153] In view of the above reasons, if Figure 8 As shown, the semiconductor device 1 is preferably configured such that the first resistor element region R1 is disposed between the side of the outer periphery of the first gate electrode region G1 that is shortest from the boundary line 90 and the boundary line 90 in a plan view of the semiconductor layer 40. It is more preferably configured such that the entire length of one side of the outer periphery of the first resistor element region R1 coincides with a portion of the side of the outer periphery of the first gate electrode region G1 that is shortest from the boundary line 90.

[0154] Likewise, it is preferred that the second resistor element region R2 be disposed between the side of the outer periphery of the second gate electrode region G2 that is shortest from the boundary line 90 and the boundary line 90. It is more preferred that the second resistor element region R2 be disposed so that the entire length of one side of the outer periphery of the second resistor element region R2 coincides with a portion of the side of the outer periphery of the second gate electrode region G2 that is shortest from the boundary line 90.

[0155] By setting it as such a configuration, the area between the first gate pad 119 and the second gate pad 129 provided to prevent mounting defects caused by contact between solders can be flexibly utilized as an area for arranging the first gate resistance element 41 and the second gate resistance element 51 without waste.

[0156] The above advantages are described in more detail.

[0157] exist Figure 8 In the semiconductor device 1 shown, the area reduction region is shown on both sides in the X direction. This is a region where the area can be appropriately reduced if further miniaturization of the semiconductor device 1 is required. As described above, the region between the first gate pad 119 and the second gate pad 129 must have a certain width to prevent solder from contacting each other, and excessive reduction is not a good idea.

[0158] Therefore, in Figure 8In the plan view, the end of the semiconductor device 1 in the X direction of the first active region 112 (or the first source electrode 11) is a place where the area can be easily reduced. In the plan view, the first region A1 is a strip-shaped region in the Y direction between the side of the outer periphery of the first gate electrode region G1 that is shortest to the first side S1 of the semiconductor layer 40 and the first side S1 of the semiconductor layer 40.

[0159] Similarly, the end of the semiconductor device 1 in the X direction of the second active region 122 (or the second source electrode 21) in the plan view is a place where the area can be easily reduced. In the plan view, the second region A2 is a strip-shaped region in the Y direction between the side of the outer periphery of the second gate electrode region G2 that is shortest to the second side S2 of the semiconductor layer 40 and the second side S2 of the semiconductor layer 40.

[0160] Right now, Figure 8 In the semiconductor device 1 of the present embodiment shown, the first resistor element region R1 and the second resistor element region R2 are provided in a manner sandwiched between the first gate electrode region G1 and the second gate electrode region G2, thereby being able to meet the requirement for reducing the area of ​​the semiconductor layer 40, that is, miniaturizing the semiconductor device 1.

[0161] Next, use FIG. 9A to FIG. 9E Semiconductor devices 3 to 7 of Comparative Examples 2 to 6 of the present embodiment will be described. Regarding semiconductor devices 3 to 7 of Comparative Examples 2 to 6, components identical to those of semiconductor device 1 are considered to have been described and are given the same reference numerals and detailed descriptions thereof, with the description centering on differences from semiconductor device 1.

[0162] By indicating FIG. 9A to FIG. 9E In Comparison Examples 2 to 6, in the semiconductor device 1 of the present embodiment, the advantages of the outer periphery of the first resistance element region R1 and the outer periphery of the second resistance element region R2 respectively only including the first corner P1 of the outer periphery of the first gate electrode region G1 and the second corner P2 of the outer periphery of the second gate electrode region G2 are described.

[0163] FIG. 9A to FIG. 9E 4 is a schematic plan view showing the shapes and arrangements of the components of the semiconductor devices 3 to 7 in a plan view of the semiconductor layer 40. FIG. 9A to FIG. 9EFor ease of understanding, only the first region A1 of the semiconductor layer 40 is divided and extracted from the components of the semiconductor devices 3 to 7, and only the first source electrode 11, the first source pad 111, the first gate pad 119, the first gate electrode region G1, and the first resistor region R1 are shown, and components other than these are omitted and illustrated. The shape and arrangement of each component in the second region A2 of the semiconductor layer 40 in a plan view can be understood to be in a line symmetric relationship with the shape and arrangement of each component in a plan view that corresponds 1:1 to each other in the first region A1, with the boundary line 90 as the symmetry axis.

[0164] In the semiconductor devices 3 to 7 of Comparative Examples 2 to 6, the first region A1 of the semiconductor layer 40 has the same shape and area in a plan view as the first region A1 of the semiconductor layer 40 of the semiconductor device 1 of the embodiment. In addition, the first gate electrode region G1, the first resistor region R1, the first active region 112, the first source pad 111, etc. also have the same area.

[0165] like Figures 9A to 9E As shown, the semiconductor devices 3 to 7 of Comparative Examples 2 to 6 have in common that the entire length of one side in the outer periphery of the first gate electrode region G1 coincides with a portion of the third side S3 of the semiconductor layer 40 .

[0166] Fig. 9A : is a schematic plan view of the semiconductor device 3 of Comparative Example 2. In the plan view, in the semiconductor device 3, the outer periphery of the first resistor element region R1 includes only one corner of the four corners of the outer periphery of the first gate electrode region G1 that has the shortest distance to the boundary line 90 but is not the shortest distance to the third side S3 of the semiconductor layer 40 (i.e., the shortest distance to the fourth side S4 of the semiconductor layer 40). Furthermore, in the semiconductor device 3, in the plan view, the first resistor element region R1 is arranged in the region between the first gate electrode region G1 and the boundary line 90.

[0167] Therefore, in Fig. 9A In the configuration shown, a first non-path region D1 is generated in the semiconductor device 3. Therefore, it can be said that the semiconductor device 1 ( Figure 8 ) is a configuration in which it is difficult to reduce the on-resistance even if the area of ​​the first active region 112 is the same.

[0168] Fig. 9B1 is a schematic plan view of the semiconductor device 4 of Comparative Example 3. In the plan view, in the semiconductor device 4, the outer periphery of the first resistor element region R1 includes only one corner of the four corners of the outer periphery of the first gate electrode region G1 that is shortest to the boundary line 90 but not shortest to the third side S3 of the semiconductor layer 40 (i.e., the distance to the fourth side S4 of the semiconductor layer 40 is the shortest).

[0169] also, Fig. 9C 1 is a schematic plan view of the semiconductor device 5 of Comparative Example 4. In the plan view, in the semiconductor device 5, the outer periphery of the first resistor element region R1 includes only one corner having the shortest distance to the first side S1 of the semiconductor layer 40 and the shortest distance to the fourth side S4 of the semiconductor layer 40 among the four corners of the outer periphery of the first gate electrode region G1.

[0170] Furthermore, in the semiconductor devices 4 and 5 , the first resistor region R1 is arranged in a region between the first gate electrode region G1 and the first source pad 111 in plan view.

[0171] Therefore, in Fig. 9B The configuration of the semiconductor device 4 shown and Fig. 9C In the configuration of the semiconductor device 5 shown in the figure, a part of the region near the first source pad 111 which contributes relatively much to conduction is intentionally replaced with the first resistor region R1 which does not contribute to conduction. Figure 8 ) compared to the configuration shown in FIG. 1 , it can be said that it is a configuration in which it is difficult to reduce the on-resistance even if the area of ​​the first active region 112 is the same.

[0172] Fig.9D 1 is a schematic plan view of the semiconductor device 6 of Comparative Example 5. In the plan view, in the semiconductor device 6, the outer periphery of the first resistor element region R1 includes only one corner having the shortest distance to the first side S1 of the semiconductor layer 40 and the shortest distance to the fourth side S4 of the semiconductor layer 40 among the four corners of the outer periphery of the first gate electrode region G1.

[0173] also, Fig.9E 1 is a schematic plan view of the semiconductor device 7 of Comparative Example 6. In the plan view, in the semiconductor device 7, the outer periphery of the first resistor element region R1 includes only one corner of the four corners of the outer periphery of the first gate electrode region G1 that has the shortest distance to the third side S3 of the semiconductor layer 40 but is not the shortest distance to the boundary line 90 (i.e., the shortest distance to the first side S1 of the semiconductor layer 40).

[0174] Furthermore, in the semiconductor device 6 and the semiconductor device 7 , the first resistance element region R1 is arranged in a region between the first gate electrode region G1 and the first side S1 of the semiconductor layer 40 in plan view.

[0175] Therefore, in Fig.9D The configuration of the semiconductor device 6 shown and Fig.9E In the configuration of the semiconductor device 7 shown in FIG. Figure 8 However, as described above, it is not possible to cope with the case where the area of ​​the semiconductor layer 40 is required to be reduced (the semiconductor device 1 is required to be miniaturized).

[0176] In addition, Fig.9D In the configuration shown, a first non-via region D1 is generated in the semiconductor device 6. Therefore, compared with the semiconductor device 1 ( Figure 8 ) compared to the configuration shown in FIG. 1 , it can be said that it is a configuration in which it is difficult to reduce the on-resistance even if the area of ​​the first active region 112 is the same.

[0177] As above, it is most preferred that Figure 3 or Figure 8 As shown in the semiconductor device 1 of the present embodiment, in a plan view, the outer periphery of the first resistor element region R1 includes only one corner (first corner P1) of the four corners of the outer periphery of the first gate electrode region G1 which has the shortest distance to the boundary line 90 and the shortest distance to the third side S3 of the semiconductor layer 40.

[0178] Similarly, it is most preferred that, in a plan view, the outer periphery of the second resistor element region R2 includes only one corner (second corner P2) of the four corners of the outer periphery of the second gate electrode region G2 which has the shortest distance to the boundary line 90 and the shortest distance to the third side S3 of the semiconductor layer 40.

[0179] By adopting the above configuration, the semiconductor device 1 of the present embodiment can ensure ESD tolerance by including a gate resistor element, and can also reduce on-resistance by increasing the ratio of the active area that can be effectively utilized to the maximum extent possible in a limited area. Furthermore, there is room for responding to the demand for miniaturization of the semiconductor device 1.

[0180] In addition, if Figure 8 As shown, in the semiconductor device 1 of the present embodiment, the transistor 10 and the transistor 20 are arranged in line symmetry with the boundary line 90 as the axis of symmetry in a plan view of the semiconductor layer 40. Therefore, there is almost no bias between the transistor 10 and the transistor 20 in terms of bidirectional electrical characteristics and heat dissipation.

[0181] Therefore, in the semiconductor device 1, it is preferable that the transistor 10 and the transistor 20 are arranged in line symmetry with the boundary line 90 as the axis of symmetry as in the above-mentioned structure. As a result, it is not easy to produce bias in electrical characteristics and heat dissipation due to different current directions. For example, in a lithium-ion battery pack of a smartphone, a tablet computer, etc., if a protection circuit using the semiconductor device 1 is constructed, it is not necessary to specially set a difference in the conduction direction of the semiconductor device 1 regardless of charging or discharging.

[0182] That is, in the plan view, the pads provided in the second area A2 are only one second source pad 121 connected to the second source electrode 21 of the second vertical MOS transistor 20 and one second gate pad 129 connected to the second gate electrode 29 of the second vertical MOS transistor 20, and the second vertical MOS transistor 20 has a second gate resistor 51 connected to the second gate electrode 29, a second gate electrode area G2 which is a rectangle that includes the second gate pad 129 in the plan view and has the largest area within a range that does not include the second source electrode 21 nor the second gate resistor 51, and a second resistor area R2 which is a rectangle that includes the second gate resistor 51 in the plan view and has the largest area within a range that does not include the second source electrode 21 nor the second gate electrode area G2, and in the plan view, the outer surface of the second gate electrode area G2 is The total length of one side in the periphery and the total length of one side in the outer periphery of the second resistor element region R2 are consistent with a portion of the side in the outer periphery of the semiconductor layer 40 that is orthogonal to the boundary line 90 and has the shortest distance to the second gate pad 129. In the plan view, the outer periphery of the second resistor element region R2 only includes one corner (first corner P1) of the four corners of the outer periphery of the second gate electrode region G2 that has the shortest distance to the boundary line 90 and the shortest distance to the side in the outer periphery of the semiconductor layer 40 that is orthogonal to the boundary line 90. In the plan view, it is preferred that the second source pad 121, the second gate pad 129, the second gate electrode region G2 and the second resistor element region R2 are respectively configured to be in a linearly symmetrical relationship with the first source pad 111, the first gate pad 119, the first gate electrode region G1 and the first resistor element region R1 with the boundary line 90 as the axis of symmetry.

[0183] You can also Fig.10 As shown, in a plan view of the semiconductor layer 40 , the entire length of one side of the outer periphery of the first resistor element region R1 is configured to coincide with a portion of the boundary line 90 , and the entire length of one side of the outer periphery of the second resistor element region R2 is configured to coincide with a portion of the boundary line 90 .

[0184] According to the above structure, Fig. 7ACompared with the semiconductor device 2 of the comparative example 1 shown in the figure, the semiconductor device 1 does not generate the first non-path region D1 and the second non-path region D2, and can reduce the area of ​​the first narrow region N1 and the area of ​​the second narrow region N2. Therefore, the area that can effectively contribute to the conduction of the semiconductor device 1 is expanded, so that the conduction resistance of the semiconductor device 1 can be reduced.

[0185] In addition, you can Fig.11 As shown, in the plan view of the semiconductor layer 40, the full length of one side in the outer periphery of the first gate electrode region G1 is configured to be consistent with a portion of the first side S1 in the outer periphery of the semiconductor layer 40 parallel to the boundary line 90, and the full length of one side in the outer periphery of the second gate electrode region G2 is configured to be consistent with a portion of the second side S2 in the outer periphery of the semiconductor layer 40 parallel to the boundary line 90.

[0186] According to the above structure, Fig. 7A Compared with the semiconductor device 2 of the comparative example 1 shown in the figure, the semiconductor device 1 does not generate the first non-path region D1 and the second non-path region D2, and can reduce the area of ​​the first narrow region N1 and the area of ​​the second narrow region N2. Therefore, the area that can effectively contribute to the conduction of the semiconductor device 1 is expanded, so that the conduction resistance of the semiconductor device 1 can be reduced.

[0187] In addition, Fig.11 The configuration shown is similar to Fig.10 The configuration shown is compared to that in plan view, in Fig.11 The first active region 112 (or the first source electrode 11) and the second active region 122 (or the second source electrode 21) are both enlarged in width in the X direction on the side close to the boundary line 90. Furthermore, except for the margin, the first active region 112 (or the first source electrode 11) and the second active region 122 (or the second source electrode 21) occupy the entire length of the boundary line 90 in the Y direction.

[0188] The opposing region where the first region A1 and the second region A2 are opposite to each other with the boundary line 90 sandwiched therebetween can use the entire length for conduction along the Y direction because the current density is the highest. That is, preferably, the opposing region is occupied by the first active region 112 (or the first source electrode 11) and the second active region 122 (or the second source electrode 21). Fig.11 In the arrangement shown, the entire length of the facing region along the Y direction can be effectively used for conduction, so that an effect of reducing conduction resistance can be obtained in particular.

[0189] It is preferable that the longest possible area of ​​the opposing region along the Y direction is effectively utilized even if it is not the entire length along the Y direction. Therefore, it is preferable that the outer periphery of the first source electrode 11 is longest in the portion closest to the boundary line 90 in a plan view. It is preferable that at least the length of the portion closest to the boundary line 90 in the outer periphery of the first source electrode 11 is longer than the length of the portion closest to the first side S1 of the semiconductor layer 40 in the outer periphery of the first source electrode 11 in a plan view.

[0190] Likewise, it is preferred that, in a plan view, the outer periphery of the second source electrode 21 is longest in a portion closest to the boundary line 90. It is preferred that, in a plan view, at least the length of the portion of the outer periphery of the second source electrode 21 closest to the boundary line 90 is longer than the length of the portion of the outer periphery of the second source electrode 21 closest to the second side S2 of the semiconductor layer 40.

[0191] The above structure can be Figure 3 or Fig.11 Such a configuration is implemented. Especially in Fig.11 In the illustrated arrangement, the first source electrode 11 and the second source electrode 21 each occupy the entire length in the Y direction along the boundary line 90 except for a margin, so that an effect of reducing on-resistance can be particularly achieved.

[0192] In addition, you can Figure 3 As shown, the entire length of one side of the outer periphery of the first control region C1 coincides with half of the third side S3 of the semiconductor layer 40 , and the entire length of one side of the outer periphery of the second control region C2 coincides with half of the third side S3 of the semiconductor layer 40 .

[0193] In addition, in other words, the above structure is that the length obtained by adding together the length of the outer periphery of the first control region C1 that is consistent with a portion of the third side S3 of the semiconductor layer 40 and the length of the outer periphery of the second control region C2 that is consistent with a portion of the third side S3 of the semiconductor layer 40 is the same as the length of one side of the outer periphery of the semiconductor layer 40 (the length of the third side S3).

[0194] Furthermore, in the plan view, with respect to the length of the portion where the outer periphery of the first control region C1 coincides with the outer periphery of the semiconductor layer 40, the length of the portion where the outer periphery of the first control region C1 coincides with the third side S3 of the semiconductor layer 40 is the longest, and with respect to the length of the portion where the outer periphery of the second control region C2 coincides with the outer periphery of the semiconductor layer 40, the length of the portion where the outer periphery of the second control region C2 coincides with the third side S3 of the semiconductor layer 40 is the longest.

[0195] According to the above structure, Fig. 7A , Figure 7B Compared with the semiconductor device 2 of the comparative example 1 shown in FIG. 1 , the semiconductor device 1 does not form the first non-via region D1 and the second non-via region D2, and Figure 8 , Fig.10 Compared with the embodiment of FIG. 1 , the area of ​​the first narrow region N1 and the area of ​​the second narrow region N2 can be minimized. Therefore, the region with high contribution to the conduction of the semiconductor device 1 is maximized, and the on-resistance of the semiconductor device 1 can be significantly reduced.

[0196] In addition, Fig.12 , Fig.13 , Fig.14 In the semiconductor device 1 shown, a portion of the first gate trench 17 and a portion of the second gate trench 27 are schematically represented by a straight line and circle marks at both ends thereof. The straight line is the gate trench, and the extension direction of the straight line is the extension direction of the gate trench. The circle marks at both ends are used to indicate the portion where the gate conductor embedded in each trench is connected to the gate wiring.

[0197] In addition, Fig.12 In the semiconductor device 1 shown, in a plan view, the first gate trench 17 and the second gate trench 27 extend in a direction orthogonal to the boundary line 90. In this case, the first gate wiring 42 and the second gate wiring 52 can be provided to surround the first source electrode 11 and the second source electrode 21, respectively, except for the portion closest to the fourth side S4 of the semiconductor layer 40.

[0198] In a plan view, in order to connect the first gate electrode 19 and the first gate conductor 15, the first gate wiring 42 may be provided on the extension line of the first gate trench 17. Similarly, in order to connect the second gate electrode 29 and the second gate conductor 25, the second gate wiring 52 may be provided on the extension line of the second gate trench 27. Therefore, in the case where the first gate trench 17 and the second gate trench 27 extend in a direction orthogonal to the boundary line 90, no adverse condition will occur even if the first gate wiring 42 and the second gate wiring 52 are not provided in the portion closest to the fourth side S4 of the semiconductor layer 40.

[0199] According to the above structure, the first gate wiring 42 and the second gate wiring 52 are not provided in the portion closest to the fourth side S4 of the semiconductor layer 40 , and the first active region 112 and the second active region 122 can be expanded accordingly, so that the on-resistance of the semiconductor device 1 can be reduced.

[0200] exist Fig.13In the semiconductor device 1 shown in FIG. 1 , the first gate trench 17 extends in a direction parallel to the boundary line 90 in a plan view. In this case, the first gate wiring 42 may be provided to surround the first source electrode 11 except for the portion closest to the first side S1 of the semiconductor layer 40. Fig.13 In the illustrated configuration, the second gate trench 27 extends in a direction parallel to the boundary line 90 in a plan view. In this case, the second gate wiring 52 may be provided to surround the second source electrode 21 except for a portion closest to the second side S2 of the semiconductor layer 40 .

[0201] According to the above structure, the first gate wiring 42 and the second gate wiring 52 are not respectively arranged at the portion closest to the first side S1 of the semiconductor layer 40 and the portion closest to the second side S2 of the semiconductor layer 40, and the first active area 112 and the second active area 122 can be expanded accordingly, so that the on-resistance of the semiconductor device 1 can be reduced.

[0202] In addition, the semiconductor device 1 may also be Fig.14 As shown, in a plan view, the first connection region connecting the first Zener diode 43 and the first source electrode 11 has a portion that overlaps only with an edge of the outer periphery of the first gate electrode region G1, where the first gate electrode region G1 is opposite to the first source electrode 11 and is parallel to the direction in which the first gate trench 17 extends.

[0203] Similarly, it can also be arranged that, in a planar view, the second connection region connecting the second Zener diode 53 and the second source electrode 21 has a portion that overlaps only with the edge of the outer periphery of the second gate electrode region G2, where the second gate electrode region G2 and the second source electrode 21 are opposite and parallel to the direction in which the second gate trench 27 extends.

[0204] According to the above structure, in the plan view of the semiconductor layer 40, the first Zener diode 43 and the first source electrode 11 can be connected without interfering with the area where the first gate wiring 42 and the first gate conductor 15 are connected. Similarly, the second Zener diode 53 and the second source electrode 21 can be connected without interfering with the area where the second gate wiring 52 and the second gate conductor 25 are connected.

[0205] Therefore, in a plan view, it is possible to prevent the area of ​​the first active region 112 and the area of ​​the second active region 122 from being reduced, so that the on-resistance of the semiconductor device 1 can be reduced.

[0206] The semiconductor device of one embodiment of the present disclosure has been described above based on the embodiment and comparative examples 1 to 6, but the present disclosure is not limited to the embodiment. As long as it does not deviate from the main purpose of the present disclosure, the embodiment may be modified to obtain a form that can be obtained by a person skilled in the art, and the form constructed by combining the constituent elements in different embodiments and modified examples may also be included in the scope of one or more forms of the present disclosure.

[0207] Industrial Applicability

[0208] A semiconductor device including the vertical MOS transistor of the present invention can be widely used as a device for controlling the conduction state of a current path.

[0209] Description of Reference Numerals

[0210] 1, 2, 3, 4, 5, 6, 7 Semiconductor devices

[0211] 10 transistor (first vertical MOS transistor)

[0212] 11 first source electrode

[0213] Parts 12, 13, 22, 23

[0214] 14 First source region

[0215] 15 First gate conductor

[0216] 16. First gate insulating film

[0217] 17 First gate trench

[0218] 18 First Body Region

[0219] 18a First connecting portion

[0220] 19 first gate electrode

[0221] 20 transistor (second vertical MOS transistor)

[0222] 21 second source electrode

[0223] 24 Second source region

[0224] 25 Second gate conductor

[0225] 26. Second gate insulating film

[0226] 27 Second gate trench

[0227] 28 Second body region

[0228] 28a Second connection portion

[0229] 29 second gate electrode

[0230] 30 Metal Layer

[0231] 32 Semiconductor substrate

[0232] 33 Low concentration impurity layer

[0233] 34 Interlayer insulation layer

[0234] 35 Passivation layer

[0235] 40 Semiconductor layer

[0236] 41 First gate resistance element

[0237] 42 first gate wiring

[0238] 43 First Zener diode

[0239] 44 First EQR

[0240] 51 Second gate resistance element

[0241] 52 Second gate wiring

[0242] 53 Second Zener diode

[0243] 54 Second EQR

[0244] 90 Boundary Line

[0245] 111 first source pad

[0246] 112 First active region

[0247] 119 first gate pad

[0248] 121 second source pad

[0249] 122 Second active region

[0250] 129 Second gate pad

[0251] A1 First Area

[0252] A2 Second Area

[0253] C1 First Control Area

[0254] C2 Second Control Area

[0255] G1 First gate electrode region

[0256] G2 Second gate electrode region

[0257] R1 First resistance element area

[0258] R2 Second resistance element area

[0259] P1 First corner

[0260] P2 Second corner

[0261] N1 First narrow area

[0262] N2 Second narrow area

[0263] D1 First non-access area

[0264] D2 Second non-access area

[0265] S1 Side 1

[0266] S2 Side 2

[0267] S3 Side 3

[0268] S4 Side 4

Claims

1. A semiconductor device of a chip size package type capable of face-down mounting, characterized in that: have: A semiconductor layer including a semiconductor substrate; A first vertical MOS transistor is formed entirely in a first region of the semiconductor layer on the upper surface side of the semiconductor layer; A second vertical MOS transistor is formed entirely in a second region adjacent to the first region in a plan view of the semiconductor layer; and A metal layer formed on the lower surface side of the semiconductor layer and in contact with and connected to the semiconductor substrate; The semiconductor substrate is a common drain region of the first vertical MOS transistor and the second vertical MOS transistor; In the above plan view, the above semiconductor layer is a square; In the above-mentioned plan view, the above-mentioned first area and the above-mentioned second area are arranged in a first direction; In the plan view, a boundary line between the first region and the second region is orthogonal to the first direction and is a straight line that divides the semiconductor layer into two equal parts in area and passes through the center of the semiconductor layer; In the above plan view, the pads provided in the above first region are only one first source pad connected to the first source electrode of the above first vertical MOS transistor and one first gate pad connected to the first gate electrode of the above first vertical MOS transistor; The first vertical MOS transistor has: A first gate resistor element connected to the first gate electrode; The first gate electrode region is a rectangular region that includes the first gate pad in the plan view and is the largest region in a range that does not include the first source electrode or the first gate resistor; and The first resistor region is a rectangular region that includes the first gate resistor in the plan view and is the largest region in a range that does not include the first source electrode or the first gate electrode region. In the plan view, the entire length of one side of the outer periphery of the first gate electrode region and the entire length of one side of the outer periphery of the first resistor region coincide with a portion of a side of the outer periphery of the semiconductor layer that is orthogonal to the boundary line and has the shortest distance to the first gate pad; In the above-mentioned plan view, the outer periphery of the above-mentioned first resistor element region only includes one of the four corners of the outer periphery of the above-mentioned first gate electrode region, which has the shortest distance to the above-mentioned boundary line and the shortest distance to the side of the outer periphery of the above-mentioned semiconductor layer that is orthogonal to the above-mentioned boundary line.

2. The semiconductor device according to claim 1, wherein In the above plan view, the pads provided in the above second region are only one second source pad connected to the second source electrode of the above second vertical MOS transistor and one second gate pad connected to the second gate electrode of the above second vertical MOS transistor; The second vertical MOS transistor has: A second gate resistor element connected to the second gate electrode; The second gate electrode region is a rectangular region that includes the second gate pad in the plan view and is the largest region in the range that does not include the second source electrode or the second gate resistor. as well as The second resistor element region is a rectangular region that includes the second gate resistor element in the plan view and is the largest region in a range that includes neither the second source electrode nor the second gate electrode region. In the plan view, the entire length of one side of the outer periphery of the second gate electrode region and the entire length of one side of the outer periphery of the second resistor region coincide with a portion of a side of the outer periphery of the semiconductor layer that is orthogonal to the boundary line and has the shortest distance to the second gate pad; In the above-mentioned plan view, the outer periphery of the above-mentioned second resistor element region includes only one corner of the outer periphery of the above-mentioned second gate electrode region, which has the shortest distance to the above-mentioned boundary line and has the shortest distance to the side of the outer periphery of the above-mentioned semiconductor layer that is orthogonal to the above-mentioned boundary line; In the above-mentioned plan view, the above-mentioned second source pad, the above-mentioned second gate pad, the above-mentioned second gate electrode region and the above-mentioned second resistor element region are configured to be in a linear symmetrical relationship with the above-mentioned first source pad, the above-mentioned first gate pad, the above-mentioned first gate electrode region and the above-mentioned first resistor element region, respectively, with the above-mentioned boundary line as the symmetry axis.

3. The semiconductor device according to claim 2, wherein: In the plan view, the entire length of one side of the outer periphery of the first resistor region coincides with a portion of the boundary line.

4. The semiconductor device according to claim 2, wherein: In the plan view, the entire length of one side of the outer periphery of the first gate electrode region coincides with a portion of a side of the outer periphery of the semiconductor layer that is parallel to the boundary line.

5. The semiconductor device according to claim 3 or 4, characterized in that In the plan view, the first gate electrode region and the first resistor element region are added together to form a first control region; In the plan view, of the two sides parallel to the boundary line in the outer periphery of the semiconductor layer, the side with the shortest distance to the first gate pad is set as the first side, and the other side opposite to the first side is set as the second side; In the plan view, of the two sides of the outer periphery of the semiconductor layer that are orthogonal to the boundary line, the side with the shortest distance to the first gate pad is set as the third side, and the other side opposite to the third side is set as the fourth side; In the plan view, the length of the portion where the outer periphery of the first control area coincides with the third side is half the length of the third side; In the plan view, the length of a portion where the outer periphery of the first control region coincides with the outer periphery of the semiconductor layer is the longest at a portion where the outer periphery of the first control region coincides with the third side.

6. The semiconductor device according to claim 4, wherein: In the plan view, the outer periphery of the first source electrode is longest in a portion closest to the boundary line.

7. The semiconductor device according to claim 5, wherein: In the plan view, in the first region, a first gate trench formed at a depth from the upper surface of the semiconductor layer to a portion of the semiconductor layer and a first gate wiring connected to the first gate electrode are formed; In the plan view, the first gate trench extends in a direction orthogonal to the boundary line; In the plan view, the first gate wiring is provided so as to surround the first source electrode except for a portion closest to the fourth side.

8. The semiconductor device according to claim 5, wherein: In the plan view, in the first region, a first gate trench formed at a depth from the upper surface of the semiconductor layer to a portion of the semiconductor layer and a first gate wiring connected to the first gate electrode are formed; In the above plan view, the above first gate trench extends in a direction parallel to the above boundary line; In the plan view, the first gate wiring is provided so as to surround the first source electrode except for a portion closest to the first side.

9. The semiconductor device according to claim 5, wherein: In the plan view, in the first region, a first gate trench formed at a depth from the upper surface of the semiconductor layer to a portion of the semiconductor layer and a first Zener diode connected to the first gate electrode and the first source electrode are formed; In the plan view, the first connection region connecting the first Zener diode and the first source electrode overlaps only with a side of the outer periphery of the first gate electrode region that is opposite to the first source electrode and parallel to the direction in which the first gate trench extends.

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