Edge capacitive coupling for quantum chips

Abstract

A quantum computing chip device provides edge-based capacitive in-chip connections. The first chip includes a first signal line having a distal end located near or on an edge of the first chip and a proximal end located away from the edge of the first chip. The second chip includes a second signal line having a distal end located near or on an edge of the second chip and a proximal end located away from the edge of the second chip. The first signal line and the second signal line are configured to conduct signals. The second signal line of the second chip is disposed to align with the first signal line of the first chip to form a capacitive bus connection.

Description

Background Art Technical Field

[0001] The present disclosure relates generally to electrical devices, and more particularly to edge capacitive coupling for quantum chips.

[0002] Description of Related Technology

[0003] Quantum computing chips are typically larger than those used in conventional CMOS electronics. At some point, the ability to manufacture and produce larger and larger quantum chips becomes difficult. At this point, in order to increase the size of the quantum device, it is desirable to connect individual quantum chips together to effectively form a larger device. When two qubits are connected together, there is a requirement to maintain the qubit state between the two qubits. However, qubit circuits are very susceptible to picking up interference or some other undesirable signal from the environment. In addition, the connection between qubits should have low loss. In this case, the "loss" is typically characterized by the frequency range of the qubit and the associated resonant structure on the qubit chip, which can be, for example, on the order of several gigahertz.

[0004] In electrical connections where dielectrics are present, the loss tangents of commonly used dielectric materials are often so lossy in nature that their use in quantum computing systems will destroy the quantum states in the qubit chain. -3 The loss tangent of the dielectric material and the resonators that are closely connected to the qubits and quantum devices operate in the gigahertz range, essentially limiting device operation to about microseconds before energy is dissipated and the qubit state is lost between the qubit connections. In practical terms, a suitable dielectric material would need to have a loss tangent of 10-6 or 10 -7 Loss tangents of the order of 10000 are needed for qubit connections, but such dielectric materials are scarce and their availability and use are impractical. Therefore, there are limited material choices available for constructing qubit electrical connections. Summary of the invention

[0005] According to an embodiment of the present disclosure, a quantum computing chip device is provided. The quantum computing chip device includes a first chip. The first chip includes a first signal line. The first signal line includes a distal end located near or on an edge of the first chip and a proximal end located away from the edge of the first chip. The quantum computing chip device also includes a second chip. The second chip includes a second signal line. The second signal line includes a distal end located near or on an edge of the second chip and a proximal end located away from the edge of the second chip. The second signal line of the second chip is arranged to align with the first signal line of the first chip to form a capacitive bus connection. The first signal line and the second signal line are configured to conduct signals. The arrangement of the first signal line of the first chip relative to the second signal line of the second chip provides an improvement in chip-to-chip coupling in the quantum computing device. By using edge-based coupling, indirect signal connection is made through a capacitive field generated by the first signal line and the second signal line. The edge-based capacitive coupling arrangement increases the number of qubits transmitted between quantum computing elements in the system, which increases the quantum computing efficiency of the system.

[0006] In an embodiment that may be combined with the preceding embodiment, a distal end of the first signal line is spaced from an edge of the first chip by substrate material. By allowing some substrate material to be between the signal line and the chip edge, a guaranteed spacing is provided between the signal lines of the cooperating chips forming a capacitive-based coupling. The physical spacing prevents unintentional electrical connections between the chips from occurring, which could potentially lose qubits in intra-chip connections.

[0007] According to an embodiment of the present disclosure, a quantum computing chip is provided. The quantum computing chip includes a substrate. The substrate includes a first end and a second end. The quantum computing chip also includes a first superconducting metal signal line. The first superconducting metal line includes a first end located between the first end of the substrate and the second end of the substrate. The second end of the superconducting metal line is located on the edge of the second end of the substrate. The quantum computing chip also includes a second superconducting metal signal line. The second superconducting metal signal line includes a first end located between the first end of the substrate and the second end of the substrate. The second end of the second superconducting metal signal line is located close to the edge of the second end of the substrate. The first superconducting metal signal line and the second superconducting metal signal line are configured to generate a capacitive field. This embodiment improves intra-chip connections in quantum computing applications by creating an edge-based capacitive field for conducting signals. Edge-based capacitive signals allow adjacent chips to transmit signals to each other, even if the chips are part of generally incompatible technologies that are traditionally not connected to each other at the intra-chip level.

[0008] In an embodiment that may be combined with the preceding embodiment, the second end of the first superconducting metal signal line and the second end of the second superconducting metal signal line are positioned in a route extending from a top surface of the substrate, over an edge of the second end of the substrate, and over a side wall of the second end of the substrate through which the signal is routed.

[0009] According to an embodiment of the present disclosure, a method for manufacturing a quantum computing device is provided. The method includes forming a chip substrate. One or more signal lines of superconducting metal are formed on the top surface of a first chip substrate, close to or in contact with the edge of the top surface of the first chip substrate. A second chip substrate is formed. One or more signal lines of superconducting metal are formed on the top surface of a second chip substrate, close to or in contact with the edge of the second top surface of the second chip substrate. The first distal end of one or more first signal lines is positioned near the second distal end of one or more second signal lines. When a signal passes through one or more first signal lines or one or more second signal lines, one or more first signal lines and one or more second signal lines form a bus connection based on capacitance. The method describes an improvement over current manufacturing methods because other methods are typically designed for current connections, the yield of which is a challenge to test before cutting chip dies. Discontinuities and other defects in current-based lines cannot be tested until after the chip is cut. Since the integrity of the signal line is independent of other signal lines, the capacitance-based signal lines formed in the above embodiments can be pre-tested before the chip is cut.

[0010] In an embodiment that may be combined with the preceding embodiments, the method includes forming a first conductive bump on the one or more first signal lines, and forming a second conductive bump on the one or more second signal lines. The first conductive bump and the second conductive bump form a capacitive-based bus connection. Typically, bumps are used only as physical connection points for wires or traces, or as spacing features to create gaps between different material layers. As can be appreciated, the bumps of the present disclosure can provide a dual function as spacers to adjacent modules while providing an edge-based capacitive connection.

[0011] The technology described herein can be implemented in a variety of ways. Example implementations are provided below with reference to the following figures. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings are illustrative embodiments. They do not show all embodiments. Additionally or alternatively, other embodiments may be used. Details that may be obvious or unnecessary may be omitted to save space or for more effective description. Some embodiments may be implemented with additional components or steps and / or without all components or steps shown. When the same number appears in different drawings, it refers to the same or similar components or steps.

[0013] Figure 1 is a schematic side view of a quantum computing device with an edge-based capacitive connection between a pair of quantum computing modules according to one embodiment.

[0014] Figure 2Ais a side, top perspective view of an interposer with edge-based capacitors for use in a quantum computing device, according to one embodiment.

[0015] Figure 2B yes Figure 2A Top view of the adapter board.

[0016] Figure 3A is a side, top perspective view of an interposer with edge-based capacitors for use in a quantum computing device according to another embodiment.

[0017] Figure 3B yes Figure 3A Top view of the adapter board.

[0018] Figure 3C According to a manufacturing process in one embodiment Figure 3B Top view of an interposer in which the capacitor plates are cut in half by forming grooves.

[0019] Figure 4A is a side, top perspective view of an interposer with edge-based capacitors for use in a quantum computing device, according to one embodiment.

[0020] Figure 4B yes Figure 4A Top view of the adapter board.

[0021] Figure 5A is a side, top perspective view of an interposer with edge-based capacitors and standoffs for use in a quantum computing device, according to one embodiment.

[0022] Figure 5B Is to use two Figure 5A A top view of the interposer board showing the connections for the quantum computing device.

[0023] Fig. 6A is a side, top perspective view of an interposer with edge-based capacitors and capacitive bumps for use in a quantum computing device according to one embodiment.

[0024] Figure 6B Is to use two Fig. 6A A top view of the interposer board showing the connections for the quantum computing device.

[0025] Fig. 7A is a side, top perspective view of an interposer with edge-based capacitors and coupling pads for use in a quantum computing device according to one embodiment.

[0026] Figure 7B Is to use two Fig. 7A A top view of the interposer board showing the connections for the quantum computing device. DETAILED DESCRIPTION

[0027] Overview

[0028] In the following detailed description, many specific details are set forth by way of example in order to provide a thorough understanding of the relevant teachings. However, it should be understood that the present teachings may be practiced without these details. In other examples, well-known methods, procedures, components and / or circuits have been described at a relatively high level without details in order to avoid unnecessarily obscuring aspects of the present teachings.

[0029] In one aspect, spatially relative terms, such as "front", "rear", "top", "bottom", "under", "below", "lower", "above", "upper", "side", "left", "right", etc., are used with reference to the orientation of the accompanying drawings being described. Since the components of the embodiments of the present disclosure can be positioned in a plurality of different directions, the directional terms are used for illustrative purposes and are by no means limiting. Therefore, it should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figure is flipped, an element described as being "below" or "below" other elements or features will be oriented as being "above" other elements or features. Therefore, for example, the term "below" can include orientations above as well as below. The device can be oriented in other ways (rotated 90 degrees or viewed or referenced in other directions), and the spatially relative descriptors used herein should be interpreted accordingly.

[0030] As used herein, the terms "lateral," "planar," and "horizontal" describe an orientation parallel to a first surface of a chip or substrate.

[0031] As used herein, the term “vertical” describes an orientation that is arranged perpendicular to a first surface of a chip, a chip carrier, a chip substrate or a semiconductor body.

[0032] As used herein, the terms "coupled" and / or "electrically coupled" do not mean that elements must be directly coupled together - intermediate elements may be provided between the "coupled" or "electrically coupled" elements. In contrast, if an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intermediate elements. The term "electrically connected" refers to a low-ohmic electrical connection between elements that are electrically connected together.

[0033] Although the terms first, second, etc. can be used to describe various elements here, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the exemplary embodiment, the first element can be referred to as the second element, and similarly, the second element can be referred to as the first element. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items.

[0034] Example embodiments are described herein with reference to cross-sectional views that are schematic representations of idealized or simplified embodiments (and intermediate structures). Thus, variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, the regions shown in the figures are schematic in nature, and their shapes do not necessarily illustrate the actual shape of regions of the device and do not limit the scope. It should be understood that the drawings and / or drawings attached to the present disclosure are exemplary, non-limiting, and are not necessarily drawn to scale.

[0035] It should be understood that other embodiments may be used and structural or logical changes may be made without departing from the spirit and scope defined by the claims. The description of the embodiments is not restrictive. In particular, the elements of the embodiments described below may be combined with elements of different embodiments.

[0036] With reference to the accompanying drawings, embodiments of the subject technology provide electrical connections in quantum computing circuits. When a signal propagates along a readout chain in a quantum computing circuit, the subject electrical structure maintains the qubit state. In an exemplary embodiment, a quantum computing device of the subject technology uses capacitive coupling on the edge of a chip or module in a circuit to provide a bus connection between different circuit elements. The capacitor structure disclosed herein can use a superconducting wire that is positioned close to or on the edge surface of an adjacent chip or module. When placed close to each other, the superconducting wire (one or more) from one chip produces a capacitive relationship with the superconducting wire (one or more) of an adjacent chip. As will be appreciated, the dielectric features in this structure provide the quality factor required to transmit the qubit output between circuit elements while maintaining the integrity of the qubit state in the output.

[0037] See now Figure 1, a pair of quantum computing modules 100 illustrating the subject technology are shown. Quantum computing modules 100 can be part of a larger quantum computing system (not shown), and in some embodiments, can represent a quantum computing device, because a circuit can be formed between computing elements on one module 100, and the output of the circuit is transmitted to a second module 100. In a general embodiment, quantum computing module 100 includes a transfer board chip 110, a quantum processing unit (QPU) or a central processing unit (CPU) 120. In a QPU, there can be a plurality of interconnected qubits. QPU / CPU 120 can be coupled to transfer board chip 110. Signals from QPU / CPU 120 can be transmitted to transfer board chip 110 through a connection layer 130. Transfer board chip 110 includes substrate 140. In some embodiments, substrate 140 can be, for example, silicon, sapphire, magnesium oxide, or quartz, however, other materials can be used depending on the application. One or more signal lines 150 are located on or near the edge of one substrate 140 and are aligned with the signal lines 150 (also located on or near the edge) of the second substrate 140 to create a capacitive bus connection shared between the first and second adapter plates 110. The signal lines 150 define capacitor elements for each cooperating adapter plate 140. Typically, the signal lines 150 use superconducting metals to form superconducting conductive containers. In some embodiments, the signal lines 150 of each module 100 can be separated by air to provide a vacuum gap. The capacitive bus connection of the quantum computing device has a low loss tangent because it avoids the use of dielectrics with poor quality factors. Therefore, signals from one QPU / CPU 120 can be transmitted to a second QPU / CPU 120 with the qubit state intact.

[0038] In the following, Figure 2A / Figure 2B-Figure 7A / Figure 7B Various contemplated embodiments of providing edge-based capacitive connections between quantum computing modules 100 are shown. Like elements use like reference numerals updated by the sequence of figure numbers. For example, chip 110 will be Figure 2A / Figure 2B It is referred to by the number "210" in Figure 3A / Figure 3B In the 310, etc. Figure 1 The substrate 140 in Figure 2A / Figure 2B The lieutenant general is called "240". Figure 3A / Figure 3B140 (etc.), and so on. Unless otherwise noted, an element described in one embodiment and figure may be the same element having the same structure in a subsequent figure even if it uses different reference numerals for the described embodiment. Thus, some elements that are common in different embodiments may not be repeatedly described or referenced. In addition, references to the "proximal end" should be considered to be on the side of the structure away from the mating surface or end of the substrate 140 (etc.). References to the "distal end" should be considered to be the end closest to the mating surface in the structure shown.

[0039] Reference now Figure 2A and 2B , shows an interposer chip 210 according to an embodiment. The interposer chip 210 may include a groove etched from the substrate 240 and lined with a superconducting metal that defines a capacitor signal line 250 element. The superconducting metal fills the groove and extends to the interior, below the top surface of the substrate 240. In some embodiments, the groove may be filled with a dielectric if desired. In the embodiment shown, the groove may be positioned so that the signal line 250 terminates at an edge 285 close to but separated from an end face 280 of the substrate 240. The end face 280 may be a sidewall of the chip 210. The end face 280 may be considered a mating surface, which in the present application will face the opposing mating surface of an adjacent interposer chip 210. Figure 1 Reference may be made to an example showing mating surfaces of the relative chips 110 facing each other to provide a capacitive connection. The chip 210 may be cut and then possibly polished so that the groove is placed close to the edge 285 of the substrate 240. In some embodiments, the substrate 240 may be a high-quality single crystal material. Some substrate materials may keep the distal end of the buffer groove from the mating surface 280, thereby providing a certain guaranteed spacing of the distal end of the groove from the edge 285. In some embodiments, the capacitor pad 255 may be formed on the distal end of the groove using a superconducting metal. The capacitor pad 255 may be formed by a liner in the groove, and the outer portion of the liner is arranged to face the mating surface 280 of the adjacent chip 210. The substrate material may be present between the capacitor pad 285 and the mating surface 280. The two chips 210 are placed close to each other so that the capacitor pads 285 (or the distal ends of the capacitor 250 lines in the absence of them) face each other, leaving a double gap of the substrate material between the pads. In this embodiment, the substrate 240 material is used as a dielectric feature.

[0040] Reference now Figure 3A , 3B 3C, shows an interposer chip 310 according to an embodiment. The interposer chip 310 is similar to the interposer chip 210 except that a different signal line 350 capacitor structure is used. Figure 3CAs shown, the embodiment describes a chip structure manufactured by creating a trench in a chip die formed with capacitor pads 355 and then cutting through the middle of the trench. A capacitor is then formed by pushing two chip modules together, and the spacing between capacitor pads 355 is defined by the width of the trench. Figure 3B The trenches formed along the lines of the capacitor pads 355 are not shown.

[0041] The interposer chip 310 may include signal lines 350 extending to or protruding through the mating surface 380 such that the superconducting metal is exposed through the mating surface 380. In an embodiment including a capacitor pad 355, the capacitor pad 355 may be flush with or protrude from the mating surface 380. In this embodiment, in addition to the fact that the dicing of the chip 310 may be performed through the grooves, the manufacturing Figure 2A and 2B The structure disclosed in is the same as that disclosed in , so that the final capacitor pad 355 is formed by the liner on the inner wall of the groove. The chip separation from the wafer can be performed by mechanical or laser cutting. The cutting can be through the groove, and the metal liner of the groove is cut in half, and the inner coating is used as the capacitor pad 355. Therefore, the cutting occurs through the groove. Here, the inside of the liner is the "active surface" of the capacitor.

[0042] Figure 4A and 4B Shown with Figure 3A and 3B An embodiment similar to the embodiment shown, except that there are no trenches for forming signal lines 450. In this embodiment, metal is deposited as a layer on the top surface of substrate 440 and patterned over edge 485 of chip 410, covering a portion of mating surface 480, such that the metallization on the top surface is connected to the edge and mating surface metallization.

[0043] Figure 5A and 5B Shown with Figure 4A and 4B The interposer chip 510 includes a signal line 550 of superconducting metal on the top surface and on the edge 585. The interposer chip 510 shown also includes one or more standoffs 560 located on the mating surface 580. When the interposer chip 510 is arranged in a capacitor circuit connecting separate modules, the standoffs 560 define a separation gap between the chip substrates 540. Embodiments may include standoffs 560 on only one interposer 510 or on both interposers 510. When both interposers 510 include standoffs 560, the standoffs 560 from the respective substrates 540 can be aligned with each other so that the length of the standoffs 560 from the respective interposers 510 is taken into account when designing the spacing between the substrates 540 and the composite capacitance in the connection.

[0044] Reference now Fig. 6A and 6B , an interposer 610 similar to interposers 310, 410, and 510 is shown, except that the metallization for the signal line 650 can be deposited only on the top surface of the substrate 640 (and not on the edge 685 or on the mating surface 680). The interposer 610 can include bumps 660 located on the top surface of the substrate 640. The bumps 660 can be metallic (e.g., solder bumps). The bumps 660 are electrically connected to the signal line 650. The bumps 660 can be located on or near the distal end of the signal line 650. When the opposing interposers 610 are positioned close to each other, the bumps 660 cooperate with each other's bumps 660 to form a capacitive field.

[0045] Fig. 7A and 7B Another embodiment of an interposer 710 is shown, which is similar to interposer 610, except that instead of using bumps 660, coupling pads 770 on the top surface of substrate 740 can bridge signal lines 750. Coupling pads 770 can be metal. The distal ends of coupling pads 770 can protrude beyond edge 785 of substrate 740. When a pair of interposers 710 are positioned for electrical connection, the distal ends of the corresponding coupling pads 770 form a capacitive-based coupling of one interposer 710 to the other interposer 710.

[0046] in conclusion

[0047] The description of various embodiments of the present teachings has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements existing in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

[0048] Although the above has described what is considered to be the best state and / or other examples, it should be understood that various modifications may be made therein, and the subject matter disclosed herein may be implemented in various forms and examples, and the teachings may be applied to many applications, only some of which are described herein. The appended claims are intended to claim any and all applications, modifications and variations that fall within the true scope of the present teachings.

[0049] The components, steps, features, objects, benefits, and advantages discussed herein are merely illustrative. None of them, or the discussion related to them, is intended to limit the scope of protection. Although various advantages have been discussed herein, it will be understood that not all embodiments necessarily include all advantages. Unless otherwise indicated, all measurements, values, ratings, positions, sizes, dimensions, and other specifications in this specification, including those set forth in the appended claims, are approximate and not exact. They are intended to have a reasonable range consistent with the functions to which they are related and the customary practices of the field to which they belong.

[0050] Many other embodiments are also contemplated. These include embodiments with fewer, additional and / or different components, steps, features, objects, benefits and advantages. These also include embodiments in which components and / or steps are arranged and / or ordered in different ways.

[0051] Although the foregoing has been described in conjunction with exemplary embodiments, it should be understood that the term "exemplary" is meant only as an example, rather than the best or optimal. Except as immediately stated above, no component, step, feature, object, benefit, advantage, or equivalent is intended or should be construed as being conferred to the public, whether or not stated in the claims, as set forth above.

[0052] It should be understood that, unless a specific meaning is elaborated in addition herein, the terms and expressions used herein have the common meaning consistent with these terms and expressions about their respective investigation and research fields. Relational terms such as first and second etc. can be used only to distinguish one entity or action from another, without requiring or implying any actual such relationship or order between these entities or actions. The terms "include", "comprise" or any other variations thereof are intended to cover non-exclusive inclusions, so that the process, method, article or device comprising a series of elements not only include those elements, but also may include other elements that are not clearly listed or are inherent to such a process, method, article or device. In the absence of further constraints, the element preceded by "one" or "an" does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0053] The abstract of the present disclosure is provided to allow the reader to quickly determine the nature of the technical disclosure. It should be understood that it is not used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing detailed description, it can be seen that in order to make the present disclosure smooth, various features are grouped together in various embodiments. This method of disclosure should not be interpreted as reflecting the intention that the claimed embodiments have more features than the features explicitly recited in each claim. On the contrary, as reflected in the attached claims, the subject matter of the invention lies in less than all the features of a single disclosed embodiment. Therefore, the following claims are hereby incorporated into the specific implementation mode, wherein each claim is independently a subject matter claimed separately.

Claims

1. A quantum computing chip device, comprising: a first chip, the first chip comprising a first signal line, the first signal line comprising a distal end located near or on an edge of the first chip and a proximal end located away from the edge of the first chip; as well as a second chip, the second chip comprising a second signal line, the second signal line comprising a distal end located near or on an edge of the second chip and a proximal end located away from the edge of the second chip, wherein the second signal line of the second chip is arranged to be aligned with the first signal line of the first chip for capacitive bus connection; and The first signal line and the second signal line are configured to conduct signals. 2 . The quantum computing chip device according to claim 1 , wherein the distal end of the first signal line is separated from the edge of the first chip by a substrate material.

3. A quantum computing chip device according to any one of the preceding claims, wherein the first signal line is positioned on a top surface of the first chip, over an edge of the first chip, and to a sidewall mating surface of the first interposer. 4 . The quantum computing chip device according to claim 1 , further comprising a trench in the substrate of the first chip, wherein the first signal line is embedded in the trench.

5. The quantum computing chip arrangement according to any of the preceding claims, further comprising a capacitor pad on a distal end of the first signal line and adjacent to an edge of the first chip. 6 . The quantum computing chip device of claim 5 , wherein the capacitor pad is embedded in a substrate of the first chip and is spaced apart from the edge of the first chip.

7. The quantum computing chip device according to any one of the preceding claims, further comprising a front side of the distal end of the first signal line, wherein the front side of the distal end of the first signal line is exposed through a side wall of the first chip. 8 . The quantum computing chip device according to claim 7 , wherein the front surface of the distal end of the first signal line is flush with the side wall of the first chip.

9. A quantum computing chip arrangement according to any one of the preceding claims, further comprising standoffs on side walls of the first chip.

10. The quantum computing chip arrangement according to any of the preceding claims, further comprising bumps on a top surface of the first chip.

11. The quantum computing chip device according to any one of the preceding claims, further comprising a first bump coupled to the first signal line and arranged to cooperate with a second bump located on the second signal line to provide capacitance.

12. The quantum computing chip device according to any one of the preceding claims, further comprising a metal sheet coupled to the first signal line, wherein the metal sheet protrudes beyond an edge of the first chip and is configured to cooperate with a second metal sheet coupled to the second signal line to provide capacitance.

13. A quantum computing chip, comprising: a substrate including a first end and a second end; a first superconducting metal signal line; as well as The second superconducting metal signal line, The first superconducting metal signal line comprises: a first end located intermediate the first end of the substrate and the second end of the substrate, and a second end positioned on an edge of the second end of the substrate; The second superconducting metal signal line comprises: a first end located intermediate the first end of the substrate and the second end of the substrate, and A second end is positioned proximate to an edge of the second end of the substrate, wherein the first superconducting metal signal line and the second superconducting metal signal line are configured to generate a capacitive field.

14. The quantum computing chip of claim 13, wherein the second end of the first superconducting metal signal line and the second end of the second superconducting metal signal line are positioned in a route extending from a top surface of the substrate, extending over an edge of the second end of the substrate, and extending over a sidewall of the second end of the substrate.

15. The quantum computing chip according to any one of claims 13 to 14, wherein the second end of the first superconducting metal signal line and the second end of the second superconducting metal signal line are exposed through the second end of the substrate.

16. The quantum computing chip according to any one of claims 13 to 15, wherein the first superconducting metal signal line and the second superconducting metal signal line are embedded in the substrate.

17. The quantum computing chip of any one of claims 13 to 16, further comprising one or more standoffs located on the sidewalls of the second end of the substrate.

18. The quantum computing chip of claim 17, wherein the one or more brackets are configured to provide spacing based on a target capacitance in coupling using the quantum computing chip.

19. The quantum computing chip according to any one of claims 13 to 18, further comprising a first conductive bump located on the first superconducting metal signal line and a second conductive bump located on the second superconducting metal signal line, wherein the capacitive field is formed between the first conductive bump and the second conductive bump.

20. The quantum computing chip according to any one of claims 13 to 19, further comprising a metal sheet coupled to the second ends of the first superconducting metal signal line and the second superconducting metal signal line, and wherein one end of the metal sheet protrudes beyond the second end of the substrate.

21. A method of manufacturing a quantum computing device, comprising: forming a first chip substrate; forming one or more first signal lines of superconducting metal on the top surface of the first chip substrate, the first signal lines being close to or in contact with an edge of the top surface of the first chip substrate; forming a second chip substrate; forming one or more second signal lines of the superconducting metal on the top surface of the second chip substrate, the second signal lines being close to or in contact with an edge of the top surface of the second chip substrate; as well as A capacitance-based bus connection is formed between first distal ends of the one or more first signal lines and second distal ends of the one or more second signal lines, and the capacitance-based bus connection is formed when it is determined that a signal passes through the one or more first signal lines or the one or more second signal lines.

22. The method of claim 21, further comprising forming a trench in the first substrate and depositing the superconducting metal into the trench, wherein the trench and deposited superconducting metal define the one or more first signal lines.

23. The method according to any one of the preceding claims 21 to 22, further comprising: depositing a layer of said superconducting metal onto a top surface of a first substrate; as well as The superconducting metal is deposited over an edge of the first substrate and onto a mating surface of the first substrate.

24. The method according to any one of the preceding claims 21 to 23, further comprising: forming a first conductive bump on the one or more first signal lines; as well as A second conductive bump is formed on the one or more second signal lines, wherein the first conductive bump and the second conductive bump form the capacitance-based bus connection.

25. The method according to any one of the preceding claims 21 to 24, further comprising: forming a first conductive sheet connected to the one or more first signal lines and protruding beyond the edge of the top surface of the first chip substrate; as well as A second conductive plate is formed that is connected to the one or more second signal lines and protrudes beyond the edge of the top surface of the second chip substrate, wherein the first conductive plate and the second conductive plate form the capacitance-based bus connection.

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