High-reliability pressure sensor preparation method and pressure sensor
By adopting the double-layer epitaxial process, PN junction isolation technology, metal molybdenum lead pads, electrochemical corrosion method and silicon-silicon bonding process in the pressure sensor, the poor durability and thermal stress problems of traditional pressure sensors in high temperature environments are solved, and higher high-temperature resistance characteristics, reliability and accuracy are achieved.
Patent Information
- Application Number
- CN202510096543.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-21
- Publication Date
- 2025-05-02
AI Technical Summary
Traditional pressure sensors have poor durability in high temperature environments, poor uniformity of pressure-sensitive films, and thermal stress problems exist in silicon-glass anode bonding process, which affects the accuracy and reliability of the sensor.
The double-layer epitaxial process and PN junction isolation technology are used to form an isolation layer and a piezoresistive layer to reduce the temperature impact; the metal molybdenum is used as the lead pad to improve the high temperature resistance characteristics; the pressure-sensitive film is accurately controlled through electrochemical corrosion to improve uniformity; the silicon-silicon bonding process is used to replace the traditional process to solve the problem of thermal expansion coefficient mismatch.
It improves the high temperature resistance characteristics and reliability of the pressure sensor, enhances the uniformity of the pressure-sensitive film and the sensitivity of the device, improves the accuracy of the sensor and the ability to suppress temperature drift and static pressure.
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Figure CN119911870A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present disclosure belong to the technical field of pressure sensors, and particularly relate to a method for preparing a high-reliability pressure sensor and a pressure sensor. Background Art
[0002] Pressure sensors are micro-electromechanical system devices used to measure pressure. Such sensors are widely used in many fields such as automobiles, industrial control, weather monitoring, medical equipment, and consumer electronics. They can convert physical pressure changes into electrical signal outputs, thereby achieving accurate monitoring of the pressure in the environment or system.
[0003] At present, the pressure sensors made by traditional manufacturing processes have limited high temperature resistance, poor uniformity of pressure-sensitive films, and the traditional silicon-glass anodic bonding process has thermal stress problems caused by the mismatch of thermal expansion coefficients between the packaging material and the sensor chip, which affects the accuracy of the sensor and the suppression of temperature drift and static pressure, thereby affecting the reliability of the pressure sensor.
[0004] Therefore, how to solve the above problems has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention
[0005] The embodiments of the present disclosure aim to solve at least one of the technical problems existing in the prior art and provide a method for preparing a high-reliability pressure sensor and a pressure sensor.
[0006] A first aspect of an embodiment of the present disclosure provides a method for preparing a high-reliability pressure sensor, comprising: providing a P-type silicon substrate;
[0007] Using an epitaxial process, an N-type silicon layer is grown on the front surface of the P-type silicon substrate;
[0008] forming an isolation layer on a surface of the N-type silicon layer away from the P-type silicon substrate;
[0009] Using an epitaxial process, forming an N-type silicon piezoresistive layer on a surface of the isolation layer away from the P-type silicon substrate, wherein the N-type silicon piezoresistive layer has a pressure-sensitive region;
[0010] Etching the N-type silicon piezoresistive layer to form piezoresistive strips and silicon conductive wires in the piezoresistive region;
[0011] Forming a protective layer covering the varistor strip and the silicon wire on the surface of the varistor strip;
[0012] Etching the protective layer to form a contact hole exposing the silicon conductive line;
[0013] forming a lead pad electrically connected to the silicon wire in the contact hole;
[0014] forming a back cavity corresponding to the position of the pressure-sensitive area on the back side of the P-type silicon substrate;
[0015] Providing a silicon substrate, and bonding the silicon substrate to the back side of the P-type silicon substrate to encapsulate the back cavity;
[0016] A gauge pressure hole communicating with the back cavity is formed on the silicon substrate.
[0017] Optionally, the isolation layer includes an oxide layer and an insulating layer sequentially stacked on a surface of the N-type silicon layer facing away from the P-type silicon substrate.
[0018] Optionally, the material of the oxide layer includes silicon oxide, wherein the silicon oxide layer is grown on the surface of the N-type silicon layer by a thermal oxidation process.
[0019] Optionally, the material of the insulating layer includes silicon nitride, wherein a silicon nitride layer is formed by depositing the surface of the oxide layer away from the P-type silicon substrate using a low-pressure chemical vapor deposition process.
[0020] Optionally, a chemical vapor deposition process is used to form a protective layer with a thickness of 300-400 nm on the surface of the varistor strip and the silicon wire.
[0021] Optionally, the protective layer is etched using ion beam etching technology to form a contact hole.
[0022] Optionally, a magnetron sputtering process is used to form a molybdenum metal lead pad in the contact hole.
[0023] Optionally, an electrochemical etching process is used to form a back cavity on the back side of the P-type silicon substrate.
[0024] Optionally, a gauge pressure hole is formed on the silicon substrate by using an inductively coupled plasma etching process.
[0025] According to a second aspect of the embodiments of the present disclosure, a high-reliability single crystal silicon pressure sensor is provided. The pressure sensor is prepared according to the method described above.
[0026] The beneficial effects of the embodiments of the present disclosure include:
[0027] 1. The double-layer epitaxial process is adopted, and the isolation layer and PN junction isolation technology are used around the varistor strip to reduce the impact of temperature performance and make the device resistant to high temperature.
[0028] 2. Metal molybdenum is used as the lead pad (Pad). Molybdenum metal has high temperature resistance and improves the operating temperature of the device.
[0029] 3. The back cavity is made by electrochemical etching method, which can achieve precise control of the pressure-sensitive film (pressure-sensitive film), make the pressure-sensitive film uniform, and improve the sensitivity of the device.
[0030] 4. Compared with the traditional silicon-glass anodic bonding process, the silicon-silicon bonding process effectively solves the thermal stress problem caused by the mismatch of thermal expansion coefficients between the packaging material and the pressure sensor, thereby improving the accuracy of the sensor and suppressing the influence of temperature drift and static pressure, thereby improving the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Figure 1 A schematic diagram of a process for preparing a high-reliability pressure sensor according to an embodiment of the present disclosure;
[0032] Figure 2-Figure 12 The present invention is a schematic structural flow chart of a method for preparing a high-reliability pressure sensor according to an embodiment of the present invention.
[0033] In the figure, 1. P-type silicon substrate; 2. N-type silicon layer; 3. isolation layer; 4. N-type silicon piezoresistive layer; 5. varistor strip; 6. protective layer; 7. contact hole; 8. lead pad; 9. back cavity; 10. silicon base; 11. gauge pressure hole. DETAILED DESCRIPTION
[0034] In order to enable those skilled in the art to better understand the technical solution of the present disclosure, the present disclosure is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.
[0035] The following is a further detailed description of the implementation methods of the present application in conjunction with the accompanying drawings and examples. The detailed descriptions and drawings of the following examples are used to illustrate the principles of the present application, but cannot be used to limit the scope of the present application, that is, the present application is not limited to the described embodiments. In the description of the present application, it should be noted that, unless otherwise specified, the meaning of "multiple" is more than two; the orientation or position relationship indicated by the terms "upper", "lower", "left", "right", "inside", "outside", etc. is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. "Vertical" is not vertical in the strict sense, but within the error tolerance range. "Parallel" is not parallel in the strict sense, but within the error tolerance range.
[0036] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.
[0037] like Figure 1-12 As shown, a method for preparing a high-reliability pressure sensor comprises:
[0038] S101 , providing a P-type silicon substrate 1 .
[0039] refer to Figure 2 In some embodiments, the thickness of the P-type silicon substrate 1 is 300um to 600um.
[0040] In a specific example, the thickness of the P-type silicon substrate 1 is 300 um.
[0041] In another specific example, the thickness of the P-type silicon substrate 1 is 600 um.
[0042] In some further embodiments, the thickness of the P-type silicon substrate 1 is 500 um.
[0043] S102 , using an epitaxial process to grow an N-type silicon layer 2 on the front surface of the P-type silicon substrate 1 .
[0044] refer to Figure 3 In some embodiments, a chemical vapor deposition (CVD), molecular beam epitaxy (MBE) or liquid phase epitaxy (LPE) process is used to grow an N-type silicon layer 2 on the front side of a P-type silicon substrate 1 .
[0045] In some embodiments, the thickness of the N-type silicon layer 2 is 10-30 um.
[0046] In a specific embodiment, the thickness of the N-type silicon layer 2 is 10 um.
[0047] In another specific embodiment, the thickness of the N-type silicon layer 2 is 30 um.
[0048] In another specific embodiment, the thickness of the N-type silicon layer 2 is 20 um.
[0049] In the present invention, the N-type silicon layer 2 and the P-type silicon substrate 1 form a PN junction isolation structure, which can effectively perform electrical isolation and reduce the impact of temperature on the performance of the sensor, thereby ensuring the reliability of the pressure sensor.
[0050] S103 , forming an isolation layer 3 on a surface of the N-type silicon layer 2 facing away from the P-type silicon substrate 1 .
[0051] refer to Figure 4 In some embodiments, the isolation layer 3 includes an oxide layer and an insulating layer sequentially stacked on a surface of the N-type silicon layer 2 facing away from the P-type silicon substrate 1 .
[0052] In some embodiments, the material of the oxide layer includes silicon oxide (TOX), wherein the silicon oxide layer is grown on the surface of the N-type silicon layer 2 by a thermal oxidation process, wherein the thermal oxidation process includes dry oxygen oxidation, wet oxygen oxidation or rapid thermal oxidation.
[0053] Specifically, a thermal oxidation treatment is performed on the surface of the first epitaxial N-type silicon layer 2 to generate a 100 nm thick silicon dioxide layer.
[0054] In the present invention, the oxide layer (TOX layer) has an insulating function and can also serve as a surface protection layer to prevent the external environment (such as moisture, pollutants, etc.) from affecting the varistor on the upper layer.
[0055] In some embodiments, the material of the insulating layer includes silicon nitride, wherein a silicon nitride layer is formed by depositing the silicon nitride layer on the surface of the oxide layer away from the P-type silicon substrate 1 using a low pressure chemical vapor deposition (LP CVD) process.
[0056] Specifically, low-pressure chemical vapor deposition is performed on the surface of the oxide layer to form 200 nm thick silicon nitride (SIN) as an insulating layer.
[0057] In the present invention, the silicon nitride layer not only provides additional electrical insulation, but also enhances the mechanical strength and corrosion resistance of the entire structure.
[0058] S104 , using an epitaxial process, an N-type silicon piezoresistive layer 4 is formed on a surface of the isolation layer 3 away from the P-type silicon substrate 1 , wherein the N-type silicon piezoresistive layer 4 has a pressure-sensitive region.
[0059] refer to Figure 5 In some embodiments, a chemical vapor deposition (CVD), molecular beam epitaxy (MBE) or liquid phase epitaxy (LPE) process is used to grow an N-type silicon piezoresistive layer 4 in the pressure-sensitive region of the isolation layer 3 .
[0060] In some embodiments, the thickness of the N-type silicon piezoresistive layer 4 is 1-3 um.
[0061] In a specific example, the thickness of the N-type silicon piezoresistive layer 4 is 1 um.
[0062] In another specific example, the thickness of the N-type silicon piezoresistive layer 4 is 3 um.
[0063] In another specific example, the thickness of the N-type silicon piezoresistive layer 4 is 2 um.
[0064] S105, etching the N-type silicon piezoresistive layer 4 to form a piezoresistive resistor strip 5 and a silicon wire in the piezoresistive region, for details, see Figure 6 .
[0065] In a specific example, a photoresist layer is spin-coated on the N-type silicon piezoresistive layer 4, and a region to be etched is defined on the photoresist layer by photolithography to form a mask pattern. The mask pattern is etched to transfer the mask pattern to the N-type silicon piezoresistive layer 4, and the etching is completed. Finally, the residual photoresist is cleaned to obtain a layer structure having a varistor strip 5 and a silicon wire.
[0066] In another specific example, a hard mask is deposited on the N-type silicon piezoresistive layer 4, and a region to be etched is defined on the hard mask by photolithography to form a mask pattern. The mask pattern is etched to transfer the mask pattern to the N-type silicon piezoresistive layer 4, and the etching is completed. Finally, the remaining hard mask is cleaned to obtain a layer structure having a varistor strip 5 and a silicon wire.
[0067] S106 , forming a protection layer 6 on the surface of the varistor strip 5 to cover the varistor strip 5 and the silicon wire.
[0068] In some embodiments, along a direction perpendicular to the front surface of the P-type silicon substrate 1 , the projections of the protection layer 6 and the isolation layer 3 both cover the projections of the varistor strip 5 and the silicon wire.
[0069] refer to Figure 7 In some embodiments, a chemical vapor deposition (CVD) process is used to form a protective layer 6 with a thickness of 300-400 nm on the surface of the varistor strip 5 and the silicon wire.
[0070] In some embodiments, the material of the protection layer 6 includes silicon nitride.
[0071] In a specific example, the thickness of the silicon nitride layer is 300 nm.
[0072] In another specific example, the thickness of the silicon nitride layer is 400 nm.
[0073] In another specific example, the thickness of the silicon nitride layer is 350 nm.
[0074] S107 , etching the protection layer 6 to form a contact hole 7 exposing the silicon conductive line.
[0075] refer to Figure 8 In some embodiments, the protective layer 6 is etched by ion beam etching (IBE) to form the contact hole 7.
[0076] In a specific example, a photoresist layer is spin-coated on the protective layer 6, and a region to be etched is defined on the photoresist layer by photolithography to form a mask pattern. The mask pattern is etched using an IBE device to transfer the mask pattern to the protective layer 6 to complete the etching. Finally, the remaining photoresist is cleaned to obtain a layer structure with a contact hole 7.
[0077] In another specific example, a hard mask is deposited on the protective layer 6, and a region to be etched is defined on the hard mask by photolithography to form a mask pattern. The mask pattern is etched using an IBE device to transfer the mask pattern to the protective layer 6 to complete the etching. Finally, the remaining hard mask is cleaned to obtain a layer structure with a contact hole 7.
[0078] S108 , forming a lead pad 8 electrically connected to the silicon wire in the contact hole 7 .
[0079] refer to Fig. 9 In some embodiments, a magnetron sputtering process is used to form a molybdenum metal lead pad 8 in the contact hole 7.
[0080] In some embodiments, the thickness of the molybdenum metal lead pad 8 is 1-2 um.
[0081] In a specific example, the thickness of the molybdenum metal lead pad 8 is 1 um.
[0082] In another specific example, the thickness of the molybdenum metal lead pad 8 is 2 um.
[0083] In another specific example, the thickness of the molybdenum metal lead pad 8 is 1.5 um.
[0084] S109, forming a back cavity 9 corresponding to the position of the pressure-sensitive area on the back side of the P-type silicon substrate 1.
[0085] refer to Fig.10 In some embodiments, a back cavity 9 is formed on the back side of the P-type silicon substrate 1 by using an electrochemical etching process.
[0086] Specifically, a groove-shaped area to be etched is defined on the back of the P-type silicon substrate 1 by photolithography technology, and the area to be etched is etched by electrochemical etching process to form a groove-shaped back cavity 9. Further, the bottom wall of the groove-shaped back cavity 9 and the pressure-sensitive area at the corresponding position, the isolation layer 3 and the protective layer 6 form a pressure-sensitive film (also called a strain film or a sensitive film). It can be understood that the bottom wall of the groove-shaped back cavity 9 is spaced and opposite to the silicon substrate 10.
[0087] In the present invention, the back cavity 9 is manufactured by an electrochemical etching process, so that the thickness and uniformity of the sensitive film can be precisely controlled.
[0088] S110, providing a silicon substrate 10, and bonding the silicon substrate 10 to the back side of the P-type silicon substrate 1 to encapsulate the back cavity 9. Fig.11 Specifically, the silicon substrate 10 is bonded to the back side of the P-type silicon substrate 1 by using a high temperature silicon-silicon bonding process.
[0089] S111 , forming a gauge pressure hole 11 communicating with the back cavity 9 on the silicon substrate 10 .
[0090] refer to Fig.12 In some embodiments, an inductively coupled plasma (ICP) etching process is used to form a gauge pressure hole 11 on the silicon substrate 10.
[0091] In a specific example, a photoresist layer is spin-coated on a silicon substrate 10, and a region to be etched is defined on the photoresist layer by photolithography to form a mask pattern. The mask pattern is etched using an ICP device, and the mask pattern is transferred to the silicon substrate 10 to complete the etching. Finally, the residual photoresist is cleaned to obtain a silicon substrate 10 with a gauge pressure hole 11.
[0092] In another specific example, a hard mask is deposited on the silicon substrate 10, and a region to be etched is defined on the hard mask by photolithography to form a mask pattern. The mask pattern is etched by an ICP device to transfer the mask pattern to the silicon substrate 10 to complete the etching. Finally, the remaining hard mask is cleaned to obtain a silicon substrate 10 with a gauge pressure hole 11.
[0093] The beneficial effects of the present invention include: 1. A double-layer epitaxial process is adopted, and an isolation layer 3 and PN junction isolation technology are used around the varistor strip 5, which reduces the influence of temperature and electrostatic performance, so that the device has high temperature resistance and high reliability.
[0094] 2. Metal molybdenum is used as the lead pad 8 (Pad). Molybdenum metal has high temperature resistance and improves the working temperature of the device.
[0095] 3. The back cavity 9 is made by electrochemical etching method, which can achieve precise control of the pressure-sensitive film (pressure-sensitive film), make the pressure-sensitive film uniform, and improve the sensitivity of the device.
[0096] 4. Compared with the traditional silicon-glass anodic bonding process, the silicon-silicon bonding process effectively solves the thermal stress problem caused by the mismatch of thermal expansion coefficients between the packaging material and the pressure sensor, thereby improving the accuracy of the sensor and suppressing the influence of temperature drift and static pressure, achieving high precision of the device.
[0097] According to a second aspect of the embodiments of the present disclosure, a high-reliability single crystal silicon pressure sensor is provided. The pressure sensor is prepared according to the above method.
[0098] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.
Claims
1. A method for preparing a high-reliability pressure sensor, characterized in that: include: Providing a P-type silicon substrate; Using an epitaxial process, an N-type silicon layer is grown on the front surface of the P-type silicon substrate; forming an isolation layer on a surface of the N-type silicon layer away from the P-type silicon substrate; Using an epitaxial process, forming an N-type silicon piezoresistive layer on a surface of the isolation layer away from the P-type silicon substrate, wherein the N-type silicon piezoresistive layer has a pressure-sensitive region; Etching the N-type silicon piezoresistive layer to form piezoresistive strips and silicon conductive wires in the piezoresistive region; Forming a protective layer covering the varistor strip and the silicon wire on the surface of the varistor strip; Etching the protective layer to form a contact hole exposing the silicon conductive line; forming a lead pad electrically connected to the silicon wire in the contact hole; forming a back cavity corresponding to the position of the pressure-sensitive area on the back side of the P-type silicon substrate; Providing a silicon substrate, and bonding the silicon substrate to the back side of the P-type silicon substrate to encapsulate the back cavity; A gauge pressure hole communicating with the back cavity is formed on the silicon substrate.
2. A method for preparing a high-reliability pressure sensor according to claim 1, characterized in that: The isolation layer includes an oxide layer and an insulating layer which are sequentially stacked on a surface of the N-type silicon layer away from the P-type silicon substrate.
3. The method for preparing a high-reliability pressure sensor according to claim 2, characterized in that: The material of the oxide layer includes silicon oxide, wherein the silicon oxide layer is grown on the surface of the N-type silicon layer by using a thermal oxidation process.
4. The method for preparing a high-reliability pressure sensor according to claim 2, characterized in that: The material of the insulating layer includes silicon nitride, wherein a silicon nitride layer is deposited on a surface of the oxide layer away from the P-type silicon substrate by using a low-pressure chemical vapor deposition process.
5. A method for preparing a high-reliability pressure sensor according to claim 1 or 2, characterized in that: A protective layer with a thickness of 300-400 nm is formed on the surface of the varistor strip and the silicon wire by using a chemical vapor deposition process.
6. A method for preparing a high-reliability pressure sensor according to claim 1 or 2, characterized in that: The protective layer is etched by using ion beam etching technology to form a contact hole.
7. A method for preparing a high-reliability pressure sensor according to claim 1 or 2, characterized in that: A magnetron sputtering process is used to form a molybdenum metal lead pad in the contact hole.
8. A method for preparing a high-reliability pressure sensor according to claim 1 or 2, characterized in that: A back cavity is formed on the back side of the P-type silicon substrate by using an electrochemical etching process.
9. A method for preparing a high-reliability pressure sensor according to claim 1 or 2, characterized in that: A gauge pressure hole is formed on the silicon substrate by using an inductively coupled plasma etching process.
10. A high reliability single crystal silicon pressure sensor, characterized in that: The pressure sensor is prepared according to the method according to any one of claims 1-9.