Method for controlling growth of quantum lines or quantum dots
By plating a dielectric film on the back of the substrate and etching and processing, a nanomesh structure is formed to promote the growth of quantum dots and quantum lines, and edge damage and impurity pollution caused by frontal processing of the substrate in the prior art is solved, and the preparation of high-energy sub-dots/quantum lines is realized.
Patent Information
- Application Number
- CN202411911552.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-24
- Publication Date
- 2025-05-02
AI Technical Summary
When processing the epitaxial surface of the substrate on the front surface of the substrate, it is easy to cause edge damage and impurity contamination, resulting in a far different nanostructure performance from the theoretical predicted value, making it difficult to prepare high-performance optoelectronic devices.
The dielectric film is plated on the back of the substrate, and the dielectric film is processed into a nanomesh structure through photolithography etching, so as to form a temperature network without affecting the quality of the front epitaxial layer, and promote the regular preparation of quantum dots and quantum lines.
Through this method, quantum dots/quantum lines with uniform size distribution, high density and good spatial order can be prepared without introducing impurities, so as to improve the performance of optoelectronic devices.
Smart Images
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Abstract
Description
Technical Field
[0001] The present application relates to a method for controlling the growth of quantum wires or quantum dots, and belongs to the field of quantum semiconductor materials. Background Art
[0002] Since the concept of "superlattice" was proposed by L.Esaki and R.Tsu of IBM in the late 1960s, quantum dots, quantum wires and quantum wells of low-dimensional semiconductor materials have become one of the most cutting-edge research fields in nanomaterials science. According to the movement of electrons in the three directions of x, y and z, low-dimensional semiconductor materials can be divided into three categories: zero-dimensional quantum dots, one-dimensional quantum wires, and two-dimensional superlattices and quantum wells. Among them, the movement of electrons in quantum dot materials is restricted in the three directions of x, y and z, and the movement of electrons in quantum wire materials is restricted in two directions. In low-dimensional semiconductor materials, there are excellent properties that are completely different from three-dimensional materials. With the reduction of material dimensions and the reduction of material structure feature sizes (<50nm), quantum size effects, quantum tunneling effects, Coulomb blockade effects, quantum interference effects, multi-body correlation and nonlinear optical effects, as well as surface and interface effects will become more and more obvious, which will reveal new phenomena and new effects unique to nano-semiconductor materials from a deeper level and form the basis of a new generation of quantum devices. For example, micro-nano electronic devices and optoelectronic devices based on quantum effects have extremely important application prospects in future nanoelectronics, photonics, and optoelectronic integration due to their inherent ultra-high speed, ultra-high frequency, ultra-high integration, high efficiency and low power consumption, extremely low threshold current density, extremely high quantum efficiency, extremely high modulation depth, extremely narrow linewidth, high characteristic temperature, and picojoule average power consumption. They are very likely to trigger a new technological revolution and are valued by governments, scientists, and entrepreneurs around the world.
[0003] Since the 1970s, the continuous development, improvement and progress of advanced thin film material growth technologies represented by molecular beam epitaxy (MBE) and metal organic chemical vapor deposition (MOCVD), ultrafine atomic processing and electron beam lithography, and the subsequent development of strain self-assembled semiconductor quantum dots and quantum wire growth technologies have created conditions for the growth, preparation and research of nano-semiconductor materials and quantum devices. At present, the industrial production and preparation technology of superlattice and quantum well materials is very mature, and quantum devices based on it, such as high electron mobility transistors (HEMT), double heterojunction transistors (HBT) and quantum well lasers (QWLD), have been widely used in the fields of optical fiber communication and mobile communication, and have formed a high-tech industry.
[0004] Molecular beam epitaxy (MBE) is essentially a thin film evaporation technology under ultra-high vacuum conditions. The basic principle is to -8In the PDMS system, the substrate and several molecular beam source furnaces are placed relatively to each other, and the various elements and dopant elements of the compound are placed in different spray furnaces respectively, and heated separately so that their molecules (or atoms) are sprayed onto the heated clean substrate surface at a certain thermal motion speed and a certain beam intensity ratio, and interact with the substrate surface (including migration, decomposition, adsorption, bonding and desorption on the surface, etc.), thereby growing a single crystal film along the crystal direction of the substrate. The substrate stage heating is to heat the back of the substrate in the form of thermal radiation, and the spray furnace sprays the molecular beam on the front of the substrate.
[0005] In general semiconductor quantum dot systems, such as InAs / GaAs, the surface density of quantum dots grown without patterning substrate epitaxy is about 10 9 ~10 11 cm 2 However, the size and height of quantum dots in the same system are not uniform, and their distribution standard deviation is very important for the performance of the device. Combining the graphic technology with the self-assembly growth technology makes it easier to obtain quantum dot arrays with uniform size distribution, high density and good spatial order.
[0006] Although the superlattice, quantum well material growth and high spatial resolution etching process can be combined to prepare nano-semiconductor quantum dots and quantum wires, and their shape, density and space can be artificially controlled within the range of the device's spatial resolution to obtain the desired structure, this processing on the front side of the substrate, i.e. the epitaxial surface, will cause edge damage and impurity contamination, resulting in device performance far from the theoretical prediction value, so the nanostructures prepared by this method are often not used to prepare high-performance optoelectronic devices. Summary of the invention
[0007] The present invention proposes to plate a dielectric film on the back of the substrate and process the dielectric film into a nano-mesh structure through photolithography and etching, thereby forming a temperature network on the front without affecting the quality of the front epitaxial layer, and promoting the regular preparation of quantum dots and quantum wires. The advantage of the method described in the present invention is that it will not cause impurity pollution on the front; the temperature network formed on the front affects the atomic chemical reaction activity, diffusion ability, surface migration rate, and atomic activation energy, and thus it is relatively easy to prepare quantum dots / quantum wires with uniform size distribution, high density, and good spatial order.
[0008] The present invention discloses a method for manufacturing a pattern substrate for controlling the growth of quantum wires or quantum dots, comprising the following steps:
[0009] (1) Preparing a GaAs substrate as a substrate, and cleaning and processing the substrate;
[0010] (2) placing the substrate in a deposition device and uniformly depositing a dielectric film on the back side of the substrate;
[0011] (3) uniformly coating a layer of electron beam glue on the back of the substrate;
[0012] (4) directly exposing the photoresist by electron beam exposure to form a grid pattern, wherein the grid spacing is 10 nm to 30 nm and the width of the grid line is 10 nm to 30 nm, and then treating the electron beam glue with a developer;
[0013] (5) evaporating a layer of chromium metal on the surface of the electron beam gel template using electron beam evaporation;
[0014] (6) using a lift-off process to form a grid pattern of chromium metal, wherein the grid spacing is 10-30 nm and the width of the grid line is 10-30 nm, thereby forming a chromium metal template;
[0015] (7) performing an etching step in an etching device, using the chromium metal template as a mask to etch the dielectric film;
[0016] (8) Use a dechroming solution to remove chromium metal.
[0017] The deposition in step (2) is carried out by chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD); the dielectric film is one or more of SiO2 and Si3N4; the thickness of the deposited layer is 0.5-3 μm, preferably 0.5-2 μm.
[0018] The electron beam gel in step (3) should be determined according to the desired nano-network structure characteristics; the thickness of the electron beam gel is 100-500nm, preferably 100-200nm.
[0019] The pattern in step (4) is one or more of a grid and a line; its thickness or diameter is 10-30 nm, preferably 10-20 nm.
[0020] The etching in step (5) is dry etching or wet etching; preferably, the dry etching is inductively coupled plasma etching.
[0021] The quantum dot density of the device prepared by the method is 5×10 10 / cm 2 ~9×10 10 / cm 2 .
[0022] Beneficial technical effects of the present invention: Compared with other methods of making structures on the front side for the preparation of quantum dots / quantum wires (affecting the quality of the epitaxial layer), the present invention can form a nano-dielectric layer network structure on the back side of the substrate through simple processes such as dielectric film plating, photolithography and etching, resulting in different temperature distributions on the front side, thereby promoting the preparation of quantum dots / quantum wires.
[0023] A dielectric film is deposited on the back of the substrate and processed by photolithography and etching to form a nano-mesh structure, thereby forming a temperature network on the front without affecting the quality of the front epitaxial layer, thereby facilitating the preparation of quantum dots and quantum wires. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 : Electron beam gel template with nano-network structure prepared by electron beam exposure;
[0025] Figure 2 : Temperature grid on the front side of the patterned substrate during the growth of simulated quantum wires or quantum dots;
[0026] Figure 3 : Schematic diagram of using patterned substrate to prepare quantum wires or quantum dots;
[0027] Figure 4 : Schematic diagram of quantum dot distribution. DETAILED DESCRIPTION
[0028] Embodiment 1:
[0029] A pattern substrate for controlling the growth of quantum wires or quantum dots and a method for making the same, comprising the following steps:
[0030] (1) preparing a GaAs substrate as a substrate, and cleaning and treating the substrate with acetone and isopropanol;
[0031] (2) A Si3N4 dielectric film was deposited on the back of the substrate using a plasma enhanced chemical vapor deposition (PECVD) process. The process gases and their flow rates were SiH4 10 sccm, NH3 100 sccm, N2 700 sccm, respectively. The process temperature was 250°C, the RF power was 50 W, and the Si3N4 dielectric film thickness was 1500 nm.
[0032] (3) a 300 nm thick layer of ZEP520 electron beam glue is uniformly coated on the back of the substrate;
[0033] (4) Electron beam exposure is used to directly expose the electron beam glue to form the required nano-mesh pattern, and then C7H 14 Treat with O2 developer to form an electron beam gel template;
[0034] (5) Use electron beam evaporation to evaporate a layer of chromium metal on the surface of the electron beam glue template with a thickness of 100 nm, a voltage of 6 KV, and an electron beam current of 60 mA.
[0035] (6) performing a lift-off process at 80° C. using an NMP stripping solution to form a chromium metal grid pattern, wherein the grid spacing is 30 nm and the width of the grid line is 30 nm, thereby forming a chromium metal template;
[0036] (7) The etching step is performed in an inductively coupled plasma etching device, and the process gases and their flow rates are SF6 35 sccm, C4F8 15 sccm, O2 8 sccm, RF power 50 W, and inductively coupled ICP power 800 W.
[0037] (8) Use a dechroming solution to remove chromium metal.
[0038] Embodiment 2:
[0039] A pattern substrate for controlling the growth of quantum wires or quantum dots and a method for making the same, comprising the following steps:
[0040] (1) preparing a GaAs substrate as a substrate, and cleaning and treating the substrate with acetone and isopropanol;
[0041] (2) A SiO2 dielectric film was deposited on the back of the substrate using a plasma enhanced chemical vapor deposition (PECVD) process. The process gases and their flow rates were SiH4 12 sccm, N2O 480 sccm, N2 240 sccm, respectively. The process temperature was 350°C, the RF power was 50 W, and the SiO2 dielectric film thickness was 1200 nm.
[0042] (3) a 180 nm thick layer of ZEP520 electron beam glue is uniformly coated on the back of the substrate;
[0043] (4) directly exposing the electron beam glue by electron beam exposure to form the desired nano-mesh pattern, and then treating it with C7H14O2 developer to form an electron beam glue template;
[0044] (5) Use electron beam evaporation to evaporate a layer of chromium metal on the surface of the electron beam glue template with a thickness of 50 nm, a voltage of 6 KV, and an electron beam current of 60 mA.
[0045] (6) performing a lift-off process at 80° C. using an NMP stripping solution to form a chromium metal grid pattern, wherein the grid spacing is 25 nm and the width of the grid line is 25 nm, thereby forming a chromium metal template;
[0046] (7) The etching step is performed in an inductively coupled plasma etching device, and the process gases and their flow rates are SF640 sccm, C4F8 15 sccm, Ar 10 sccm, O2 8 sccm, RF power 60 W, and inductively coupled ICP power 800 W.
[0047] (8) Use a dechroming solution to remove chromium metal.
[0048] The above contents are merely examples and explanations of the concept of the present invention. Those skilled in the art may make various modifications or additions to the specific embodiments described or replace them in a similar manner. As long as they do not deviate from the concept of the invention or exceed the scope defined by the present invention, they shall all fall within the protection scope of the present invention.
Claims
1. A method for manufacturing a patterned substrate for controlling the growth of quantum wires or quantum dots, comprising the following steps: (1) Preparing a GaAs substrate as a substrate, and cleaning and processing the substrate; (2) placing the substrate in a deposition device and uniformly depositing a dielectric film on the back side of the substrate; (3) uniformly coating a layer of electron beam glue on the back of the substrate; (4) directly exposing the photoresist by electron beam exposure to form a grid pattern, wherein the grid spacing is 10 nm to 30 nm, and the width of the grid line is 10 nm to 30 nm, and then treating the electron beam glue with a developer to form an electron beam glue template; (5) evaporating a layer of chromium metal on the surface of the electron beam gel template using electron beam evaporation; (6) using a lift-off process to form a grid pattern of chromium metal, wherein the grid spacing is 10-30 nm and the width of the grid line is 10-30 nm, thereby forming a chromium metal template; (7) performing an etching step in an etching device, using the chromium metal template as a mask to etch the dielectric film; (8) Use a dechroming solution to remove chromium metal.
2. The method according to claim 1, characterized in that The deposition in step (2) is carried out by chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD).
3. The method according to claim 1, characterized in that The dielectric film in step (2) is one or more of SiO2 and Si3N4.
4. The method according to claim 1, characterized in that The thickness of the deposited dielectric layer in step (2) is 0.5-3 μm, preferably 0.5-2 μm.
5. The method according to claim 1, characterized in that The selection of the electron beam colloid in step (3) should be determined according to the desired nano-network structure characteristics; the thickness of the electron beam colloid is 100-500nm, preferably 100-200nm.
6. The method according to claim 1, characterized in that The pattern in step (4) is one or more of a grid and a line, and its thickness or diameter is 10-30 nm, preferably 10-20 nm.
7. The method according to claim 1, characterized in that The thickness of the chromium metal evaporated by electron beam in step (4) is 30-200 nm, preferably 30-100 nm.
8. The method according to claim 1, characterized in that The etching in step (5) is dry etching or wet etching; preferably, the dry etching is inductively coupled plasma etching.
9. A device prepared according to the method according to any one of claims 1 to 8, characterized in that The density of quantum dots or wires is 5×10 10 / cm 2 ~9×10 10 / cm 2 .