System and method for accelerating IST power-on self-test of vehicle-mounted chip and storage medium

Abstract

The invention discloses an I ST power-on self-test acceleration system and method for a vehicle-mounted chip and a storage medium. The method has the advantages that a mechanism that a Logi c BIST test can be carried out after power-on reset is released is utilized, meanwhile, the reset of the PLL is released, the PLL reads adjusted clock parameters from eFuse and can quickly enter a Lock clock stable state, the PLL carries out Logic BIST Pattern test at the same time, and due to the fact that the PLL is an analog circuit and is isolated from a digital circuit of the LBIST in design, the test result of the LBIST cannot be influenced. Through the improvement, the MBIST test can be quickly entered without the need of starting PLL clock parameter configuration to wait for clock locking after the LBIST Pattern test is finished, and the MBIST test is started after the maximum time of a PLL Lock is usually waited in the original mode of configuring the PLL with the Pattern. By means of the improvement mode, the intermediate waiting time of IST can be greatly shortened.

Description

Technical Field

[0001] The present invention relates to the technical field of vehicle-mounted control systems, and in particular to a system, method and storage medium for accelerating the IST power-on self-test of a vehicle-mounted chip. Background Art

[0002] With the increasing popularity of intelligent driving and new energy vehicles, the safety of vehicle systems is of vital importance. Different automotive chips in vehicle systems have different safety levels according to their functions and uses. ISO26262 defines safety levels according to the characteristics of the car, and functional safety design is particularly important. IST (In-System-Test) is a common functional safety protection method for power-on self-test. It has been widely used in vehicle chips. It can complete the internal detection test of the chip within the specified time during each chip startup process, and determine whether to start the chip based on the test results.

[0003] There are many ways to implement IST. The common way is to use ROM Code to place the functional point pattern to be tested in the storage space of ROM. During the chip startup process, the IST control logic reads the pattern from the ROM space and sends it to the unit to be tested in a certain sequence. The test results are sent to the system control unit through the interface, such as the soc system. IST testing is divided into LBIST and MBIST testing, which respectively detect digital logic and memory failures of the chip during functional use. Generally, the pattern is designed according to the physically implemented Block hierarchy. There are as many groups of patterns as there are blocks to cover the circuit test of the entire chip. In the case of a large chip scale, it will take a long time to complete the testing of all patterns, because the pattern is usually tested linearly. In the design of automotive chips, there are generally requirements for the startup time of the chip. This means that the more patterns there are, the longer the test time will be. Under the fixed startup time requirement, it will inevitably affect the time required for the startup of subsequent functional modules. The LBIST of IST performs digital logic tests under a low-frequency clock, while the MBIST needs to be tested under a high-frequency clock. Therefore, MBIST needs to wait for the on-chip PLL to lock before it can test the corresponding pattern. The PLL is generally configured by extracting the clock parameters of the pattern. This means that after the LBIST test is completed, the PLL is made to work at the target frequency by reading the configuration parameters of the ROM Code. The PLL Lock time itself takes a long time, so the entire IST process test takes a long time to complete. Summary of the invention

[0004] In order to solve the above problems of the prior art solutions, the present invention shortens the IST test time through system process control to reduce the time overhead of power-on self-test.

[0005] In order to achieve the above object, the present invention adopts the following technical solution: a method for accelerating the IST power-on self-test of an on-board chip, comprising the following steps:

[0006] S1, after the chip is powered on, wait for the power supply to stabilize, then release the power-on-reset, and reset is released;

[0007] S2, read the configuration parameters from the eFuse, mainly including the enable signal of the IST test pattern and the high-frequency clock parameters after PLL adjustment. At this time, the control of the IST test process is started, and the PLL clock parameters are configured at the same time, waiting for the PLL clock to enter the locked state;

[0008] S3, start the IST test process, first determine whether to perform LBIST test, if not, then enter the test judgment process of whether MBIST is needed, otherwise start the LBIST test of each Block, wait for the test to be completed and also enter the test judgment process of whether MBIST is needed;

[0009] S4, enter the MBIST test judgment process. If it is determined that the MBIST test is not required, the IST test is directly ended and the Boot startup and hardware initialization are started. Otherwise, the MBIST test is required. At the same time, it is necessary to determine whether the PLL is locked. If the PLL is not currently locked, wait for the PLL lock until the clock is locked before starting the MBIST test. Wait for all MBIST Pattern tests to be completed, which means that the IST power-on self-test process is completed and the Boot startup and hardware initialization are started.

[0010] Furthermore, a ROM is used to store all the pattern data required for IST testing, and the ROM is a read-only memory that is not easily lost when power is off.

[0011] Furthermore, EFUSE is used to store the enable control of the IST test pattern and the clock configuration parameters after PLL adjustment.

[0012] Furthermore, the EFUSE is configured using stable configuration parameters that are burned in during chip mass production.

[0013] Furthermore, a crystal oscillator clock CRYSTAL is used as a reference input clock, which is a low-speed clock; the PLL obtains a stable fast clock output according to the clock parameter configuration, and provides a high-speed clock for the MBIST test of IST and the BOOT startup and hardware initialization functions of the chip.

[0014] Furthermore, a MUX is used to select whether the test clock is a low-speed clock or a high-speed clock according to the mode of the test process.

[0015] Furthermore, IST_CTRL is used to read the test pattern from the ROM, input it to the corresponding test Block to obtain the test result, and feed it back to the system control unit; Block is the smallest test unit of each pattern to be tested, and LBIST and MBIST tests are required to be performed separately, and the results are obtained according to the input test pattern operation to compare and output the pass / fail result.

[0016] Furthermore, the method adopted is to write the parameters of the PLL after the re-chip test into EFUSE to accelerate the PLL locking; the specific process of the re-chip test is: configure the clock parameters of the PLL by software, observe the clock lock moment through an oscilloscope, calculate the clock lock time, obtain the minimum clock lock time after multiple adjustments, and record the clock parameters of the shortest lock time, and finally burn the clock parameters into EFUSE.

[0017] The present invention also provides a device for accelerating the IST power-on self-test of a vehicle-mounted chip, comprising:

[0018] ROM, used to store all Pattern data required for IST testing. The ROM is a read-only memory connected to the IST_CTRL signal;

[0019] EFUSE, used to store the enable control of the IST test pattern and the clock configuration parameters after PLL adjustment. The EFUSE is configured using the stable configuration parameters burned in during chip mass production; connected to IST_CTRL and System signals;

[0020] System, used to configure and control logic to complete IST test process control; connected with IST_CTRL and PLL signals;

[0021] CRYSTAL is the crystal oscillator clock, which is used as the reference input clock. The input clock itself is a low-speed clock. It is connected to the PLL and MUX signals.

[0022] PLL, used to obtain stable and fast clock output according to clock parameter configuration, and provide high-speed clock for MBIST test of IST and BOOT startup and hardware initialization function of chip; connected with MUX signal;

[0023] MUX, used to select whether the test clock is a low-speed or high-speed clock according to the test process mode; connected to multiple Block signals;

[0024] IST_CTRL is mainly responsible for reading the test pattern from the ROM, inputting it to the corresponding test block to obtain the test results, and feeding them back to the system control unit;

[0025] Multiple Blocks are the minimum test units of each pattern to be tested. They need to perform LBIST and MBIST tests respectively, and compare the results obtained based on the input test pattern operation to output pass / fail results; all of the multiple Blocks are connected to the IST_CTRL signal.

[0026] The present invention also provides a computer-readable storage medium containing a computer program, which, when executed by one or more processors, implements the method for accelerating the IST power-on self-test of an on-board chip as described in any of the above items.

[0027] In the prior art, after the chip is powered on, the IST test must be completed first before the Boot startup and hardware initialization process can be normally entered. The IST test needs to complete the LBIST and MBIST tests corresponding to each Pattern, and the LBIST does not need to be tested under a high-frequency clock. The advantage of the present invention is that after the power-on reset is released, the mechanism of the Logic BIST test can be performed, and the reset of the PLL is released at the same time, so that the clock parameters after the PLL reads the adjustment from the eFuse can quickly enter the Lock clock stable state, and the Logic BIST Pattern test performed simultaneously, because the PLL itself is an analog circuit, it is isolated from the digital circuit of the LBIST in design, and the test result of the LBIST will not be affected. After this improvement, it is not necessary to start the PLL clock parameter configuration after the LBIST Pattern test is completed and wait for the clock to lock, and the MBIST test can be quickly entered. The original Pattern configuration PLL mode usually waits for the maximum time of a PLL Lock, and then starts the MBIST test. The intermediate waiting time of IST can be greatly reduced by the above improved method. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is the power-on startup time of the vehicle chip;

[0029] Figure 2 Schematic diagram of the design structure for accelerating the power-on self-test of the vehicle-mounted chip IST;

[0030] Figure 3This is a flow chart of the accelerated design of the vehicle-mounted chip IST power-on self-test of the present invention. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] Explanation of terminology used in this article:

[0033] eFuse is electronic fuse;

[0034] IST, or In-System Test, is a technology that detects and diagnoses the system itself during system operation. It includes Logic BIST (also abbreviated as LBIST) and Memory BIST (also abbreviated as MBIST), which are common self-test processes. Logic BIST is responsible for completing the test of the chip's digital circuits, while Memory BIST is responsible for the read and write test of the chip's storage modules. LBIST pattern, or Logic Built-In Self Test, is a key part of LBIST (Logic Built-In Self Test, a self-test mechanism implemented inside the chip).

[0035] PLL is a phase-locked loop circuit;

[0036] Block is the smallest test unit for each pattern to be tested. It needs to perform LBIST and MBIST tests respectively, and obtain the results based on the input test pattern operation and compare them to output the pass / fail results.

[0037] like Figure 1 As shown in the figure, the on-board chip often performs self-test during the power-on process for the purpose of functional safety. The Logic BIST and Memory BIST of IST are common self-test processes. The Logic BIST is responsible for completing the test of the chip digital circuit, while the Memory BIST is responsible for the read and write test of the chip storage module. Therefore, the power-on startup process of the on-board chip includes three parts, such as Figure 1The t0 in the figure indicates the time from the start of power supply to the stable power supply and the reset release of the chip, t1 indicates the time for the system IST self-test to start after the chip reset is released, including the sum of the time of LBIST and MBIST, and t2 indicates the clock required for CPU Boot startup and hardware initialization. There are certain requirements for the total power-on time of the on-board chip, so it is necessary to reduce the time of each part. The present invention mainly provides an acceleration method for IST power-on self-test to accelerate the process of chip startup.

[0038] like Figure 3 As shown, a method for accelerating the IST power-on self-test of a vehicle-mounted chip includes the following steps:

[0039] S1, after the chip is powered on, wait for the power supply to stabilize, then release the power-on-reset (power-on reset), and reset is released;

[0040] S2, then read the configuration parameters from the eFuse, mainly including the enable signal of the IST test pattern and the high-frequency clock parameters after PLL adjustment. At this time, the control of the IST test process is started, and the PLL clock parameters are configured at the same time, waiting for the PLL clock to enter the locked state;

[0041] S3, start the IST test process, first determine whether to perform LBIST test, if not, then enter the test judgment process of whether MBIST is needed, otherwise start the LBIST test of each Block, wait for the test to be completed and also enter the test judgment process of whether MBIST is needed;

[0042] S4, enter the MBIST test judgment process. If it is determined that the MBIST test is not required, the IST test is directly ended and the Boot startup and hardware initialization are started. Otherwise, the MBIST test is required. At the same time, it is necessary to determine whether the PLL is locked. If the PLL is not currently locked, wait for the PLL lock until the clock is locked before starting the MBIST test. Wait for all MBIST Pattern tests to be completed, which means that the IST power-on self-test process is completed and the Boot startup and hardware initialization are started.

[0043] In some embodiments, a ROM may be used to store all pattern data required for IST testing. The ROM is a read-only memory that does not easily lose data when power is off.

[0044] In some embodiments, EFUSE may be used to store the enable control of the IST test pattern and the clock configuration parameters after PLL calibration.

[0045] In some embodiments, the EFUSE may be configured using stable configuration parameters that are burned in during chip mass production.

[0046] In some embodiments, a crystal oscillator clock CRYSTAL is used as a reference input clock, which is a low-speed clock; the PLL obtains a stable fast clock output according to the clock parameter configuration, and provides a high-speed clock for the MBIST test of IST and the BOOT startup and hardware initialization functions of the chip.

[0047] In some embodiments, a MUX is used to select whether the test clock is a low-speed clock or a high-speed clock according to the mode of the test process.

[0048] In some embodiments, IST_CTRL is used to read the test pattern from the ROM, input it to the corresponding test Block to obtain the test result, and feed it back to the system control unit; Block is the smallest test unit of each pattern to be tested, and LBIST and MBIST tests need to be performed separately, and the results obtained according to the input test pattern operation are compared and output as pass / fail results.

[0049] Figure 3 The invention shows the accelerated test flow chart of the on-board chip power-on self-starting. First, after the chip is powered on, wait for the power supply to be stable, then release the power-on-reset, and start reading the configuration parameters from the efuse after the reset is released, mainly including the enable signal of the IST test pattern and the high-frequency clock parameters after the PLL is adjusted. At this time, the control of the IST test process is started, and the PLL clock parameters are configured at the same time, and the PLL clock is waited to enter the locked state. Start the IST test process, first determine whether it is necessary to perform the LBIST test, if not, enter the test judgment process of whether the MBIST is needed, otherwise, start the LBIST test of each Block, wait for the test to be completed and enter the test judgment process of whether the MBIST is needed. At this time, if it is determined that the MBIST test is not needed, the IST test is directly terminated, and the Boot startup and hardware initialization are started. Otherwise, the MBIST test is needed, and it is necessary to determine whether the PLL is locked. If the PLL is not currently locked, wait for the PLL lock until the clock is locked before starting the MBIST test, and wait for all MBIST Pattern tests to be completed, which means that the IST power-on self-test process is finished, and the Boot startup and hardware initialization are started.

[0050] like Figure 2 As shown, the present invention also provides a device for accelerating the IST power-on self-test of a vehicle-mounted chip, comprising:

[0051] ROM is used to store all pattern data required for IST testing. The ROM is a read-only memory and is connected to the IST_CTRL chip signal. Among them, IST_CTRL is a control unit built into the chip. This control logic is responsible for reading the IST test pattern for testing and belongs to the built-in logic.

[0052] EFUSE, used to store the enable control of the IST test pattern and the clock configuration parameters after PLL adjustment. The EFUSE is configured using the stable configuration parameters burned in during chip mass production; connected to IST_CTRL and System signals;

[0053] System, used to configure and control logic to complete IST test process control; connected with IST_CTRL and PLL signals;

[0054] CRYSTAL is the crystal oscillator clock, which is used as the reference input clock. The input clock itself is a low-speed clock. It is connected to the PLL and MUX signals.

[0055] PLL, used to obtain stable and fast clock output according to clock parameter configuration, and provide high-speed clock for MBIST test of IST and BOOT startup and hardware initialization function of chip; connected with MUX signal;

[0056] MUX, used to select whether the test clock is a low-speed or high-speed clock according to the test process mode; connected to multiple Block signals;

[0057] IST_CTRL is mainly responsible for reading the test pattern from the ROM, inputting it to the corresponding test block to obtain the test results, and feeding them back to the system control unit;

[0058] Multiple Blocks are the minimum test units of each pattern to be tested. They need to perform LBIST and MBIST tests respectively, and compare the results obtained based on the input test pattern operation to output pass / fail results; all of the multiple Blocks are connected to the IST_CTRL signal. Figure 2 The circuit in the Figure 3 The software for accelerating the design process of the vehicle-mounted chip IST power-on self-test can achieve the purpose of the present invention. Of course, other circuits or computers can also be combined to achieve Figure 3 The software for accelerating the design process of the vehicle-mounted chip IST power-on self-test illustrated as an example is a feasible solution as long as it can achieve the purpose of the present invention.

[0059] Specifically, Figure 2The schematic diagram of the acceleration device structure for the power-on self-test of an on-board chip is shown. Assuming that the maximum time required for PLL locking is tPLL_LOCK_MAX, and the time required for all LBIST pattern tests of IST to complete is tLBIST, the test time of min(tPLL_LOCK_MAX, tLBIST) can be saved. The device includes ROM, which is used to store the pattern data required for all IST tests. It is a read-only storage that is not easily lost when power is off; EFUSE is used to store the enable control of the IST test pattern and the clock configuration parameters after PLL adjustment. It is a stable configuration parameter for chip mass production; System configuration and control logic are mainly based on Figure 3 The flowchart is used to complete the IST test process control; CRYSTAL is the crystal oscillator clock, which is used as the reference clock input. The input clock itself is a low-speed clock; PLL obtains a stable and fast clock output according to the clock parameter configuration, and provides a high-speed clock for the MBIST test of IST and the BOOT startup and hardware initialization functions of the chip; MUX selects whether the test clock is a low-speed or high-speed clock according to the mode of the test process; IST_CTRL is mainly responsible for reading the test pattern from the ROM, inputting it to the corresponding test Block to obtain the test result, and feeding it back to the system control unit; Block is the smallest test unit of each pattern to be tested, which needs to be tested by LBIST and MBIST respectively, and the result obtained by the input test pattern operation is compared and the pass / fail result is output.

[0060] The present invention also provides a computer-readable storage medium containing a computer program, which, when executed by one or more processors, implements the method for accelerating the IST power-on self-test of an on-board chip as described in any of the above items.

[0061] In the prior art, after the chip is powered on, the IST test must be completed first before the Boot startup and hardware initialization process can be normally entered. The IST test needs to complete the LBIST and MBIST tests corresponding to each Pattern, and the LBIST does not need to be tested under a high-frequency clock. The advantage of the present invention is that after the power-on reset is released, the mechanism of the Logic BIST test can be performed, and the reset of the PLL is released at the same time, so that the clock parameters after the PLL reads the adjustment from the eFuse can quickly enter the Lock clock stable state, and the Logic BIST Pattern test performed simultaneously, because the PLL itself is an analog circuit, it is isolated from the digital circuit of the LBIST in design, and the test result of the LBIST will not be affected. After this improvement, it is not necessary to start the PLL clock parameter configuration after the LBIST Pattern test is completed and wait for the clock to lock, and the MBIST test can be quickly entered. The original Pattern configuration PLL mode usually waits for the maximum time of a PLL Lock, and then starts the MBIST test. The intermediate waiting time of IST can be greatly reduced by the above improved method.

[0062] The present invention can effectively reduce the time required for the IST test pattern by improving the process of waiting for PLL locking in the MBIST test in parallel with the LBIST test, thereby achieving the effect of accelerating the IST self-test, thereby providing more time for function startup.

[0063] In addition, the design of the external system controlling the IST test process can flexibly control the test process at a relatively low control logic cost, thus accelerating the test time. The PLL configuration parameters and commands that originally needed to be stored in ROM can be saved, thereby reducing the size of the ROM and the chip area.

[0064] The IST Pattern ROM Code itself is not rewritable, so the original PLL configuration parameters and commands placed in the ROM lack flexibility. If there is a problem with the parameters, all MBIST test patterns will fail. The method adopted by the present invention is to write the parameters of the PLL after the chip return test and adjustment into EFUSE to accelerate the PLL locking, which can effectively save the locking time and greatly reduce the probability of losing lock.

[0065] The specific process of the chip rewind test is: configure the clock parameters of the PLL through software, observe the clock lock moment through an oscilloscope, calculate the clock lock time, and obtain the minimum clock lock time after multiple adjustments, and record the clock parameters with the shortest lock time, and finally burn the clock parameters into EFUSE. The principle is that PLL is an analog circuit, and the fast and stable clock requires calibration of the corresponding clock parameters. The parameters are not fixed, and the fastest and most stable configuration parameters need to be obtained through debugging in actual applications. This adjustment method can save the clock lock time and reduce the power-on startup time during the actual chip power-on process; at the same time, it can reduce the risk of PLL not working properly.

[0066] The present invention can enable or disable the corresponding test pattern through process control, has very good flexibility, and can adjust the number of test patterns according to the test time, thereby reducing the test time of the IST power-on self-test.

[0067] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A method for accelerating the IST power-on self-test of an on-board chip, characterized in that: The following steps are involved: S1, after the chip is powered on, wait for the power supply to stabilize, then release the power-on-reset, and reset is released; S2, read the configuration parameters from the eFuse, mainly including the enable signal of the IST test pattern and the high-frequency clock parameters after PLL adjustment. At this time, the control of the IST test process is started, and the PLL clock parameters are configured at the same time, waiting for the PLL clock to enter the locked state; S3, start the IST test process, first determine whether to perform LBIST test, if not, then enter the test judgment process of whether MBIST is needed, otherwise start the LBIST test of each Block, wait for the test to be completed and also enter the test judgment process of whether MBIST is needed; S4, enter the MBIST test judgment process. If it is determined that the MBIST test is not required, the IST test is directly ended and the Boot startup and hardware initialization are started. Otherwise, the MBIST test is required. At the same time, it is necessary to determine whether the PLL is locked. If the PLL is not currently locked, wait for the PLL lock until the clock is locked before starting the MBIST test. Wait for all MBIST Pattern tests to be completed, which means that the IST power-on self-test process is completed and the Boot startup and hardware initialization are started.

2. The method for accelerating the IST power-on self-test of the vehicle-mounted chip according to claim 1, characterized in that: ROM is used to store all pattern data required for IST testing. The ROM is a read-only memory that does not easily lose data when power is off.

3. The method for accelerating the IST power-on self-test of the vehicle-mounted chip according to claim 2, characterized in that: EFUSE is used to store the enable control of the IST test pattern and the clock configuration parameters after PLL adjustment.

4. The method for accelerating the IST power-on self-test of the vehicle-mounted chip according to claim 3, characterized in that: The EFUSE is configured using stable configuration parameters that are burned in during chip mass production.

5. The method for accelerating the IST power-on self-test of the vehicle-mounted chip according to claim 4, characterized in that: The crystal clock CRYSTAL is used as the reference input clock, which is a low-speed clock; the PLL obtains a stable fast clock output according to the clock parameter configuration, and provides a high-speed clock for the MBIST test of IST and the BOOT startup and hardware initialization functions of the chip.

6. The method for accelerating the IST power-on self-test of the vehicle-mounted chip according to claim 5, characterized in that: MUX is used to select whether the test clock is a low-speed or high-speed clock according to the test process mode.

7. The method for accelerating the IST power-on self-test of the vehicle-mounted chip according to claim 6, characterized in that: IST_CTRL is used to read the test pattern from ROM, input it to the corresponding test Block to obtain the test result, and feed it back to the system control unit; Block is the smallest test unit of each pattern to be tested, and LBIST and MBIST tests need to be performed separately, and the results obtained according to the input test pattern operation are compared and output as pass / fail results.

8. The method for accelerating the IST power-on self-test of the vehicle-mounted chip according to claim 7, characterized in that: The method adopted is to write the parameters of the PLL after the re-chip test into EFUSE to accelerate the PLL locking; the specific process of the re-chip test is: configure the clock parameters of the PLL by software, observe the clock lock moment through an oscilloscope, calculate the clock lock time, obtain the minimum clock lock time after multiple adjustments, and record the clock parameters with the shortest lock time, and finally burn the clock parameters into EFUSE.

9. A device for accelerating the IST power-on self-test of an on-board chip, characterized in that: include: ROM, used to store all Pattern data required for IST testing. The ROM is a read-only memory connected to the IST_CTRL signal; EFUSE is used to store the enable control of the IST test pattern and the clock configuration parameters after PLL adjustment. The EFUSE is configured using the stable configuration parameters burned in during chip mass production; Connect with IST_CTRL and System signals; System, used to configure and control logic to complete IST test process control; Connected with IST_CTRL and PLL signals; CRYSTAL is the crystal oscillator clock, which is used as the reference input clock. The input clock itself is a low-speed clock. It is connected to the PLL and MUX signals. PLL, used to obtain stable and fast clock output according to clock parameter configuration, and provide high-speed clock for MBIST test of IST and BOOT startup and hardware initialization functions of chip; Connect with MUX signal; MUX, used to select whether the test clock is a low-speed or high-speed clock according to the test process mode; connected to multiple Block signals; IST_CTRL is mainly responsible for reading the test pattern from the ROM and inputting it to the corresponding test block to obtain the test results and feed them back to the system control unit; Multiple Blocks are the minimum test units of each pattern to be tested. They need to perform LBIST and MBIST tests respectively, and compare the results obtained based on the input test pattern operation to output pass / fail results; all of the multiple Blocks are connected to the IST_CTRL signal.

10. A computer-readable storage medium containing a computer program, characterized in that: When the computer program is executed by one or more processors, the method for accelerating the IST power-on self-test of the vehicle-mounted chip described in any one of claims 1-8 is implemented.

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