Digital low-power-consumption high-reliability over-temperature protection circuit

Abstract

The invention discloses a digitally implemented low-power-consumption high-reliability over-temperature protection circuit, which belongs to the field of analog circuit design and comprises a positive temperature coefficient voltage generator, a comparator and a logic circuit, one input end of the positive temperature coefficient voltage generator is connected with a clock signal; the other input end of the positive temperature coefficient voltage generator is connected with the output end of the logic circuit; the output end of the positive temperature coefficient voltage generator is connected with the positive input end of the comparator, and the output end of the comparator is connected with one input end of the logic circuit. A positive temperature coefficient voltage generator is used for generating a voltage signal in direct proportion to temperature; the comparator generates an over-temperature protection signal which is not latched by comparing the positive temperature coefficient voltage with the band-gap reference voltage; and the logic circuit is used for latching the over-temperature protection signal output by the comparator into the memory, and changing an over-temperature protection detection temperature point by returning the latch signal to the positive temperature voltage generator, so that an over-temperature protection hysteresis function is realized.

Description

Technical Field

[0001] The invention relates to the field of analog circuit design, in particular to a digitally realized low-power and high-reliability over-temperature protection circuit. Background Art

[0002] In linear and switching regulated power supply chips, the increase in power loss inside the chip will cause the temperature inside the chip to rise sharply. When the temperature inside the chip rises to a certain value, the chip will burn due to overheating. Therefore, an over-temperature protection circuit is required inside the power supply chip. The over-temperature protection circuit inside the chip compares a temperature sensor with a reference voltage with a zero temperature coefficient to achieve real-time temperature detection. When the voltage on the temperature sensor exceeds the reference voltage, the over-temperature protection circuit provides a protection signal to the chip to prevent the chip from overheating and damage.

[0003] The traditional over-temperature protection circuit uses an NPN transistor to generate a voltage that is positively correlated with temperature as a temperature sensing signal, and the NPN transistor has a large leakage current at high temperatures. If the bias current in the over-temperature protection circuit is relatively small, the accuracy of the temperature value of the over-temperature protection will be affected by the leakage current, which will seriously reduce the accuracy of the over-temperature protection circuit, thereby reducing the reliability of the chip. In automotive applications, the internal operating temperature requirements of the chip are very high. The maximum internal temperature of the automotive application chip is 175 degrees, which requires the chip to have high thermal reliability; at the same time, because the power supply method is battery-powered, this puts higher requirements on the standby power consumption of the chip, that is, the chip must have low power consumption and high reliability. However, traditional over-temperature protection technology is difficult to implement in a low-power environment, which urgently requires an over-temperature protection circuit with low power consumption and high reliability. Summary of the invention

[0004] With regard to the above problems existing in the prior art, the object of the present invention is to provide a digitally implemented low-power and high-reliability over-temperature protection circuit to solve the problems raised in the above background technology.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] A digitally realized low-power and high-reliability over-temperature protection circuit comprises a positive temperature coefficient voltage generator, a comparator and a logic circuit; one input end of the positive temperature coefficient voltage generator is connected to a clock signal TSD_EN; the other input end of the positive temperature coefficient voltage generator is connected to an output signal TSD of the logic circuit;

[0007] The output terminal of the positive temperature coefficient voltage generator is connected to the positive input terminal of the comparator, and the negative input terminal of the comparator is connected to the reference voltage VBG;

[0008] The comparator is connected to the synchronous control clock signal TSD_EN and the clock signal TSD_RESET;

[0009] The output terminal of the comparator is connected to an input terminal of the logic circuit, and the output terminal of the comparator outputs a signal TSD_CMP_OUT;

[0010] The clock input terminal of the logic circuit is connected to the clock signal TSD_EN and the clock signal TSD_CLK;

[0011] The output terminal of the logic circuit outputs a signal TSD.

[0012] As a further solution of the present invention: the positive temperature coefficient voltage generator includes PMOS tube PM31, PMOS tube PM32, PMOS tube PM33, PMOS tube PM34, PMOS tube PM35, PMOS tube PM36, PMOS tube PM37; NMOS tube NM33, NMOS tube NM34, NMOS tube NM35, NMOS tube NM36; resistor R1, resistor R2, resistor R3; capacitor C1; current source I31; inverter INV31, inverter INV32;

[0013] The input end of the inverter INV31 is connected to the clock signal TSD_EN; the input end of the inverter INV32 is connected to the output signal TSD of the logic circuit;

[0014] The output end of the inverter INV31 is connected to the gate of the NMOS tube NM35; the source of the NMOS tube NM35 is grounded;

[0015] The output end of the inverter INV32 is connected to the gate of the NMOS tube NM36, and the drain of the NMOS tube NM36 is connected to one end of the resistor R2 and one end of the resistor R3 at the same time; the other end of the resistor R2 is connected to the drain of the NMOS tube NM35, and the source of the NMOS tube NM36 is grounded; the other end of the resistor R3 is grounded;

[0016] The input end of the inverter INV31 is connected to the gate of the PMOS tube PM35 and the gate of the PMOS tube PM36 at the same time;

[0017] The drain of the PMOS transistor PM36 is simultaneously connected to the drain of the PMOS transistor PM34, the gate of the PMOS transistor PM37, and the input end of the current source I31; the output end of the current source I31 is grounded;

[0018] The drain of the PMOS tube PM35 is simultaneously connected to the gate of the PMOS tube PM34, the gate of the PMOS tube PM31, the gate of the PMOS tube PM32, and the gate of the PMOS tube PM33;

[0019] The drain of the PMOS tube PM37 is simultaneously connected to the drain of the PMOS tube PM31, the drain of the NMOS tube NM33, the gate of the NMOS tube NM33, and the gate of the NMOS tube NM34;

[0020] The gate of the PMOS tube PM32 is connected to the drain of the PMOS tube PM32 and the drain of the NMOS tube NM34 at the same time;

[0021] The drain of the PMOS tube PM33 is connected to the drain of the NMOS tube NM35;

[0022] The source of the NMOS tube NM33 is connected to the emitter of the transistor Q31; the base of the transistor Q31 and the collector of the transistor Q31 are both grounded;

[0023] The source of the NMOS transistor NM34 is connected to one end of the resistor R1 , and the other end of the resistor R1 is connected to the emitter of the transistor Q32 ; the base of the transistor Q32 and the collector of the transistor Q32 are both grounded.

[0024] As a further solution of the present invention: one input end of the positive temperature coefficient voltage generator is the input end of the inverter INV31; the other input end of the positive temperature coefficient voltage generator is the input end of the inverter INV32, and the drain of the NMOS tube NM35 is the output end of the positive temperature coefficient voltage generator.

[0025] As a further solution of the present invention: the drain of the NMOS tube NM35 is connected to the positive electrode of the capacitor C1, and the negative electrode of the capacitor C1 is grounded.

[0026] As a further solution of the present invention: the source of the PMOS tube PM35 in the positive temperature coefficient voltage generator is connected to the power supply VCC, and the source of the PMOS tube PM36 is connected to the power supply VCC.

[0027] As a further solution of the present invention: the source of the PMOS tube PM34, the source of the PMOS tube PM31, the source of the PMOS tube PM32, and the source of the PMOS tube PM33 in the positive temperature coefficient voltage generator are all connected to the power supply VCC.

[0028] As a further solution of the present invention: the source of the PMOS tube PM37 in the positive temperature coefficient voltage generator is connected to the power supply VCC.

[0029] As a further solution of the present invention: the comparator includes PMOS tube PM21, PMOS tube PM22, PMOS tube PM23, PMOS tube PM24, PMOS tube PM25, PMOS tube PM26, PMOS tube PM27, PMOS tube PM28; NMOS tube NM21, NMOS tube NM22, NMOS tube NM23, NMOS tube NM24, NMOS tube NM25, NMOS tube NM26, NMOS tube NM27, NMOS tube NM28, NMOS tube NM29, NMOS tube NM30, NMOS tube NM31, NMOS tube NM32; current source I0; inverter INV21;

[0030] The gate of the PMOS tube PM21 is connected to the drain of the NMOS tube NM35 in the positive temperature coefficient voltage generator;

[0031] The gate of the PMOS tube PM22 is connected to the reference voltage VBG;

[0032] The source of the PMOS transistor PM21 and the source of the PMOS transistor PM22 are both connected to the output end of the current source I0; the input end of the current source I0 is connected to the power supply VCC;

[0033] The gate of the PMOS transistor PM21 is connected to the drain of the NMOS transistor NM29, and the gate of the PMOS transistor PM22 is connected to the source of the NMOS transistor NM29; the gate of the NMOS transistor NM29 is connected to the clock signal TSD_RESET;

[0034] The drain of the PMOS tube PM21 is simultaneously connected to the drain of the NMOS tube NM24, the drain of the NMOS tube NM22, the gate of the NMOS tube NM21, the gate of the NMOS tube NM22, the gate of the NMOS tube NM23, and the drain of the NMOS tube NM30;

[0035] The drain of the PMOS tube PM22 is simultaneously connected to the drain of the NMOS tube NM29, the drain of the NMOS tube NM23, the drain of the NMOS tube NM25, the gate of the NMOS tube NM24, the gate of the NMOS tube NM25, and the gate of the NMOS tube NM26;

[0036] The gate of the NMOS tube NM29 and the gate of the NMOS tube NM30 are both connected to the output end of the inverter INV21, and the input end of the inverter INV21 is connected to the clock signal TSD_EN;

[0037] The source of the NMOS tube NM29 and the source of the NMOS tube NM30 are both grounded;

[0038] The drain of the NMOS tube NM21 is simultaneously connected to the drain of the PMOS tube PM23, the gate of the PMOS tube PM23, the gate of the PMOS tube PM24, and the drain of the PMOS tube PM27; the gate of the PMOS tube PM27 is connected to the input end of the inverter INV21; the source of the PMOS tube PM27, the source of the PMOS tube PM23, and the source of the PMOS tube PM24 are all connected to the power supply VCC;

[0039] The source of the NMOS tube NM21, the source of the NMOS tube NM22, the source of the NMOS tube NM23, the source of the NMOS tube NM24, the source of the NMOS tube NM25, and the source of the NMOS tube NM26 are grounded;

[0040] The drain of the NMOS tube NM26 is simultaneously connected to the drain of the PMOS tube PM25, the gate of the PMOS tube PM25, the gate of the PMOS tube PM26, and the drain of the PMOS tube PM28; the gate of the PMOS tube PM28 is connected to the input end of the inverter INV21; the source of the PMOS tube PM28, the source of the PMOS tube PM25, and the source of the PMOS tube PM26 are all connected to the power supply VCC;

[0041] The drain of the PMOS tube PM24 is simultaneously connected to the drain of the NMOS tube NM31, the drain of the NMOS tube NM27, the gate of the NMOS tube NM27, and the gate of the NMOS tube NM28;

[0042] The drain of the PMOS tube PM26 is connected to the drain of the NMOS tube NM28 and the drain of the NMOS tube NM32 at the same time;

[0043] The gate of the NMOS tube NM31 is connected to the gate of the NMOS tube NM32 and the gate of the NMOS tube NM29 at the same time;

[0044] The source of the NMOS tube NM31 , the source of the NMOS tube NM27 , the source of the NMOS tube NM28 , and the source of the NMOS tube NM32 are all grounded.

[0045] As a further solution of the present invention: the gate of the PMOS tube PM21 is the positive input terminal of the comparator, the gate of the PMOS tube PM22 is the negative input terminal of the comparator, and the drain of the PMOS tube PM26 is the output terminal of the comparator.

[0046] As a further solution of the present invention: the logic circuit includes D flip-flops D0, D flip-flops D1, and D flip-flops D2; AND gate AND21; inverters INV11 and INV12;

[0047] The input terminal D of the D flip-flop D0 is connected to the drain of the PMOS tube PM26 in the comparator;

[0048] The two input ends of the AND gate AND21 are connected to the clock signal TSD_EN and the clock signal TSD_CLK respectively, and the output end of the AND gate AND21 is simultaneously connected to the clock end CLK of the D flip-flop D0, the clock end CLK of the D flip-flop D1, and the clock end CLK of the D flip-flop D2;

[0049] The output terminal Q of the D flip-flop D0 is connected to the input terminal D of the D flip-flop D1; the output terminal Q of the D flip-flop D1 is connected to the input terminal D of the D flip-flop D2;

[0050] The output terminal Q of the D flip-flop D2 is connected to the input terminal of the inverter INV11, the output terminal of the inverter INV11 is connected to the input terminal of the inverter INV12, the output terminal of the inverter INV11 is the output terminal of the logic circuit, and the output terminal of the inverter INV11 outputs the signal TSD.

[0051] Compared with the prior art, the present invention has the following beneficial effects:

[0052] The over-temperature protection circuit architecture provided by the present invention includes a positive temperature coefficient voltage generator, which is used to generate a voltage signal proportional to the temperature; a voltage comparator, which generates an over-temperature protection signal that is not latched by comparing the positive temperature coefficient voltage and the bandgap reference voltage; an over-temperature protection logic circuit, which is used to latch the over-temperature protection signal output by the comparator into a memory, and change the over-temperature protection detection temperature point by feeding back the latched signal to the positive temperature voltage generator, thereby realizing the over-temperature protection hysteresis function. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 The circuit architecture diagram of a digitally implemented low-power and high-reliability over-temperature protection circuit disclosed in an embodiment is shown.

[0054] Figure 2 The present invention discloses a digital signal timing waveform diagram of a digitally realized low-power and high-reliability over-temperature protection circuit disclosed in an embodiment.

[0055] Figure 3 The present invention is a schematic diagram of a module circuit of a positive temperature coefficient voltage generator in a digitally realized low-power and high-reliability over-temperature protection circuit disclosed in an embodiment.

[0056] Figure 4 The present invention is a schematic diagram of a module circuit of a comparator in a digitally realized low-power and high-reliability over-temperature protection circuit disclosed in an embodiment.

[0057] Figure 5 The present invention is a module circuit schematic diagram of a logic circuit in a digitally realized low-power and high-reliability over-temperature protection circuit disclosed in an embodiment. DETAILED DESCRIPTION

[0058] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention; it is obvious that the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0059] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "provided with", "connected", and "connected" should be understood in a broad sense; for example, it can be a fixed connection, a detachable connection, or an integral connection, a mechanical connection, or an electrical connection, a direct connection, or an indirect connection through an intermediate medium, or the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0060] The invention relates to an over-temperature protection circuit structure with low power consumption and high reliability. The circuit is mainly used in linear and switching voltage-stabilized power supplies and belongs to the technology in the field of analog circuit design.

[0061] See also Figure 1 , a digitally realized low-power and high-reliability over-temperature protection circuit, comprising a positive temperature coefficient voltage generator, a comparator and a logic circuit; one input end of the positive temperature coefficient voltage generator is connected to a clock signal TSD_EN; the other input end of the positive temperature coefficient voltage generator is connected to an output signal TSD of the logic circuit;

[0062] The output terminal of the positive temperature coefficient voltage generator is connected to the positive input terminal of the comparator, and the negative input terminal of the comparator is connected to the reference voltage VBG;

[0063] The comparator is connected to the synchronous control clock signal TSD_EN and the clock signal TSD_RESET;

[0064] The output terminal of the comparator is connected to an input terminal of the logic circuit, and the output terminal of the comparator outputs a signal TSD_CMP_OUT;

[0065] The clock input terminal of the logic circuit is connected to the clock signal TSD_EN and the clock signal TSD_CLK;

[0066] The output terminal of the logic circuit outputs a signal TSD;

[0067] Figure 1This is the over-temperature protection circuit architecture diagram proposed by the present invention, which is mainly composed of three modules, including a positive temperature coefficient voltage generation circuit module, a comparator module and a logic circuit module. In this solution, the reference voltage VBG in the system needs to be provided externally, and the VBG needs to have driving capability; in addition, three synchronous control clock signals, TSD_EN, TSD_RESET and TSD_CLK, need to be provided.

[0068] The TSD_EN signal is an enable signal. When the signal is at a high level, all modules are in a working state and consume static current. When the signal is at a low level, all modules are in a shutdown state and no current is consumed at this time. The output of the positive temperature coefficient voltage generation circuit module is K*ΔVBE. The voltage signal is a positive temperature coefficient voltage. When the temperature reaches the overtemperature point, the voltage satisfies K*ΔVBE=VBG. The non-inverting input terminal of the comparator module is K*ΔVBE, and the inverting input terminal is VBG. When the non-inverting input terminal of the comparator is higher than the inverting input terminal, the comparator output TSD_CMP_OUT is a high level, otherwise, the comparator output is a low level. The logic circuit module latches the comparator output signal of the current cycle at the rising edge of the clock TSD_CLK, samples the comparator output once in each cycle and stores it, which improves the anti-interference of the overtemperature signal, and uses the stored overtemperature signal TSD to change the temperature point of overtemperature detection, increase the hysteresis window of the overtemperature protection circuit, and improve the reliability of the system.

[0069] Figure 2 The digital signal timing waveform diagram of the over-temperature protection circuit proposed by the present invention requires the system to provide three clock signals, which are provided according to the timing relationship of the diagram, namely TSD_EN, TSD_RESET, and TSD_CLK. TSD_EN generates a pulse with a pulse width of TON in each cycle, which is used to control the start of the over-temperature protection module; TSD_RESET generates a pulse with a fixed width starting from the rising edge of TSD_EN, which is used to reset the comparator input stage to ensure that the bias in the over-temperature protection circuit starts smoothly; TSD_CLK generates a narrow pulse after a delay of Tdelay from the rising edge of TSD_EN, which serves as the clock signal of the D flip-flop.

[0070] The solution to achieve low power consumption and high reliability is to reduce the average power consumption of the system by dynamically turning on the module. If the current consumed when the over-temperature protection circuit is turned on is IQ, and the turn-on time is TON, and the system is repeatedly turned on for a period of T, then the average current consumed by the system is IQ*(TON / T). The duty cycle of the system is D=TON / T. If D=0.1 and IQ=10μA, then the average current consumed by the system is 1μA. In this way, high reliability and low power consumption are achieved. The use of digital methods to latch the over-temperature protection signal also improves the anti-interference ability of the system.

[0071] Figure 3 The present invention provides a module circuit schematic diagram of a positive temperature coefficient voltage generator, which includes a PMOS tube PM31, a PMOS tube PM32, a PMOS tube PM33, a PMOS tube PM34, a PMOS tube PM35, a PMOS tube PM36, and a PMOS tube PM37; an NMOS tube NM33, an NMOS tube NM34, an NMOS tube NM35, and an NMOS tube NM36; a resistor R1, a resistor R2, and a resistor R3; a capacitor C1; a current source I31; an inverter INV31, and an inverter INV32;

[0072] One input end of the positive temperature coefficient voltage generator is the input end of the inverter INV31; the other input end of the positive temperature coefficient voltage generator is the input end of the inverter INV32;

[0073] The input end of the inverter INV31 is connected to the clock signal TSD_EN; the input end of the inverter INV32 is connected to the output signal TSD of the logic circuit;

[0074] The output end of the inverter INV31 is connected to the gate of the NMOS tube NM35; the drain of the NMOS tube NM35 is the output end of the positive temperature coefficient voltage generator; the source of the NMOS tube NM35 is grounded;

[0075] The output end of the inverter INV32 is connected to the gate of the NMOS tube NM36, and the drain of the NMOS tube NM36 is connected to one end of the resistor R2 and one end of the resistor R3 at the same time; the other end of the resistor R2 is connected to the drain of the NMOS tube NM35, and the source of the NMOS tube NM36 is grounded; the other end of the resistor R3 is grounded;

[0076] The drain of the NMOS tube NM35 is connected to the positive electrode of the capacitor C1, and the negative electrode of the capacitor C1 is grounded;

[0077] The input end of the inverter INV31 is connected to the gate of the PMOS tube PM35 and the gate of the PMOS tube PM36 at the same time;

[0078] The source of the PMOS tube PM35 is connected to the power supply VCC, and the source of the PMOS tube PM36 is connected to the power supply VCC;

[0079] The drain of the PMOS transistor PM36 is simultaneously connected to the drain of the PMOS transistor PM34, the gate of the PMOS transistor PM37, and the input end of the current source I31; the output end of the current source I31 is grounded;

[0080] The drain of the PMOS tube PM35 is simultaneously connected to the gate of the PMOS tube PM34, the gate of the PMOS tube PM31, the gate of the PMOS tube PM32, and the gate of the PMOS tube PM33;

[0081] The source of the PMOS tube PM34, the source of the PMOS tube PM31, the source of the PMOS tube PM32, and the source of the PMOS tube PM33 are all connected to the power supply VCC;

[0082] The source of the PMOS tube PM37 is connected to the power supply VCC;

[0083] The drain of the PMOS tube PM37 is simultaneously connected to the drain of the PMOS tube PM31, the drain of the NMOS tube NM33, the gate of the NMOS tube NM33, and the gate of the NMOS tube NM34;

[0084] The gate of the PMOS tube PM32 is connected to the drain of the PMOS tube PM32 and the drain of the NMOS tube NM34 at the same time;

[0085] The drain of the PMOS tube PM33 is connected to the drain of the NMOS tube NM35;

[0086] The source of the NMOS tube NM33 is connected to the emitter of the transistor Q31; the base of the transistor Q31 and the collector of the transistor Q31 are both grounded;

[0087] The source of the NMOS tube NM34 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the emitter of the transistor Q32; the base of the transistor Q32 and the collector of the transistor Q32 are both grounded;

[0088] The PNP transistor substrate of the positive temperature coefficient voltage generator has a simpler device structure, does not have a large area of ​​reverse biased junction to the ground, and has low high temperature leakage, so it is more suitable as the core circuit of the over-temperature protection in the present invention. The positive temperature coefficient current is generated by ΔVBE, and then the current signal is converted into a voltage signal K*ΔVBE through a resistor to achieve K times amplification, K=R2 / R1, and the temperature detection value of the over-temperature protection circuit is changed by changing the K value.

[0089] Figure 4 The present invention provides a comparator module circuit schematic diagram, wherein the comparator includes a PMOS tube PM21, a PMOS tube PM22, a PMOS tube PM23, a PMOS tube PM24, a PMOS tube PM25, a PMOS tube PM26, a PMOS tube PM27, and a PMOS tube PM28; an NMOS tube NM21, an NMOS tube NM22, an NMOS tube NM23, an NMOS tube NM24, an NMOS tube NM25, an NMOS tube NM26, an NMOS tube NM27, an NMOS tube NM28, an NMOS tube NM29, an NMOS tube NM30, an NMOS tube NM31, and an NMOS tube NM32; a current source I0; an inverter INV21;

[0090] The gate of the PMOS tube PM21 is the positive input terminal of the comparator, and the gate of the PMOS tube PM21 is connected to the drain of the NMOS tube NM35 in the positive temperature coefficient voltage generator;

[0091] The gate of the PMOS tube PM22 is the negative input terminal of the comparator, and the gate of the PMOS tube PM22 is connected to the reference voltage VBG;

[0092] The source of the PMOS transistor PM21 and the source of the PMOS transistor PM22 are both connected to the output end of the current source I0; the input end of the current source I0 is connected to the power supply VCC;

[0093] The gate of the PMOS transistor PM21 is connected to the drain of the NMOS transistor NM29, and the gate of the PMOS transistor PM22 is connected to the source of the NMOS transistor NM29; the gate of the NMOS transistor NM29 is connected to the clock signal TSD_RESET;

[0094] The drain of the PMOS tube PM21 is simultaneously connected to the drain of the NMOS tube NM24, the drain of the NMOS tube NM22, the gate of the NMOS tube NM21, the gate of the NMOS tube NM22, the gate of the NMOS tube NM23, and the drain of the NMOS tube NM30;

[0095] The drain of the PMOS tube PM22 is simultaneously connected to the drain of the NMOS tube NM29, the drain of the NMOS tube NM23, the drain of the NMOS tube NM25, the gate of the NMOS tube NM24, the gate of the NMOS tube NM25, and the gate of the NMOS tube NM26;

[0096] The gate of the NMOS tube NM29 and the gate of the NMOS tube NM30 are both connected to the output end of the inverter INV21, and the input end of the inverter INV21 is connected to the clock signal TSD_EN;

[0097] The source of the NMOS tube NM29 and the source of the NMOS tube NM30 are both grounded;

[0098] The drain of the NMOS tube NM21 is simultaneously connected to the drain of the PMOS tube PM23, the gate of the PMOS tube PM23, the gate of the PMOS tube PM24, and the drain of the PMOS tube PM27; the gate of the PMOS tube PM27 is connected to the input end of the inverter INV21; the source of the PMOS tube PM27, the source of the PMOS tube PM23, and the source of the PMOS tube PM24 are all connected to the power supply VCC;

[0099] The source of the NMOS tube NM21, the source of the NMOS tube NM22, the source of the NMOS tube NM23, the source of the NMOS tube NM24, the source of the NMOS tube NM25, and the source of the NMOS tube NM26 are grounded;

[0100] The drain of the NMOS tube NM26 is simultaneously connected to the drain of the PMOS tube PM25, the gate of the PMOS tube PM25, the gate of the PMOS tube PM26, and the drain of the PMOS tube PM28; the gate of the PMOS tube PM28 is connected to the input end of the inverter INV21; the source of the PMOS tube PM28, the source of the PMOS tube PM25, and the source of the PMOS tube PM26 are all connected to the power supply VCC;

[0101] The drain of the PMOS tube PM24 is simultaneously connected to the drain of the NMOS tube NM31, the drain of the NMOS tube NM27, the gate of the NMOS tube NM27, and the gate of the NMOS tube NM28;

[0102] The drain of the PMOS tube PM26 is the output terminal of the comparator, and the drain of the PMOS tube PM26 is connected to the drain of the NMOS tube NM28 and the drain of the NMOS tube NM32 at the same time;

[0103] The gate of the NMOS tube NM31 is connected to the gate of the NMOS tube NM32 and the gate of the NMOS tube NM29 at the same time;

[0104] The source of the NMOS tube NM31, the source of the NMOS tube NM27, the source of the NMOS tube NM28, and the source of the NMOS tube NM32 are all grounded;

[0105] The comparator uses cross-coupled feedback technology to improve the response speed of the comparator to the input signal; because the comparator uses a fully symmetrical transconductance amplifier (OTA) architecture, this makes the comparator have a smaller system offset, which improves the detection accuracy of the comparator. In order to improve the response speed of the comparator, the comparator input needs to be RESET within a short period of time at the beginning of each cycle. On the one hand, this is to wait for the core analog circuit bias to be established to prevent errors; on the other hand, this is to improve the sensitivity of detecting differential input signals. There is no need to wait for the comparator input signal to stabilize before detection in each cycle. As long as the direction of change of the input signal is used, it can be detected whether the chip is overheated: during the TSD_RESET high level period, the input of the comparator is VBG, and the differential signal is 0. After the TSD_RESET high level ends, the positive temperature coefficient voltage of the comparator's in-phase input begins to change, which will cause the differential voltage at the comparator input to start changing. Due to the high sensitivity of the comparator, the differential voltage can be quickly flipped as long as it is greater than its minimum detectable voltage difference, so high-speed detection is achieved.

[0106] Figure 5It is a circuit schematic diagram of a logic circuit module proposed by the present invention. The logic circuit includes a D flip-flop D0, a D flip-flop D1, and a D flip-flop D2; an AND gate AND21; an inverter INV11 and an inverter INV12;

[0107] The input terminal D of the D flip-flop D0 is connected to the drain of the PMOS tube PM26 in the comparator;

[0108] The two input ends of the AND gate AND21 are connected to the clock signal TSD_EN and the clock signal TSD_CLK respectively, and the output end of the AND gate AND21 is simultaneously connected to the clock end CLK of the D flip-flop D0, the clock end CLK of the D flip-flop D1, and the clock end CLK of the D flip-flop D2;

[0109] The output terminal Q of the D flip-flop D0 is connected to the input terminal D of the D flip-flop D1; the output terminal Q of the D flip-flop D1 is connected to the input terminal D of the D flip-flop D2;

[0110] The output terminal Q of the D flip-flop D2 is connected to the input terminal of the inverter INV11, the output terminal of the inverter INV11 is connected to the input terminal of the inverter INV12, the output terminal of the inverter INV11 is the output terminal of the logic circuit, and the output terminal of the inverter INV11 outputs a signal TSD;

[0111] The input signal of the logic circuit is the comparator output signal TSD_CMP_OUT. This signal is latched through the synchronous cascade of three D flip-flops, which is equivalent to the over-temperature signal being received by the system after three clock cycles, and has a certain filtering effect. When the over-temperature signal is triggered, the TSD signal is provided to the positive temperature coefficient voltage generation module to change the current over-temperature protection temperature detection point. TSD_EN and TSD_CLK constitute a gated clock signal, which latches the D input signal of the D flip-flop at each rising edge of TSD_CLK.

[0112] The purpose of the present invention is to solve the problem that traditional over-temperature protection circuits cannot achieve high reliability and low power consumption, and propose a new over-temperature protection system architecture circuit, chip and electronic device.

[0113] The over-temperature protection circuit architecture provided by the present invention includes a positive temperature coefficient voltage generator, which is used to generate a voltage signal proportional to the temperature; a voltage comparator, which generates an over-temperature protection signal that is not latched by comparing the positive temperature coefficient voltage and the bandgap reference voltage; an over-temperature protection logic circuit, which is used to latch the over-temperature protection signal output by the comparator into a memory, and change the over-temperature protection detection temperature point by feeding back the latched signal to the positive temperature voltage generator, thereby realizing the over-temperature protection hysteresis function.

[0114] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. Therefore, the embodiments should be considered exemplary and non-restrictive from any point of view. The scope of the present invention is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present invention, and any reference numerals in the claims should not be considered as limiting the claims involved.

[0115] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A digitally implemented low power consumption and high reliability over-temperature protection circuit, characterized in that: It includes a positive temperature coefficient voltage generator, a comparator and a logic circuit; one input end of the positive temperature coefficient voltage generator is connected to a clock signal TSD_EN; the other input end of the positive temperature coefficient voltage generator is connected to an output signal TSD of the logic circuit; The output terminal of the positive temperature coefficient voltage generator is connected to the positive input terminal of the comparator, and the negative input terminal of the comparator is connected to the reference voltage VBG; The comparator is connected to the synchronous control clock signal TSD_EN and the clock signal TSD_RESET; The output terminal of the comparator is connected to an input terminal of the logic circuit, and the output terminal of the comparator outputs a signal TSD_CMP_OUT; The clock input terminal of the logic circuit is connected to the clock signal TSD_EN and the clock signal TSD_CLK; The output terminal of the logic circuit outputs a signal TSD.

2. A digitally implemented low power consumption and high reliability over-temperature protection circuit according to claim 1, characterized in that: The positive temperature coefficient voltage generator includes PMOS tube PM31, PMOS tube PM32, PMOS tube PM33, PMOS tube PM34, PMOS tube PM35, PMOS tube PM36, PMOS tube PM37; NMOS tube NM33, NMOS tube NM34, NMOS tube NM35, NMOS tube NM36; resistors R1, R2, R3; capacitor C1; current source I31; inverters INV31, INV32; The input end of the inverter INV31 is connected to the clock signal TSD_EN; the input end of the inverter INV32 is connected to the output signal TSD of the logic circuit; The output end of the inverter INV31 is connected to the gate of the NMOS tube NM35; the source of the NMOS tube NM35 is grounded; The output end of the inverter INV32 is connected to the gate of the NMOS tube NM36, and the drain of the NMOS tube NM36 is connected to one end of the resistor R2 and one end of the resistor R3 at the same time; the other end of the resistor R2 is connected to the drain of the NMOS tube NM35, and the source of the NMOS tube NM36 is grounded; the other end of the resistor R3 is grounded; The input end of the inverter INV31 is connected to the gate of the PMOS tube PM35 and the gate of the PMOS tube PM36 at the same time; The drain of the PMOS transistor PM36 is simultaneously connected to the drain of the PMOS transistor PM34, the gate of the PMOS transistor PM37, and the input end of the current source I31; the output end of the current source I31 is grounded; The drain of the PMOS tube PM35 is simultaneously connected to the gate of the PMOS tube PM34, the gate of the PMOS tube PM31, the gate of the PMOS tube PM32, and the gate of the PMOS tube PM33; The drain of the PMOS tube PM37 is simultaneously connected to the drain of the PMOS tube PM31, the drain of the NMOS tube NM33, the gate of the NMOS tube NM33, and the gate of the NMOS tube NM34; The gate of the PMOS tube PM32 is connected to the drain of the PMOS tube PM32 and the drain of the NMOS tube NM34 at the same time; The drain of the PMOS tube PM33 is connected to the drain of the NMOS tube NM35; The source of the NMOS tube NM33 is connected to the emitter of the transistor Q31; the base of the transistor Q31 and the collector of the transistor Q31 are both grounded; The source of the NMOS tube NM34 is connected to one end of the resistor R1 , and the other end of the resistor R1 is connected to the emitter of the transistor Q32 ; the base of the transistor Q32 and the collector of the transistor Q32 are both grounded.

3. A digitally implemented low power consumption and high reliability over-temperature protection circuit according to claim 2, characterized in that: One input end of the positive temperature coefficient voltage generator is the input end of the inverter INV31; the other input end of the positive temperature coefficient voltage generator is the input end of the inverter INV32, and the drain of the NMOS tube NM35 is the output end of the positive temperature coefficient voltage generator.

4. A digitally implemented low power consumption and high reliability over-temperature protection circuit according to claim 3, characterized in that: The drain of the NMOS tube NM35 is connected to the positive electrode of the capacitor C1, and the negative electrode of the capacitor C1 is grounded.

5. A digitally implemented low power consumption and high reliability over-temperature protection circuit according to claim 4, characterized in that: The source of the PMOS transistor PM35 in the positive temperature coefficient voltage generator is connected to the power source VCC, and the source of the PMOS transistor PM36 is connected to the power source VCC.

6. A digitally implemented low power consumption and high reliability over-temperature protection circuit according to claim 5, characterized in that: The source of the PMOS transistor PM34 , the source of the PMOS transistor PM31 , the source of the PMOS transistor PM32 , and the source of the PMOS transistor PM33 in the positive temperature coefficient voltage generator are all connected to the power source VCC.

7. A digitally implemented low power consumption and high reliability over-temperature protection circuit according to claim 6, characterized in that: The source of the PMOS transistor PM37 in the positive temperature coefficient voltage generator is connected to the power supply VCC.

8. The digitally implemented low power consumption and high reliability over-temperature protection circuit according to claim 1, characterized in that: The comparator includes PMOS tube PM21, PMOS tube PM22, PMOS tube PM23, PMOS tube PM24, PMOS tube PM25, PMOS tube PM26, PMOS tube PM27, PMOS tube PM28; NMOS tube NM21, NMOS tube NM22, NMOS tube NM23, NMOS tube NM24, NMOS tube NM25, NMOS tube NM26, NMOS tube NM27, NMOS tube NM28, NMOS tube NM29, NMOS tube NM30, NMOS tube NM31, NMOS tube NM32; current source I0; inverter INV21; The gate of the PMOS tube PM21 is connected to the drain of the NMOS tube NM35 in the positive temperature coefficient voltage generator; The gate of the PMOS tube PM22 is connected to the reference voltage VBG; The source of the PMOS transistor PM21 and the source of the PMOS transistor PM22 are both connected to the output end of the current source I0; the input end of the current source I0 is connected to the power supply VCC; The gate of the PMOS transistor PM21 is connected to the drain of the NMOS transistor NM29, and the gate of the PMOS transistor PM22 is connected to the source of the NMOS transistor NM29; the gate of the NMOS transistor NM29 is connected to the clock signal TSD_RESET; The drain of the PMOS tube PM21 is simultaneously connected to the drain of the NMOS tube NM24, the drain of the NMOS tube NM22, the gate of the NMOS tube NM21, the gate of the NMOS tube NM22, the gate of the NMOS tube NM23, and the drain of the NMOS tube NM30; The drain of the PMOS tube PM22 is simultaneously connected to the drain of the NMOS tube NM29, the drain of the NMOS tube NM23, the drain of the NMOS tube NM25, the gate of the NMOS tube NM24, the gate of the NMOS tube NM25, and the gate of the NMOS tube NM26; The gate of the NMOS tube NM29 and the gate of the NMOS tube NM30 are both connected to the output end of the inverter INV21, and the input end of the inverter INV21 is connected to the clock signal TSD_EN; The source of the NMOS tube NM29 and the source of the NMOS tube NM30 are both grounded; The drain of the NMOS tube NM21 is simultaneously connected to the drain of the PMOS tube PM23, the gate of the PMOS tube PM23, the gate of the PMOS tube PM24, and the drain of the PMOS tube PM27; the gate of the PMOS tube PM27 is connected to the input end of the inverter INV21; the source of the PMOS tube PM27, the source of the PMOS tube PM23, and the source of the PMOS tube PM24 are all connected to the power supply VCC; The source of the NMOS tube NM21, the source of the NMOS tube NM22, the source of the NMOS tube NM23, the source of the NMOS tube NM24, the source of the NMOS tube NM25, and the source of the NMOS tube NM26 are grounded; The drain of the NMOS tube NM26 is simultaneously connected to the drain of the PMOS tube PM25, the gate of the PMOS tube PM25, the gate of the PMOS tube PM26, and the drain of the PMOS tube PM28; the gate of the PMOS tube PM28 is connected to the input end of the inverter INV21; the source of the PMOS tube PM28, the source of the PMOS tube PM25, and the source of the PMOS tube PM26 are all connected to the power supply VCC; The drain of the PMOS tube PM24 is simultaneously connected to the drain of the NMOS tube NM31, the drain of the NMOS tube NM27, the gate of the NMOS tube NM27, and the gate of the NMOS tube NM28; The drain of the PMOS tube PM26 is connected to the drain of the NMOS tube NM28 and the drain of the NMOS tube NM32 at the same time; The gate of the NMOS tube NM31 is connected to the gate of the NMOS tube NM32 and the gate of the NMOS tube NM29 at the same time; The source of the NMOS tube NM31 , the source of the NMOS tube NM27 , the source of the NMOS tube NM28 , and the source of the NMOS tube NM32 are all grounded.

9. A digitally implemented low power consumption and high reliability over-temperature protection circuit according to claim 8, characterized in that: The gate of the PMOS transistor PM21 is the positive input terminal of the comparator, the gate of the PMOS transistor PM22 is the negative input terminal of the comparator, and the drain of the PMOS transistor PM26 is the output terminal of the comparator.

10. The digitally implemented low power consumption and high reliability over-temperature protection circuit according to claim 1, characterized in that: The logic circuit includes D flip-flops D0, D flip-flops D1, and D flip-flops D2; AND gate AND21; inverters INV11 and INV12; The input terminal D of the D flip-flop D0 is connected to the drain of the PMOS tube PM26 in the comparator; The two input ends of the AND gate AND21 are connected to the clock signal TSD_EN and the clock signal TSD_CLK respectively, and the output end of the AND gate AND21 is simultaneously connected to the clock end CLK of the D flip-flop D0, the clock end CLK of the D flip-flop D1, and the clock end CLK of the D flip-flop D2; The output terminal Q of the D flip-flop D0 is connected to the input terminal D of the D flip-flop D1; the output terminal Q of the D flip-flop D1 is connected to the input terminal D of the D flip-flop D2; The output terminal Q of the D flip-flop D2 is connected to the input terminal of the inverter INV11, the output terminal of the inverter INV11 is connected to the input terminal of the inverter INV12, the output terminal of the inverter INV11 is the output terminal of the logic circuit, and the output terminal of the inverter INV11 outputs the signal TSD.

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