A Hybrid Integrated Circuit Intelligent Detection Method and System

Abstract

This invention relates to the field of circuit testing and management technology, and particularly to an intelligent testing method and system for hybrid integrated circuits. The method includes the following steps: Preparing for testing by installing an electrical parameter tester, an infrared thermal imager, and an electromagnetic compatibility analyzer at different ports and key locations within the hybrid integrated circuit, thereby generating a fully tested hybrid integrated circuit; initiating synchronous acquisition according to a preset synchronous acquisition frequency to generate an electrical parameter set, chip operating temperature distribution, and electromagnetic radiation spectrum of circuit operation; performing fault detection based on the electrical parameter set, chip operating temperature distribution, and electromagnetic radiation spectrum of circuit operation, generating corresponding fault detection results; and recommending repair methods for the corresponding hybrid integrated circuit, generating recommended repair schemes for the fault severity of the hybrid integrated circuit, and executing the corresponding hybrid integrated circuit fault repair work. This invention can analyze and feedback the test results in real time and accurately.

Description

Technical Field

[0001] This invention relates to the field of circuit testing and management technology, and in particular to a hybrid integrated circuit intelligent testing method and system. Background Technology

[0002] Hybrid integrated circuits combine multiple technologies such as semiconductor integrated circuits, thick-film integrated circuits, and thin-film integrated circuits. Their complex internal structures include active devices, passive components, and multi-layer interconnects. They are typically composed of different types of circuit components (such as silicon chips, ceramic substrates, inorganic materials, and organic materials), and the synergistic effect of their electrical and thermal properties significantly impacts the stability and efficiency of the entire system. However, traditional testing methods mainly rely on manual operation of specialized testing instruments, such as oscilloscopes and multimeters, to measure circuit parameters point by point. This is not only time-consuming and labor-intensive but also highly susceptible to human error, and suffers from problems such as internal micro-short circuits, potential thermal issues, and electromagnetic crosstalk between multi-layer interconnects, leading to inaccurate test results. Summary of the Invention

[0003] Therefore, it is necessary for the present invention to provide a hybrid integrated circuit intelligent detection method and system to solve at least one of the above-mentioned technical problems.

[0004] To achieve the above objectives, a hybrid integrated circuit intelligent detection method includes the following steps:

[0005] Step S1: Prepare for testing by installing electrical parameter testers, infrared thermal imagers, and electromagnetic compatibility analyzers at different ports and key locations within the hybrid integrated circuit, and fixing the hybrid integrated circuit with the test equipment installed on the test fixture, so as to generate a fully tested hybrid integrated circuit.

[0006] Step S2: Start the electrical parameter tester, infrared thermal imager, and electromagnetic compatibility analyzer to perform multi-mode synchronous data acquisition on the tested hybrid integrated circuit according to the preset synchronous acquisition frequency, so as to generate the electrical parameter set, chip operating temperature distribution, and electromagnetic radiation spectrum of the circuit operation corresponding to the hybrid integrated circuit; perform electrical fault detection on the tested hybrid integrated circuit based on the electrical parameter set corresponding to the hybrid integrated circuit, and generate circuit electrical fault detection results;

[0007] Step S3: Based on the chip operating temperature distribution and the electromagnetic radiation spectrum of the circuit operation corresponding to the hybrid integrated circuit, thermal failure and magnetic interference fault detection are performed on the tested hybrid integrated circuit to generate circuit thermal failure fault detection results and circuit electromagnetic interference fault detection results.

[0008] Step S4: Based on the circuit electrical fault detection results, circuit thermal failure fault detection results, or circuit electromagnetic interference fault detection results, recommend fault repair for the corresponding hybrid integrated circuit, generate a recommended repair scheme for the fault degree of the hybrid integrated circuit, and execute the corresponding hybrid integrated circuit fault repair work.

[0009] Furthermore, step S1 includes the following steps:

[0010] Step S11: Perform high-resolution X-ray tomography on the hybrid integrated circuit to generate internal three-dimensional structural information of the hybrid integrated circuit, so as to clearly present the circuit layout and electronic component connection method at different levels.

[0011] Step S12: Use an electron microscope to perform microscopic imaging detail analysis on the hybrid integrated circuit to obtain the corresponding microscopic structural details of the hybrid integrated circuit, so as to capture the micro solder joints and wire details of the circuit parts;

[0012] Step S13: Perform structural data fusion to construct the internal three-dimensional structural information and the minute structural details of the hybrid integrated circuit to generate an internal structural mapping map of the hybrid integrated circuit;

[0013] Step S14: Based on the internal structure mapping map of the hybrid integrated circuit, predict the key detection points of each port part in the hybrid integrated circuit to predict and extract the nodes on the high-frequency signal transmission path of the circuit and the pins of electronic components with large power dissipation, and generate the detection points of different ports and key parts corresponding to the hybrid integrated circuit; install electrical parameter testers, infrared thermal imagers and electromagnetic compatibility analyzers at the detection points of different ports and key parts corresponding to the hybrid integrated circuit.

[0014] Step S15: Obtain the physical dimensions and surface material characteristics of the hybrid integrated circuit; fix the hybrid integrated circuit after installation on the testing equipment onto the test fixture, and perform adaptation and calibration of the testing equipment corresponding to the hybrid integrated circuit based on the physical dimensions and surface material characteristics of the hybrid integrated circuit, so as to adaptively adjust the measurement range and sensitivity of the testing equipment, and generate calibration testing equipment adaptation and installation parameters; prepare the testing equipment corresponding to the hybrid integrated circuit for testing based on the calibration testing equipment adaptation and installation parameters, so as to generate a fully tested hybrid integrated circuit.

[0015] Furthermore, step S2 includes the following steps:

[0016] Step S21: Start the electrical parameter tester, infrared thermal imager and electromagnetic compatibility analyzer to perform multi-mode data synchronous acquisition on the tested hybrid integrated circuit according to the preset synchronous acquisition frequency, so as to generate the electrical parameter set, chip operating temperature distribution and electromagnetic radiation spectrum of the circuit operation corresponding to the hybrid integrated circuit.

[0017] Step S22: Perform time synchronization processing on the electrical parameter set corresponding to the hybrid integrated circuit to generate the electrical parameter set corresponding to the hybrid integrated circuit in the same time range;

[0018] Step S23: Obtain the rated current, rated voltage, calibration resistor, and calibration capacitor corresponding to the hybrid integrated circuit;

[0019] Step S24: Obtain the characteristic parameters of the electronic components corresponding to the hybrid integrated circuit, and perform an acceptable fluctuation range analysis on each electrical parameter of the hybrid integrated circuit based on the characteristic parameters of the electronic components corresponding to the hybrid integrated circuit to obtain the acceptable fluctuation range value of each electrical parameter of the hybrid integrated circuit; determine the maximum and minimum thresholds of the corresponding acceptable fluctuation range values ​​based on the rated current, rated voltage, rated resistor, and rated capacitor of the hybrid integrated circuit to obtain the maximum and minimum thresholds of each electrical parameter of the hybrid integrated circuit.

[0020] Step S25: Based on the electrical parameter set corresponding to the hybrid integrated circuit in the same time range, perform electrical fault detection on the maximum and minimum thresholds corresponding to each electrical parameter of the hybrid integrated circuit, and generate circuit electrical fault detection results.

[0021] Furthermore, the electrical parameter set mentioned in step S21 specifically includes the current, voltage, resistance, and capacitance parameters corresponding to the hybrid integrated circuit.

[0022] Furthermore, step S25 includes the following steps:

[0023] Timing point extraction is performed on the electrical parameter set corresponding to the hybrid integrated circuit under the same timing range to obtain the specific values ​​of each electrical parameter of the hybrid integrated circuit at each timing point, including the specific values ​​of current, voltage, resistance and capacitance.

[0024] If the specific value of the current corresponding to each timing point of the hybrid integrated circuit is less than the minimum current threshold of the hybrid integrated circuit and the specific value of the voltage corresponding to each timing point of the hybrid integrated circuit is normal, then the hybrid integrated circuit is detected to have an open circuit fault.

[0025] If the specific value of the current corresponding to each timing point of the hybrid integrated circuit is greater than the maximum current threshold of the hybrid integrated circuit and the specific value of the voltage corresponding to each timing point of the hybrid integrated circuit is less than the minimum voltage threshold of the hybrid integrated circuit, then a short circuit fault is detected in the hybrid integrated circuit.

[0026] If the specific current value of the hybrid integrated circuit at each timing point is zero and the specific voltage value of the hybrid integrated circuit at each timing point is normal, then the hybrid integrated circuit is detected to have an open circuit fault.

[0027] If the specific value of the resistor corresponding to each timing point of the hybrid integrated circuit is greater than the maximum resistance threshold or less than the minimum resistance threshold, or if the specific value of the capacitor corresponding to each timing point of the hybrid integrated circuit is greater than the maximum capacitance threshold or less than the minimum capacitance threshold, then the hybrid integrated circuit is detected to have a parameter drift fault.

[0028] Furthermore, step S3 includes the following steps:

[0029] Step S31: Obtain the dimensions, spacing, and arrangement of electronic components near the chip within the tested hybrid integrated circuit;

[0030] Step S32: Perform chip thermal conduction topology analysis on the tested hybrid integrated circuit based on the size, spacing and arrangement of electronic components to clearly show the thermal conduction network from the heat-generating components to the heat dissipation path, and obtain the internal thermal conduction topology network of the circuit chip.

[0031] Step S33: Perform thermal stress distribution analysis on the tested hybrid integrated circuit based on the internal thermal conduction topology network of the circuit chip to generate the thermal stress distribution field of the circuit chip corresponding to the hybrid integrated circuit.

[0032] Step S34: Based on the thermal stress distribution field of the circuit chip corresponding to the hybrid integrated circuit, perform thermal failure detection on the corresponding fully tested hybrid integrated circuit, so as to determine each thermal anomaly sensitive area according to the thermal stress distribution of each part of the chip, and determine whether the corresponding thermal failure phenomenon occurs based on the temperature change of each thermal anomaly sensitive area according to the preset thermal failure critical temperature threshold, so as to generate circuit thermal failure detection results.

[0033] Step S35: Perform electromagnetic interference fault detection on the tested hybrid integrated circuit based on the electromagnetic radiation spectrum of the circuit operation corresponding to the hybrid integrated circuit, so as to generate the circuit electromagnetic interference fault detection result.

[0034] Furthermore, step S35 includes the following steps:

[0035] Step S351: Obtain the layout and connection method of each electronic component and wire in the complete test hybrid integrated circuit, and evaluate the electromagnetic radiation interference impact of the complete test hybrid integrated circuit based on the layout and connection method of each electronic component and wire to generate an electromagnetic radiation interference impact factor.

[0036] Step S352: Obtain the electromagnetic spectrum of the circuit under normal operation corresponding to the hybrid integrated circuit, and perform electromagnetic phase difference analysis on the electromagnetic radiation spectrum of the circuit operation based on the electromagnetic spectrum of the circuit under normal operation corresponding to the hybrid integrated circuit to obtain the electromagnetic radiation phase difference of the integrated circuit operation.

[0037] Step S353: Perform electromagnetic interference amplitude and frequency analysis on the electromagnetic radiation spectrum of the circuit corresponding to the hybrid integrated circuit to obtain the electromagnetic interference amplitude and frequency of the integrated circuit.

[0038] Step S354: Based on the electromagnetic radiation interference influence factor, the electromagnetic radiation phase difference of the integrated circuit operation, the electromagnetic interference amplitude of the integrated circuit, and the electromagnetic interference frequency of the integrated circuit, the electromagnetic interference calculation formula is used to calculate the electromagnetic interference of the electromagnetic radiation spectrum of the circuit operation corresponding to the hybrid integrated circuit, and the electromagnetic radiation interference value corresponding to the hybrid integrated circuit is obtained.

[0039] Step S355: Compare and judge the electromagnetic radiation interference value corresponding to the hybrid integrated circuit according to the preset circuit electromagnetic interference fault threshold. If the electromagnetic radiation interference value is greater than or equal to the preset circuit electromagnetic interference fault threshold, it is determined that the hybrid integrated circuit has external electromagnetic source interference; if the electromagnetic radiation interference value is less than the preset circuit electromagnetic interference fault threshold, it is determined that the hybrid integrated circuit has electromagnetic interference generated by the internal circuit, so as to generate the circuit electromagnetic interference fault detection result.

[0040] Furthermore, the electromagnetic radiation interference calculation formula mentioned in step S354 is as follows:

[0041] ;

[0042] In the formula, This represents the electromagnetic radiation interference value. The time interval for electromagnetic interference calculation. For time-varying parameters, This refers to the total components of the corresponding frequency elements within the electromagnetic radiation spectrum during circuit operation. The first in the electromagnetic radiation spectrum of the circuit operation The electromagnetic interference amplitude of the integrated circuit corresponding to each frequency component. The first in the electromagnetic radiation spectrum of the circuit operation The electromagnetic interference frequencies of integrated circuits corresponding to each frequency component. The first in the electromagnetic radiation spectrum of the circuit operation The electromagnetic radiation phase difference between each frequency component and the normal operating electromagnetic spectrum The frequency components of electromagnetic radiation For the first Electromagnetic radiation attenuation factor corresponding to each frequency component. For the first Electromagnetic interference suppression constants corresponding to each frequency component. This is a correction factor for the electromagnetic radiation interference value.

[0043] Furthermore, step S4 includes the following steps:

[0044] Step S41: Based on the circuit electrical fault detection results, circuit thermal failure fault detection results, or circuit electromagnetic interference fault detection results, perform fault mode feature analysis on the corresponding hybrid integrated circuits to extract the abnormal current and voltage fluctuations of the corresponding electrical faults, the uneven temperature distribution of the thermal failure faults, and the abnormal spectrum features of the electromagnetic interference faults for each fault type, and clarify the relationship between different fault types and features to obtain the abnormal fault mode features corresponding to the hybrid integrated circuits.

[0045] Step S42: Based on the abnormal characteristics of the fault modes corresponding to the hybrid integrated circuit, perform in-depth analysis of the fault root causes of the hybrid integrated circuit to identify the fault root cause clues hidden under the fault manifestations of the hybrid integrated circuit, so as to generate: circuit fault root cause in-depth analysis clue set.

[0046] Step S43: Based on the clue set of in-depth analysis of the root causes of circuit faults, recommend repair solutions for hybrid integrated circuits and generate recommended repair solutions for the fault severity of the hybrid integrated circuits. For electrical faults, electronic component replacement and circuit rewiring strategies are adopted. For thermal failure faults, heat dissipation system optimization and electronic component de-rating are involved. For electromagnetic interference faults, if they are caused by external electromagnetic sources, electromagnetic shielding is added to effectively block external interference from entering the hybrid integrated circuit. If the electromagnetic interference is generated by internal circuits, the circuit layout is redesigned to reduce crosstalk between signals, and the corresponding hybrid integrated circuit fault repair work is performed.

[0047] Furthermore, the present invention also provides a hybrid integrated circuit intelligent testing system for performing the hybrid integrated circuit intelligent testing method described above, the hybrid integrated circuit intelligent testing system comprising:

[0048] The circuit testing preparation module is used to prepare for testing by installing electrical parameter testers, infrared thermal imagers and electromagnetic compatibility analyzers at different ports and key parts of the hybrid integrated circuit, and fixing the hybrid integrated circuit with the testing equipment installed on the test fixture, so as to generate a fully tested hybrid integrated circuit.

[0049] The synchronous acquisition and electrical detection module is used to activate the electrical parameter tester, infrared thermal imager, and electromagnetic compatibility analyzer according to the preset synchronous acquisition frequency to synchronously acquire multi-modal data of the tested hybrid integrated circuit, so as to generate the electrical parameter set, chip operating temperature distribution, and electromagnetic radiation spectrum of the circuit operation corresponding to the hybrid integrated circuit; and to perform electrical fault detection on the tested hybrid integrated circuit based on the electrical parameter set corresponding to the hybrid integrated circuit, thereby generating the circuit electrical fault detection results.

[0050] The thermal failure and electromagnetic interference detection module is used to perform thermal failure and electromagnetic interference fault detection on the tested hybrid integrated circuit based on the chip operating temperature distribution and the electromagnetic radiation spectrum of the circuit operation, so as to generate circuit thermal failure fault detection results and circuit electromagnetic interference fault detection results.

[0051] The circuit fault recommendation and repair module is used to recommend and repair faults for corresponding hybrid integrated circuits based on the circuit electrical fault detection results, circuit thermal failure fault detection results, or circuit electromagnetic interference fault detection results, and generate a recommended repair scheme for the fault degree of the hybrid integrated circuit to perform the corresponding hybrid integrated circuit fault repair work.

[0052] The beneficial effects of this invention are:

[0053] 1. Compared with existing technologies, the intelligent testing method for hybrid integrated circuits proposed in this invention has the following advantages: By installing an electrical parameter tester, an infrared thermal imager, and an electromagnetic compatibility analyzer at key locations within the hybrid integrated circuit, a foundation is laid for subsequent multimodal data acquisition. The key to this process lies in the precise selection of testing instruments, enabling detailed electrical and physical testing of different ports and key locations within the hybrid integrated circuit. This multidimensional testing and inspection allows for a comprehensive evaluation of the hybrid integrated circuit's operating status and provides strong support for subsequent fault diagnosis. Fixing the testing equipment and placing the circuit on a test fixture ensures that the equipment is not affected by external interference or vibration during testing, further improving the accuracy and reliability of the test data. Secondly, by preset a synchronous acquisition frequency, the electrical parameter tester, infrared thermal imager, and electromagnetic compatibility analyzer are activated for synchronous data acquisition. The key to this process is the synchronous acquisition of multimodal data, including electrical parameters, chip operating temperature distribution, and electromagnetic radiation spectrum, enabling comprehensive analysis of fault detection from multiple perspectives and improving the accuracy of fault diagnosis. Electrical fault detection based on this data can detect electrical anomalies in circuits in real time, such as overcurrent, short circuits, or open circuits, thereby identifying potential fault risks at an early stage and ensuring the reliability and safety of the circuit. Then, by utilizing the chip's operating temperature distribution and electromagnetic radiation spectrum, thermal failure and electromagnetic interference fault detection are performed on hybrid integrated circuits. Thermal failure detection uses temperature data collected by an infrared thermal imager to identify overheating phenomena in the circuit. During the operation of electronic equipment, excessive temperature is often a key factor causing circuit failures, leading to component performance degradation or even damage. Furthermore, electromagnetic interference fault detection analyzes the electromagnetic radiation spectrum collected by an electromagnetic compatibility analyzer to assess whether the electromagnetic radiation generated during circuit operation exceeds safe limits or interferes with other devices. This allows for timely adjustments to the circuit design or the implementation of effective shielding measures to reduce the impact of electromagnetic interference on other systems. This enables real-time detection of internal micro-short circuits, potential thermal failures, and crosstalk between multilayer interconnects, providing crucial support for ensuring the reliability of hybrid integrated circuits under extreme operating environments and contributing to the optimization of overall circuit performance and anti-interference capabilities.Finally, by recommending fault repair solutions for hybrid integrated circuits based on the detection results of electrical faults, thermal failure faults, or electromagnetic interference faults, a comprehensive understanding of the types and severity of faults present in different aspects of the circuit can be achieved. For example, electrical faults involve component performance degradation or short circuits / open circuits; thermal failures are related to improper heat dissipation design or component overload; and electromagnetic interference problems are caused by poor electromagnetic shielding or grounding design. By systematically analyzing these faults, customized repair solutions can be provided for hybrid integrated circuits, including replacing damaged components, optimizing circuit design, improving heat dissipation performance, and adding electromagnetic shielding layers. This process not only helps improve the stability and performance of the circuit but also extends its service life and prevents equipment downtime and production losses caused by faults. It can greatly improve the efficiency of fault handling while ensuring the scientific validity and effectiveness of the repair solutions.

[0054] 2. The hybrid integrated circuit intelligent testing system proposed in this invention consists of a circuit testing preparation module, a synchronous acquisition and electrical testing module, a thermal failure and electromagnetic interference detection module, and a circuit fault recommendation and repair module. It can realize any hybrid integrated circuit intelligent testing method described in this invention. It is used to combine the operations between the computer programs running on each module to realize the hybrid integrated circuit intelligent testing method. The internal structure of the system cooperates with each other, which can greatly reduce repetitive work and manpower input, and can quickly and effectively provide a more accurate and efficient hybrid integrated circuit intelligent testing process, thereby simplifying the operation process of the hybrid integrated circuit intelligent testing system. Attached Figure Description

[0055] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0056] Figure 1 This is a schematic diagram of the steps of the intelligent detection method for hybrid integrated circuits of the present invention;

[0057] Figure 2 for Figure 1 A detailed flowchart of step S1;

[0058] Figure 3 for Figure 1 A detailed flowchart of step S2. Detailed Implementation

[0059] The technical method of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0060] Furthermore, the accompanying drawings are merely illustrative of the invention and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor methods and / or microcontroller methods.

[0061] It should be understood that although the terms "first," "second," etc., may be used herein to describe various units, these units should not be limited by these terms. These terms are used merely to distinguish one unit from another. For example, without departing from the scope of the exemplary embodiments, a first unit may be referred to as a second unit, and similarly, a second unit may be referred to as a first unit. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0062] To achieve the above objectives, please refer to Figures 1 to 3 This invention provides a hybrid integrated circuit intelligent detection method, the method comprising the following steps:

[0063] Step S1: Prepare for testing by installing electrical parameter testers, infrared thermal imagers, and electromagnetic compatibility analyzers at different ports and key locations within the hybrid integrated circuit, and fixing the hybrid integrated circuit with the test equipment installed on the test fixture, so as to generate a fully tested hybrid integrated circuit.

[0064] Step S2: Start the electrical parameter tester, infrared thermal imager, and electromagnetic compatibility analyzer to perform multi-mode synchronous data acquisition on the tested hybrid integrated circuit according to the preset synchronous acquisition frequency, so as to generate the electrical parameter set, chip operating temperature distribution, and electromagnetic radiation spectrum of the circuit operation corresponding to the hybrid integrated circuit; perform electrical fault detection on the tested hybrid integrated circuit based on the electrical parameter set corresponding to the hybrid integrated circuit, and generate circuit electrical fault detection results;

[0065] Step S3: Based on the chip operating temperature distribution and the electromagnetic radiation spectrum of the circuit operation corresponding to the hybrid integrated circuit, thermal failure and magnetic interference fault detection are performed on the tested hybrid integrated circuit to generate circuit thermal failure fault detection results and circuit electromagnetic interference fault detection results.

[0066] Step S4: Based on the circuit electrical fault detection results, circuit thermal failure fault detection results, or circuit electromagnetic interference fault detection results, recommend fault repair for the corresponding hybrid integrated circuit, generate a recommended repair scheme for the fault degree of the hybrid integrated circuit, and execute the corresponding hybrid integrated circuit fault repair work.

[0067] In the embodiments of this invention, please refer to Figure 1 The diagram shown is a flowchart illustrating the steps of the intelligent detection method for hybrid integrated circuits according to the present invention. In this example, the intelligent detection method for hybrid integrated circuits includes the following steps:

[0068] Step S1: Prepare for testing by installing electrical parameter testers, infrared thermal imagers, and electromagnetic compatibility analyzers at different ports and key locations within the hybrid integrated circuit, and fixing the hybrid integrated circuit with the test equipment installed on the test fixture, so as to generate a fully tested hybrid integrated circuit.

[0069] In this embodiment of the invention, by accurately selecting and installing an electrical parameter tester, an infrared thermal imager, and an electromagnetic compatibility analyzer, the equipment is ensured to comprehensively measure the electrical parameters, thermal parameters, and electromagnetic radiation of the hybrid integrated circuit. Specifically, the electrical parameter tester is installed at different ports and key parts of the hybrid integrated circuit, such as input / output terminals, power amplifiers, and power supply sections, to capture electrical data such as voltage, current, resistance, and capacitance. Simultaneously, the infrared thermal imager should be installed on the chip surface and circuit board surface to ensure real-time monitoring of the temperature distribution of the hybrid integrated circuit. The electromagnetic compatibility analyzer is installed around the circuit to detect the intensity and spectrum of electromagnetic radiation. All testing instruments must be fixed in standard test fixtures after installation to prevent positional shifts during testing, thereby ensuring the accuracy of the test results. The fixtures must not only stabilize the position of the equipment but also ensure good contact between the equipment and the circuit to ensure smooth signal transmission. Through this step, the preliminary testing preparation work for the hybrid integrated circuit is completed, ensuring the smooth progress of subsequent multimodal data acquisition and ultimately generating a fully tested hybrid integrated circuit.

[0070] Step S2: Start the electrical parameter tester, infrared thermal imager, and electromagnetic compatibility analyzer to perform multi-mode synchronous data acquisition on the tested hybrid integrated circuit according to the preset synchronous acquisition frequency, so as to generate the electrical parameter set, chip operating temperature distribution, and electromagnetic radiation spectrum of the circuit operation corresponding to the hybrid integrated circuit; perform electrical fault detection on the tested hybrid integrated circuit based on the electrical parameter set corresponding to the hybrid integrated circuit, and generate circuit electrical fault detection results;

[0071] In this embodiment of the invention, an electrical parameter tester, an infrared thermal imager, and an electromagnetic compatibility analyzer are activated simultaneously for data acquisition according to a preset synchronous acquisition frequency. First, after the electrical parameter tester is activated, it automatically scans various key nodes of the circuit, including electrical parameters such as voltage, current, resistance, and capacitance, based on its acquisition frequency, and records this data to form an electrical parameter set. The infrared thermal imager then begins to scan the circuit surface in real time, generating a temperature distribution map of the chip's working area and detecting hot spots in the circuit using thermal imaging technology. The electromagnetic compatibility analyzer begins to collect electromagnetic radiation generated during circuit operation, measuring the electromagnetic radiation spectrum, with particular attention to the generation of high-frequency noise. The three instruments work synchronously to ensure multi-dimensional data coverage, encompassing important indicators such as electrical performance, thermal performance, and electromagnetic compatibility. Through this operation, the system can acquire complete operating status data of the hybrid integrated circuit in real time. Simultaneously, based on this multi-modal data, electrical faults are further detected. By analyzing the electrical parameter set, electrical faults in the circuit, such as open circuits, short circuits, open circuits, parameter drift, and overload, are identified in a timely manner, ultimately generating circuit electrical fault detection results.

[0072] Step S3: Based on the chip operating temperature distribution and the electromagnetic radiation spectrum of the circuit operation corresponding to the hybrid integrated circuit, thermal failure and magnetic interference fault detection are performed on the tested hybrid integrated circuit to generate circuit thermal failure fault detection results and circuit electromagnetic interference fault detection results.

[0073] In this embodiment of the invention, thermal failure and electromagnetic interference fault detection are performed based on previously collected temperature distribution and electromagnetic radiation spectrum information. In this step, the temperature distribution map recorded by the infrared thermal imager is first used to analyze the temperature rise of each area of ​​the circuit, especially the current-intensive areas such as power pins, driver chips, and connecting components, to check for abnormal high temperatures. Excessive temperature rise can lead to thermal failure of components or short circuits. Therefore, the thermal failure detection algorithm can identify the parts whose temperature exceeds the normal operating range, thereby generating thermal failure fault detection results. At the same time, the electromagnetic radiation spectrum data provided by the electromagnetic compatibility analyzer is used to detect whether the circuit generates excessive electromagnetic interference, especially high-frequency noise. By comparing with standard electromagnetic radiation values, it is possible to identify whether there is an electromagnetic radiation spectrum that does not meet the specifications, thereby performing electromagnetic interference fault detection, and finally generating circuit thermal failure fault detection results and circuit electromagnetic interference fault detection results.

[0074] Step S4: Based on the circuit electrical fault detection results, circuit thermal failure fault detection results, or circuit electromagnetic interference fault detection results, recommend fault repair for the corresponding hybrid integrated circuit, generate a recommended repair scheme for the fault degree of the hybrid integrated circuit, and execute the corresponding hybrid integrated circuit fault repair work.

[0075] In this embodiment of the invention, based on previous fault detection results, corresponding fault repair schemes are automatically generated according to the detection results of electrical faults, thermal failure faults, or electromagnetic interference faults. Specifically, if the electrical fault detection results show that the circuit has an open circuit, short circuit, open circuit, or overload, it will recommend replacing the relevant components or adjusting the circuit design to reduce the current load; if the thermal failure fault detection results show that some components are overheating, it will suggest adding heat dissipation devices or improving the circuit layout to improve heat dissipation; and the electromagnetic interference fault detection results suggest that the shielding design of the circuit needs to be optimized or the operating frequency reduced. Based on the severity and scope of the fault type, a fault repair scheme is generated, and a repair priority is assigned to each repair scheme to guide subsequent repair operations. The repair scheme includes not only specific repair suggestions but also redesign of the circuit board or chip to ensure that the most effective measures are taken during the repair process, thereby ensuring that the hybrid integrated circuit can return to normal operation after repair. The core of this process is to tailor solutions through comprehensive analysis of multimodal data to ensure the accuracy and efficiency of the fault repair process, and finally generate a recommended repair scheme for the fault level of the hybrid integrated circuit to perform the corresponding hybrid integrated circuit fault repair work.

[0076] Furthermore, step S1 includes the following steps:

[0077] Step S11: Perform high-resolution X-ray tomography on the hybrid integrated circuit to generate internal three-dimensional structural information of the hybrid integrated circuit, so as to clearly present the circuit layout and electronic component connection method at different levels.

[0078] Step S12: Use an electron microscope to perform microscopic imaging detail analysis on the hybrid integrated circuit to obtain the corresponding microscopic structural details of the hybrid integrated circuit, so as to capture the micro solder joints and wire details of the circuit parts;

[0079] Step S13: Perform structural data fusion to construct the internal three-dimensional structural information and the minute structural details of the hybrid integrated circuit to generate an internal structural mapping map of the hybrid integrated circuit;

[0080] Step S14: Based on the internal structure mapping map of the hybrid integrated circuit, predict the key detection points of each port part in the hybrid integrated circuit to predict and extract the nodes on the high-frequency signal transmission path of the circuit and the pins of electronic components with large power dissipation, and generate the detection points of different ports and key parts corresponding to the hybrid integrated circuit; install electrical parameter testers, infrared thermal imagers and electromagnetic compatibility analyzers at the detection points of different ports and key parts corresponding to the hybrid integrated circuit.

[0081] Step S15: Obtain the physical dimensions and surface material characteristics of the hybrid integrated circuit; fix the hybrid integrated circuit after installation on the testing equipment onto the test fixture, and perform adaptation and calibration of the testing equipment corresponding to the hybrid integrated circuit based on the physical dimensions and surface material characteristics of the hybrid integrated circuit, so as to adaptively adjust the measurement range and sensitivity of the testing equipment, and generate calibration testing equipment adaptation and installation parameters; prepare the testing equipment corresponding to the hybrid integrated circuit for testing based on the calibration testing equipment adaptation and installation parameters, so as to generate a fully tested hybrid integrated circuit.

[0082] As an embodiment of the present invention, reference is made to... Figure 2 As shown, Figure 1 A detailed flowchart of step S1 is shown below. In this embodiment, step S1 includes the following steps:

[0083] Step S11: Perform high-resolution X-ray tomography on the hybrid integrated circuit to generate internal three-dimensional structural information of the hybrid integrated circuit, so as to clearly present the circuit layout and electronic component connection method at different levels.

[0084] In this embodiment of the invention, when performing high-resolution X-ray tomography on a hybrid integrated circuit, the hybrid integrated circuit sample is first placed on the sample holder of the X-ray tomography scanner to ensure its position is fixed. An appropriate X-ray energy is selected, usually a lower energy X-ray, to ensure that the circuit board can be effectively penetrated and detailed information can be obtained without damaging the circuit. Through X-ray scanning at multiple angles, the device will form different tomographic images based on the differences in the absorption rate of X-rays at different angles. Based on the tomographic images, a reconstruction algorithm such as filtered back projection or iterative reconstruction algorithm is used to generate a three-dimensional structural map of the hybrid integrated circuit. This image shows the internal structure of each layer of the circuit board, the wiring, and the position of electronic components. It can clearly present the hierarchical structure of the circuit board and the complex connection methods between circuits, which is especially helpful in identifying high-frequency signal paths and key nodes of power transmission. Finally, the internal three-dimensional structural information of the hybrid integrated circuit is generated.

[0085] Step S12: Use an electron microscope to perform microscopic imaging detail analysis on the hybrid integrated circuit to obtain the corresponding microscopic structural details of the hybrid integrated circuit, so as to capture the micro solder joints and wire details of the circuit parts;

[0086] In this embodiment of the invention, the hybrid integrated circuit sample is processed to a size suitable for microscopic observation. This typically involves cutting it into thin slices or using other methods such as polishing to ensure a smooth sample surface. The sample is then placed on the stage of an electron microscope, and the accelerating voltage and current parameters are adjusted. A suitable scanning mode (e.g., scanning electron microscope (SE mode) or backscattered electron microscope (BSE mode) is selected to ensure that the required high-resolution image can be acquired. During the scanning process, the electron microscope captures reflected or scattered electron signals by interacting with the sample surface through the electron beam, forming an image that shows solder joints and circuit connection lines. By adjusting the focal length and image enhancement algorithm, minute details of the circuit board can be observed, such as wire details, solder joint morphology, and contact quality of circuit connection points. These microscopic imaging details help reveal microscopic defects or soldering problems in the circuit, ultimately obtaining the structural minute detail information corresponding to the hybrid integrated circuit.

[0087] Step S13: Perform structural data fusion to construct the internal three-dimensional structural information and the minute structural details of the hybrid integrated circuit to generate an internal structural mapping map of the hybrid integrated circuit;

[0088] In this embodiment of the invention, by aligning the three-dimensional image generated by high-resolution X-ray tomography with the microscopic image from an electron microscope, and using an image matching algorithm, such as a feature-point-based matching method, the spatial positions of the two are ensured to be consistent. Then, a data fusion algorithm (such as a weighted average method or a mutual information method) is used to synthesize the structural data from the two different sources. The fused structural information will show the internal and surface structure of the circuit board, including multi-level details from macro to micro, and can accurately describe the position and interrelationship of each electronic component, wire, and solder point. This information will constitute a complete internal structure mapping map of the hybrid integrated circuit, which can help with subsequent circuit performance analysis and defect location, and finally generate the internal structure mapping map of the hybrid integrated circuit.

[0089] Step S14: Based on the internal structure mapping map of the hybrid integrated circuit, predict the key detection points of each port part in the hybrid integrated circuit to predict and extract the nodes on the high-frequency signal transmission path of the circuit and the pins of electronic components with large power dissipation, and generate the detection points of different ports and key parts corresponding to the hybrid integrated circuit; install electrical parameter testers, infrared thermal imagers and electromagnetic compatibility analyzers at the detection points of different ports and key parts corresponding to the hybrid integrated circuit.

[0090] In this embodiment of the invention, by analyzing the key areas of the circuit, particularly high-frequency signal transmission paths and pins of components with high power dissipation, based on the generated internal structure mapping map of the hybrid integrated circuit, the parts related to high-frequency signal transmission in the circuit diagram are first identified. These signal paths are usually closely related to the circuit layout, signal integrity, and current flow. Using simulation analysis tools (such as electromagnetic field simulation software), the signal transmission path is predicted, and areas of possible current density concentration are determined, especially wires through which current flows or pins of electronic components with high resistance. Then, by extracting data from the mapping map, key detection points in high-frequency signal transmission paths and high-power areas are determined, thereby generating detection points for different ports and key parts of the hybrid integrated circuit. To further improve the accuracy of detection, thermal simulation software can be used to predict the temperature rise area on the circuit, assisting in locating electronic components with severe heat generation. Electrical parameter testers, infrared thermal imagers, and electromagnetic compatibility analyzers are installed at the detection points of different ports and key parts of the hybrid integrated circuit.

[0091] Step S15: Obtain the physical dimensions and surface material characteristics of the hybrid integrated circuit; fix the hybrid integrated circuit after installation on the testing equipment onto the test fixture, and perform adaptation and calibration of the testing equipment corresponding to the hybrid integrated circuit based on the physical dimensions and surface material characteristics of the hybrid integrated circuit, so as to adaptively adjust the measurement range and sensitivity of the testing equipment, and generate calibration testing equipment adaptation and installation parameters; prepare the testing equipment corresponding to the hybrid integrated circuit for testing based on the calibration testing equipment adaptation and installation parameters, so as to generate a fully tested hybrid integrated circuit.

[0092] In this embodiment of the invention, after predicting the key testing points of the hybrid integrated circuit, the testing equipment is adapted and installed. First, the physical dimensions and surface material characteristics of the hybrid integrated circuit are determined, including the size, shape, surface coating, and material of the circuit board. Then, based on this physical information, the previously installed testing equipment, such as electrical parameter testers, infrared thermal imagers, and electromagnetic compatibility analyzers, is adapted and calibrated. For example, the measurement range and sensitivity of the equipment are adaptively adjusted to ensure that they can accurately respond to the electrical signals and thermal characteristics of the circuit. During equipment installation, precision clamps are used to firmly secure the hybrid integrated circuit on the test bench, and the installation angle and contact method of the equipment are adjusted according to the specific shape of the circuit to ensure that the data during the test is accurate and reliable. Through these calibration steps, corresponding testing equipment adaptation and installation parameters are generated. Meanwhile, after completing equipment adaptation and calibration, the final pre-test preparation is carried out. At this point, the HIC is fixed on the test fixture, and all test equipment interfaces with the circuit are accurately connected. First, the working status of all instruments is checked to ensure that the electrical parameter tester can accurately read the current and voltage values ​​of the circuit, the infrared thermal imager can normally acquire the temperature distribution on the circuit surface, and the electromagnetic compatibility analyzer can normally monitor electromagnetic radiation and interference. On this basis, the test parameters (such as voltage range, temperature range, frequency response, etc.) are set through the software interface to make all test equipment in the best state so as to perform high-precision measurements, generate corresponding test reports, record equipment status, test results and calibration parameters, and finally generate a complete test of the hybrid integrated circuit.

[0093] Furthermore, step S2 includes the following steps:

[0094] Step S21: Start the electrical parameter tester, infrared thermal imager and electromagnetic compatibility analyzer to perform multi-mode data synchronous acquisition on the tested hybrid integrated circuit according to the preset synchronous acquisition frequency, so as to generate the electrical parameter set, chip operating temperature distribution and electromagnetic radiation spectrum of the circuit operation corresponding to the hybrid integrated circuit.

[0095] Step S22: Perform time synchronization processing on the electrical parameter set corresponding to the hybrid integrated circuit to generate the electrical parameter set corresponding to the hybrid integrated circuit in the same time range;

[0096] Step S23: Obtain the rated current, rated voltage, calibration resistor, and calibration capacitor corresponding to the hybrid integrated circuit;

[0097] Step S24: Obtain the characteristic parameters of the electronic components corresponding to the hybrid integrated circuit, and perform an acceptable fluctuation range analysis on each electrical parameter of the hybrid integrated circuit based on the characteristic parameters of the electronic components corresponding to the hybrid integrated circuit to obtain the acceptable fluctuation range value of each electrical parameter of the hybrid integrated circuit; determine the maximum and minimum thresholds of the corresponding acceptable fluctuation range values ​​based on the rated current, rated voltage, rated resistor, and rated capacitor of the hybrid integrated circuit to obtain the maximum and minimum thresholds of each electrical parameter of the hybrid integrated circuit.

[0098] Step S25: Based on the electrical parameter set corresponding to the hybrid integrated circuit in the same time range, perform electrical fault detection on the maximum and minimum thresholds corresponding to each electrical parameter of the hybrid integrated circuit, and generate circuit electrical fault detection results.

[0099] As an embodiment of the present invention, reference is made to... Figure 3 As shown, Figure 1 A detailed flowchart of step S2 is shown below. In this embodiment, step S2 includes the following steps:

[0100] Step S21: Start the electrical parameter tester, infrared thermal imager and electromagnetic compatibility analyzer to perform multi-mode data synchronous acquisition on the tested hybrid integrated circuit according to the preset synchronous acquisition frequency, so as to generate the electrical parameter set, chip operating temperature distribution and electromagnetic radiation spectrum of the circuit operation corresponding to the hybrid integrated circuit.

[0101] In this embodiment of the invention, an electrical parameter tester, an infrared thermal imager, and an electromagnetic compatibility analyzer are set according to a preset synchronous acquisition frequency. These devices are configured to simultaneously begin acquiring data at the same time interval. The electrical parameter tester is responsible for measuring the electrical parameters of the hybrid integrated circuit, such as current, voltage, resistance, and capacitance. The infrared thermal imager detects the temperature distribution of the chip through infrared radiation, records the thermal effects of each component, and forms a temperature spectrum. The electromagnetic compatibility analyzer captures the electromagnetic radiation spectrum and records the electromagnetic interference and its frequency characteristics generated by the circuit during operation. The synchronous acquisition process must ensure that the timestamps of all devices are accurately aligned to ensure that reasonable fusion and analysis can be performed during subsequent data processing, ultimately generating the electrical parameter set, chip operating temperature distribution, and electromagnetic radiation spectrum of the circuit operation corresponding to the hybrid integrated circuit.

[0102] Step S22: Perform time synchronization processing on the electrical parameter set corresponding to the hybrid integrated circuit to generate the electrical parameter set corresponding to the hybrid integrated circuit in the same time range;

[0103] In this embodiment of the invention, the previously acquired electrical parameter set is time-synchronized. Specifically, a high-precision clock source is used to calibrate the time data of different testing instruments to ensure that current, voltage, resistance, capacitance, and other acquired electrical data can be compared and analyzed in the same time sequence. Through time synchronization, data deviations caused by acquisition delays between different devices can be eliminated. The synchronization process uses a dedicated synchronization processing algorithm to interpolate and align the data according to the timestamps of each data point, ensuring that all electrical parameters are completely consistent on the time axis. The processed electrical parameter set represents the electrical state of the hybrid integrated circuit at the same moment, and finally generates the electrical parameter set corresponding to the hybrid integrated circuit in the same time range.

[0104] Step S23: Obtain the rated current, rated voltage, calibration resistor, and calibration capacitor corresponding to the hybrid integrated circuit;

[0105] In this embodiment of the invention, the rated current, rated voltage, rated resistance, and rated capacitance of the hybrid integrated circuit are extracted from electrical parameter testers and other measuring devices. This operation first requires obtaining these basic electrical parameters by consulting circuit design documents or measuring under standard conditions. These parameters are usually specified in the technical specifications of the hybrid integrated circuit or confirmed by calibration tools provided by the equipment manufacturer. Rated current and rated voltage are usually the basic electrical indicators for normal circuit operation, while rated resistance and rated capacitance are usually obtained by laboratory testing or design calibration. These parameters provide a reference for subsequent fluctuation range analysis to ensure that the circuit operates within a preset safety range, and finally obtain the rated current, rated voltage, rated resistance, and rated capacitance corresponding to the hybrid integrated circuit.

[0106] Step S24: Obtain the characteristic parameters of the electronic components corresponding to the hybrid integrated circuit, and perform an acceptable fluctuation range analysis on each electrical parameter of the hybrid integrated circuit based on the characteristic parameters of the electronic components corresponding to the hybrid integrated circuit to obtain the acceptable fluctuation range value of each electrical parameter of the hybrid integrated circuit; determine the maximum and minimum thresholds of the corresponding acceptable fluctuation range values ​​based on the rated current, rated voltage, rated resistor, and rated capacitor of the hybrid integrated circuit to obtain the maximum and minimum thresholds of each electrical parameter of the hybrid integrated circuit.

[0107] In this embodiment of the invention, characteristic parameters of each electronic component in the hybrid integrated circuit are obtained. These characteristic parameters include the component's operating voltage, current load capacity, frequency response, temperature sensitivity, etc., and are usually provided by the component manufacturer. Based on this, an acceptable fluctuation range analysis is performed on the electrical parameters in the hybrid integrated circuit. Circuit simulation software is used to simulate various operating conditions, and combined with the tolerance requirements during circuit design, the acceptable fluctuation range of each electrical parameter is obtained, including the acceptable fluctuation ranges corresponding to current, voltage, resistance, and capacitance. Through this fluctuation range analysis, the variation limit of each electrical parameter under normal operating conditions can be determined. Then, based on the rated current, rated voltage, rated resistor, and rated capacitor, the fluctuation range of these electrical parameters is further limited, and the maximum threshold (i.e., the sum of each rated parameter and the fluctuation range) and minimum threshold (i.e., the difference between each rated parameter and the fluctuation range) of each parameter are calculated. These thresholds will serve as the standard for subsequent fault detection to ensure that the electrical parameters do not deviate from the predetermined range and to avoid circuit faults. Finally, the maximum and minimum thresholds corresponding to each electrical parameter of the hybrid integrated circuit are obtained.

[0108] Step S25: Based on the electrical parameter set corresponding to the hybrid integrated circuit in the same time range, perform electrical fault detection on the maximum and minimum thresholds corresponding to each electrical parameter of the hybrid integrated circuit, and generate circuit electrical fault detection results.

[0109] In this embodiment of the invention, fault detection is performed on each electrical parameter based on the previously time-synchronized set of electrical parameters and the calculated maximum and minimum thresholds. Specifically, each parameter value is compared with its corresponding maximum and minimum thresholds to detect whether it exceeds a preset range. If the value of an electrical parameter exceeds its maximum or minimum threshold, it is determined to be an electrical fault. Electrical fault detection can be automatically completed by a fault detection algorithm. The algorithm generates an alarm signal based on the set thresholds, indicating the specific fault type (including open circuit, short circuit, open circuit, and parameter drift fault). This process, through continuous tracking of the real-time monitored electrical parameters, can promptly detect electrical anomalies or problems related to temperature, electromagnetic fields, etc., that affect circuit function, and ultimately generate circuit electrical fault detection results.

[0110] Furthermore, step S25 includes the following steps:

[0111] Timing point extraction is performed on the electrical parameter set corresponding to the hybrid integrated circuit under the same timing range to obtain the specific values ​​of each electrical parameter of the hybrid integrated circuit at each timing point, including the specific values ​​of current, voltage, resistance and capacitance.

[0112] In this embodiment of the invention, a specialized timing analysis tool is designed to perform timing analysis on hybrid integrated circuits. This tool must be capable of extracting electrical parameters such as current, voltage, resistance, and capacitance at different time points. The specific operation process includes first setting the operating timing range of the circuit, i.e., defining the range of various time points during circuit operation. Then, timing simulation software (such as SPICE simulation tool) is used to simulate each timing point of the circuit, recording various electrical parameters, mainly including current, voltage, resistance, and capacitance values. For current and voltage measurements, the circuit simulation tool records the current and voltage changes at each node at each timing point. For resistance and capacitance, the simulation tool calculates the changes in resistance and capacitance based on the circuit's design parameters and physical characteristics, obtaining a mapping relationship between a set of timing points and corresponding electrical parameter values. Finally, the specific values ​​of each electrical parameter of the hybrid integrated circuit at each timing point are obtained, including the specific values ​​of current, voltage, resistance, and capacitance.

[0113] Preferably, if the specific value of the current corresponding to each timing point of the hybrid integrated circuit is less than the minimum current threshold corresponding to the hybrid integrated circuit and the specific value of the voltage corresponding to each timing point of the hybrid integrated circuit is normal, then an open circuit fault is detected and determined in the hybrid integrated circuit.

[0114] In this embodiment of the invention, the relationship between current and voltage is checked based on the previously obtained electrical parameters of the timing points. In specific operation, the current value of each timing point is first compared. If the current value of the timing point is lower than the minimum current threshold set by the circuit (for example, lower than a certain specific current value), and the voltage value of the timing point is confirmed to be normal (the voltage value is within the set normal range), then an open circuit fault is judged to exist based on this condition. An open circuit fault is usually manifested as the inability of current to flow, while the voltage value is not significantly affected. This is consistent with the characteristics of circuit interruption under open circuit conditions. When the above conditions are met, an open circuit fault is immediately reported in the circuit, and further location and analysis are performed.

[0115] Preferably, if the specific value of the current corresponding to each timing point of the hybrid integrated circuit is greater than the maximum current threshold corresponding to the hybrid integrated circuit and the specific value of the voltage corresponding to each timing point of the hybrid integrated circuit is less than the minimum voltage threshold corresponding to the hybrid integrated circuit, then a short circuit fault is detected and determined in the hybrid integrated circuit.

[0116] In this embodiment of the invention, short-circuit faults are detected by combining previously determined timing electrical parameter data and setting maximum thresholds for current and voltage. Specifically, the current and voltage values ​​at each timing point are extracted. If the current value at a certain timing point exceeds a preset maximum current threshold (e.g., when the current exceeds a certain current value), and the voltage value is lower than a preset minimum voltage threshold (e.g., when the voltage value is too low), then it can be determined that there is a short-circuit fault at that timing point. Short-circuit faults usually cause excessive current and reduced voltage because the current flows directly through the short-circuit path, causing overcurrent. Through this method, the system can detect short-circuit faults in real time and perform further location processing.

[0117] Preferably, if the specific value of the current corresponding to each timing point of the hybrid integrated circuit is zero and the specific value of the voltage corresponding to each timing point of the hybrid integrated circuit is normal, then an open circuit fault is detected in the hybrid integrated circuit.

[0118] In this embodiment of the invention, by analyzing the state of current and voltage based on previously obtained electrical parameters, if at a certain timing point the current value is zero (usually meaning that no current flows in the circuit), and the voltage value at that timing point is within the normal range (e.g., the voltage value is within the set operating voltage range), it can be determined that an open circuit fault has occurred at that timing point. An open circuit fault is usually manifested as obstruction of current flow, while the voltage value may not change significantly. Therefore, by detecting a situation where the current is zero and the voltage is normal, it can be determined that there is an open circuit problem in a certain part of the circuit. The system will then issue an alarm and perform further fault location.

[0119] Preferably, if the specific value of the resistor corresponding to each timing point of the hybrid integrated circuit is greater than the maximum resistance threshold or less than the minimum resistance threshold, or the specific value of the capacitor corresponding to each timing point of the hybrid integrated circuit is greater than the maximum capacitance threshold or less than the minimum capacitance threshold, then the hybrid integrated circuit is detected and judged to have a parameter drift fault.

[0120] In this embodiment of the invention, resistance and capacitance values ​​are monitored based on previously extracted electrical parameter data. The operation process includes comparing the resistance and capacitance values ​​at each time point and checking whether they exceed the set maximum or minimum threshold. If the resistance value at a certain time point in the circuit is greater than the set maximum resistance threshold or less than the set minimum resistance threshold, or if the capacitance value at that time point is greater than the maximum capacitance threshold or less than the minimum capacitance threshold, it can be determined that there is a parameter drift fault in the circuit. Parameter drift is usually caused by changes in resistance or capacitance due to aging of components in the circuit or environmental changes (such as temperature fluctuations), which affects the normal operation of the circuit. Through this fault detection method, parameter drift problems in the circuit can be detected in a timely manner, and engineers can be reminded to conduct further analysis and repair.

[0121] Furthermore, step S3 includes the following steps:

[0122] Step S31: Obtain the dimensions, spacing, and arrangement of electronic components near the chip within the tested hybrid integrated circuit;

[0123] In this embodiment of the invention, a high-resolution scanning electron microscope (SEM) is used to scan the fully tested hybrid integrated circuit to accurately obtain the dimensional information of each electronic component within the chip. By comparing this information with the circuit design file, the dimensional data of each electronic component in the circuit is extracted, especially key components such as resistors, capacitors, and transistors. Next, CAD software is used to digitally model the circuit layout. This model is used to accurately measure the spacing and arrangement of each component. For complex multilayer circuits, dedicated 3D modeling software (such as ANSYS or SolidWorks) is used to create a three-dimensional model, and the interlayer distances and relative positional relationships of components are extracted. Finally, the corresponding electronic component dimensions, spacing, and arrangement are obtained.

[0124] Step S32: Perform chip thermal conduction topology analysis on the tested hybrid integrated circuit based on the size, spacing and arrangement of electronic components to clearly show the thermal conduction network from the heat-generating components to the heat dissipation path, and obtain the internal thermal conduction topology network of the circuit chip.

[0125] In this embodiment of the invention, a thermal conduction model of the circuit chip is constructed using previously obtained data on the size, spacing, and arrangement of electronic components. This model needs to consider the thermal conductivity of the material, the shape of the heat dissipation channel, and the location of the heat-generating components. Based on this, computational fluid dynamics (CFD) software (such as ANSYS Fluent or COMSOL Multiphysics) is used to perform thermal conduction topology analysis. This software calculates the heat source distribution of each heat-generating component within the chip, analyzes its heat transfer path with other components, and generates a thermal conduction network diagram inside the circuit chip. Through simulation, the path of heat transfer from the heat-generating components to the heat dissipation device can be clearly shown, potential areas of poor heat dissipation can be identified, and the circuit design can be further optimized based on the results of the thermal conduction analysis to ensure temperature control and stability of the circuit during operation, ultimately obtaining the internal thermal conduction topology network of the circuit chip.

[0126] Step S33: Perform thermal stress distribution analysis on the tested hybrid integrated circuit based on the internal thermal conduction topology network of the circuit chip to generate the thermal stress distribution field of the circuit chip corresponding to the hybrid integrated circuit.

[0127] In this embodiment of the invention, based on the previously obtained thermal conduction topology network of the circuit chip, thermal stress analysis is first performed on each component inside the chip, and the thermal conduction network is simulated using finite element analysis (FEA) methods (such as ANSYS Mechanical or ABAQUS). This analysis considers the differences in thermal expansion coefficients of different materials inside the chip, the stress effect of temperature gradient on the materials, and the geometry of the internal structure. By analyzing the thermal stress distribution, a thermal stress distribution field map of the circuit chip is generated, showing the changes in thermal stress in each part caused by temperature changes. Based on this distribution field, the areas inside the chip most susceptible to thermal stress and the possible thermal failure risk areas can be determined, and finally, the thermal stress distribution field of the circuit chip corresponding to the hybrid integrated circuit is generated.

[0128] Step S34: Based on the thermal stress distribution field of the circuit chip corresponding to the hybrid integrated circuit, perform thermal failure detection on the corresponding fully tested hybrid integrated circuit, so as to determine each thermal anomaly sensitive area according to the thermal stress distribution of each part of the chip, and determine whether the corresponding thermal failure phenomenon occurs based on the temperature change of each thermal anomaly sensitive area according to the preset thermal failure critical temperature threshold, so as to generate circuit thermal failure detection results.

[0129] In this embodiment of the invention, thermal failure fault detection of hybrid integrated circuits is performed based on the previously generated thermal stress distribution field of the circuit chip. By analyzing the thermal stress distribution in different regions inside the chip, and using thermal failure models (such as thermal cycling fatigue models, thermal expansion failure models, etc.), combined with the thermal failure critical temperature threshold designed for the chip, it is determined which regions have thermal failure due to excessive thermal stress. For each region that has failed, thermal simulation analysis tools are used to further calculate its temperature change and compare it with the preset thermal failure critical temperature to determine whether thermal failure exists. If thermal failure occurs, the region is marked as a fault region, and corresponding thermal failure fault detection results are generated, ultimately generating circuit thermal failure fault detection results.

[0130] Step S35: Perform electromagnetic interference fault detection on the tested hybrid integrated circuit based on the electromagnetic radiation spectrum of the circuit operation corresponding to the hybrid integrated circuit, so as to generate the circuit electromagnetic interference fault detection result.

[0131] In this embodiment of the invention, the electromagnetic radiation spectrum of the hybrid integrated circuit is analyzed in detail using electromagnetic simulation software (such as CST Studio or HFSS). This process includes measuring the electromagnetic radiation spectrum of the circuit under different operating conditions, identifying the corresponding electromagnetic interference sources, and detecting whether there are abnormal electromagnetic noise or interference signals in a specific frequency band by analyzing the radiation spectrum of the circuit. After detecting electromagnetic interference, the circuit is improved using methods such as electromagnetic shielding and filtering design. An electromagnetic interference fault detection report is generated based on the simulation results, clearly indicating the source of the electromagnetic interference fault and its impact on the circuit performance, and finally generating the circuit electromagnetic interference fault detection result.

[0132] Furthermore, step S35 includes the following steps:

[0133] Step S351: Obtain the layout and connection method of each electronic component and wire in the complete test hybrid integrated circuit, and evaluate the electromagnetic radiation interference impact of the complete test hybrid integrated circuit based on the layout and connection method of each electronic component and wire to generate an electromagnetic radiation interference impact factor.

[0134] In this embodiment of the invention, the layout and connection methods between electronic components and wires of a hybrid integrated circuit are obtained. This process uses the layout diagram in the circuit design file (such as PCB design diagram or circuit diagram), and identifies and classifies the electronic components, such as capacitors, resistors, transistors, etc., one by one. At the same time, the electrical connections between each component and other components are marked. Subsequently, electromagnetic interference (EMI) simulation is performed on the circuit layout using electromagnetic field simulation tools (such as ANSYS HFSS or COMSOL Multiphysics). Through these tools, the coupling effect between wires, current flow, and electromagnetic wave propagation between different components can be analyzed, thereby generating an electromagnetic radiation interference influence factor. This factor quantifies the degree of influence of the layout of each component and wire in the circuit on electromagnetic radiation. It should be noted that all connection methods and component layouts must be accurately reproduced in the simulation model to ensure the accuracy of the electromagnetic influence assessment, and finally generate the electromagnetic radiation interference influence factor.

[0135] Step S352: Obtain the electromagnetic spectrum of the circuit under normal operation corresponding to the hybrid integrated circuit, and perform electromagnetic phase difference analysis on the electromagnetic radiation spectrum of the circuit operation based on the electromagnetic spectrum of the circuit under normal operation corresponding to the hybrid integrated circuit to obtain the electromagnetic radiation phase difference of the integrated circuit operation.

[0136] In this embodiment of the invention, the electromagnetic spectrum of the hybrid integrated circuit during normal operation is obtained. This spectrum reflects the electromagnetic radiation characteristics of the circuit under normal operating conditions, including the radiation intensity and waveform of each frequency band. The electromagnetic radiation signal generated by the circuit during operation is measured using a spectrum analyzer (such as Keysight N9030A) to obtain its spectrum data. Then, based on the circuit's operating spectrum, the phase difference of the signal in different frequency bands is calculated using a phase difference analysis algorithm (such as Fourier transform). The change in phase difference reflects the electromagnetic interference situation of the circuit under different operating conditions. By comparing the phase difference at different time points or under different circuit conditions, the electromagnetic radiation phase difference of the integrated circuit during normal operation is obtained. This helps to identify potential electromagnetic interference sources and provides data support for subsequent electromagnetic interference analysis, ultimately obtaining the electromagnetic radiation phase difference of the integrated circuit during operation.

[0137] Step S353: Perform electromagnetic interference amplitude and frequency analysis on the electromagnetic radiation spectrum of the circuit corresponding to the hybrid integrated circuit to obtain the electromagnetic interference amplitude and frequency of the integrated circuit.

[0138] In this embodiment of the invention, the amplitude and frequency of electromagnetic interference are obtained by further analyzing the electromagnetic radiation spectrum of the hybrid integrated circuit. A high-precision spectrum analyzer is used to scan the electromagnetic radiation spectrum of the circuit and record the radiation intensity of each frequency band during circuit operation. The spectrum analyzer can accurately measure the radiation power at each frequency point, thereby obtaining the interference amplitude of each frequency band. By statistically analyzing these data, the frequency bands with high amplitude radiation can be identified, and the frequency and amplitude characteristics of electromagnetic interference can be inferred. During the analysis, special attention should be paid to distinguishing between noise signals and normal signals to ensure that only real electromagnetic interference signals are processed and not misjudged as normal operating signals. Finally, the electromagnetic interference amplitude and frequency of the integrated circuit are obtained.

[0139] Step S354: Based on the electromagnetic radiation interference influence factor, the electromagnetic radiation phase difference of the integrated circuit operation, the electromagnetic interference amplitude of the integrated circuit, and the electromagnetic interference frequency of the integrated circuit, the electromagnetic interference calculation formula is used to calculate the electromagnetic interference of the electromagnetic radiation spectrum of the circuit operation corresponding to the hybrid integrated circuit, and the electromagnetic radiation interference value corresponding to the hybrid integrated circuit is obtained.

[0140] In this embodiment of the invention, a suitable electromagnetic radiation interference calculation formula is constructed by combining the total components of the corresponding frequency components in the electromagnetic radiation spectrum of the circuit operation, the electromagnetic interference amplitude of the integrated circuit corresponding to the frequency component components, the electromagnetic interference frequency of the integrated circuit, the electromagnetic radiation phase difference between the electromagnetic spectrum and the normal operation electromagnetic spectrum, the electromagnetic radiation frequency components, the electromagnetic radiation attenuation factor, the electromagnetic interference suppression constant, and related parameters to calculate the electromagnetic interference of the electromagnetic radiation spectrum of the circuit operation corresponding to the hybrid integrated circuit. By combining the structural characteristics of the wires, power supply, grounding, etc. in the circuit, electromagnetic wave propagation and interference calculation are performed. Electromagnetic simulation software (such as CST Studio) is used to perform more detailed electromagnetic field simulation of the circuit, accurately calculate the interference value of each frequency band, and finally obtain the electromagnetic radiation interference value corresponding to the hybrid integrated circuit.

[0141] Step S355: Compare and judge the electromagnetic radiation interference value corresponding to the hybrid integrated circuit according to the preset circuit electromagnetic interference fault threshold. If the electromagnetic radiation interference value is greater than or equal to the preset circuit electromagnetic interference fault threshold, it is determined that the hybrid integrated circuit has external electromagnetic source interference; if the electromagnetic radiation interference value is less than the preset circuit electromagnetic interference fault threshold, it is determined that the hybrid integrated circuit has electromagnetic interference generated by the internal circuit, so as to generate the circuit electromagnetic interference fault detection result.

[0142] In this embodiment of the invention, the electromagnetic interference value obtained is compared with a preset electromagnetic interference fault threshold to determine whether the hybrid integrated circuit is affected by an external electromagnetic source. First, an electromagnetic interference fault threshold is set, which can be determined by historical fault data or electromagnetic compatibility standards (such as IEC 61000). If the calculated electromagnetic interference value is greater than or equal to the threshold, it indicates that the circuit is affected by an external electromagnetic source and there is a risk of external interference. If the electromagnetic interference value is lower than the threshold, it indicates that the interference originates from inside the circuit. Through this step, the source type of interference can be accurately determined, and finally, the circuit electromagnetic interference fault detection result is generated.

[0143] Furthermore, the electromagnetic radiation interference calculation formula mentioned in step S354 is as follows:

[0144] ;

[0145] In the formula, This represents the electromagnetic radiation interference value. The time interval for electromagnetic interference calculation. For time-varying parameters, This refers to the total components of the corresponding frequency elements within the electromagnetic radiation spectrum during circuit operation. The first in the electromagnetic radiation spectrum of the circuit operation The electromagnetic interference amplitude of the integrated circuit corresponding to each frequency component. The first in the electromagnetic radiation spectrum of the circuit operation The electromagnetic interference frequencies of integrated circuits corresponding to each frequency component. The first in the electromagnetic radiation spectrum of the circuit operation The electromagnetic radiation phase difference between each frequency component and the normal operating electromagnetic spectrum The frequency components of electromagnetic radiation For the first Electromagnetic radiation attenuation factor corresponding to each frequency component. For the first Electromagnetic interference suppression constants corresponding to each frequency component. This is a correction factor for the electromagnetic radiation interference value.

[0146] This invention, through specific mathematical models and verification, derives an electromagnetic interference (EMI) calculation formula. This formula is used to calculate EMI on the electromagnetic radiation spectrum of a hybrid integrated circuit. By modeling each frequency component within the circuit's electromagnetic radiation spectrum, the calculation of EMI is not limited to a single frequency but encompasses multiple frequency components. The contribution of each frequency component to EMI is evaluated individually, enabling a more detailed capture of complex EMI phenomena. By introducing electromagnetic radiation phase difference, the formula accurately reflects the relative time delay or displacement between different frequency components, which helps simulate the interference superposition effect caused by phase differences in actual circuits. The formula uses... A frequency attenuation factor is introduced, representing the signal attenuation effect as the electromagnetic radiation frequency changes. This calculation method can reflect the attenuation phenomenon that high-frequency signals may experience in actual circuits, helping to more accurately assess the contribution of the high-frequency component to electromagnetic interference. By introducing... The suppression term in the formula further considers the suppression effect of electromagnetic interference, especially in the high-frequency range. Circuits typically suppress signals at specific frequencies (e.g., through filtering), which improves the accuracy of high-frequency noise or interference calculations. It also incorporates multiple circuit and electromagnetic parameters (such as electromagnetic radiation phase difference, amplitude, and frequency) for calculation, comprehensively simulating the electromagnetic environment during circuit operation. This comprehensive consideration of circuit operating states, phase differences, electromagnetic spectrum, and other multi-dimensional factors helps to more fully evaluate the impact of electromagnetic interference on circuit performance. Secondly, the formula involves integral calculations, using time integration to consider the dynamic process of electromagnetic interference changing over time, more realistically simulating the cumulative effect of electromagnetic interference in the circuit over time. Finally, the formula provides a specific electromagnetic radiation interference value, which can be compared with a preset electromagnetic interference fault threshold, thereby enabling electromagnetic interference fault detection for hybrid integrated circuits. This quantitative assessment effectively helps engineers determine whether a circuit is affected by electromagnetic interference and distinguish whether the interference source is an internal circuit fault or an external electromagnetic source. In summary, this formula fully considers the electromagnetic radiation interference value. Electromagnetic interference calculation time interval Time variable parameter The total components of the corresponding frequency elements within the electromagnetic radiation spectrum during circuit operation The circuit operates within the electromagnetic radiation spectrum of the first The electromagnetic interference amplitude of the integrated circuit corresponding to each frequency component The circuit operates within the electromagnetic radiation spectrum of the first The integrated circuit electromagnetic interference frequency corresponding to each frequency component. The circuit operates within the electromagnetic radiation spectrum of the first The electromagnetic radiation phase difference between each frequency component and the normal operating electromagnetic spectrum Electromagnetic radiation frequency components , No. Electromagnetic radiation attenuation factor corresponding to each frequency component , No. Electromagnetic interference suppression constant corresponding to each frequency component Correction factor for electromagnetic radiation interference values According to electromagnetic radiation interference values The interrelationships among the above parameters constitute a functional relationship:

[0147] ;

[0148] This formula enables the calculation of electromagnetic interference (EMI) in the electromagnetic radiation spectrum of circuits operating with hybrid integrated circuits. Furthermore, it includes a correction coefficient for the EMI value. The introduction of this feature allows for adjustments based on errors that occur during the calculation process, thereby improving the accuracy and applicability of the electromagnetic radiation interference calculation formula.

[0149] Furthermore, step S4 includes the following steps:

[0150] Step S41: Based on the circuit electrical fault detection results, circuit thermal failure fault detection results, or circuit electromagnetic interference fault detection results, perform fault mode feature analysis on the corresponding hybrid integrated circuits to extract the abnormal current and voltage fluctuations of the corresponding electrical faults, the uneven temperature distribution of the thermal failure faults, and the abnormal spectrum features of the electromagnetic interference faults for each fault type, and clarify the relationship between different fault types and features to obtain the abnormal fault mode features corresponding to the hybrid integrated circuits.

[0151] In this embodiment of the invention, fault mode characteristic analysis is performed on the hybrid integrated circuit based on the results of electrical fault detection, thermal failure fault detection, or electromagnetic interference fault detection. Specifically, this involves acquiring current and voltage signals using current and voltage sensors installed in the circuit, and monitoring the fluctuations of these signals in real time using an oscilloscope or data acquisition device. In electrical fault analysis, abnormal fluctuations in the monitored current and voltage signals are considered electrical fault characteristics, manifested as sudden changes in current or voltage or continuous abnormal waveforms. For thermal failure faults, a temperature distribution map of the hybrid integrated circuit is obtained using a thermal imager, analyzing the distribution of areas with abnormal temperatures, identifying areas of uneven temperature, and thus determining potential thermal failure faults. For electromagnetic interference faults, a spectrum analyzer is used to scan the spectrum of signals generated in the circuit, identifying abnormal peaks or electromagnetic noise in the spectrum. These spectral features can be used to diagnose electromagnetic interference sources. All analysis results are mapped to corresponding fault modes, and matching analysis is performed on different types of fault features to identify typical abnormal features for each fault type. Based on these features, the correspondence between electrical faults, thermal failure faults, and electromagnetic interference faults can be clarified, ultimately yielding the abnormal fault mode characteristics corresponding to the hybrid integrated circuit.

[0152] Step S42: Based on the abnormal characteristics of the fault modes corresponding to the hybrid integrated circuit, perform in-depth analysis of the fault root causes of the hybrid integrated circuit to identify the fault root cause clues hidden under the fault manifestations of the hybrid integrated circuit, so as to generate: circuit fault root cause in-depth analysis clue set.

[0153] In this embodiment of the invention, by deeply analyzing the previously extracted abnormal features of fault modes, potential root causes hidden beneath the fault manifestations are identified. Specifically, based on data such as current, voltage, temperature, and spectrum, multi-dimensional data fusion and processing are performed using professional fault diagnosis software to classify and identify fault modes. Then, by further analyzing the current and voltage fluctuation characteristics exhibited by electrical faults and the layout and connection relationships of circuit components, the root cause of the fault is inferred to be due to the aging or damage of a certain component, or a circuit design defect. In thermal failure faults, temperature distribution map analysis identifies the core components in the overheated area, further suggesting that heat accumulation is caused by poor heat dissipation system design or excessive component load. The root cause of electromagnetic interference faults is identified through spectrum analysis to find the source of abnormal interference signals, and combined with circuit design, the corresponding electromagnetic interference source is identified, whether due to external environmental factors or internal circuit wiring problems. Based on the analysis results, a deep analysis clue set of fault root causes containing all possible fault source clues is generated. This set includes detailed possible fault points and inferred root causes, ultimately generating: a deep analysis clue set of circuit fault root causes.

[0154] Step S43: Based on the clue set of in-depth analysis of the root causes of circuit faults, recommend repair solutions for hybrid integrated circuits and generate recommended repair solutions for the fault severity of the hybrid integrated circuits. For electrical faults, electronic component replacement and circuit rewiring strategies are adopted. For thermal failure faults, heat dissipation system optimization and electronic component de-rating are involved. For electromagnetic interference faults, if they are caused by external electromagnetic sources, electromagnetic shielding is added to effectively block external interference from entering the hybrid integrated circuit. If the electromagnetic interference is generated by internal circuits, the circuit layout is redesigned to reduce crosstalk between signals, and the corresponding hybrid integrated circuit fault repair work is performed.

[0155] In this embodiment of the invention, a recommended repair scheme for hybrid integrated circuit faults is determined by analyzing the clue set of root cause analysis of circuit faults. For electrical faults, the specific electronic components that need to be replaced are first determined based on the abnormal fluctuations in current and voltage, such as replacing aging or damaged resistors, capacitors, etc., and the circuit is rewired according to the circuit design requirements to ensure the stability and reliability of the circuit. For thermal failure faults, if the temperature distribution map analysis reveals that certain areas are too hot, the circuit is repaired by optimizing the heat dissipation system, such as adding heat sinks or improving the layout of the heat sink to reduce the temperature of critical components. In addition, electronic components can be cooled according to their actual temperature tolerance. For high-temperature environments, components are selected to better suit the application. For electromagnetic interference faults, if the external electromagnetic source is the source of interference, external interference signals are isolated by adding electromagnetic shielding or improving the electromagnetic compatibility of the external environment. If the electromagnetic interference is caused by internal circuit design defects, the circuit layout needs to be redesigned, especially in the transmission path of high-frequency signals. The routing layout is optimized to reduce crosstalk between signals, or an electromagnetic isolator is added to eliminate unnecessary interference. The repair plan will combine the characteristics of different fault types to formulate targeted and efficient repair strategies to ensure that the hybrid integrated circuit can be restored to its best working state and finally perform the corresponding hybrid integrated circuit fault repair work.

[0156] Furthermore, the present invention also provides a hybrid integrated circuit intelligent testing system for performing the hybrid integrated circuit intelligent testing method described above, the hybrid integrated circuit intelligent testing system comprising:

[0157] The circuit testing preparation module is used to prepare for testing by installing electrical parameter testers, infrared thermal imagers and electromagnetic compatibility analyzers at different ports and key parts of the hybrid integrated circuit, and fixing the hybrid integrated circuit with the testing equipment installed on the test fixture, so as to generate a fully tested hybrid integrated circuit.

[0158] The synchronous acquisition and electrical detection module is used to activate the electrical parameter tester, infrared thermal imager, and electromagnetic compatibility analyzer according to the preset synchronous acquisition frequency to synchronously acquire multi-modal data of the tested hybrid integrated circuit, so as to generate the electrical parameter set, chip operating temperature distribution, and electromagnetic radiation spectrum of the circuit operation corresponding to the hybrid integrated circuit; and to perform electrical fault detection on the tested hybrid integrated circuit based on the electrical parameter set corresponding to the hybrid integrated circuit, thereby generating the circuit electrical fault detection results.

[0159] The thermal failure and electromagnetic interference detection module is used to perform thermal failure and electromagnetic interference fault detection on the tested hybrid integrated circuit based on the chip operating temperature distribution and the electromagnetic radiation spectrum of the circuit operation, so as to generate circuit thermal failure fault detection results and circuit electromagnetic interference fault detection results.

[0160] The circuit fault recommendation and repair module is used to recommend and repair faults for corresponding hybrid integrated circuits based on the circuit electrical fault detection results, circuit thermal failure fault detection results, or circuit electromagnetic interference fault detection results, and generate a recommended repair scheme for the fault degree of the hybrid integrated circuit to perform the corresponding hybrid integrated circuit fault repair work.

[0161] Therefore, the embodiments should be considered as exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of the equivalents of the application are intended to be included within the invention.

[0162] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features of the invention herein.

Claims

1. A hybrid integrated circuit intelligent detection method, characterized in that, Includes the following steps: Step S1: Prepare for testing by installing electrical parameter testers, infrared thermal imagers, and electromagnetic compatibility analyzers at different ports and key locations within the hybrid integrated circuit, and fixing the hybrid integrated circuit with the test equipment installed on the test fixture, so as to generate a fully tested hybrid integrated circuit. Step S2: Based on a preset synchronous acquisition frequency, the electrical parameter tester, infrared thermal imager, and electromagnetic compatibility analyzer are activated to synchronously acquire multi-modal data of the tested hybrid integrated circuit, generating the electrical parameter set, chip operating temperature distribution, and electromagnetic radiation spectrum corresponding to the hybrid integrated circuit; based on the electrical parameter set corresponding to the hybrid integrated circuit, electrical fault detection is performed on the tested hybrid integrated circuit to generate circuit electrical fault detection results; wherein, the electrical fault detection includes the following steps: Timing point extraction is performed on the electrical parameter set corresponding to the hybrid integrated circuit under the same timing range to obtain the specific values ​​of each electrical parameter of the hybrid integrated circuit at each timing point, including the specific values ​​of current, voltage, resistance and capacitance. If the specific current value corresponding to each timing point of the hybrid integrated circuit is less than the minimum current threshold of the hybrid integrated circuit and the specific voltage value corresponding to each timing point of the hybrid integrated circuit is normal, then an open circuit fault is detected in the hybrid integrated circuit. If the specific value of the current corresponding to each timing point of the hybrid integrated circuit is greater than the maximum current threshold of the hybrid integrated circuit and the specific value of the voltage corresponding to each timing point of the hybrid integrated circuit is less than the minimum voltage threshold of the hybrid integrated circuit, then a short circuit fault is detected in the hybrid integrated circuit. If the specific current value of the hybrid integrated circuit at each timing point is zero and the specific voltage value of the hybrid integrated circuit at each timing point is normal, then the hybrid integrated circuit is detected to have an open circuit fault. If the specific value of the resistor corresponding to each timing point of the hybrid integrated circuit is greater than the maximum resistance threshold or less than the minimum resistance threshold, or if the specific value of the capacitor corresponding to each timing point of the hybrid integrated circuit is greater than the maximum capacitance threshold or less than the minimum capacitance threshold, then the hybrid integrated circuit is detected to have a parameter drift fault. Step S3: Based on the chip operating temperature distribution and the electromagnetic radiation spectrum of the circuit operation corresponding to the hybrid integrated circuit, thermal failure and magnetic interference fault detection are performed on the tested hybrid integrated circuit to generate circuit thermal failure fault detection results and circuit electromagnetic interference fault detection results; wherein, the magnetic interference fault detection includes the following steps: Step S351: Obtain the layout and connection method of each electronic component and wire in the complete test hybrid integrated circuit, and evaluate the electromagnetic radiation interference impact of the complete test hybrid integrated circuit based on the layout and connection method of each electronic component and wire to generate an electromagnetic radiation interference impact factor. Step S352: Obtain the electromagnetic spectrum of the circuit under normal operation corresponding to the hybrid integrated circuit, and perform electromagnetic phase difference analysis on the electromagnetic radiation spectrum of the circuit operation based on the electromagnetic spectrum of the circuit under normal operation corresponding to the hybrid integrated circuit to obtain the electromagnetic radiation phase difference of the integrated circuit operation. Step S353: Perform electromagnetic interference amplitude and frequency analysis on the electromagnetic radiation spectrum of the circuit corresponding to the hybrid integrated circuit to obtain the electromagnetic interference amplitude and frequency of the integrated circuit. Step S354: Based on the electromagnetic radiation interference influence factor, the phase difference of electromagnetic radiation during integrated circuit operation, the amplitude of electromagnetic interference during integrated circuit operation, and the frequency of electromagnetic interference during integrated circuit operation, the electromagnetic interference calculation formula is used to calculate the electromagnetic interference of the electromagnetic radiation spectrum corresponding to the hybrid integrated circuit, thereby obtaining the electromagnetic radiation interference value corresponding to the hybrid integrated circuit; wherein, the specific electromagnetic radiation interference calculation formula is as follows: ； In the formula, This represents the electromagnetic radiation interference value. The time interval for electromagnetic interference calculation. For time-varying parameters, This refers to the total components of the corresponding frequency elements within the electromagnetic radiation spectrum during circuit operation. The first in the electromagnetic radiation spectrum of the circuit operation The electromagnetic interference amplitude of the integrated circuit corresponding to each frequency component. The first in the electromagnetic radiation spectrum of the circuit operation The electromagnetic interference frequencies of integrated circuits corresponding to each frequency component. The first in the electromagnetic radiation spectrum of the circuit operation The electromagnetic radiation phase difference between each frequency component and the normal operating electromagnetic spectrum The frequency components of electromagnetic radiation For the first Electromagnetic radiation attenuation factor corresponding to each frequency component. For the first Electromagnetic interference suppression constants corresponding to each frequency component. This is a correction factor for the electromagnetic radiation interference value; Step S355: Compare and judge the electromagnetic radiation interference value corresponding to the hybrid integrated circuit according to the preset circuit electromagnetic interference fault threshold. If the electromagnetic radiation interference value is greater than or equal to the preset circuit electromagnetic interference fault threshold, it is determined that the hybrid integrated circuit has external electromagnetic source interference; if the electromagnetic radiation interference value is less than the preset circuit electromagnetic interference fault threshold, it is determined that the hybrid integrated circuit has electromagnetic interference generated by the internal circuit, so as to generate the circuit electromagnetic interference fault detection result. Step S4: Based on the circuit electrical fault detection results, circuit thermal failure fault detection results, or circuit electromagnetic interference fault detection results, recommend fault repair for the corresponding hybrid integrated circuit, generate a recommended repair scheme for the fault degree of the hybrid integrated circuit, and execute the corresponding hybrid integrated circuit fault repair work.

2. The intelligent detection method for hybrid integrated circuits according to claim 1, characterized in that, Step S1 includes the following steps: Step S11: Perform high-resolution X-ray tomography on the hybrid integrated circuit to generate internal three-dimensional structural information of the hybrid integrated circuit, so as to clearly present the circuit layout and electronic component connection method at different levels. Step S12: Use an electron microscope to perform microscopic imaging detail analysis on the hybrid integrated circuit to obtain the corresponding microscopic structural details of the hybrid integrated circuit, so as to capture the micro solder joints and wire details of the circuit parts; Step S13: Perform structural data fusion to construct the internal three-dimensional structural information and the minute structural details of the hybrid integrated circuit to generate an internal structural mapping map of the hybrid integrated circuit; Step S14: Based on the internal structure mapping map of the hybrid integrated circuit, predict the key detection points of each port part in the hybrid integrated circuit to predict and extract the nodes on the high-frequency signal transmission path of the circuit and the pins of electronic components with large power dissipation, and generate the detection points of different ports and key parts corresponding to the hybrid integrated circuit; install electrical parameter testers, infrared thermal imagers and electromagnetic compatibility analyzers at the detection points of different ports and key parts corresponding to the hybrid integrated circuit. Step S15: Obtain the physical dimensions and surface material characteristics of the hybrid integrated circuit; fix the hybrid integrated circuit after installation on the testing equipment onto the test fixture, and perform adaptation and calibration of the testing equipment corresponding to the hybrid integrated circuit based on the physical dimensions and surface material characteristics of the hybrid integrated circuit, so as to adaptively adjust the measurement range and sensitivity of the testing equipment, and generate calibration testing equipment adaptation and installation parameters; prepare the testing equipment corresponding to the hybrid integrated circuit for testing based on the calibration testing equipment adaptation and installation parameters, so as to generate a fully tested hybrid integrated circuit.

3. The intelligent detection method for hybrid integrated circuits according to claim 1, characterized in that, Step S2 includes the following steps: Step S21: Start the electrical parameter tester, infrared thermal imager and electromagnetic compatibility analyzer to perform multi-mode data synchronous acquisition on the tested hybrid integrated circuit according to the preset synchronous acquisition frequency, so as to generate the electrical parameter set, chip operating temperature distribution and electromagnetic radiation spectrum of the circuit operation corresponding to the hybrid integrated circuit. Step S22: Perform time synchronization processing on the electrical parameter set corresponding to the hybrid integrated circuit to generate the electrical parameter set corresponding to the hybrid integrated circuit in the same time range; Step S23: Obtain the rated current, rated voltage, calibration resistor, and calibration capacitor corresponding to the hybrid integrated circuit; Step S24: Obtain the characteristic parameters of the electronic components corresponding to the hybrid integrated circuit, and perform an acceptable fluctuation range analysis on each electrical parameter of the hybrid integrated circuit based on the characteristic parameters of the electronic components corresponding to the hybrid integrated circuit to obtain the acceptable fluctuation range value of each electrical parameter of the hybrid integrated circuit; determine the maximum and minimum thresholds of the corresponding acceptable fluctuation range values ​​based on the rated current, rated voltage, rated resistor, and rated capacitor of the hybrid integrated circuit to obtain the maximum and minimum thresholds of each electrical parameter of the hybrid integrated circuit. Step S25: Based on the electrical parameter set corresponding to the hybrid integrated circuit in the same time range, perform electrical fault detection on the maximum and minimum thresholds corresponding to each electrical parameter of the hybrid integrated circuit, and generate circuit electrical fault detection results.

4. The intelligent detection method for hybrid integrated circuits according to claim 3, characterized in that, The electrical parameter set mentioned in step S21 specifically includes the current, voltage, resistance, and capacitance parameters corresponding to the hybrid integrated circuit.

5. The intelligent detection method for hybrid integrated circuits according to claim 1, characterized in that, Step S3 includes the following steps: Step S31: Obtain the dimensions, spacing, and arrangement of electronic components near the chip within the tested hybrid integrated circuit; Step S32: Perform chip thermal conduction topology analysis on the tested hybrid integrated circuit based on the size, spacing and arrangement of electronic components to clearly show the thermal conduction network from the heat-generating components to the heat dissipation path, and obtain the internal thermal conduction topology network of the circuit chip. Step S33: Perform thermal stress distribution analysis on the tested hybrid integrated circuit based on the internal thermal conduction topology network of the circuit chip to generate the thermal stress distribution field of the circuit chip corresponding to the hybrid integrated circuit. Step S34: Based on the thermal stress distribution field of the circuit chip corresponding to the hybrid integrated circuit, perform thermal failure detection on the corresponding fully tested hybrid integrated circuit, so as to determine each thermal anomaly sensitive area according to the thermal stress distribution of each part of the chip, and determine whether the corresponding thermal failure phenomenon occurs based on the temperature change of each thermal anomaly sensitive area according to the preset thermal failure critical temperature threshold, so as to generate circuit thermal failure detection results. Step S35: Perform electromagnetic interference fault detection on the tested hybrid integrated circuit based on the electromagnetic radiation spectrum of the circuit operation corresponding to the hybrid integrated circuit, so as to generate the circuit electromagnetic interference fault detection result.

6. The intelligent detection method for hybrid integrated circuits according to claim 1, characterized in that, Step S4 includes the following steps: Step S41: Based on the circuit electrical fault detection results, circuit thermal failure fault detection results, or circuit electromagnetic interference fault detection results, perform fault mode feature analysis on the corresponding hybrid integrated circuits to extract the abnormal current and voltage fluctuations of the corresponding electrical faults, the uneven temperature distribution of the thermal failure faults, and the abnormal spectrum features of the electromagnetic interference faults for each fault type, and clarify the relationship between different fault types and features to obtain the abnormal fault mode features corresponding to the hybrid integrated circuits. Step S42: Based on the abnormal characteristics of the fault modes corresponding to the hybrid integrated circuit, perform in-depth analysis of the fault root causes of the hybrid integrated circuit to identify the fault root cause clues hidden under the fault manifestations of the hybrid integrated circuit, so as to generate: circuit fault root cause in-depth analysis clue set. Step S43: Based on the clue set of in-depth analysis of the root causes of circuit faults, recommend repair solutions for hybrid integrated circuits and generate recommended repair solutions for the fault severity of the hybrid integrated circuits. For electrical faults, electronic component replacement and circuit rewiring strategies are adopted. For thermal failure faults, heat dissipation system optimization and electronic component de-rating are involved. For electromagnetic interference faults, if they are caused by external electromagnetic sources, electromagnetic shielding is added to effectively block external interference from entering the hybrid integrated circuit. If the electromagnetic interference is generated by internal circuits, the circuit layout is redesigned to reduce crosstalk between signals, and the corresponding hybrid integrated circuit fault repair work is performed.

7. A hybrid integrated circuit intelligent detection system, characterized in that, For performing the hybrid integrated circuit intelligent detection method as described in claim 1, the hybrid integrated circuit intelligent detection system comprises: The circuit testing preparation module is used to prepare for testing by installing electrical parameter testers, infrared thermal imagers and electromagnetic compatibility analyzers at different ports and key parts of the hybrid integrated circuit, and fixing the hybrid integrated circuit with the testing equipment installed on the test fixture, so as to generate a fully tested hybrid integrated circuit. The synchronous acquisition and electrical detection module is used to activate the electrical parameter tester, infrared thermal imager, and electromagnetic compatibility analyzer according to the preset synchronous acquisition frequency to synchronously acquire multi-modal data of the tested hybrid integrated circuit, so as to generate the electrical parameter set, chip operating temperature distribution, and electromagnetic radiation spectrum of the circuit operation corresponding to the hybrid integrated circuit; and to perform electrical fault detection on the tested hybrid integrated circuit based on the electrical parameter set corresponding to the hybrid integrated circuit, thereby generating the circuit electrical fault detection results. The thermal failure and electromagnetic interference detection module is used to perform thermal failure and electromagnetic interference fault detection on the tested hybrid integrated circuit based on the chip operating temperature distribution and the electromagnetic radiation spectrum of the circuit operation, so as to generate circuit thermal failure fault detection results and circuit electromagnetic interference fault detection results. The circuit fault recommendation and repair module is used to recommend and repair faults for corresponding hybrid integrated circuits based on the circuit electrical fault detection results, circuit thermal failure fault detection results, or circuit electromagnetic interference fault detection results, and generate a recommended repair scheme for the fault degree of the hybrid integrated circuit to perform the corresponding hybrid integrated circuit fault repair work.

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