Method and device for testing multi-layer laminated mainboard

Abstract

The invention discloses a testing method and device for a multi-layer laminated mainboard, and relates to the technical field of mainboard testing, and the testing method for the multi-layer laminated mainboard comprises the steps: based on specific structure parameters of the multi-layer laminated mainboard, carrying out testing through employing an electromagnetic detection signal matched with the specific structure parameters, so as to obtain an electromagnetic abnormal region; according to the method, the electromagnetic abnormal area is detected, the layered current injection test is executed in the electromagnetic abnormal area through the probe to obtain the electrical abnormal area, and then the obtained electromagnetic abnormal area and the electrical abnormal area are subjected to space matching to jointly judge the defect, so that the detection accuracy of the multi-layer laminated mainboard is improved, and the detection efficiency is improved. The detection mode does not need to detect each layer of the multi-layer laminated mainboard one by one, so that the testing efficiency of the multi-layer laminated mainboard is improved.

Description

Technical Field

[0001] The present application relates to the technical field of motherboard testing, and in particular to a method and device for testing a multi-layer stacked motherboard. Background Art

[0002] Motherboard testing is used to ensure that the performance and quality of the motherboard meet the design requirements, and is a vital part of the electronic product manufacturing process. With the continuous development of electronic technology, multi-layer motherboards are widely used in various electronic devices due to their high density and high performance.

[0003] Traditional multi-layer motherboard testing is generally performed by testing each layer of the multi-layer motherboard one by one, which is not only time-consuming and labor-intensive, but also inefficient. In addition, due to the complex interlayer structure of the multi-layer motherboard, the existing testing methods are also difficult to accurately detect some minor defects inside it.

[0004] The above contents are only used to assist in understanding the technical solution of the present application and do not constitute an admission that the above contents are prior art. Summary of the invention

[0005] The main purpose of the present application is to provide a multi-layer stacked motherboard testing method and device, aiming to improve the accuracy and testing efficiency of the multi-layer stacked motherboard testing.

[0006] To achieve the above objectives, the present application proposes a multi-layer stacked motherboard testing method, the method comprising:

[0007] Determine an electromagnetic detection frequency band based on the number of layers and the dielectric constant of the multi-layer stacked mainboard, and transmit a corresponding electromagnetic detection signal to the multi-layer stacked mainboard at the electromagnetic detection frequency band to obtain original electromagnetic field data;

[0008] Calculate the interlayer magnetic field gradient change rate of the multi-layer stacked motherboard based on the original electromagnetic field data;

[0009] When the interlayer magnetic field gradient change rate is greater than a preset magnetic field gradient change rate threshold, determining a corresponding electromagnetic anomaly area;

[0010] Performing a layered current injection test in the electromagnetic abnormal area by using a probe to obtain the electrical abnormal area;

[0011] The electromagnetic abnormal area is spatially matched with the electrical abnormal area, and when the overlap between the two is higher than a preset threshold, it is determined that there is a valid defect, and the corresponding defect coordinates are output.

[0012] In one embodiment, the step of determining the electromagnetic detection frequency band based on the number of layers and the dielectric constant of the multi-layer laminated mainboard, and transmitting a corresponding electromagnetic detection signal to the multi-layer laminated mainboard at the electromagnetic detection frequency band to obtain the original electromagnetic field data includes:

[0013] Determine the reference electromagnetic frequency according to the following formula:

[0014] ;

[0015] in, represents the reference electromagnetic frequency, Indicates the number of layers of a multi-stacked motherboard; Indicates the dielectric constant of the multi-layer stacked motherboard;

[0016] The electromagnetic detection frequency band is determined based on the reference electromagnetic frequency and the dielectric constant of the multi-layer stacked motherboard, wherein:

[0017] When the dielectric constant of the multi-layer laminated motherboard is less than 3.5, the electromagnetic detection frequency band is determined to be: ;

[0018] When the dielectric constant of the multi-layer laminated motherboard is greater than 3.5, the electromagnetic detection frequency band is determined to be: .

[0019] In one embodiment, before the step of calculating the interlayer magnetic field gradient change rate of the multi-layer laminated mainboard based on the original electromagnetic field data, the method further includes:

[0020] The blind hole ratio of the multi-layer stacked mainboard is identified, and when the blind hole ratio is greater than a preset threshold, an electromagnetic detection signal of a preset frequency band is additionally emitted to the multi-layer stacked mainboard.

[0021] In one embodiment, before the step of calculating the interlayer magnetic field gradient change rate of the multi-layer laminated mainboard based on the original electromagnetic field data, the method further includes:

[0022] The polarization direction of the electromagnetic detection signal is determined based on the number of layers of the electromagnetic multi-layer stacked motherboard, specifically including:

[0023] When the number of layers of the multi-layer stacked mainboard is an even number, determining that the polarization direction of the electromagnetic detection signal is left-hand circular polarization;

[0024] When the number of layers of the multi-layer stacked mainboard is an odd number, the polarization direction of the electromagnetic detection signal is determined to be right-hand circular polarization.

[0025] In one embodiment, the step of calculating the interlayer magnetic field gradient change rate of the multi-layer laminated motherboard based on the original electromagnetic field data includes:

[0026] Performing eddy current compensation on the original electromagnetic field data to obtain electromagnetic field data after eddy current compensation;

[0027] Calculating the interlayer magnetic field gradient of the multi-layer stacked motherboard based on the compensated electromagnetic field data;

[0028] The interlayer magnetic field gradient change rate of the multi-layer laminated main board is calculated based on the interlayer magnetic field gradient.

[0029] In one embodiment, the interlayer magnetic field gradient is calculated according to the following formula:

[0030] ;

[0031] in, represents the interlayer magnetic field gradient, Indicates the first The electromagnetic field data of the layer, Indicates The dielectric thickness of the layer motherboard;

[0032] The interlayer magnetic field gradient change rate is calculated according to the following formula:

[0033] ;

[0034] in, Indicates the rate of change of the interlayer magnetic field gradient of the multi-layer stacked motherboard, Indicates The interlayer magnetic field gradient of the layer, Indicates The dielectric thickness of the main board.

[0035] In one embodiment, when the interlayer magnetic field gradient change rate is greater than a preset magnetic field gradient change rate threshold, the step of determining the corresponding electromagnetic abnormal area includes:

[0036] When the interlayer magnetic field gradient change rate is greater than a preset magnetic field gradient change rate threshold, the corresponding abnormal plane coordinates are determined, and the corresponding abnormal interlayer coordinates are determined by the time difference positioning method;

[0037] Determine corresponding abnormal three-dimensional coordinates based on the abnormal plane coordinates and the abnormal interlayer coordinates;

[0038] The area within a first preset radius with the abnormal three-dimensional coordinates as the center is recorded as the electromagnetic abnormal area.

[0039] In one embodiment, the step of performing a layered current injection test on the electromagnetic abnormal area through a probe to obtain the electrical abnormal area includes:

[0040] Inject multiple levels of preset direct current in sequence at preset time intervals at the abnormal three-dimensional coordinates through the probe, and record the area within a second preset radius centered on the abnormal three-dimensional coordinates as the initial electrical abnormal area; wherein the second preset radius is greater than the first preset radius;

[0041] Acquire the potential distribution in the initial electrical anomaly region, and when there is a sub-region in the initial electrical anomaly region whose potential gradient in two consecutive preset direct current steps is greater than a preset potential gradient threshold, use the sub-region as an electrical anomaly correction region;

[0042] Injecting an alternating current of a corresponding frequency into the electrical anomaly correction area based on the potential distribution of the electrical anomaly correction area, and obtaining a corresponding phase angle and impedance;

[0043] Injecting a corresponding pulse current into the electrical anomaly correction area according to the phase angle and the impedance, and acquiring corresponding waveform characteristics through a time domain reflection test;

[0044] The electrical abnormality correction region is corrected according to the waveform characteristics to generate a corresponding electrical abnormality region.

[0045] In one embodiment, the method further comprises:

[0046] Determine the corresponding defect type according to the waveform characteristics;

[0047] After the step of spatially matching the electromagnetic abnormal area with the electrical abnormal area, determining that a valid defect exists when the overlap between the two is higher than a preset threshold, and outputting the corresponding defect coordinates, the method further includes:

[0048] Output the corresponding defect type.

[0049] In addition, to achieve the above-mentioned purpose, the present application also proposes a multi-layer stacked motherboard testing device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and the computer program is configured to implement the steps of the multi-layer stacked motherboard testing method.

[0050] The multi-layer stacked motherboard testing method proposed in the present application determines the electromagnetic detection frequency band based on the number of layers and dielectric constant of the multi-layer stacked motherboard, and transmits the corresponding electromagnetic detection signal to the multi-layer stacked motherboard at the electromagnetic detection frequency band to obtain the original electromagnetic field data; then calculates the interlayer magnetic field gradient change rate of the multi-layer stacked motherboard based on the original electromagnetic field data; and when the interlayer magnetic field gradient change rate is greater than the preset magnetic field gradient change rate threshold, determines the corresponding electromagnetic abnormal area; then performs a layered current injection test in the electromagnetic abnormal area through a probe to obtain the electrical abnormal area; finally, the electromagnetic abnormal area is spatially matched with the electrical abnormal area, and when the overlap between the two is higher than the preset threshold, it is determined that there is an effective defect, and the corresponding defect coordinates are output. In this way, the present application uses an electromagnetic detection signal matching the specific structural parameters of the multi-layer stacked motherboard to perform a test to obtain the electromagnetic abnormal area, and performs a layered current injection test in the electromagnetic abnormal area through a probe to obtain the electrical abnormal area, and then spatially matches the acquired electromagnetic abnormal area with the electrical abnormal area to jointly determine the defect, thereby improving the accuracy of the multi-layer stacked motherboard detection, and the above detection method does not need to detect each layer of the multi-layer stacked motherboard one by one, thereby improving the test efficiency of the multi-layer stacked motherboard. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0052] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0053] Figure 1 A schematic diagram of a flow chart provided for an embodiment of a multi-layer stacked motherboard testing method of the present application;

[0054] Figure 2 A flow chart of another embodiment of the multi-layer stacked motherboard testing method provided by the present application;

[0055] Figure 3 A schematic diagram of a flow chart provided for another embodiment of the multi-layer stacked motherboard testing method of the present application;

[0056] Figure 4 For this application Figure 1 Detailed flowchart of step S200;

[0057] Figure 5 For this application Figure 1 Detailed flow chart of step S300;

[0058] Figure 6 For this application Figure 1 Detailed flowchart of step S400;

[0059] Figure 7 A structural schematic diagram of an embodiment of a multi-layer stacked motherboard testing device provided in the present application.

[0060] Description of Figure Numbers:

[0061] 10. Memory; 20. Processor.

[0062] The purpose, features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0063] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0064] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0065] The main solution of the embodiment of the present application is: determine the electromagnetic detection frequency band based on the number of layers and dielectric constant of the multi-layer stacked mainboard, and transmit the corresponding electromagnetic detection signal to the multi-layer stacked mainboard at the electromagnetic detection frequency band to obtain original electromagnetic field data; then calculate the interlayer magnetic field gradient change rate of the multi-layer stacked mainboard based on the original electromagnetic field data; and when the interlayer magnetic field gradient change rate is greater than the preset magnetic field gradient change rate threshold, determine the corresponding electromagnetic abnormal area; then perform a layered current injection test in the electromagnetic abnormal area through a probe to obtain the electrical abnormal area; finally, spatially match the electromagnetic abnormal area with the electrical abnormal area, and determine that there is a valid defect when the overlap between the two is higher than the preset threshold, and output the corresponding defect coordinates.

[0066] In this embodiment, for the convenience of description, the following description is made by taking a test device for identifying a multi-layer stacked motherboard as the execution subject.

[0067] In the prior art, motherboard testing is used to ensure that the performance and quality of the motherboard meet the design requirements, which is a crucial part of the electronic product manufacturing process. With the continuous development of electronic technology, multi-layer motherboards are widely used in various electronic devices due to their high density and high performance.

[0068] Traditional multi-layer motherboard testing is generally performed by testing each layer of the multi-layer motherboard one by one, which is not only time-consuming and labor-intensive, but also inefficient. In addition, due to the complex interlayer structure of the multi-layer motherboard, the existing testing methods are also difficult to accurately detect some minor defects inside it.

[0069] The solution provided by the present application is to improve the accuracy of multi-layer stacked motherboard detection by using electromagnetic detection signals matching the specific structural parameters of the multi-layer stacked motherboard for testing to obtain the electromagnetic abnormal area, and to perform a layered current injection test in the electromagnetic abnormal area through a probe to obtain the electrical abnormal area, and then to spatially match the acquired electromagnetic abnormal area and the electrical abnormal area to jointly determine the defects. The above detection method does not require testing each layer of the multi-layer stacked motherboard one by one, thereby improving the testing efficiency of the multi-layer stacked motherboard.

[0070] It should be noted that the execution subject of this embodiment can be a computing service device with data processing, network communication and program running functions, such as a tablet computer, a personal computer, etc., or an electronic device capable of realizing the above functions, a multi-layer stacked motherboard testing device, etc. The following takes a multi-layer stacked motherboard testing device as an example to illustrate this embodiment and the following embodiments.

[0071] Based on this, the present application embodiment provides a multi-layer stacked motherboard testing method, referring to Figure 1 In this embodiment, the multi-layer stacked motherboard testing method includes steps S100 to S500, wherein:

[0072] Step S100, determining an electromagnetic detection frequency band based on the number of layers and the dielectric constant of the multi-layer laminated mainboard, and transmitting a corresponding electromagnetic detection signal to the multi-layer laminated mainboard at the electromagnetic detection frequency band to obtain original electromagnetic field data.

[0073] It is understandable that due to the complex structure of the multi-layer stacked motherboard, different numbers of layers and dielectric constants respond differently to the electromagnetic detection signal. The more layers of the multi-layer stacked motherboard, the more significant the dielectric superposition effect that the electromagnetic signal experiences during the penetration process. The high-frequency component is easily absorbed by the surface due to the skin effect, and the low-frequency component can penetrate into the inner layer, but it may cause signal blur due to multi-path reflection. At the same time, material layers with different dielectric constants will cause non-uniform changes in electromagnetic wave velocity, aggravate signal phase distortion, and make it difficult for traditional single-band scanning to accurately capture deep-seated tiny defects. Therefore, it is necessary to adapt the electromagnetic detection frequency band according to the actual number of layers and dielectric properties of the multi-layer stacked motherboard, balance signal attenuation and defect sensitivity, so as to penetrate the complex stacked structure and lock hidden physical anomalies.

[0074] In a feasible implementation, step S100 includes determining the reference electromagnetic frequency according to the following formula:

[0075] ;

[0076] in, represents the reference electromagnetic frequency, Indicates the number of layers of a multi-stacked motherboard; Indicates the dielectric constant of a multi-layer stacked motherboard.

[0077] In this embodiment, the dielectric constant of the multi-layer stacked motherboard in the above formula is specifically the average effective dielectric constant of the multi-layer stacked motherboard, which can be weighted and calculated according to the dielectric constant of each layer of the motherboard. The constant "15GHz" in the above formula is an empirical constant, which is obtained through multiple experiments and is used to balance the signal penetration ability and defect detection sensitivity. For example, when detecting a 10-layer FR-4 motherboard ( ), When testing a 6-layer Rogers board ( ), The reference electromagnetic frequency calculated by this formula can be used as the starting point of the actual frequency scan, and a certain frequency range can be set around the reference frequency as the electromagnetic detection frequency band.

[0078] In a feasible embodiment, after obtaining the reference electromagnetic frequency, step S100 further includes determining the electromagnetic detection frequency band based on the reference electromagnetic frequency and the dielectric constant of the multi-layer stacked motherboard, wherein:

[0079] When the dielectric constant of the multi-layer laminated motherboard is less than 3.5, the electromagnetic detection frequency band is determined to be: ;

[0080] When the dielectric constant of the multi-layer laminated motherboard is greater than 3.5, the electromagnetic detection frequency band is determined to be: .

[0081] In this embodiment, the setting of the dielectric constant threshold of 3.5 is determined based on the typical characteristics of high-frequency and conventional PCB materials, the laws of electromagnetic wave propagation and engineering experience. In specific implementation, similar dielectric constant thresholds (such as 3.4, 3.6, etc.) can also be used for frequency band division. When the dielectric constant of a multi-layer stacked motherboard is small, the propagation speed of electromagnetic waves in it is faster and the attenuation is smaller. Therefore, the frequency range of the electromagnetic detection frequency band can be appropriately increased to improve the detection accuracy. When the dielectric constant of a multi-layer stacked motherboard is large, the propagation speed of electromagnetic waves in it is slower and the attenuation is larger. Therefore, it is necessary to appropriately reduce the frequency range of the electromagnetic detection frequency band to ensure that the signal can penetrate the multi-layer stacked motherboard to achieve the detection purpose. For example, when detecting a 10-layer FR-4 motherboard ( ), , then its actual frequency range is 0.57GHz~1.37GHz, and when testing a 6-layer Rogers board ( ), , then its actual frequency band is 1.15GHz~1.73GHz. In this way, by adapting the electromagnetic detection frequency band according to the actual number of layers and dielectric properties of the multi-layer stacked motherboard, balancing signal attenuation and defect sensitivity, the electromagnetic detection signal can penetrate the complex stacked structure and lock hidden physical anomalies.

[0082] In one possible implementation, reference Figure 1-2 Before step S200, the method further includes step S1001, identifying the blind hole ratio of the multi-layer stacked motherboard, and when the blind hole ratio is greater than a preset threshold, additionally transmitting an electromagnetic detection signal of a preset frequency band to the multi-layer stacked motherboard.

[0083] In this embodiment, the blind hole ratio of the multi-layer stacked motherboard can be identified by the image recognition module of the multi-layer stacked motherboard testing device. The image recognition module can analyze the scanned image of the multi-layer stacked motherboard, calculate the number and total area of ​​the blind holes, and then obtain the blind hole ratio. The setting of the preset threshold can be determined according to the conventional design parameters of the multi-layer stacked motherboard and the actual test requirements, and is not specifically limited here. When the blind hole ratio exceeds the preset threshold, it means that there may be a large number of blind hole structures inside the multi-layer stacked motherboard, and these blind holes may interfere with the electromagnetic detection signal and affect the accuracy of defect detection. Therefore, it is necessary to additionally transmit an electromagnetic detection signal of a preset frequency band to the multi-layer stacked motherboard. The preset frequency band can be determined according to the characteristics of the blind hole structure and the actual test requirements to ensure that the signal can penetrate the blind hole structure and achieve the detection purpose. In this way, the accuracy of the multi-layer stacked motherboard test can be further improved.

[0084] In one possible implementation, reference Figure 1 , Figure 3 Before step S200, the method further includes step S1002, determining the polarization direction of the electromagnetic detection signal based on the number of layers of the electromagnetic multi-layer stacked mainboard, specifically including: when the number of layers of the multi-layer stacked mainboard is an even number, determining the polarization direction of the electromagnetic detection signal to be left-hand circular polarization; when the number of layers of the multi-layer stacked mainboard is an odd number, determining the polarization direction of the electromagnetic detection signal to be right-hand circular polarization.

[0085] In this embodiment, in the detection of multi-layer stacked motherboards, the stacked structure of odd and even layers has different effects on the reflection and propagation path of electromagnetic waves. The even-numbered layers are prone to multiple reflection interference due to symmetry. Therefore, left-hand circular polarization is used in this embodiment to suppress the crosstalk of the same-direction reflection signal; while the odd-numbered layers cause the electromagnetic coupling path to be skewed due to asymmetry. Therefore, right-hand circular polarization is used in this embodiment to adapt the waveguide phase shift characteristics and enhance the electromagnetic field distortion characteristics at the defect. By matching the rotation direction with the number of layers, the background noise interference can be minimized, and the electromagnetic response contrast of interlayer micro-short circuits or dielectric anomalies can be improved, thereby improving the sensitivity and accuracy of defect detection.

[0086] In this embodiment, the electromagnetic detection signal can be transmitted to the multi-layer stacked motherboard through a programmable antenna array. The programmable antenna array can dynamically adjust its radiation characteristics, such as directivity and polarization, according to the preset electromagnetic detection frequency band to ensure that the electromagnetic detection signal can evenly and effectively cover the entire test area of ​​the multi-layer stacked motherboard. In addition, the programmable antenna array can also realize the multi-input and multi-output function to simultaneously transmit and receive multiple electromagnetic detection signals, further improving the test efficiency. The original electromagnetic field data can be collected by the electromagnetic field data acquisition module in the multi-layer stacked motherboard test device. The electromagnetic field data acquisition module can monitor and record the electromagnetic field generated by the interaction between the emitted electromagnetic detection signal and the multi-layer stacked motherboard in real time, thereby obtaining the original electromagnetic field data containing the internal defect information of the multi-layer stacked motherboard. By obtaining the original electromagnetic field data, it can provide a data basis for the subsequent identification of defects in the multi-layer stacked motherboard.

[0087] Step S200, calculating the interlayer magnetic field gradient change rate of the multi-layer laminated motherboard based on the original electromagnetic field data.

[0088] In this embodiment, the interlayer magnetic field gradient change rate refers to the change rate of the magnetic field strength between the layers of the multi-layer laminated mainboard, which reflects the unevenness of the electromagnetic field distribution inside the multi-layer laminated mainboard. By calculating the interlayer magnetic field gradient change rate, the areas where the electromagnetic field changes abnormally can be identified, and these areas are often the locations where defects exist inside the multi-layer laminated mainboard. When calculating the interlayer magnetic field gradient change rate, a preset formula or numerical differentiation method can be used to process the original electromagnetic field data to obtain the gradient value of the magnetic field strength of each layer, and then the interlayer magnetic field gradient change rate is obtained. When the interlayer magnetic field gradient change rate exceeds the preset threshold, it can be considered that there is an electromagnetic anomaly in the area and further detection is required.

[0089] In one possible implementation, reference Figure 4 , the step S200 includes steps S210 to S230, wherein:

[0090] Step S210, performing eddy current compensation on the original electromagnetic field data to obtain eddy current compensated electromagnetic field data.

[0091] In this embodiment, since the propagation of the electromagnetic detection signal in the multi-layer stacked motherboard will be affected by the eddy current effect, the measurement of the electromagnetic field data will be biased. Therefore, before calculating the interlayer magnetic field gradient change rate, it is necessary to perform eddy current compensation on the original electromagnetic field data to eliminate the influence of the eddy current effect on the measurement results. The specific method of eddy current compensation can be determined according to the material, structure and frequency of the electromagnetic detection signal of the multi-layer stacked motherboard, and is not specifically limited here. Through eddy current compensation, more accurate electromagnetic field data can be obtained, providing a reliable basis for subsequent calculations.

[0092] Step S220, calculating the interlayer magnetic field gradient of the multi-layer laminated motherboard based on the compensated electromagnetic field data.

[0093] In this embodiment, after obtaining the electromagnetic field data after eddy current compensation, the interlayer magnetic field gradient can be calculated based on the data. The interlayer magnetic field gradient refers to the change in the magnetic field strength between two adjacent layers of a multi-layer laminated motherboard, which reflects the subtle differences in the electromagnetic field distribution inside the multi-layer laminated motherboard. By calculating the interlayer magnetic field gradient, it is possible to further identify areas where the electromagnetic field has undergone slight changes, which may be the locations of potential defects inside the multi-layer laminated motherboard. When calculating the interlayer magnetic field gradient, a preset formula can be used to process the compensated electromagnetic field data to obtain the gradient value of the magnetic field strength of each layer.

[0094] In a feasible implementation manner, the interlayer magnetic field gradient is calculated according to the following formula:

[0095] ;

[0096] in, represents the interlayer magnetic field gradient, Indicates the first The electromagnetic field data of the layer, Indicates The dielectric thickness of the main board.

[0097] In this embodiment, the dielectric thickness can be obtained through the design parameters of the multi-layer laminated motherboard or actual measurement. By calculating the interlayer magnetic field gradient of each layer, the subtle difference in the electromagnetic field distribution inside the multi-layer laminated motherboard can be obtained, providing an important basis for subsequent defect determination.

[0098] Step S230, calculating the interlayer magnetic field gradient change rate of the multi-layer laminated mainboard based on the interlayer magnetic field gradient.

[0099] In this embodiment, based on the calculated interlayer magnetic field gradient, the interlayer magnetic field gradient change rate can be further obtained. The interlayer magnetic field gradient change rate refers to the change rate of the magnetic field gradient value between the layers of the multi-layer laminated motherboard, which reflects the degree of uneven distribution of the electromagnetic field inside the multi-layer laminated motherboard. By comparing the interlayer magnetic field gradient change rate with the preset threshold, it can be determined whether there is an electromagnetic abnormal area inside the multi-layer laminated motherboard. When the interlayer magnetic field gradient change rate is greater than the preset threshold, it can be considered that there is an electromagnetic abnormality in the area.

[0100] In a feasible implementation manner, the interlayer magnetic field gradient change rate is calculated according to the following formula:

[0101] ;

[0102] in, Indicates the rate of change of the interlayer magnetic field gradient of the multi-layer stacked motherboard, Indicates The interlayer magnetic field gradient of the layer, Indicates In this embodiment, the dielectric thickness can be obtained through design parameters of the multi-layer stacked main board or actual measurement.

[0103] Step S300, when the interlayer magnetic field gradient change rate is greater than a preset magnetic field gradient change rate threshold, determining a corresponding electromagnetic abnormal area.

[0104] In this embodiment, the setting of the preset magnetic field gradient change rate threshold can be comprehensively determined based on factors such as conventional design parameters of the multi-layer stacked motherboard, actual test requirements, and historical test data. When the interlayer magnetic field gradient change rate exceeds the preset threshold, it means that there is an electromagnetic anomaly in the corresponding area inside the multi-layer stacked motherboard, which may be the location of the defect. At this time, the system can automatically mark these electromagnetic anomaly areas and generate corresponding test reports for further analysis and processing by testers. In this way, rapid and accurate detection of internal defects of multi-layer stacked motherboards can be achieved, improving test efficiency and accuracy.

[0105] In one possible implementation, reference Figure 5 , step S300 includes steps S310 to S330, wherein:

[0106] Step S310, when the interlayer magnetic field gradient change rate is greater than a preset magnetic field gradient change rate threshold, the corresponding abnormal plane coordinates are determined, and the corresponding abnormal interlayer coordinates are determined by the time difference positioning method.

[0107] In this embodiment, the coordinates of the abnormal plane can be specifically determined according to the coordinate system established by the multi-layer stacked motherboard testing device based on a preset origin (for example, the lower left corner of the multi-layer stacked motherboard), and the coordinate system can accurately record the position of the electromagnetic abnormal area on the plane of the multi-layer stacked motherboard. The time difference positioning rule uses the time difference of the electromagnetic detection signal propagating in the multi-layer stacked motherboard to determine the interlayer position where the abnormality is located. Since the speed and path of the electromagnetic detection signal propagating between different layers may be different, the interlayer coordinates of the abnormality can be calculated by measuring the time difference of the electromagnetic detection signal reaching the abnormal area, and combining the interlayer structure and medium characteristics of the multi-layer stacked motherboard.

[0108] Step S320, determining corresponding abnormal three-dimensional coordinates based on the abnormal plane coordinates and the abnormal interlayer coordinates.

[0109] In this embodiment, the abnormal three-dimensional coordinates can be obtained by combining the abnormal plane coordinates and the abnormal interlayer coordinates, and the three-dimensional coordinates can accurately describe the specific position of the electromagnetic abnormal area in the multi-layer laminated motherboard. By determining the abnormal three-dimensional coordinates, the internal defects of the multi-layer laminated motherboard can be accurately located, providing an important basis for subsequent defect analysis and processing.

[0110] Step S330: record an area within a first preset radius with the abnormal three-dimensional coordinates as the center as the electromagnetic abnormal area.

[0111] In this embodiment, the specific value of the first preset radius can be determined comprehensively based on factors such as the size of the multi-layer stacked motherboard, the test accuracy requirements, and actual test experience. By setting the first preset radius, it can be ensured that the electromagnetic abnormal area and the surrounding areas that may be affected are included in the detection range, thereby improving the comprehensiveness and accuracy of defect detection.

[0112] Step S400: performing a layered current injection test in the electromagnetic abnormal area by using a probe to obtain the electrical abnormal area.

[0113] In this embodiment, the probe can be positioned to the precise position of the electromagnetic anomaly area through the multi-layer stacked motherboard test device, and then a current of preset frequency and amplitude can be injected into the area. During the current injection process, the multi-layer stacked motherboard test device will monitor and record the current distribution and voltage changes between the layers in real time. By comparing the current and voltage data of the normal area and the electromagnetic anomaly area, the area where the electrical properties have changed abnormally, that is, the electrical anomaly area, can be identified. These areas often correspond to the defect locations inside the multi-layer stacked motherboard. By obtaining the electrical anomaly area, it is possible to provide support for the subsequent spatial matching of the electromagnetic anomaly area and the electrical anomaly area to confirm the defect.

[0114] In a feasible implementation, before step S400, the method further includes starting an impedance matching network at a corresponding position of the electromagnetic anomaly area. In this embodiment, the main function of the impedance matching network is to adjust the impedance relationship between the electromagnetic detection signal and the multi-layer stacked motherboard to reduce signal reflection and energy loss, thereby improving the penetration ability and detection sensitivity of the electromagnetic detection signal. By starting the impedance matching network, it can be ensured that the electromagnetic detection signal can interact with the multi-layer stacked motherboard more effectively, thereby obtaining more accurate electromagnetic field data. In specific implementation, the parameters and specific structure of the impedance matching network can be dynamically adjusted according to the material, structure of the multi-layer stacked motherboard and the frequency of the electromagnetic detection signal to achieve the best matching effect.

[0115] In one possible implementation, reference Figure 6 , the step S400 includes steps S410 to S450, wherein:

[0116] Step S410, injecting multiple levels of preset direct current in sequence at preset time intervals at the abnormal three-dimensional coordinates through the probe, and recording the area within a second preset radius centered on the abnormal three-dimensional coordinates as the initial electrical abnormal area; wherein the second preset radius is larger than the first preset radius.

[0117] In this embodiment, the specific values ​​of the preset time interval and the multi-level preset DC current can be flexibly set according to the material, structural characteristics and actual test requirements of the multi-layer stacked motherboard, and are not limited here. By injecting multiple levels of preset DC current in sequence, the changes in electrical properties at different depths inside the multi-layer stacked motherboard can be gradually revealed, so as to more accurately locate the electrical abnormality area. The setting of the initial electrical abnormality area is to ensure that possible electrical abnormality areas and their surrounding potentially affected areas are included in the detection range. The design of the second preset radius being larger than the first preset radius can cover a wider area during the current injection test phase, thereby improving the comprehensiveness and accuracy of defect detection.

[0118] Step S420, obtaining the potential distribution in the initial electrical anomaly region, and when there is a sub-region in the initial electrical anomaly region whose potential gradient in two consecutive preset DC current steps is greater than a preset potential gradient threshold, the sub-region is used as an electrical anomaly correction region.

[0119] In this embodiment, the potential gradient is the amount of change in potential per unit length, which reflects the distribution of electric field strength. During the current injection test, by monitoring and recording the potential values ​​of each point in the initial electrical anomaly area, the potential distribution diagram of the area can be obtained. In two consecutive preset DC current steps, if the potential gradient of a sub-area is greater than the preset potential gradient threshold, it means that the electric field strength of the area has changed significantly, and it is likely to be the location of the internal defects of the multi-layer stacked motherboard. Therefore, using these sub-areas as electrical anomaly correction areas can narrow the scope of defect location and improve the accuracy of detection. In specific implementation, the setting of the preset potential gradient threshold can be comprehensively determined based on the material, structural characteristics and actual test requirements of the multi-layer stacked motherboard.

[0120] Step S430: injecting an alternating current of a corresponding frequency into the electrical anomaly correction area based on the potential distribution of the electrical anomaly correction area, and obtaining a corresponding phase angle and impedance.

[0121] In this embodiment, by injecting an alternating current of a corresponding frequency into the electrical anomaly correction area, the electromagnetic field in the area can be further excited and its response characteristics can be monitored. Phase angle and impedance are important parameters for describing the response of the electromagnetic field, and they can reflect subtle changes in the internal electrical properties of the multi-layer stacked motherboard. During the current injection process, the multi-layer stacked motherboard test device will monitor and record the phase angle and impedance data of the electrical anomaly correction area in real time. By comparing the phase angle and impedance data of the normal area with the electrical anomaly correction area, the electrical anomaly area can be further confirmed to provide a basis for accurate determination of defects.

[0122] Step S440, injecting a corresponding pulse current into the electrical anomaly correction area according to the phase angle and the impedance, and acquiring a corresponding waveform feature through a time domain reflection test.

[0123] In this embodiment, the time domain reflection test is a method for detecting the change of the characteristic impedance of the transmission line by using the reflection principle of electromagnetic waves in the transmission line. When the pulse current is injected into the electrical anomaly correction area, if there is a defect in the area, it will cause the reflection and scattering of the electromagnetic wave. The corresponding waveform receiver of the multi-layer stacked motherboard test device can capture the reflected electromagnetic wave signal and convert it into the corresponding waveform feature.

[0124] Step S450, correcting the electrical abnormality correction region according to the waveform characteristics to generate a corresponding electrical abnormality region.

[0125] In this embodiment, by comparing and analyzing the waveform characteristics under different pulse current injections, the scope of the electrical anomaly area can be further confirmed. The change in waveform characteristics is often closely related to the type, size and location of defects inside the multi-layer stacked motherboard. For example, certain specific waveform distortions may indicate the presence of defects such as cracks, holes or material unevenness. During the correction process, the electrical anomaly correction area can be subdivided and adjusted according to the similarities and differences of the waveform characteristics to ensure that the final generated electrical anomaly area can accurately reflect the defects inside the multi-layer stacked motherboard, so as to achieve in-depth analysis and precise positioning of the internal defects of the multi-layer stacked motherboard.

[0126] In a feasible implementation manner, the method further includes determining a corresponding defect type according to the waveform feature.

[0127] In this embodiment, since the change of waveform characteristics is often closely related to the defect type, size and position inside the multi-layer stacked motherboard. Therefore, the correspondence between the waveform characteristics and the defect type can be established in advance, and the correspondence can be established and optimized based on a large amount of experimental data and historical test experience to ensure the accuracy and reliability of the defect type determination. After determining the defect type, the tester can take corresponding repair measures for different types of defects to improve the quality and reliability of the multi-layer stacked motherboard. Through the correspondence between the above-mentioned waveform characteristics and defect types, the waveform characteristics obtained are compared with the waveform characteristics corresponding to different defect types, and the defect type can be accurately determined.

[0128] Step S500, spatially matching the electromagnetic abnormal area with the electrical abnormal area, determining that a valid defect exists when the overlap between the two is higher than a preset threshold, and outputting the corresponding defect coordinates.

[0129] In this embodiment, the spatial matching of the electromagnetic abnormal area and the electrical abnormal area can be achieved by comparing the position information of the two. Specifically, the coordinate system established by the multi-layer stacked motherboard testing device can be used to compare the three-dimensional coordinates of the electromagnetic abnormal area and the electrical abnormal area to determine the spatial relationship between them. The setting of the preset threshold can be comprehensively determined based on factors such as the test accuracy requirements of the multi-layer stacked motherboard, defect detection standards, and actual testing experience. When the overlap between the electromagnetic abnormal area and the electrical abnormal area is higher than the preset threshold, it means that the two areas are highly consistent in spatial position, which usually indicates that there is indeed a defect inside the multi-layer stacked motherboard. At this time, the system can be determined as a valid defect and output the corresponding defect coordinates.

[0130] In this embodiment, the defect coordinates can be obtained by comprehensively analyzing the three-dimensional coordinates of the electromagnetic abnormal area and the electrical abnormal area. Specifically, the center coordinates or geometric center of gravity of the electromagnetic abnormal area and the electrical abnormal area can be used as the preliminary estimated value of the defect coordinates, and then finely adjusted in combination with factors such as the shape, size and overlap degree of the two to obtain accurate defect coordinates. The output of the defect coordinates can be in a variety of ways, such as directly displaying on the display screen of the multi-layer stacked motherboard test device, generating a test report containing defect coordinate information, or exporting in the form of a data file, so that the tester can intuitively understand the specific location and distribution of the internal defects of the multi-layer stacked motherboard, so as to facilitate subsequent defect repair.

[0131] In a feasible implementation manner, the method further includes outputting a corresponding defect type.

[0132] In this embodiment, after determining that there is a valid defect and outputting the corresponding defect coordinates, the system can further output the corresponding defect type to provide key reference information for subsequent defect repair work. Specifically, the tester can select the corresponding repair method and tool according to the output defect type to efficiently solve the problems inside the multi-layer stacked motherboard. In addition, the output of the defect type also helps the tester to trace and analyze the production process and quality control process of the multi-layer stacked motherboard, so as to find out the possible causes of the defects and take effective measures to improve them, so as to improve the overall quality and reliability of the multi-layer stacked motherboard.

[0133] In this embodiment, the multi-layer stacked motherboard testing method determines the electromagnetic detection frequency band based on the number of layers and dielectric constant of the multi-layer stacked motherboard, and transmits the corresponding electromagnetic detection signal to the multi-layer stacked motherboard at the electromagnetic detection frequency band to obtain the original electromagnetic field data; then calculates the interlayer magnetic field gradient change rate of the multi-layer stacked motherboard based on the original electromagnetic field data; and when the interlayer magnetic field gradient change rate is greater than the preset magnetic field gradient change rate threshold, the corresponding electromagnetic abnormal area is determined; then the probe performs a layered current injection test in the electromagnetic abnormal area to obtain the electrical abnormal area; finally, the electromagnetic abnormal area is spatially matched with the electrical abnormal area, and when the overlap between the two is higher than the preset threshold, it is determined that there is an effective defect, and the corresponding defect coordinates are output. In this way, the present application is based on the specific structural parameters of the multi-layer stacked motherboard, and uses the electromagnetic detection signal matching it to perform the test to obtain the electromagnetic abnormal area, and performs a layered current injection test in the electromagnetic abnormal area by the probe to obtain the electrical abnormal area, and then the obtained electromagnetic abnormal area and the electrical abnormal area are spatially matched to jointly determine the defect, thereby improving the accuracy of the multi-layer stacked motherboard detection, and the above detection method does not need to detect each layer of the multi-layer stacked motherboard one by one, thereby improving the test efficiency of the multi-layer stacked motherboard.

[0134] The present application also provides a multi-layer stacked motherboard testing device, referring to Figure 7 The multi-layer stacked motherboard testing device includes a memory 10, a processor 20, and a computer program stored in the memory 10 and executable on the processor 20, wherein the computer program is configured to implement the steps of the multi-layer stacked motherboard testing method.

[0135] The multi-layer stacked motherboard testing device provided by the present application adopts the multi-layer stacked motherboard testing method in the above embodiment, which can improve the accuracy and testing efficiency of the multi-layer stacked motherboard testing. Compared with the prior art, the beneficial effects of the multi-layer stacked motherboard testing device provided by the present application are the same as the beneficial effects of the multi-layer stacked motherboard testing method provided by the above embodiment, and other technical features in the multi-layer stacked motherboard testing device are the same as the features disclosed in the above embodiment method, which will not be repeated here.

[0136] The above descriptions are only some embodiments of the present application, and are not intended to limit the patent scope of the present application. All equivalent structural changes made using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect applications in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A multi-layer stacked motherboard testing method, characterized in that: The method includes: Determine an electromagnetic detection frequency band based on the number of layers and the dielectric constant of the multi-layer stacked mainboard, and transmit a corresponding electromagnetic detection signal to the multi-layer stacked mainboard at the electromagnetic detection frequency band to obtain original electromagnetic field data; Calculate the interlayer magnetic field gradient change rate of the multi-layer stacked motherboard based on the original electromagnetic field data; When the interlayer magnetic field gradient change rate is greater than a preset magnetic field gradient change rate threshold, determining a corresponding electromagnetic anomaly area; Performing a layered current injection test in the electromagnetic abnormal area by using a probe to obtain the electrical abnormal area; The electromagnetic abnormal area is spatially matched with the electrical abnormal area, and when the overlap between the two is higher than a preset threshold, it is determined that there is a valid defect, and the corresponding defect coordinates are output.

2. The multi-layer motherboard testing method according to claim 1, characterized in that: The step of determining the electromagnetic detection frequency band based on the number of layers and the dielectric constant of the multi-layer laminated mainboard, and transmitting a corresponding electromagnetic detection signal to the multi-layer laminated mainboard at the electromagnetic detection frequency band to obtain the original electromagnetic field data includes: Determine the reference electromagnetic frequency according to the following formula: ； in, represents the reference electromagnetic frequency, Indicates the number of layers of a multi-stacked motherboard; Indicates the dielectric constant of the multi-layer stacked motherboard; The electromagnetic detection frequency band is determined based on the reference electromagnetic frequency and the dielectric constant of the multi-layer stacked motherboard, wherein: When the dielectric constant of the multi-layer laminated motherboard is less than 3.5, the electromagnetic detection frequency band is determined to be: ; When the dielectric constant of the multi-layer laminated motherboard is greater than 3.5, the electromagnetic detection frequency band is determined to be: .

3. The multi-layered motherboard testing method according to claim 2, characterized in that: Before the step of calculating the interlayer magnetic field gradient change rate of the multi-layer laminated mainboard based on the original electromagnetic field data, the method further includes: The blind hole ratio of the multi-layer stacked mainboard is identified, and when the blind hole ratio is greater than a preset threshold, an electromagnetic detection signal of a preset frequency band is additionally emitted to the multi-layer stacked mainboard.

4. The multi-layer motherboard testing method according to claim 1, wherein: Before the step of calculating the interlayer magnetic field gradient change rate of the multi-layer laminated mainboard based on the original electromagnetic field data, the method further includes: The polarization direction of the electromagnetic detection signal is determined based on the number of layers of the electromagnetic multi-layer stacked motherboard, specifically including: When the number of layers of the multi-layer stacked mainboard is an even number, determining that the polarization direction of the electromagnetic detection signal is left-hand circular polarization; When the number of layers of the multi-layer stacked mainboard is an odd number, the polarization direction of the electromagnetic detection signal is determined to be right-hand circular polarization.

5. The multi-layered motherboard testing method according to claim 1, wherein: The step of calculating the interlayer magnetic field gradient change rate of the multi-layer stacked motherboard based on the original electromagnetic field data includes: Performing eddy current compensation on the original electromagnetic field data to obtain electromagnetic field data after eddy current compensation; Calculating the interlayer magnetic field gradient of the multi-layer stacked motherboard based on the compensated electromagnetic field data; The interlayer magnetic field gradient change rate of the multi-layer laminated main board is calculated based on the interlayer magnetic field gradient.

6. The multi-layered motherboard testing method according to claim 5, characterized in that: The interlayer magnetic field gradient is calculated according to the following formula: ； in, represents the interlayer magnetic field gradient, Indicates the first The electromagnetic field data of the layer, Indicates The dielectric thickness of the layer motherboard; The interlayer magnetic field gradient change rate is calculated according to the following formula: ； in, Indicates the rate of change of the interlayer magnetic field gradient of the multi-layer stacked motherboard, Indicates The interlayer magnetic field gradient of the layer, Indicates The dielectric thickness of the main board.

7. The multi-layered motherboard testing method according to claim 1, wherein: When the interlayer magnetic field gradient change rate is greater than a preset magnetic field gradient change rate threshold, the step of determining the corresponding electromagnetic abnormal area comprises: When the interlayer magnetic field gradient change rate is greater than a preset magnetic field gradient change rate threshold, the corresponding abnormal plane coordinates are determined, and the corresponding abnormal interlayer coordinates are determined by the time difference positioning method; Determine corresponding abnormal three-dimensional coordinates based on the abnormal plane coordinates and the abnormal interlayer coordinates; The area within a first preset radius with the abnormal three-dimensional coordinates as the center is recorded as the electromagnetic abnormal area.

8. The multi-layered motherboard testing method according to claim 7, characterized in that: The step of performing a layered current injection test in the electromagnetic abnormal area by using a probe to obtain the electrical abnormal area includes: Inject multiple levels of preset direct current in sequence at preset time intervals at the abnormal three-dimensional coordinates through the probe, and record the area within a second preset radius centered on the abnormal three-dimensional coordinates as the initial electrical abnormal area; wherein the second preset radius is greater than the first preset radius; Acquire the potential distribution in the initial electrical anomaly region, and when there is a sub-region in the initial electrical anomaly region whose potential gradient in two consecutive preset DC current steps is greater than a preset potential gradient threshold, use the sub-region as an electrical anomaly correction region; Injecting an alternating current of a corresponding frequency into the electrical anomaly correction area based on the potential distribution of the electrical anomaly correction area, and obtaining a corresponding phase angle and impedance; Injecting a corresponding pulse current into the electrical anomaly correction area according to the phase angle and the impedance, and acquiring corresponding waveform characteristics through a time domain reflection test; The electrical abnormality correction region is corrected according to the waveform characteristics to generate a corresponding electrical abnormality region.

9. The multi-layered motherboard testing method according to claim 8, characterized in that: The method further comprises: Determine the corresponding defect type according to the waveform characteristics; After the step of spatially matching the electromagnetic abnormal area with the electrical abnormal area, determining that a valid defect exists when the overlap between the two is higher than a preset threshold, and outputting the corresponding defect coordinates, the method further includes: Output the corresponding defect type.

10. A multi-layer stacked motherboard testing device, characterized in that: The multi-layer stacked motherboard testing device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the multi-layer stacked motherboard testing method as described in any one of claims 1 to 9.

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