Wafer testing method and device and storage medium

Abstract

The invention provides a wafer test method and device and a storage medium, and the method comprises the steps: obtaining a test data file, obtaining a test data file of a to-be-tested wafer, testing a to-be-tested bare chip of the to-be-tested wafer, and obtaining an initial test result of the to-be-tested wafer; determining a retest area of the wafer to be tested according to the initial test result; the retest area is determined according to the offset of the to-be-tested bare chip which does not pass the test, and the retest area comprises at least one untested bare chip; and testing the to-be-tested wafer according to the bare chip information of the retest area to obtain a retest result of the to-be-tested wafer. According to the technical scheme, the test data file does not need to be replaced in the test process, cycle test is supported, and different test bare chip coordinates can be dynamically obtained in each test, so that the test time is shortened, the hardware use loss is reduced, and the accuracy of the yield is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of wafer testing, and in particular to a wafer testing method, device and storage medium. Background Art

[0002] At present, the semiconductor industry is developing rapidly and the output is increasing. More and more attention is paid to the testing time, cost and yield rate of wafers. Most of the testing methods used in existing technologies are single-step process testing methods. After the test of the current test file is completed, if the test needs to be adjusted, the test file needs to be modified each time before the test operation is performed. Data is obtained once for each test, and the cycle is repeated.

[0003] However, the single-step process test method has the defects that the test file for each test is immutable and needs to be manually modified to retest. Therefore, under this premise, how to shorten the test time, reduce the loss of hardware usage, and improve the yield rate is a problem worthy of attention. Therefore, a method that can save test time, reduce the operation process, and improve the bare die (DIE) coverage and accuracy of wafer testing is imperative. Summary of the invention

[0004] In view of this, an object of the present invention is to provide a wafer testing method, device and storage medium to shorten the testing time, reduce hardware usage loss and improve the accuracy of the yield rate.

[0005] In a first aspect, an embodiment of the present invention provides a wafer testing method, the method comprising: obtaining a test data file of a wafer to be tested, testing a bare die to be tested of the wafer to be tested, and obtaining an initial test result of the wafer to be tested; determining a retest area of ​​the wafer to be tested based on the initial test result; determining the retest area based on an offset of the bare die to be tested that has not passed the test, the retest area including at least one untested bare die; testing the wafer to be tested based on the bare die information of the retest area, and obtaining a retest result of the wafer to be tested.

[0006] In an optional embodiment of the present application, the above-mentioned wafer to be tested is divided into multiple test areas, and the initial test results include a first pass rate of the wafer to be tested, and multiple second pass rates corresponding to the multiple test areas; the retest area of ​​the wafer to be tested is determined according to the initial test results, including: determining the wafer to be tested or the test area as a retest object according to the first pass rate and the multiple second pass rates; and determining the retest area according to the bare die to be tested that failed the test in the retest object.

[0007] In an optional embodiment of the present application, the above-mentioned determination of the retest area of ​​the wafer to be tested based on the initial test results also includes: if the first pass rate meets the requirements, and there are pass rates to be retested that do not meet the requirements among the multiple second pass rates, then the test area corresponding to the pass rate to be retested is determined as the retest object; based on the bare chips to be tested that failed the test in the retest object, the retest area is determined; if the first pass rate does not meet the requirements, the wafer to be tested is determined as the retest object; and the retest area is determined based on all the bare chips to be tested in the retest object.

[0008] In an optional embodiment of the present application, the above-mentioned determining the retest area based on the bare die to be tested that failed the test in the retest object includes: determining the coordinates of the bare die to be tested that failed the test, the height and width of the bare die, and the offset value based on the test data file; determining the coordinates of the retest area based on the coordinates of the bare die to be tested, the height and width of the bare die, and the offset value.

[0009] In an optional embodiment of the present application, the above-mentioned testing of the wafer to be tested according to the bare chip information of the retest area to obtain the retest result of the wafer to be tested also includes: judging whether to update the retest area in the retest object according to the retest result; if the retest area is updated, the wafer to be tested is tested again based on the updated retest area to obtain a new retest result.

[0010] In an optional embodiment of the present application, if the re-survey area is updated as mentioned above, it also includes: setting the re-survey area to be updated as the current re-survey area, judging whether a new re-survey area can be obtained by offsetting according to the current re-survey area; if a new re-survey area cannot be obtained, updating the offset parameters of the current re-survey area to re-judgment whether a new re-survey area can be obtained; if a new re-survey area cannot be obtained according to the current re-survey area, updating the offset parameters of the previous re-survey area, and determining a new re-survey area by re-offsetting according to the previous re-survey area.

[0011] In an optional embodiment of the present application, the above-mentioned determining whether a new re-measurement area can be obtained by shifting according to the current re-measurement area includes: The position information in a retest area is obtained according to the current offset parameter to determine whether it is at the edge of the wafer and / or overlaps with other retest areas.

[0012] In an optional embodiment of the present application, the above-mentioned determining whether to update the retest area in the retest object based on the retest results also includes: determining whether the number of bare chips in the retest area meets the individual judgment requirements; if the number of bare chips meets the individual judgment requirements, determining whether to update the retest area in the retest object based on the retest results of a single retest area; if the number of bare chips does not meet the individual judgment requirements, determining whether to update the retest area in the retest object based on all the retest results in the retest object.

[0013] In an optional embodiment of the present application, the above-mentioned method of testing the wafer to be tested according to the die information of the retest area to obtain the retest result of the wafer to be tested includes: obtaining the die information of the retest area, updating the die information to the configuration file, the die information at least includes the die coordinate information; obtaining the die information of the configuration file, setting the die to be tested based on the die information, completing the retest of the wafer to be tested and obtaining the retest result of the wafer to be tested.

[0014] In an optional embodiment of the present application, the coordinates of the retest area are determined based on the coordinates of the die to be tested, the height and width of the die, and the offset value, including: determining the coordinates of the retest area based on the coordinates of the die to be tested, the height and width of the die, and the offset value by the following formula: ; ;in, and are the x-coordinate and y-coordinate of the lower left corner of the die in the retest area, and are the offset values ​​in the x and y directions respectively, and are the height and width of the die, and are the x-coordinate and y-coordinate of the die to be tested, is a step function.

[0015] In a second aspect, an embodiment of the present invention further provides a wafer testing device, the device comprising: a wafer initial testing module, used to obtain a test data file of a wafer to be tested, test a bare die to be tested of the wafer to be tested, and obtain an initial test result of the wafer to be tested; a retest area determination module, used to determine a retest area of ​​the wafer to be tested according to the initial test result; the retest area is determined according to the offset of the bare die to be tested that fails the test, and the retest area includes at least one untested bare die; a wafer retest module, used to test the wafer to be tested according to the bare die information of the retest area, and obtain a retest result of the wafer to be tested.

[0016] In a third aspect, an embodiment of the present invention further provides a computer-readable storage medium, which stores computer-executable instructions. When the computer-executable instructions are called and executed by a processor, the computer-executable instructions prompt the processor to implement the above-mentioned wafer testing method.

[0017] The embodiments of the present invention bring the following beneficial effects: The embodiment of the present invention provides a wafer testing method, device and storage medium, which obtains a test data file, obtains a test data file of a wafer to be tested, tests a bare die to be tested of the wafer to be tested, and obtains an initial test result of the wafer to be tested; determines a retest area of ​​the wafer to be tested according to the initial test result, the retest area includes at least one untested bare die; tests the wafer to be tested according to the bare die information of the retest area, and obtains a retest result of the wafer to be tested. In this method, while the test data file does not need to be replaced during the test process, cyclic testing is supported, and different test bare die coordinates can be dynamically obtained for each test, thereby shortening the test time, reducing hardware usage loss, and improving the accuracy of the yield rate.

[0018] Other features and advantages of the present disclosure will be set forth in the following description, or some features and advantages may be inferred or unambiguously determined from the description, or may be learned by implementing the above-mentioned technology of the present disclosure.

[0019] In order to make the above-mentioned objectives, features and advantages of the present disclosure more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 A flowchart of a wafer testing method provided by an embodiment of the present invention; Figure 2 A flowchart of another wafer testing method provided by an embodiment of the present invention; Figure 3 A schematic diagram of dividing a wafer to be tested into a plurality of test areas provided in an embodiment of the present invention; Figure 4 A schematic diagram of retesting area 1 provided in an embodiment of the present invention; Figure 5 A schematic diagram of a wafer testing method provided by an embodiment of the present invention; Figure 6 A schematic structural diagram of a wafer testing device provided by an embodiment of the present invention; Figure 7 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0023] At present, the semiconductor industry is developing rapidly and the output is increasing. The test time, cost and yield rate of wafers are becoming more and more important. Most of the test methods used in the existing technology are single-step process test methods. After the test of the current test file is completed, if the test needs to be adjusted, the test file needs to be modified each time before the test operation is performed. The test is performed once and the data is obtained once, and the cycle repeats. Or only the bare chips that have not passed the test can be tested repeatedly, but the wafer factory generally needs to test other untested wafers to increase the data sample size when the first test result is not ideal, so as to analyze more problems. At this time, the test operation can only be performed after the test file is modified each time. Under this premise, how to shorten the test time, reduce the loss of hardware use, and improve the yield rate is a problem worthy of attention. Therefore, a method that can save test time, reduce the operation process, and improve the bare chip coverage and accuracy of wafer testing is imperative.

[0024] However, the prior art has the following defects: 1) Based on most of the current wafer testing processes, the test files for each test are still kept immutable, which is not flexible enough and the data results are relatively simple. In order to obtain flexible data results for comparative observation or to obtain general conclusions, it is necessary to change the test files in time and compare them with a correct standard.

[0025] 2) In the existing technology, the retest function is enabled only under certain conditions (it can only test the previously set bare chips again, and cannot cover the previously unset bare chips for testing). However, this method is too customized, and retesting is not allowed if specific conditions are not met. At the same time, it increases the complexity of the code and requires the introduction of complex code logic.

[0026] 3) In the prior art, if one wants to dynamically obtain the test DIE coordinates for testing, one needs to stop the current test and manually modify the test file to achieve the purpose of modifying the test area, which is still not flexible enough in operation.

[0027] Based on this, an embodiment of the present invention provides a wafer testing method, device and storage medium, which can support cyclic testing without changing the test data file during the testing process, and can dynamically obtain different test DIE coordinates for each test, thereby shortening the test time, reducing hardware usage loss, and improving the accuracy of the yield rate.

[0028] To facilitate understanding of this embodiment, a wafer testing method disclosed in an embodiment of the present invention is first introduced in detail.

[0029] Embodiment 1: The present invention provides a wafer testing method. Figure 1 A flow chart of a wafer testing method is shown, and the wafer testing method includes the following steps: Step S102 , obtaining a test data file of the wafer to be tested, testing the bare die to be tested of the wafer to be tested, and obtaining an initial test result of the wafer to be tested.

[0030] In this embodiment, a test data file of a wafer to be tested can be obtained, and the properties of the wafer to be tested are preset in the test data file, including values ​​such as wafer size, quadrant, center coordinates, width and height of the die, offset value, etc. After obtaining the test data file, the test environment of the software and hardware to be tested can be deployed in this embodiment.

[0031] Step S104 , determining a retest area of ​​the wafer to be tested according to the initial test result, wherein the retest area includes at least one untested bare die.

[0032] In this embodiment, it can be determined whether the requirements are met based on the initial test results of the wafer to be tested. If the initial test results do not meet the requirements, it is necessary to select other bare chips for retesting, i.e., retesting. If retesting is required, in this embodiment, the retest area of ​​the wafer to be tested can be determined based on the initial test results, and then untested bare chips can be selected from the retest area for retesting.

[0033] Specifically, the retest area is determined according to the offset of the die to be tested that failed the test, and the test is performed by reacquiring untested die around the die to be tested that failed the test.

[0034] Step S106 , testing the wafer to be tested according to the bare die information of the retest area to obtain a retest result of the wafer to be tested.

[0035] This embodiment can retest the wafer to be tested based on the die information of the retest area, and use the qualified rate of the untested die in the retest area as the retest result. If the retest result still does not meet the requirements, this embodiment can reselect the retest area for another retest, and cycle multiple times until the retest result meets the requirements or the retest area cannot be obtained.

[0036] If the retest result meets the requirements, the test is completed. In this embodiment, more sampled test data can be obtained based on the initial test results and the retest results. Therefore, in this embodiment, dynamic acquisition of die coordinates for retesting is supported, and the test data file does not need to be replaced during the test process, which saves some operation time at the software and hardware levels, increases the diversity of test data, and greatly improves the accuracy of the yield rate.

[0037] The embodiment of the present invention provides a wafer testing method, which includes obtaining a test data file, obtaining a test data file of a wafer to be tested, testing a bare die to be tested of the wafer to be tested, and obtaining an initial test result of the wafer to be tested; determining a retest area of ​​the wafer to be tested according to the initial test result, wherein the retest area includes at least one untested bare die; testing the wafer to be tested according to the bare die information of the retest area, and obtaining a retest result of the wafer to be tested. In this method, while the test data file does not need to be replaced during the test process, cyclic testing is supported, and different test bare die coordinates can be dynamically obtained for each test, thereby shortening the test time, reducing hardware usage loss, and improving the accuracy of the yield rate.

[0038] Embodiment 2: This embodiment provides another wafer testing method, which is implemented on the basis of the above embodiment. Figure 2 A flow chart of another wafer testing method is shown, and the wafer testing method includes the following steps: Step S202 , obtaining a test data file of the wafer to be tested, testing the bare die to be tested of the wafer to be tested, and obtaining an initial test result of the wafer to be tested.

[0039] Among them, the above-mentioned test data file includes the wafer properties of the wafer to be tested and the information of the test die; the wafer properties include at least one of the following: wafer size, number of areas, height and width of the die, coordinates of the center die of the wafer, coordinates of the die to be tested of the wafer; the information of the test die includes the offset value.

[0040] In this embodiment, the wafer properties of the wafer to be tested and the information of the related test die can be pre-set in the test data file. This setting can be used as the data for the initial test during the test process. Once the setting is completed, the preset information can no longer be changed during the subsequent retest. After this embodiment, the test environment can be prepared and the software and hardware test environment can be deployed.

[0041] This embodiment can use a test data file for testing, wherein corresponding parameters can be set, and the test can be executed after deployment. The number of regions can be determined as n based on the test data file. Where n is a positive integer greater than or equal to 1; the wafer is divided into n test regions, and a bare die is selected from each region for testing based on the test data file and the test environment to determine the test data for this time.

[0042] See also Figure 3 A schematic diagram of dividing a wafer to be tested into several test areas is shown. Figure 3 The wafer to be tested is divided into 4 test areas (i.e., n=4). In subsequent tests, each test area can randomly select bare chips for testing to prevent the selection of test bare chips from being too concentrated.

[0043] Step S204, determining a retest region of the wafer to be tested according to the initial test result; the retest region is determined according to the offset of the bare die to be tested that failed the test, and the retest region includes at least one bare die that has not been tested.

[0044] In some embodiments, the wafer to be tested is divided into multiple test areas, and the initial test results include a first pass rate of the wafer to be tested, and multiple second pass rates corresponding to the multiple test areas; based on the first pass rate and the multiple second pass rates, the wafer to be tested or the test area is determined as a retest object; and the retest area is determined based on the bare die to be tested that failed the test in the retest object.

[0045] The initial test results in this embodiment may include a first pass rate of the entire wafer to be tested, and multiple second pass rates corresponding to each test area of ​​the wafer to be tested. By dividing the wafer into multiple test areas, only the test areas that do not meet the requirements can be retested separately; the division of the test areas determines the division mode according to the test requirements, such as it can be divided into five rings, and the offset rules are determined according to the division mode, and the division mode can be selected by the user or automatically determined according to the test content.

[0046] Among them, standard test data can be obtained; based on the initial test data and the standard test data, it is determined whether the bare die of this test is qualified, thereby determining the second qualified rate of the bare die in each test area and the first qualified rate of the entire wafer to be tested.

[0047] This embodiment can execute test examples (the test data file may include test examples, and the test examples include information about the relevant test dies and information on how to perform the test) to obtain initial test data, and compare the initial test data with standard test data to determine whether each die is qualified.

[0048] Before the test, the present embodiment can first test the data of all the dies on a standard wafer, thereby obtaining a standard and correct data file, namely the above-mentioned standard test data. During the test, the present embodiment can test the dies in different test areas to obtain initial test data, and the initial test data is compared with the standard test data to determine whether the dies in each area are qualified.

[0049] After determining whether each bare die is qualified, in this embodiment, a retest object can be further determined, wherein the retest object can be the entire wafer to be tested, or one or several test areas of the wafer to be tested.

[0050] In some embodiments, if the first pass rate meets the requirements, and there are pass rates to be retested that do not meet the requirements among the multiple second pass rates, then the test area corresponding to the pass rate to be retested is determined as the retest object; the retest area is determined based on the bare chips to be tested that failed the test in the retest object; if the first pass rate does not meet the requirements, the wafer to be tested is determined as the retest object; and the retest area is determined based on all the bare chips to be tested in the retest object.

[0051] For example, after determining whether each bare die is qualified, the first qualified rate of all test areas of the wafer to be tested can be further determined in this embodiment. If the first qualified rate does not meet the requirements, it means that all test areas of the wafer to be tested need to be retested. At this time, the retest object can be all test areas of the wafer to be tested.

[0052] Alternatively, if the first qualified rate meets the requirements, in this embodiment, a second qualified rate of each test area of ​​the wafer to be tested can be further determined. If the second qualified rate of the test object and / or the target area does not meet the requirements, it means that the target area needs to be retested. At this time, the retest object can be the target area.

[0053] After determining the retest object, the present embodiment can further determine the retest area of ​​the retest object. In the present embodiment, a retest area can be selected around the unqualified bare die of the retest object, and a specified number of bare die in the retest area can be retested, and then the retested test data can be compared with the standard test data to determine whether the bare die in the retested area to be tested is qualified. It is worth noting that if the wafer to be tested is the retest object, the retest area can only include one untested bare die offset according to the wafer to be tested.

[0054] In some embodiments, the coordinates of the die under test that failed the test, the height and width of the die, and the offset value can be determined based on the test data file; the coordinates of the retest area can be determined based on the coordinates of the die under test, the height and width of the die, and the offset value.

[0055] Among them, the test object is taken as an example of a certain area to be tested. In this embodiment, the number of bare chips to be retested (assuming it is 9) can be determined first, and the size of the area to be tested (3×3) can be determined based on the number of bare chips to be retested. According to the visual comparison analysis function, the unqualified bare chips in the area to be tested can be determined, and an anchor frame of the above size (3×3) is set around the unqualified bare chips, and the new bare chip coordinates in the anchor frame are obtained for retesting (i.e., retesting). If the pass rate of the retest is still less than the threshold, the anchor frame position can be cyclically moved for retesting again until the anchor frame range exceeds the wafer to be tested. At this time, the part of the anchor frame that exceeds the wafer to be tested is not tested, and the part of the anchor frame that does not exceed the wafer is tested.

[0056] For example, see Figure 4 The diagram shows a retest of area 1. Assume that 10 dies are selected for testing in area 1, and 2 dies fail the first test (the pass rate threshold is defined as 90%, and the pass rate of the first test is 80% < the threshold 90%). When retesting, you need to first determine the size of the anchor frame ( Figure 4 In the example, the 6 die in the anchor frame are retested. If only 2 of the 6 retested die are qualified, the retest qualified rate is 33.33% < the threshold value of 90%, and the anchor frame needs to be reselected for retesting.

[0057] The coordinates of the retest area can be determined by the following formula based on the coordinates of the die to be tested, the height and width of the die, and the offset value: ; ; in, and are the x-coordinate and y-coordinate of the lower left corner of the die in the retest area, and are the offset values ​​in the x and y directions respectively, and are the height and width of the die, and are the x-coordinate and y-coordinate of the die to be tested, is a step function.

[0058] The x coordinate of the lower left corner of the anchor box needs to be re-determined each time the test is repeated. and the y coordinate . The first time the retest and The x-coordinate and y-coordinate of the lower left corner of the die to be tested can be used for retesting after the second time. and They can be the x-coordinate and y-coordinate of the lower left corner of the anchor box during the previous remeasurement.

[0059] In some embodiments, it can also be determined whether to update the retest area in the retest object based on the retest result; if the retest area is updated, the wafer to be tested is tested again based on the updated retest area to obtain a new retest result.

[0060] If the retest results of the wafer to be tested (which can be the qualified rate of a single retest area or all retest areas) still do not meet the requirements, retesting is required. At this time, the retest area needs to be updated in the retest object; the wafer to be tested is tested again based on the updated retest area to obtain a new retest result.

[0061] See also Figure 5 The schematic diagram of a wafer testing method shown in the figure shows that if the qualified rate is less than the threshold value after the initial test, retesting is required. Each retesting requires moving the anchor frame to determine the qualified rate of the bare die in the anchor frame until the qualified rate of the bare die in the retested anchor frame is greater than or equal to the threshold value, then the cyclic retesting ends, and the final test result of the wafer can be determined based on the initial test result and the retest result. At the same time, the present embodiment can also mark the retest result in the final test result.

[0062] In some embodiments, updating the resurvey area may be performed as follows: the resurvey area to be updated is set as the current resurvey area, and it is determined whether a new resurvey area can be obtained by offsetting based on the current resurvey area; if a new resurvey area cannot be obtained, the offset parameters of the current resurvey area are updated to re-determine whether a new resurvey area can be obtained; if a new resurvey area cannot be obtained based on the current resurvey area, the offset parameters of the previous resurvey area are updated, and the new resurvey area is determined by re-offsetting based on the previous resurvey area.

[0063] Among them, the current resurvey area is obtained according to the offset parameters of the previous resurvey area. If the current resurvey area needs to be updated, in case that the new resurvey area is located at the edge or overlaps with other resurvey areas, in order to ensure the quality of the acquired data, it will be determined first whether a resurvey area that meets the requirements can be obtained. If not, the offset parameters will be updated (for example, the offset direction will be updated. For example, the four corners are set as the offset directions, and the offset parameters of different angles can be obtained in turn in a clockwise or counterclockwise direction for update; of course, the offset parameters can be a combination of one or both of the offset direction and the offset amount); if a resurvey area that meets the requirements cannot be obtained around the current resurvey area, a new resurvey area can be obtained by updating the offset parameters of the previous resurvey area.

[0064] In some embodiments, determining whether a new retest area can be obtained by shifting the current retest area includes: obtaining position information within a retest area according to current shift parameters, and determining whether it is at the edge of the wafer and / or overlaps with other retest areas.

[0065] In some embodiments, whether to update the retest area in the retest object is determined based on the retest results. A simple judgment can be made based on the yield of the retest results, and a comprehensive judgment can be made based on the bare chip data in the retest area. For example, it can be determined whether the number of bare chips in the retest area meets the individual judgment requirements; if the number of bare chips meets the individual judgment requirements, then it is determined whether to update the retest area in the retest object based on the retest results of a single retest area; if the number of bare chips does not meet the individual judgment requirements, then it is determined whether to update the retest area in the retest object based on all the retest results in the retest object.

[0066] After updating the retest area, the embodiment may also determine whether the number of bare dies in the retest area meets the individual determination requirement. For example, the determination requirement may be that each retest requires 10 untested bare dies in the retest area.

[0067] If the number of untested bare chips in the retest area is greater than or equal to 10, it is considered that the retest area meets the judgment requirements, and it can be determined whether to update the retest area in the retest object based on the retest results of the single retest area. If the number of untested bare chips in the retest area is less than 10, it is considered that the retest area does not meet the judgment requirements, and it can be determined whether to update the retest area in the retest object based on all the retest results in the retest object.

[0068] Step S206, obtaining die information of the retest area, and updating the die information to the configuration file, wherein the die information at least includes die coordinate information; obtaining the die information of the configuration file, setting the die to be tested based on the die information, completing the retest of the wafer to be tested and obtaining the retest result of the wafer to be tested.

[0069] When retesting, the die information of the retest area can be obtained and updated to the configuration file, where the die information at least includes the die coordinate information; the die information of the configuration file is obtained and set as the die to be tested, and the retest of the wafer to be tested is completed, thereby obtaining the retest result of the wafer to be tested.

[0070] The wafer testing method provided by the embodiment of the present invention has the following advantages: 1) Reduce time cost: In the past, if you want to test different test dies or retest a specified scenario, you need to stop the test, manually change the test data, and stop the machine. This will take up a lot of testing time during the mass production process, and the operation is also cumbersome. The above method provided by the embodiment of the present invention can support multiple cycles of testing when there is no need to change the test data file, and different test dies can be selected for each test, thereby reducing the time cost of operation.

[0071] 2) Improving the accuracy of yield rate: In traditional sampling tests, the test data is relatively simple, too concentrated, and has a small coverage rate. The above-mentioned method provided by the embodiment of the present invention can diversify the test samples, enrich the test data, and improve the accuracy of the yield rate.

[0072] 3) Wide range of applicable scenarios: The rules for cyclic retesting of the mobile anchor frame used in this invention are not only applicable to WAT (wafer acceptance test) testers and WLR (wafer wafer reliability test, Level Reliability Testing) testers, but also support various types of wafer tests and are widely applicable.

[0073] Embodiment three: Corresponding to the above method embodiment, the present invention provides a wafer testing device, see Figure 6 The structure diagram of a wafer testing device shown in FIG. 1 includes: The wafer initial test module 61 is used to obtain the test data file of the wafer to be tested, test the bare die to be tested of the wafer to be tested, and obtain the initial test result of the wafer to be tested; A retest region determination module 62 is used to determine a retest region of the wafer to be tested according to the initial test result; the retest region is determined according to the offset of the die to be tested that failed the test, and the retest region includes at least one untested die; The wafer retest module 63 is used to test the wafer to be tested according to the bare die information in the retest area to obtain the retest result of the wafer to be tested.

[0074] The embodiment of the present invention provides a wafer testing device, which obtains a test data file, obtains a test data file of a wafer to be tested, tests a bare die to be tested of the wafer to be tested, and obtains an initial test result of the wafer to be tested; determines a retest area of ​​the wafer to be tested according to the initial test result, the retest area includes at least one untested bare die; tests the wafer to be tested according to the bare die information of the retest area, and obtains a retest result of the wafer to be tested. In this method, while the test data file does not need to be replaced during the test process, cyclic testing is supported, and different test bare die coordinates can be dynamically obtained for each test, thereby shortening the test time, reducing hardware usage loss, and improving the accuracy of the yield rate.

[0075] The wafer to be tested is divided into multiple test areas, and the initial test results include a first pass rate of the wafer to be tested and multiple second pass rates corresponding to the multiple test areas; the retest area determination module is used to determine the wafer to be tested or the test area as a retest object based on the first pass rate and the multiple second pass rates; and determine the retest area based on the bare die to be tested that failed the test in the retest object.

[0076] The above-mentioned retest area determination module is also used to determine the test area corresponding to the pass rate to be retested as the retest object if the first pass rate meets the requirements and there are pass rates to be retested that do not meet the requirements among the multiple second pass rates; determine the retest area based on the bare chips to be tested that failed the test in the retest object; if the first pass rate does not meet the requirements, determine the wafer to be tested as the retest object; determine the retest area based on all the bare chips to be tested in the retest object.

[0077] The retest area determination module is used to determine the coordinates of the untested die, the height and width of the die, and the offset value based on the test data file; and determine the coordinates of the retest area based on the coordinates of the untested die, the height and width of the die, and the offset value.

[0078] The retest area determination module is also used to determine whether to update the retest area in the retest object according to the retest result; if the retest area is updated, the wafer to be tested is tested again based on the updated retest area to obtain a new retest result.

[0079] The above-mentioned re-survey area determination module is also used to set the re-survey area to be updated as the current re-survey area, and judge whether a new re-survey area can be obtained by offsetting according to the current re-survey area. If the new re-survey area cannot be obtained, the offset parameters of the current re-survey area are updated to re-judgment whether a new re-survey area can be obtained; if the new re-survey area cannot be obtained according to the current re-survey area, the offset parameters of the previous re-survey area are updated, and the new re-survey area is determined by re-offsetting according to the previous re-survey area.

[0080] The retest area determination module is further used to obtain position information within a retest area according to the current offset parameter, and determine whether it is at the edge of the wafer and / or overlaps with other retest areas.

[0081] The above-mentioned retest area determination module is used to determine whether the number of bare chips in the retest area meets the individual judgment requirements; if the number of bare chips meets the individual judgment requirements, it is determined whether to update the retest area in the retest object based on the retest results of a single retest area; if the number of bare chips does not meet the individual judgment requirements, it is determined whether to update the retest area in the retest object based on all the retest results in the retest object.

[0082] The above-mentioned retest area determination module is used to obtain the die information of the retest area and update the die information to the configuration file, where the die information at least includes the die coordinate information; obtain the die information of the configuration file, set the die to be tested based on the die information, complete the retest of the wafer to be tested and obtain the retest result of the wafer to be tested.

[0083] The retest area determination module is used to determine the coordinates of the retest area based on the coordinates of the die to be tested, the height and width of the die, and the offset value by the following formula: ; ;in, and are the x-coordinate and y-coordinate of the lower left corner of the die in the retest area, and are the offset values ​​in the x and y directions respectively, and are the height and width of the die, and are the x-coordinate and y-coordinate of the die to be tested, is a step function.

[0084] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the wafer testing device described above can refer to the corresponding process in the aforementioned embodiment of the wafer testing method, and will not be repeated here.

[0085] Embodiment 4: The embodiment of the present invention also provides an electronic device for running the above wafer testing method; see Figure 7 A structural schematic diagram of an electronic device is shown, which includes a memory 100 and a processor 101, wherein the memory 100 is used to store one or more computer instructions, and the one or more computer instructions are executed by the processor 101 to implement the above-mentioned wafer testing method.

[0086] Further, Figure 7 The electronic device shown further includes a bus 102 and a communication interface 103 , and the processor 101 , the communication interface 103 and the memory 100 are connected via the bus 102 .

[0087] The memory 100 may include a high-speed random access memory (RAM), and may also include a non-volatile memory, such as at least one disk storage. The communication connection between the system network element and at least one other network element is realized through at least one communication interface 103 (which may be wired or wireless), and the Internet, wide area network, local area network, metropolitan area network, etc. may be used. The bus 102 may be an ISA bus, a PCI bus, or an EISA bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 7 Only one bidirectional arrow is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0088] The processor 101 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit or software instructions in the processor 101. The above processor 101 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiments of the present invention can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in conjunction with the embodiments of the present invention can be directly embodied as a hardware decoding processor for execution, or a combination of hardware and software modules in the decoding processor for execution. The software module may be located in a storage medium mature in the art, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory 100, and the processor 101 reads the information in the memory 100 and completes the steps of the method of the above embodiment in combination with its hardware.

[0089] An embodiment of the present invention also provides a computer-readable storage medium, which stores computer-executable instructions. When the computer-executable instructions are called and executed by a processor, the computer-executable instructions prompt the processor to implement the above-mentioned wafer testing method. The specific implementation can be found in the method embodiment, which will not be repeated here.

[0090] The computer program product of the wafer testing method, device and storage medium provided in the embodiments of the present invention includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the method in the previous method embodiment. The specific implementation can be found in the method embodiment, which will not be repeated here.

[0091] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system and / or device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0092] In addition, in the description of the embodiments of the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0093] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0094] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0095] Finally, it should be noted that the above-described embodiments are only specific implementations of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The protection scope of the present invention is not limited thereto. Although the present invention is described in detail with reference to the above-mentioned embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-mentioned embodiments within the technical scope disclosed by the present invention, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A wafer testing method, characterized in that: The method comprises: Acquire a test data file of a wafer to be tested, test a bare die to be tested of the wafer to be tested, and obtain an initial test result of the wafer to be tested; Determine a retest area of ​​the wafer to be tested according to the initial test result; the retest area is determined according to the offset of the bare die to be tested that failed the test, and the retest area includes at least one bare die that has not been tested; The wafer to be tested is tested according to the bare die information of the retest area to obtain a retest result of the wafer to be tested.

2. The testing method according to claim 1, characterized in that: The wafer to be tested is divided into a plurality of test areas, and the initial test result includes a first qualified rate of the wafer to be tested and a plurality of second qualified rates corresponding to the plurality of test areas; Determining a retest area of ​​the wafer to be tested according to the initial test result includes: Determining the wafer to be tested or the test area as a retest object according to the first qualified rate and a plurality of the second qualified rates; A retest area is determined according to the bare chips to be tested that have failed the test in the retest object.

3. The testing method according to claim 2, characterized in that: Determining a retest area of ​​the wafer to be tested according to the initial test result, further comprising: If the first qualified rate meets the requirement, and there is a qualified rate to be retested that does not meet the requirement among the plurality of the second qualified rates, then determining the test area corresponding to the qualified rate to be retested as the retest object; and determining the retest area according to the bare die to be tested that failed the test in the retest object; If the first qualified rate does not meet the requirement, the wafer to be tested is determined as a retest object; and a retest area is determined according to all the bare dies to be tested in the retest object.

4. The testing method according to claim 2, characterized in that: Determining a retest area according to the untested bare die in the retest object includes: Determine the coordinates of the die to be tested that failed the test, the height and width of the die, and the offset value based on the test data file; The coordinates of the retest area are determined based on the coordinates of the die to be tested, the height and width of the die, and the offset value.

5. The testing method according to claim 2, characterized in that: The wafer to be tested is tested according to the bare die information of the retest area to obtain a retest result of the wafer to be tested, and further includes: Determining whether to update the retest area in the retest object according to the retest result; If the retest area is updated, the wafer to be tested is tested again based on the updated retest area to obtain a new retest result.

6. The testing method according to claim 5, characterized in that: If the retest area is updated, it also includes: Set the re-measurement area to be updated as the current re-measurement area, and determine whether a new re-measurement area can be obtained by offsetting the current re-measurement area. If a new re-measurement area cannot be obtained, update the offset parameters of the current re-measurement area and re-determine whether a new re-measurement area can be obtained. If a new resurvey area cannot be obtained based on the current resurvey area, the offset parameters of the previous resurvey area are updated, and the new resurvey area is determined based on the offset of the previous resurvey area.

7. The testing method according to claim 5, characterized in that: Determine whether a new re-test area can be obtained by offsetting the current re-test area, including: The position information in a retest area is obtained according to the current offset parameter to determine whether it is at the edge of the wafer and / or overlaps with other retest areas.

8. The testing method according to claim 5, characterized in that: Judging whether to update the retest area in the retest object according to the retest result also includes: Determining whether the number of bare chips in the retest area meets the individual determination requirements; If the number of bare chips meets the individual determination requirement, determining whether to update the retest area in the retest object according to the retest result of the single retest area; If the number of bare chips does not meet the individual determination requirement, it is determined whether to update the retest area in the retest object according to all retest results in the retest object.

9. The testing method according to claim 1, characterized in that: Testing the wafer to be tested according to the bare die information of the retest area to obtain a retest result of the wafer to be tested, including: Obtaining die information of the retest area, and updating the die information into a configuration file, wherein the die information at least includes die coordinate information; The die information of the configuration file is obtained, the die to be tested is set based on the die information, the retest of the wafer to be tested is completed and the retest result of the wafer to be tested is obtained.

10. The method according to claim 4, characterized in that Determining the coordinates of the retest area based on the coordinates of the die to be tested, the height and width of the die, and the offset value includes: The coordinates of the retest area are determined based on the coordinates of the die to be tested, the height and width of the die, and the offset value by the following formula: ； ； in, and are the x-coordinate and y-coordinate of the lower left corner of the die in the retest area, and are the offset values ​​in the x and y directions respectively, and are the height and width of the die, respectively, and are the x-coordinate and y-coordinate of the die to be tested, is a step function.

11. A wafer testing device, characterized in that: The device comprises: The wafer initial test module is used to obtain the test data file of the wafer to be tested, test the bare die to be tested of the wafer to be tested, and obtain the initial test result of the wafer to be tested; A retest area determination module, configured to determine a retest area of ​​the wafer to be tested according to the initial test result; the retest area is determined according to the offset of the die to be tested that failed the test, and the retest area includes at least one untested die; The wafer retest module is used to test the wafer to be tested according to the bare die information of the retest area to obtain the retest result of the wafer to be tested.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions. When the computer-executable instructions are called and executed by a processor, the computer-executable instructions prompt the processor to implement the wafer testing method according to any one of claims 1 to 10.

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