Memory page migration method and related device thereof

Abstract

The invention discloses a memory page migration method and related device.The memory page migration method comprises the steps that first information of a memory page is obtained, the first information is used for representing the reliability of the memory page, and the first information is obtained based on static analysis of a program; when the first information of the memory page changes, obtaining a target memory node of the memory page; and the memory page is migrated to the target memory node, so that the reliability of the memory system is improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a memory page migration method and related devices. Background Art

[0002] In heterogeneous memory systems, the failure rates of different memory sticks vary, but current mainstream operating systems have no mechanism to manage application process data according to memory reliability levels, which results in a decrease in the overall reliability of the system.

[0003] In order to improve the reliability of memory, the current general method of tracing is to migrate memory pages. The program behavior of the executable program executed online is tracked, and then the memory pages are migrated based on the tracing data to improve the reliability of memory. However, this method can only analyze a program executed online once, which is very expensive. Summary of the invention

[0004] The present application provides a memory page migration method and related devices, which can improve the reliability of the memory system.

[0005] In a first aspect, the present application provides a method for migrating a memory page, comprising:

[0006] First, first information of a memory page is obtained, wherein the first information is used to characterize the reliability of the memory page and is obtained based on static analysis of the program; then, when the first information of the memory page changes, a target memory node of the memory page is obtained; finally, the memory page is migrated to the target memory node.

[0007] Compared with the online migration of memory pages based on a single program being executed, this application performs online analysis based on the first information obtained by static analysis, which can take into account different program inputs, flexibly generate different configuration files, and does not occupy resources during program execution, so that when performing page migration, dynamic migration can be performed directly based on the first information generated offline, thereby ensuring the stability of program execution. In addition, based on the first information generated by static analysis, the behavior of different program executions is accurately analyzed, thereby achieving more accurate and fine-grained reliability analysis, migrating pages to the most suitable memory medium, and improving the reliability of the memory system.

[0008] In a possible implementation, the first information of the memory page is obtained based on the read / write characteristics and / or cache characteristics of the data and instructions in the memory page.

[0009] In this implementation, the reliability of the memory page is analyzed based on the read and write characteristics and / or cache characteristics of the data and instructions in the memory page, so that a more accurate and fine-grained reliability analysis can be achieved.

[0010] In a possible implementation, the read and write characteristics of data and instructions include read and write error tolerance of data and instructions.

[0011] In this implementation, based on the statistics of the fault tolerance rate of the read and write behaviors of the data in the memory pages, a more accurate and fine-grained reliability analysis can be performed in combination with the read and write behaviors of the data, so that the pages can be migrated to the most suitable memory medium, thereby achieving the purpose of placing businesses with higher fault tolerance in high-performance memory and businesses with lower fault tolerance in ordinary memory.

[0012] In a possible implementation, the cache characteristics of data and instructions include cache fault tolerance of data and instructions.

[0013] In this implementation, based on the statistics of the fault tolerance rate of the cache behavior of the data in the memory page, a more accurate and fine-grained reliability analysis can be performed in combination with the cache behavior of the data, so that the page can be migrated to the most suitable memory medium, thereby achieving the purpose of placing businesses with higher fault tolerance in high-performance memory and businesses with lower fault tolerance in ordinary memory.

[0014] In a possible implementation, the first information of the memory page is obtained based on the heat of the memory page and the read / write characteristics and / or cache characteristics of the data and instructions in the memory page.

[0015] In this implementation, the memory reliability problem is divided into multiple dimensions for consideration, and the reliability of the memory page is evaluated from multiple aspects such as the heat of the memory page and the read and write characteristics and / or cache characteristics of the data, thereby improving the accuracy of the memory reliability analysis.

[0016] In a possible implementation, the program includes multiple logic blocks, each logic block corresponds to at least one memory page, and the condition for the first information of the memory page corresponding to the first logic block to change is:

[0017] The first logic block jumps when it is executed.

[0018] In a possible implementation, obtaining a target memory node of a memory page includes:

[0019] Get the first information of the changed memory page;

[0020] Acquire second information, where the second information includes reliability information corresponding to each memory node of the non-uniform memory access NUMA;

[0021] The target memory node is determined according to the first information and the second information of the changed memory page.

[0022] In this implementation, the reliability of the memory page and the reliability of each memory node of NUMA are comprehensively considered to migrate the memory page to the most appropriate memory node.

[0023] In a possible implementation, the second information further includes: memory access latency information corresponding to each memory node of the NUMA, system overhead corresponding to each memory node after the changed memory page is migrated, and user demand information.

[0024] In a possible implementation, before migrating the memory page to the target memory node, the method further includes:

[0025] The memory node where the determined memory page is located is inconsistent with the target memory node.

[0026] In a second aspect, the present application provides a memory page migration device, the device comprising:

[0027] A memory information acquisition module, used to acquire first information of a memory page, the first information is used to characterize the reliability of the memory page, and the first information is obtained based on static analysis of the program;

[0028] A memory node acquisition module, used to acquire a target memory node of a memory page when the first information of the memory page changes;

[0029] The memory page migration module is used to migrate the memory page to the target memory node.

[0030] In a possible implementation, the first information of the memory page is obtained based on the read / write characteristics and / or cache characteristics of the data and instructions in the memory page.

[0031] In a possible implementation, the read and write characteristics of data and instructions include read and write error tolerance of data and instructions.

[0032] In a possible implementation, the cache characteristics of data and instructions include cache fault tolerance of data and instructions.

[0033] In a possible implementation, the first information of the memory page is obtained based on the heat of the memory page and the read / write characteristics and / or cache characteristics of the data and instructions in the memory page.

[0034] In a possible implementation, the program includes multiple logic blocks, each logic block corresponds to at least one memory page, and the condition for the first information of the memory page corresponding to the first logic block to change is:

[0035] The first logic block jumps when it is executed.

[0036] In a possible implementation, the memory node acquisition module is further used to:

[0037] Get the first information of the changed memory page;

[0038] Acquire second information, where the second information includes reliability information corresponding to each memory node of the non-uniform memory access NUMA;

[0039] The target memory node is determined according to the first information and the second information of the changed memory page.

[0040] In a possible implementation, the second information further includes: memory access latency information corresponding to each memory node of the NUMA, system overhead corresponding to each memory node after the changed memory page is migrated, and user demand information.

[0041] In a possible implementation, before migrating the memory page to the target memory node, the memory page migration module is further used to:

[0042] The memory node where the determined memory page is located is inconsistent with the target memory node.

[0043] In a third aspect, the present application provides a controller, including a memory and a processor;

[0044] Memory for storing computer programs;

[0045] A processor is used to execute a computer program so that the control device implements the method in the above-mentioned first aspect or any possible implementation manner of the first aspect.

[0046] In a fourth aspect, the present application provides a computer program product, which, when executed by a computer, implements the method in the above-mentioned first aspect or any possible implementation manner of the first aspect.

[0047] In a fifth aspect, the present application provides a chip system, which includes a processor for implementing the method in the first aspect or any possible implementation of the first aspect. In one possible design, the chip system also includes a memory for storing program instructions and / or data. The chip system can be composed of a chip, or can include a chip and other discrete devices.

[0048] In a sixth aspect, the present application provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the method in the above-mentioned first aspect or any possible implementation manner of the first aspect is implemented.

[0049] The solutions of the second to sixth aspects mentioned above are used to implement or cooperate with the method in the first aspect or any possible implementation method thereof, and therefore can achieve the same or corresponding beneficial effects as the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 A schematic diagram of the structure of a controller provided in an embodiment of the present application;

[0051] Figure 2a A schematic diagram of an architecture for applying a memory page migration method;

[0052] Figure 2b Another architecture diagram for applying the memory page migration method;

[0053] Figure 3a A schematic diagram of a flow chart of a memory page migration method provided in an embodiment of the present application;

[0054] Figure 3b A schematic diagram of a flow chart of the static analysis phase of the memory page migration method provided in an embodiment of the present application;

[0055] Figure 4 A schematic diagram of the cache analysis principle based on abstract interpretation;

[0056] Figure 5 A schematic diagram of a control flow graph obtained based on a program provided in an embodiment of the present application;

[0057] Figure 6 A schematic diagram of an analysis of the fault-tolerant path and the non-fault-tolerant path of the read and write behavior provided in the embodiment of the present application;

[0058] Figure 7 A schematic diagram of a corresponding loop body in a control flow graph of a program provided in an embodiment of the present application;

[0059] Figure 8a A weight diagram of a read-write path provided in an embodiment of the present application;

[0060] Figure 8b Another weight diagram of the read and write paths provided in the embodiment of the present application;

[0061] Figure 8c Another weight diagram of the read and write paths provided in the embodiment of the present application;

[0062] Figure 8d Another weight diagram of the read and write paths provided in the embodiment of the present application;

[0063] Fig. 9 A schematic diagram of a storage format of configuration information of a loop body provided in an embodiment of the present application;

[0064] Fig.10 A schematic diagram of an architecture for applying a memory page migration method provided in an embodiment of the present application;

[0065] Fig.11 A schematic diagram of the structure of a memory page migration device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0066] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of this application. It is known to those skilled in the art that with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0067] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or modules is not necessarily limited to those steps or modules that are clearly listed, but may include other steps or modules that are not clearly listed or inherent to these processes, methods, products or devices.

[0068] The term "and / or" in this application can be a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this application generally indicates that the associated objects before and after are in an "or" relationship.

[0069] It should also be noted that, in some alternative implementations, the functions / acts noted may occur out of the order of the drawings. For example, two figures shown in succession may in fact occur substantially simultaneously or may sometimes be performed in the reverse order, depending on the functions / acts involved.

[0070] In the embodiments of the present application, unless otherwise specified, the meaning of "at least one" refers to one or more, and the meaning of "plurality" refers to two or more. It is understood that in the present application, "when", "if" and "if" all refer to the device making corresponding processing under certain objective circumstances, and do not limit the time, nor do they require that there must be a judgment action when the device is implemented, nor do they mean that there are other limitations. In addition, the special word "exemplary" means "used as an example, embodiment or illustrative". Any embodiment described as "exemplary" is not necessarily interpreted as being superior or better than other embodiments.

[0071] The embodiments of the present application are described below in conjunction with the accompanying drawings. Those skilled in the art will appreciate that, with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0072] First of all, in order to better understand the solutions of the embodiments of the present application, the relevant terms and concepts that may be involved in the embodiments of the present application are introduced below.

[0073] 1. Static analysis

[0074] Static analysis is a software analysis technique that is used to examine the characteristics, structure, and problems of source code or binary code without actually running the program, and to analyze the specific behavior of the program, including cache and memory access characteristics.

[0075] 2. Control Flow Graph

[0076] A control flow graph is a graphical representation method used to represent control structures in program code. It is a directed graph in which nodes represent the logic blocks (basic blocks) of the program and edges represent the control flow transfers of the program. A control flow graph can better understand the execution flow of a program, including conditional statements (such as if-else, switch), loop structures (such as for, while), function calls, etc. A control flow graph is an important tool for software static analysis, optimization, and debugging.

[0077] 3. Page Migration

[0078] Page migration refers to the process of migrating a page (or memory block) in memory from one physical location to another.

[0079] 4. Non Uniform Memory Access (NUMA)

[0080] NUMA is a memory architecture designed for multi-processor computers where memory access time depends on the location of the memory relative to the processor. In a NUMA architecture, a processor can access its own local memory faster than non-local memory (memory located on another processor or memory shared between processors).

[0081] 5. Non-uniform memory access balance (NUMA balance)

[0082] NUMA balance, also known as NUMA balancing, is an optimization technology that aims to minimize memory access latency caused by the NUMA architecture and improve system performance. It improves the performance and response speed of the computer system by reasonably allocating tasks to processor cores that can access local memory and optimizing memory page migration, moving the memory pages required for tasks from remote memory to local memory.

[0083] 6. PROT_NONE

[0084] A flag bit in a page table entry is a memory protection flag, which is usually used in operating systems and memory management. When a memory page is marked as PROT_NONE, it means that the content of the page cannot be read, written or executed, but the corresponding physical address exists.

[0085] 7. NUMA hinting fault

[0086] If a processor core accesses the local memory area where other processor cores are located instead of its own local memory area, it can be regarded as a page fault interrupt caused by accessing a page with the PROT_NONE flag.

[0087] In order to better understand the solution of the embodiment of the present application, the application scenario of the embodiment of the present application is described below. The memory page migration method provided in the embodiment of the present application is mainly applied to a server / server cluster. The server generally includes an application layer, a hardware layer and an operating system. The embodiment of the present application is executed by a controller set in the operating system.

[0088] See also Figure 1 , Figure 1 A schematic diagram of the structure of a controller provided in an embodiment of the present application. Figure 1 As shown, the controller 100 is implemented by a general bus architecture.

[0089] The controller 100 includes at least one processor 101 , a communication bus 102 , a memory 103 , and at least one communication interface 104 .

[0090] The processor 101, memory 103, and communication interface 104 communicate via the communication bus 102, and may also communicate via other means such as wireless transmission. The memory 103 is used to store instructions, and the processor 101 is used to execute the instructions stored in the memory 103. The memory 103 stores program codes, and the processor 101 can call the program codes stored in the memory 103 to execute. Figure 3a For specific implementation of steps 301 to 304 in the embodiment shown, please refer to Figure 3a The detailed description of steps 301 to 304 in the illustrated embodiment is not repeated here.

[0091] Optionally, the processor 101 is a general-purpose central processing unit (CPU), and may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA), or other programmable logic devices (PLD), transistor logic devices, hardware components, or any combination thereof. The above-mentioned PLD is a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0092] The communication bus 102 is used to transmit information between the processor 101, the memory 103 and the communication interface 104. The communication bus 102 is divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0093] Optionally, the memory 103 is a read-only memory (ROM) or other types of static storage devices that can store static information and instructions. Alternatively, the memory 103 is a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions. Alternatively, the memory 103 is an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited to this. Optionally, the memory 103 exists independently and is connected to the processor 101 through the communication bus 102. Optionally, the memory 103 and the processor 101 are integrated together.

[0094] The communication interface 104 uses any transceiver-like device for communicating with other devices or communication networks. The communication interface 104 includes a wired communication interface. Optionally, the communication interface 104 also includes a wireless communication interface. Among them, the wired communication interface is, for example, an Ethernet interface. The Ethernet interface is an optical interface, an electrical interface or a combination thereof. The wireless communication interface is a wireless local area network (WLAN) interface, a cellular network communication interface or a combination thereof, etc.

[0095] In a specific implementation, as an embodiment, the processor 101 includes one or more CPUs, such as Figure 1 CPU0 and CPU1 are shown in the figure.

[0096] In a specific implementation, as an embodiment, the controller 100 includes multiple processors, such as Figure 1 1 and 105. Each of these processors is a single-core processor (single-CPU) or a multi-core processor (multi-CPU). The processor here refers to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0097] In some embodiments, the memory 103 is used to store program codes for executing the solution of the present application, and the processor 101 executes the program codes stored in the memory 103 .

[0098] It is to be understood that the method steps in the embodiments of the present application may be implemented in hardware or in software instructions executable by the processor 101. The software instructions may be composed of corresponding software modules, and the software modules may be stored in random access memory, flash memory, read-only memory, programmable read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, hard disk, mobile hard disk, CD-ROM or any other form of storage medium known in the art. In addition, the scope of the device described in the present application is not limited thereto, and the structure of the device may not be subject to the following. Fig.11 A device may be a stand-alone device or may be part of a larger device. For example, a device may be:

[0099] (1) Independent integrated circuit IC, or chip, or chip system or subsystem;

[0100] (2) having a set of one or more ICs, and optionally, the IC set may also include a storage component for storing data and / or instructions;

[0101] (3) Modules that can be embedded in other devices;

[0102] (4) Receivers, terminals, intelligent terminals, wireless devices, handheld devices, mobile units, vehicle-mounted devices, artificial intelligence devices, machine equipment, household equipment, medical equipment, industrial equipment, etc.;

[0103] (5)Others

[0104] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0105] Understandably, Figure 1 The structure of the controller shown is only an example. The memory page migration method provided in the embodiment of the present application can be applied to the structure described above but is not limited to it, and is not limited here.

[0106] exist Figure 1 Based on the controller shown, the present application is mainly applied to the computer field, especially to the computer memory technology field. At present, in heterogeneous memory systems, the failure rates of different memory sticks vary, but the current mainstream operating system has no mechanism to manage application process data according to the memory reliability level, which leads to a decrease in the overall reliability of the system.

[0107] In order to improve the memory reliability of heterogeneous memory systems that mix high-performance memory devices with ordinary memory devices, the following two methods are commonly used:

[0108] Method 1:

[0109] See also Figure 2a , Figure 2a The following is a schematic diagram of an architecture for applying a memory page migration method. Method 1 tracks the program behavior of the executable program by tracking the access count method, and then performs page migration to improve the reliability of the memory system. Figure 2a As shown, the architecture includes software modules and hardware modules, wherein the software module includes a tracing parser, a page migration decider, a page migration engine, a memory manager, and a reliability detector, and the hardware module includes a tracing collector, a memory module, and an interface between the application program of the application program module and the software module.

[0110] The logical (working / connection) relationship between software and hardware is as follows: the application interacts with the operating system through an interface, and when the program is executed, the hardware architecture tracking collector collects information and feeds it back to the tracking parser at the operating system layer, which then performs operations such as page migration.

[0111] The specific steps of the memory page migration method are as follows:

[0112] (1) The tracking collector collects information.

[0113] The tracing collector monitors the processor's instruction execution and memory accesses and records memory access patterns, such as which memory pages are frequently accessed and which are rarely accessed;

[0114] (2) The tracking parser parses the information and obtains the tracking data.

[0115] At the operating system level, the trace parser receives and parses the collected trace data and extracts useful information from the trace data, such as page access frequency, access pattern, etc.

[0116] (3) The page migration decider evaluates the access pattern and importance of memory pages based on the tracking data.

[0117] (4) The page migration decision maker determines whether page migration is required. If yes, execute (5) and (6). If no, execute (6).

[0118] The page migration decider uses certain strategies and algorithms to determine whether page migration is needed to optimize memory access performance and stability.

[0119] (5) The page migration engine migrates the page.

[0120] If the page migration decider determines that page migration is required, the page migration engine is responsible for performing the actual page migration operation; the page migration engine moves memory pages from one physical memory location to another to achieve an optimized memory layout.

[0121] (6) The memory manager tracks and maintains the usage of memory resources, and the reliability monitor monitors memory errors and failures during page migration.

[0122] Method 1 mainly migrates pages based on the tracking method to place businesses with higher fault tolerance in high-performance memory and businesses with lower fault tolerance in ordinary memory. Method 1 can dynamically migrate pages based on the frequency and importance of page usage, which can reduce the possibility of memory error accumulation on a specific node, reduce system instability caused by memory failures, and thus improve the reliability of the memory system.

[0123] However, method 1 has the following shortcomings: it is highly dependent on hardware, requires the addition of custom counters, and the program execution path changes with different inputs. In addition, the tracing-based method cannot take into account the differences in fault tolerance caused by different inputs, has high overhead, high complexity, and relies on tracing data. Data is obtained during program execution and cannot be judged in advance.

[0124] The reasons for these deficiencies are as follows: the tracing-based method can only be used for a certain program execution, and cannot accurately analyze the different behaviors of different input program executions, which has limitations. In addition, tracking and collecting data on memory access patterns will bring certain performance overheads and require the addition of additional hardware configurations, which will result in additional processor and memory resource usage, and have a certain impact on system performance. Implementing a tracing-based page migration system may require complex hardware and software support. In addition, the modules and algorithms involved may be relatively complex, requiring precise data parsing and page migration decision logic; the performance and effectiveness of tracing-based page migration technology are heavily dependent on the quality and accuracy of tracing data. If the memory access pattern cannot be accurately captured, the effectiveness of the technology may be affected.

[0125] Method 2:

[0126] See also Figure 2b , Figure 2b Another architecture diagram for applying the memory page migration method. The architecture includes software modules and hardware modules, wherein the software modules include application modules and operating system modules, and the hardware modules include double data rate synchronous dynamic random access memory (DDR SDRAM) memory modules and CPU modules. These software modules can realize reasonable memory allocation and page migration, and can improve the performance of applications running on NUMA hardware systems.

[0127] The logical (working / connection) relationship between software and hardware is as follows:

[0128] The heterogeneity of memory in the memory module in the hardware is reported through the ACPI Table, allowing the operating system to perceive the heterogeneity of the underlying memory in terms of reliability. The heterogeneous memory in terms of reliability will be divided into different nodes, and then NUMA Balancing will determine the corresponding nodes for page allocation and page migration.

[0129] The specific steps of the memory page migration method are as follows:

[0130] (1) Periodically scan the task's address space and modify the page table entries to be inaccessible.

[0131] Periodically scan the address space of the task and modify the page table entry to be inaccessible, such as PROT_NONE in Linux. A NUMA hinting fault will occur when the data is accessed later.

[0132] (2) In the case of a NUMA hinting fault, the page table is modified to have the correct permissions so that execution can continue, and the nodes and tasks that have accessed the page and the page faults that occurred on each node are tracked.

[0133] (3) Decide whether to migrate the page based on historical records.

[0134] NUMA Balancing improves the performance of applications running on NUMA hardware systems. Under NUMA Balancing scheduling, local nodes are often selected for memory allocation, or pages are migrated to local memory to reduce the latency caused by cross-node memory access. However, there are still some shortcomings: only considering the improvement of system performance but ignoring the consideration of system reliability.

[0135] These deficiencies are caused by the following reasons:

[0136] Under NUMA Balancing, in order to reduce the latency caused by cross-node memory access, pages are often migrated to local memory nodes without considering the risk attributes of the pages themselves and the reliability of the memory. This may cause high-risk pages to be migrated to low-reliability memory, damaging system reliability.

[0137] In order to solve the above problems, the present application embodiment provides a memory page migration method, which is applied to Figure 1 Specifically, first, firstly, obtain the first information of the memory page, wherein the first information is used to characterize the reliability of the memory page, and the first information is obtained based on static analysis of the program; then, when the first information of the memory page changes, obtain the target memory node of the memory page; finally, migrate the memory page to the target memory node.

[0138] Compared with the online migration of memory pages based on a single program being executed, this application performs online analysis based on the first information obtained by static analysis, which can take into account different program inputs, flexibly generate different configuration files, and does not occupy resources during program execution, so that when performing page migration, dynamic migration can be performed directly based on the first information generated offline, thereby ensuring the stability of program execution. In addition, based on the first information generated by static analysis, the behavior of different program executions is accurately analyzed, thereby achieving more accurate and fine-grained reliability analysis, migrating pages to the most suitable memory medium, and improving the reliability of the memory system.

[0139] For ease of understanding, the following is a detailed description of the memory page migration method provided by the embodiment of the present application in conjunction with the accompanying drawings and application scenarios. It is known to those skilled in the art that with the development of technology and the emergence of new scenarios, the technical solutions provided by the embodiment of the present application are also applicable to similar technical problems.

[0140] See also Figure 3a , Figure 3a A flow chart of a memory page migration method provided in an embodiment of the present application is shown in FIG. Figure 1 The controller shown is executed. Figure 3a As shown, the controller executes the following steps 301 to 304.

[0141] Before step 301, in a possible implementation, in the static analysis phase, the method includes steps 301a to 301g, which are performed offline. Figure 3b , Figure 3b A flow chart of the static analysis phase of the memory page migration method provided in an embodiment of the present application.

[0142] Step 301a: The controller obtains executable programs and hardware information.

[0143] In this embodiment, the controller obtains the executable program to be analyzed and processed and the configuration information of the general computer or server that executes the program, including the computer memory size, configuration, and the strategy used for memory management, as well as the specific information of the cache. For example: operating system version (kernel version), processor version (based on which architecture), memory information (size, frequency), cache information, NUMA architecture information.

[0144] Exemplarily, a server with an OpenEuler operating system (for example, kernel version 22.09) and a Kunpeng 920 processor (for example, based on ARM v8 architecture, aarch64 instruction set) is used as an example for explanation. The hardware information that the controller needs to obtain includes: OpenEuler operating system (kernel version 22.09), processor Kunpeng 920 (for example, based on ARM v8 architecture, aarch64 instruction set), memory size (for example, 96G), and cache information. Among them, the cache information is divided into three levels, L1, L2, and L3. Assume that the server contains 6 NUMA nodes, of which NUMA nodes 0-3 each contain 20 cores, NUMA nodes 4-5 do not contain cores, NUMA nodes 0, 1, 2, and 4 each contain 32GB of memory, NUMA node 3 contains 16GB of memory, and NUMA node 5 contains 48GB of memory.

[0145] It is understandable that this embodiment is illustrated and verified in the environment of OpenEuler operating system, ARM v8 architecture and aarch64 instruction set. On the premise that the system architecture applied in this embodiment matches the general computer architecture, this embodiment can theoretically be used for general-purpose computers under any architecture and is applicable to all architectures.

[0146] Step 301b: The controller performs binary encoding on the executable program and analyzes the hardware information to obtain binary information and cache configuration information.

[0147] In this embodiment, the controller performs binary encoding on the executable program to be analyzed to obtain a binary file of the executable program. At the same time, the controller analyzes the specific cache information obtained in step 301a and calculates all cache-related information, such as cache line size, cache strategy (such as whether it is set associative, etc.), and if it is set associative, how many ways are associated and how many groups are there, and other cache configuration information.

[0148] The controller will encode the program in the hardware environment described in step 301a to obtain program binary information (such as the file suffix ".o" in the Linux system). At the same time, the controller performs further calculations based on the cache information obtained from step 301a.

[0149] In this embodiment, the cache configuration information calculated by the controller is, for example: the L1 cache (divided into data cache and instruction cache) is a four-way set associative strategy with 256 groups; the L2 cache (regardless of data cache and instruction cache) is eight-way set associative; the L3 cache (regardless of data cache and instruction cache) is also eight-way set associative.

[0150] Step 301c: The controller disassembles the binary information and analyzes the cache behavior in the program according to the cache configuration information to obtain the assembled program and cache status information.

[0151] In this embodiment, the controller obtains the binary information of the executable program output in step 301b, disassembles the binary information, and obtains the assembly program of the executable program. At the same time, the controller models and analyzes the cache behavior based on the cache configuration information obtained in step 301b to obtain cache status information.

[0152] Optionally, the cache status information includes a cache hit status and a cache miss status.

[0153] Optionally, the controller uses a WCET analysis method to analyze cache behavior and obtain cache status information.

[0154] After obtaining the assembly program, the controller analyzes the cache behavior based on the Worst-case Execution Time (WCET) method to obtain the result of whether the instruction or data is a cache hit or a cache miss.

[0155] Exemplarily, in this embodiment, the controller uses the Objdump function package in the OpenEuler operating system to disassemble specific instructions and disassemble the executable program binary code into the assembly program corresponding to the executable program (for example, in this example, the executable program binary code with the file suffix ".o" should be disassembled into the assembly program corresponding to the executable program with the suffix ".asm"). At the same time, the controller uses the WCET analysis method to model the cache behavior. Please refer to Figure 4 , Figure 4 A schematic diagram of the cache analysis principle based on abstract interpretation. Figure 4 As shown, the controller uses abstract modeling to perform cache behavior analysis in a static manner, maps all possibilities of actual program execution to the abstract level, obtains the most conservative cache behavior through static analysis, and then makes the static analysis as close as possible to the actual program execution by concretizing functions.

[0156] Step 301d: The controller analyzes the assembly information to obtain a control flow graph corresponding to the program.

[0157] In this embodiment, the controller analyzes the behavior of the assembly instructions in the assembly program, and generates a control flow graph of the program according to different types of behaviors, clarifies all possible behaviors in the program execution, formally represents the possible flow of logic block execution during the program execution, and obtains all possibilities in the real-time execution process. Among them, the assembly instructions may include jump instructions and memory access instructions.

[0158] The controller analyzes the meaning and location of each instruction in the program based on the instruction granularity. Specifically, the program is divided into multiple logic blocks. The controller divides the logic blocks in the control flow graph according to the jump instructions and the location of the specific instructions. Then, based on the analysis conclusions, the controller determines the relationship between the blocks, and then connects the logic blocks based on the determined relationship to form a complete control flow graph.

[0159] Please refer to Figure 5 , Figure 5 A schematic diagram of a control flow graph obtained based on a program provided in an embodiment of the present application is provided, in which a portion of the assembler program corresponding to the executable program to be analyzed is intercepted for specific analysis and explanation. Figure 5 As shown, the controller is divided into four logic blocks according to the jump instructions and the instruction positions to which the jump instructions jump, corresponding to Figure 5 The assembly code of the four parts shown in (a) in FIG. Then, the controller determines the relationship between the logic blocks according to the instruction behavior analysis results and connects the logic blocks. Figure 5 As shown in (b) of Figure 5 The four logic blocks divided in (a) are connected, and the connection between the four blocks is determined according to the conditional jump and the jump position relationship. After the connection, the control flow graph of the program is obtained. Among them, the le path from 0x400784 to 0x4007bc is the jump path, and 0x400784 to 0x4007a8 is sequential execution.

[0160] Step 301e, the controller obtains the read and write information of the data and instructions in the memory page according to the control flow graph and the cache status information.

[0161] In this embodiment, the controller continues to analyze the behavior of the assembly instructions in depth according to the control flow graph of the program, and clarifies the jump information and the memory access information of each logic block of the program. The controller locates the memory access read and write behaviors that appear in the program, divides the memory access read and write instructions according to the read and write behaviors, and then models the memory access behaviors according to the obtained information, clarifies the read and write paths, read before write, and read before write, etc.

[0162] In a possible implementation, the read and write characteristics of data and instructions include read and write error tolerance of data and instructions.

[0163] In this implementation, the read and write fault tolerance of data and instructions in the program refers to the fault tolerance of the memory access characteristics of each specific variable corresponding to the data and instructions in the program in the specified memory page, where the specific variable can be understood as the data address in the memory. The controller analyzes the data read and write behavior of the same data address or variable to obtain the read and write fault tolerance of the data address.

[0164] Taking the memory page as the granularity, the read and write fault tolerance rate corresponding to the memory page is equivalent to the ratio of the read and write fault tolerance rate of the data addresses corresponding to all the data and instructions contained in the entire page to the number of data addresses.

[0165] The controller mainly calculates the read-write fault tolerance rate based on the fact that the program's write operation on the variable can overwrite the previous data error, thereby eliminating its impact on the correctness of the system execution. The specific calculation method of the read-write fault tolerance rate can be:

[0166] See also Figure 6 , Figure 6 A schematic diagram of the analysis of the fault-tolerant path and the non-fault-tolerant path of the read and write behavior provided in the embodiment of the present application. Assume that V1, V2, and V3 are respectively reading and writing to the same data address. Figure 6 As shown in the figure, in the case of V1, the controller first performs a memory read operation, then a memory UCE (Uncorrectable Error) occurs, and then a memory write operation is performed. At this time, the write operation will overwrite the memory UCE, so that the controller can read the correct content when performing the following two memory read operations. In the case of V2, the controller has a memory UCE after the memory write operation, and then immediately performs a memory read operation. At this time, a memory error will occur and the program cannot be executed normally. According to the above principles, the concept of fault-tolerant path is defined as: the path from each memory write operation to any memory read or memory write operation before this operation, and the concept of non-fault-tolerant path is defined as: the path from each memory read operation to any memory read or memory write operation before this operation. Then, for each variable, its read and write fault tolerance rate is defined as: the ratio of the total length of the fault-tolerant path of the executable program to the total length of the non-fault-tolerant path.

[0167] exist Figure 6 In the example, the read and write fault tolerance of the variable is tw1+tw2+tw3 / tr1+tr2. tw1 is the number of instructions included between the read memory operation R and the write memory operation W, and the same is true for tw2 and tw3. tr1 and tr2 are the number of instructions included between the write memory operation W and the read memory operation R and between the read memory operation R and the read memory operation R, respectively.

[0168] Figure 6 The diagram shown corresponds to the case where the program is executed only once. From a macro perspective, we need to consider issues such as the number of loops in the executable program, and then obtain the fault tolerance rate based on the granularity of memory pages. The number of executable program loops will affect the read and write behavior. For the treatment of the number of loops, please refer to Figure 7 , Figure 7 A schematic diagram of the corresponding loop body in the control flow diagram of the program provided in the embodiment of the present application. Figure 7As shown, L1, L2, and L3 represent loop1, loop2, and loop3, i.e., loop 1, loop 2, and loop 3. The numbers following the three loop identifiers in the figure represent the number of times the loop needs to be executed (i.e., loop bound). All three loops need to be executed 10 times. Then, analyzing the nested relationship between loops, loop L1 nests loop L2, so the number of times the read and write behavior in loop L2 is executed needs to be multiplied by L1 and L2, i.e., 100 times. Therefore, after the read and write behavior of the executable program in the three loops is converted to the granularity of memory pages, the specific results are shown in the figure. Among them, the logic block of w_p1 may contain multiple read and write instructions, and the read and write addresses of the variables corresponding to each read and write instruction are different. Therefore, for each variable or data address, there is a corresponding read and write fault tolerance rate.

[0169] Considering the number of loops in the executable program, the fault tolerance rate can be defined as the product of length and number. The length here specifically refers to the number of cycles executed by the corresponding fault-tolerant path or non-fault-tolerant path, which can be specifically the number of assembly instructions contained in the fault-tolerant path or non-fault-tolerant path; the length specifically refers to the expected number of executions of the fault-tolerant path or non-fault-tolerant path, which can be specifically the number of instruction executions. That is, for each variable, the read and write fault tolerance rate of the variable should be the product of the read and write fault tolerance rate under a single cycle and the number of instruction executions. Figure 6 The calculated read-write fault tolerance is the read-write fault tolerance in a single cycle, assuming Figure 7 When the logic block of w_p1 shown is executed once, the read-write fault tolerance rate of a corresponding variable is n. The logic block of w_p1 will be executed 100 times in total. Then, the read-write fault tolerance rate corresponding to the variable is the product of 100 and n.

[0170] In addition to considering the number of loops in the executable program, it is also necessary to consider the possibility of each logic block being executed. In static analysis, each logic block has different paths when it is executed downward. The direction of the logic block represents the possibility of the executable program being executed online. In static analysis, weights are added to the execution paths of the logic blocks, and the weight of each path is analyzed according to different conditions. Please refer to Figure 8a , Figure 8a A weight diagram of a read / write path provided in an embodiment of the present application. Figure 8aIn the example, R1 and W1 marked in the logic block correspond to the read and write operations of data 1, respectively. Similarly, R2 and W2 are read and write operations of data 2, respectively. In static analysis, each logic block has different paths when it is executed downward. The direction of the logic block represents the possibility of the executable program being executed online. In static analysis, weights are added to the execution paths of the logic blocks, and the weights of each path are analyzed according to different conditions. The sum of the out-degree weights of each logic block should be 1, and the sum of the in-degree weights of the logic blocks that will definitely be executed is 1. If there are no conditions, the outbound weights of each logic block are the same. Correspondingly, based on Figure 6 and Figure 7 After calculating the read and write fault tolerance of each variable in the example shown, it is necessary to multiply it by the corresponding weight to obtain the final read and write fault tolerance.

[0171] It should be understood that the purpose of weight is mainly to represent the execution probability of different read and write paths. In the case of static analysis, the program has not been executed yet, and the weight is set manually, but it is necessary to ensure that the sum of the out-degree weight of each logic block should be 1. If there is no condition, the out-edge weight of each logic block is the same to reduce the error between programs.

[0172] For example, see Figure 8b , Figure 8b Another weight diagram of the read and write paths provided in the embodiment of the present application. For data 2, assuming that the number of cycles is 100, such as Figure 8b As shown, taking the path shown in 8b as an example, for the path from R2 to W2, it is assumed that the read and write fault tolerance rate of data 2 executing a single instruction is tw1 / tr1. Among them, tw1 is the number of instructions included in R2 and W2, and tr1 is the number of instructions included in W2 and R2.

[0173] After considering the dimensions of loop instructions and weights, the read and write fault tolerance of data 2 should be:

[0174]

[0175] See also Figure 8c , Figure 8c Another weight diagram of the read and write paths provided in the embodiment of the present application. For data 2, assuming that the number of cycles is 100, Figure 8c For example, the fault-tolerant path from R2 to W2 includes two paths. For the non-fault-tolerant path from W2 to R2, since W2 cannot return to R2 in the loop, Figure 8c The path shown does not have any non-fault-tolerant situation in the reading and writing behavior, so the reading and writing behavior of data 2 must be fault-tolerant.

[0176] See also Figure 8d , Figure 8dAnother weight diagram of the read and write paths provided in the embodiment of the present application. For data 2, assuming that the number of cycles is 100, Figure 8d Taking the path shown in the figure as an example, the fault-tolerant path from R2 to W2 includes two paths with different weights. Therefore, the read and write fault tolerance rate of data 2 executing a single instruction is tw1 and tw2 are the number of instructions corresponding to the two paths between R2 and W2. For the non-fault-tolerant path from W2 to R2, there is only one path with the same weight. Therefore, the non-fault-tolerant rate of reading and writing data 2 for executing a single instruction is

[0177] After considering the dimensions of loop instructions and weights, the read and write fault tolerance of data 2 should be:

[0178]

[0179] In addition to the fault tolerance for the reading and writing behavior of data and instructions in the program. Optionally, in some programs with fault tolerance (such as machine learning applications such as target recognition), the program itself can also set a certain fault tolerance to ensure the reliability of memory. If the impact of data errors on the accuracy of execution results is within an acceptable range, and the execution results of the program meet the requirements that the system behavior is not affected within a certain accuracy range, then the data belongs to the low risk level.

[0180] Optionally, when calculating the read / write fault tolerance rate corresponding to each data address, the controller divides the size of the data address using cache line as the granularity.

[0181] In the actual execution process, the controller reads and writes according to the cache line granularity. In this embodiment, the read and write behavior is analyzed according to the cache line granularity, which is closer to reality and can improve the accuracy of the analysis, thereby improving the reliability of the memory.

[0182] The controller divides the read and write characteristics according to the cache line granularity. In simple terms, read and write operations are performed at the cache line size granularity. Read operations on data that has been in the cache are not considered as reading the memory, but can be directly obtained from the cache (if the data is in the cache, the data in the cache will prevail, and errors in the memory will not affect it). If errors occur in the data in the subsequent memory, it will not affect the data in the cache.

[0183] Specifically, for each data address, the controller may limit the size of the data address to be consistent with the size of the cache line. For example, if the size of the data address is smaller than the cache line, the size of the data address is increased to the cache line; if it is larger than the cache line, the data address is divided into data addresses of multiple cache line sizes.

[0184] Step 301f, the controller obtains cache information of data and instructions in the memory page according to the cache status information.

[0185] In this embodiment, the controller analyzes the cache behavior of data and instructions in the memory page in combination with the cache hit and miss information to obtain cache information.

[0186] Optionally, the cache characteristics of the data and instructions include cache tolerance of the data and instructions.

[0187] The controller designs a reasonable risk level classification algorithm based on the analysis results of the cache behavior, that is, the cache status information of cache hits or misses, combined with the fact that during program execution, if a piece of data is accessed in the cache, before the data is written back to the memory, the error of the data in the memory will not affect the correctness of the execution of the system itself. If the cache is completely hit, it is fully fault-tolerant. According to the ratio of cache hits and misses, the fault tolerance calculated by abstract analysis of the cache behavior is called the cache fault tolerance rate.

[0188] Taking the memory page as the granularity, the cache fault tolerance rate corresponding to the memory page is equivalent to the ratio of the number of cache hit behaviors to the number of cache miss behaviors of all data and instructions contained in the entire page.

[0189] It is understandable that the execution order of step 301e and step 301f is not limited and can be set according to actual needs.

[0190] Step 301g: The controller calculates the first information of the memory page according to the read and write information and / or cache information of the data and instructions in the memory page.

[0191] In this embodiment, the controller comprehensively considers the characteristics of the read and write behavior and / or cache behavior of the data and instructions in the memory page, and evaluates the reliability of the memory page based on the read and write information and / or cache information.

[0192] Optionally, the first information of the memory page includes arrangement information of the risk level of the memory page.

[0193] The controller divides the risk levels according to the program behavior of the program to be executed. The first level is each loop in the program (here the entire program is regarded as the outermost loop), and the second level is the memory page. Each memory page of each loop of the executed program has a risk level parameter obtained by static analysis.

[0194] In a possible implementation, the controller calculates the first information of the memory page according to the read and write information and / or cache information of the data and instructions in the memory page.

[0195] In this implementation, after obtaining the read-write information and / or cache information, the controller can calculate the risk level of the memory page based on the read-write information and / or cache information, and evaluate the reliability of the memory page based on the information on the read-write behavior and / or cache behavior of the memory page.

[0196] Optionally, when the controller calculates the risk level of the memory page based on the read and write fault tolerance or cache fault tolerance of the memory page, the memory pages can be arranged in a certain order based on the read and write fault tolerance or cache fault tolerance of each memory page to obtain arrangement information of the risk level of the memory page.

[0197] Optionally, when the controller calculates the risk level of a memory page based on the read / write fault tolerance rate and cache fault tolerance rate of the memory page, the read / write fault tolerance rate and the cache fault tolerance rate may be normalized to obtain the total fault tolerance rate of the memory page, and the risk level of the page may be determined based on the total fault tolerance rate. After the controller obtains the risk level of each memory page, the arrangement information of the memory page may be generated in order from low to high or from high to low.

[0198] In a possible implementation, the controller calculates the first information of the memory page according to the heat of the memory page and the read and write information and / or cache information of the data and instructions in the memory page.

[0199] In this implementation, the controller can evaluate the risk level of the memory page based on the first information of the memory page calculated based on the read-write information and / or cache information, so that each page in the high-risk memory should include as much low-risk data as possible. Taking into account the page heat and risk level, the recommended memory layout is generated, and high-heat and low-risk data is stored in a high-speed and low-reliability storage medium, and low-heat and high-risk data is stored in a low-speed and high-reliability storage medium, thereby achieving the purpose of improving system performance while maintaining system stability.

[0200] It is understandable that, when the risk levels of two memory pages are the same, the controller may evaluate the reliability of the memory pages based on the heat of the two memory pages.

[0201] Optionally, the heat of a memory page is obtained based on the access frequency of the memory page, which can be understood as the sum of the number of read and write instructions in the memory page. If there is a nested loop, the heat of the memory page is the product of the number of read and write instructions and the number of loops. The controller uses the memory page as the granularity range to perform data statistics on read and write features, and finally obtains the heat results of the memory pages involved in the executable program under static analysis. The more read and write times, the higher the heat.

[0202] This embodiment generates a page tolerance parameter configuration file based on the fault tolerance rate and heat of the memory page for use in dynamic scheduling, stores high-heat and low-risk data in a high-speed and low-reliability storage medium, and stores low-heat and high-risk data in a low-speed and high-reliability storage medium.

[0203] The above is the execution process of the static analysis phase. The following is an explanation of the online execution process of the controller. After obtaining the risk distribution information of the memory page through static analysis, a page risk level profile corresponding to the program can be generated so that the memory page can be migrated directly based on the page risk level profile in the online phase.

[0204] It is understandable that this embodiment can solve the problem of different program inputs by statically analyzing the program, and implement hierarchical management according to memory reliability in a static manner that is pure software, not perceived by users, and does not modify business codes. In response to the memory reliability problem, the problem is divided into multiple dimensions for consideration, and the demand for heterogeneous memory attributes of memory pages can be obtained. Then, through static analysis offline, the nodes where the memory pages have changed in heterogeneous memory attributes can be obtained. In this way, configuration files can be generated flexibly, and memory can be arranged during memory allocation or dynamic migration during online execution. In addition, read-write behavior and cache behavior analysis based on static analysis is essential. If it is performed from a dynamic analysis, it is impossible to migrate in advance before the program behavior changes.

[0205] Step 301: The controller obtains first information of a memory page.

[0206] In this embodiment, the controller obtains first information of the memory page based on static analysis of the program, wherein the first information is used to characterize the reliability of the memory page.

[0207] Optionally, the first information of the memory page is obtained based on the read / write characteristics and / or cache characteristics of the data and instructions in the memory page.

[0208] Optionally, the first information of the memory page is obtained based on the heat of the memory page and the read / write characteristics and / or cache characteristics of the data and instructions in the memory page.

[0209] The specific calculation process can be found in step 301g, which will not be repeated here.

[0210] Step 302: The controller determines whether the first information of the memory page has changed. If yes, step 303 is executed. If no, the operation is stopped.

[0211] This embodiment is mainly executed in a page fault interrupt, wherein the program includes multiple logic blocks, each logic block corresponds to at least one memory page. In a possible implementation, the condition for the first information of the memory page corresponding to the first logic block to change is:

[0212] The first logic block jumps when it is executed.

[0213] In this implementation, the controller compares the loop numbers, and if they are different, it loads the new loop's page risk level file, and then performs page migration according to the new page risk level file. Specifically, when the program enters a page fault interrupt, it saves the interrupted instruction address of the interrupted process in the ESR_EL1 register, reads the register value, and determines the loop instruction address partition configuration information based on the controller flow graph obtained by static analysis, determines the control flow graph position of the current process, and detects whether a loop jump has occurred.

[0214] The loop instruction address partition configuration information obtained by static analysis will be loaded into the memory when the program is running. The loop instruction address partition configuration information will save the corresponding relationship between the loop number and the instruction address. The format is "loop number, loop start instruction address - loop end instruction address". For details, please refer to Fig. 9 The content shown, Fig. 9 A schematic diagram of the storage format of the configuration information of the loop body provided in the embodiment of the present application. In a page fault interrupt, the interrupted instruction address of the interrupted process will be saved in the ESR_EL1 register. The instruction address executed by the current process can be obtained by reading the value of the register ESR_EL1 register, and the corresponding loop number is searched in the saved loop instruction address partition configuration information according to the instruction address. At the same time, the controller has saved the loop number detected by the last page fault interrupt, and the loop numbers obtained twice are compared. If they are not equal, a loop jump behavior occurs.

[0215] Among them, the purpose of loop number comparison is: in this embodiment, the configuration file obtained by the controller through static analysis is given in the granularity of loop. During the running of the program, by detecting whether the loop jumps, it is determined whether the risk level of the page has changed. Since whether the risk information of the memory page changes is based on the granularity of the loop, that is, the same page may correspond to different risk levels under different loops. For example, in loop1, the memory page is read and written 100 times, but in loop2, this memory page is read and written 10,000 times, and the corresponding risk information is different. Therefore, this embodiment determines whether the loop has jumped by detecting which loop the program is currently executing, and judges based on the loop number detected by the last page fault interrupt to determine whether the risk information of the page has changed.

[0216] It is understandable that during online execution, if no page fault occurs, the current execution position of the program cannot be obtained. For programs running on a server / server cluster, there is no such thing as a small program size that does not require page migration operations, and page faults triggered by NUMA balancing are bound to exist.

[0217] In another possible implementation, the controller may determine whether a loop jump occurs based on the instrumentation statement.

[0218] In this implementation, during offline analysis, the controller can insert a plug-in statement at the loop boundary according to the program divided by loop granularity. The plug-in statement is a system call used to switch from user mode to kernel mode. The plug-in statement will introduce a parameter, that is, the loop number where the plug-in statement is located. When the process runs to the plug-in statement, it is determined that the loop corresponding to the plug-in statement has jumped, and the loop number corresponding to the loop and the risk information of the memory page corresponding to the loop number are obtained.

[0219] Step 303: The controller obtains the target memory node of the memory page.

[0220] In this embodiment, after the controller determines that the first information of the memory page has changed, it will first determine the memory page corresponding to the loop according to the loop number of the loop where the jump occurs, and load the page risk level configuration file corresponding to the memory page from the external memory to the memory. The controller migrates the page of the process according to the latest page risk level configuration file of the process to ensure the reliability of the system. After determining the memory page to be migrated, the controller needs to determine the target memory node to which the memory page to be migrated is to be migrated.

[0221] When the controller determines the target node, it needs to comprehensively consider system reliability and performance. For system reliability, it is mainly reflected in the matching of the risk level of the page and the reliability of the NUMA node memory. For system performance, it is mainly reflected in the memory access latency between the controller and the memory node that accesses the page. In addition, the overhead caused by the page migration itself will also be considered.

[0222] In a possible implementation, the controller obtains the target memory node of the memory page, including:

[0223] Get the first information of the changed memory page;

[0224] Acquire second information, where the second information includes reliability information corresponding to each memory node of the non-uniform memory access NUMA;

[0225] The target memory node is determined according to the first information and the second information of the changed memory page.

[0226] In this implementation, the controller can determine the target memory node based only on the first information of the memory page and the reliability information corresponding to each memory node of the NUMA. Correspondingly, in another optional implementation, the controller can determine the target memory node based on multiple dimensions. In this implementation, the second information also includes: the memory access latency information corresponding to each memory node of the NUMA, the system overhead corresponding to each memory node after the changed memory page is migrated, and the user demand information.

[0227] For ease of explanation, a specific description is given from multiple dimensions.

[0228] Before the controller determines the target memory node, it needs to obtain relevant information, including the risk information of the page, the reliability information of the memory nodes on each NUMA node, and the memory access latency between each NUMA node. After obtaining the relevant information, the controller determines which NUMA memory node the page should be migrated to based on the target function.

[0229] max F=W_reliability*f_reliability+W_performance*f_performance–penalty,

[0230] W_reliability and W_performance are user demand information, which is a trade-off between system reliability and system performance. f_reliability is used to measure the matching relationship between page risk level and memory reliability. f_performance is used to measure the delay of page access after process memory migration. Penalty is used to measure the overhead caused by page migration to the system.

[0231] Among them, W_reliability and W_performance can be adjusted according to user needs. For example, if performance is oriented, W_performance can be set to a relatively high value. If you want the reliability of the memory system to be higher, W_reliability can be set to a relatively high value.

[0232] There are many memory nodes in the NUMA architecture, and the reliability information, memory access latency, and system overhead of migrating memory pages to each memory node are different for each memory node. In order to determine which memory node has the highest reliability for page migration, in an optional implementation, the controller simulates the calculated objective function values ​​of the page under different memory nodes, and determines the memory node corresponding to the maximum objective function value as the target memory node.

[0233] Step 304: The controller migrates the memory page to the target memory node.

[0234] In an embodiment of the present application, after detecting that a loop jump occurs and determining a target memory node, the controller will migrate the memory page to the target memory node.

[0235] Since a single loop may correspond to multiple memory pages, in order to reduce the damage to the computer memory system performance, it is best to avoid migrating too many pages at a time. On this basis, the controller can sort the pages in descending order according to the page risk level based on the page risk level profile, and migrate the pages based on the order, so as to prioritize the migration of higher-risk memory pages as much as possible, thereby ensuring the reliability of the system. At the same time, the controller needs to control the number of page migrations, and no longer migrate when a certain threshold is reached.

[0236] In a possible implementation, before the controller migrates the memory page to the target memory node, the method further includes:

[0237] The memory node where the determined memory page is located is inconsistent with the target memory node.

[0238] In this implementation, after determining the target memory node, if the controller determines that the target memory node is different from the memory node where the page corresponding to the loop where the jump occurs is located, the page corresponding to the loop is migrated.

[0239] Optionally, the controller migrates the memory page to the target memory node only when it determines that the memory node where the memory page is located is inconsistent with the target memory node and the space occupied by the memory page is smaller than the free space of the target memory node.

[0240] It is understandable that the controller determines in advance that the space occupied by the memory page to be migrated is less than the free space of the target memory node, mainly to improve the reliability of the memory. However, in an example, assuming that the space occupied by the memory page is 10 units and the free space of the target memory node is 8 units, the controller can also migrate part of the memory page to be migrated that occupies 8 units to the target memory node, which can also improve the reliability of the memory to a certain extent.

[0241] It is worth noting that this embodiment combines the results of static analysis to perform dynamic page migration. Based on the NUMABalancing mechanism, the context of the program's control flow is determined during the NUMA fault period to obtain the program's future execution state. According to the difference in page states before and after the program's control flow graph, the page is migrated to the most suitable memory medium, truly realizing the reasonable arrangement of memory pages and improving the stability of the memory system.

[0242] In order to explain this embodiment more clearly, this embodiment describes the product implementation form of the provided memory page migration method. For example, please refer to Fig.10 , Fig.10 A schematic diagram of an architecture for applying a memory page migration method provided in an embodiment of the present application.

[0243] like Fig.10 As shown, the execution module of this embodiment is divided into two parts, namely a static analysis module and a dynamic scheduling module.

[0244] At the static analysis level, we plan to conduct variable life cycle analysis based on program loops, and conduct more accurate and fine-grained page heat analysis based on the life cycle characteristics of variables;

[0245] The static analysis module is designed to evaluate the risk level and access popularity of data through multi-dimensional static analysis of the program, establish a mapping relationship between data and different memory media, store high-hot and low-risk data in high-speed and low-reliability storage media, and store low-hot and high-risk data in low-speed and high-reliability storage media, thereby achieving the purpose of improving system performance while maintaining system stability. The main functions of the static analysis module are as follows:

[0246] Generate assembly file: Input the program binary file required for program static analysis, and then disassemble it on a specific system (theoretically, this method can be used in any system environment, such as the widely used ARM architecture, X86 architecture, and RISCV operating systems) to obtain the assembly file (i.e., the assembly program corresponding to the executable program) used for variable risk assessment of static analysis;

[0247] Generate control flow graph: After receiving the assembly program disassembled from the input binary file, analyze the assembly instruction behavior of ARMv8 to distinguish jump instructions, read and write instructions, etc., so as to generate a control flow graph for subsequent analysis. Then, perform static analysis based on the WCET analysis method. Finally, summarize the variable risk assessment technology and form an analysis summary.

[0248] Analyze cache behavior and read / write behavior: First, according to the results obtained after analyzing the assembly instructions, further detailed division and calculation are performed to obtain the access frequency of each memory page, so as to statically calculate and evaluate the heat of each memory page, and continue to analyze the read / write behavior of each specific variable, so as to analyze its access characteristics. According to the characteristic that the program's write operation on the variable can overwrite the previous data error and eliminate its impact on the correctness of the system execution, the fault tolerance of the access characteristics of each specific variable in the specified memory page is obtained. Then, based on the results of the static analysis of the cache in the WCET analysis method, further analysis is performed. According to the characteristic that during the program execution, if a data is accessed in the cache, before the data is written back to the memory, the error of the data in the memory will not affect the correctness of the execution of the system itself, and finally the cache characteristic fault tolerance of each memory page is calculated and analyzed. It should be understood that in some programs with fault-tolerant properties (such as machine learning applications such as target recognition), the execution results of the program meet the system behavior within a certain accuracy range. Therefore, if the impact of data errors on the correctness of the execution results is within an acceptable range, the variable belongs to a low risk level.

[0249] Output the risk distribution information of memory pages: According to the risk parameter analysis results, integrate and standardize, design a reasonable risk level division algorithm, and divide the process data into multiple risk levels according to the amount of data in the specific process and the multi-dimensional variable risk assessment results. Further analysis and processing to obtain the variable risk level parameters, specifically, the risk level is divided according to the program behavior of the program to be executed. The first level is each loop in the program (here the entire program is regarded as the outermost loop), and the second level is the memory page. Each memory page of each loop of the executed program has a risk level parameter obtained by static analysis. At the same time, this module organizes the previously obtained content. The specific manifestation obtained here is the address of the output memory page (the address of the page contained in the loop), the memory page heat value under static analysis, and the memory page risk level parameter (for different memory pages under different loops). Then design a reasonable memory mapping strategy to provide strong support for dynamic migration.

[0250] The static analysis module can be executed completely offline. After obtaining the results of the static analysis, that is, after the risk level parameters are obtained through risk-aware memory layout, the server will execute the program online and perform page scheduling through the reliability-aware kernel, thereby achieving the purpose of improving system reliability. Fig.10 The implementation form of this embodiment in the server is given. The static analysis module is mainly used to generate risk distribution information corresponding to the memory page. After the static analysis results are obtained offline, the application is run on the server deployed with the reliability-aware kernel. The reliability-aware kernel obtains and uses the static analysis results to dynamically schedule the pages occupied by the application.

[0251] At the dynamic monitoring level, a lightweight process-level monitoring mechanism is proposed to capture the dynamic behavior of the process to trigger dynamic migration of pages.

[0252] The dynamic scheduling module aims to combine fine-grained static analysis and high-precision dynamic monitoring to achieve efficient page migration and reduce memory system failures. It needs to be effectively combined with the static analysis module. At the level of dynamic and static collaborative analysis, it is planned to establish an information transmission mechanism for static analysis and dynamic monitoring to achieve the fusion of information between the two and achieve more efficient page migration. The main functions of the dynamic scheduling module are as follows:

[0253] Page migration: Reliability-aware NUMA Balancing considers whether to migrate pages that cause page faults in NUMA hinting faults, without involving other pages occupied by the process. In addition, there is a certain delay between the change of page risk level and the actual page migration in reliability-aware NUMA Balancing. It is hoped that the page risk level change can trigger page migration to migrate high-risk pages to high-reliability memory in a timely manner to ensure system reliability. The risk level of process data in static analysis is given at the loop granularity. There will be loop jumps during process operation. By obtaining the instruction address of the process at the page fault interrupt in the page fault interrupt, according to the correspondence between the instruction address and the loop given by static analysis, it is detected whether the current process running point has generated a loop jump. If a loop jump occurs, it means that the page risk level information of the process data has changed, and the memory distribution of the process needs to be readjusted to migrate high-risk pages to high-reliability memory to ensure system reliability. Since the page risk level configuration file of static analysis sorts pages in descending order according to the page risk level, when the loop jumps, page migration needs to check in order whether the pages involved in the page risk level configuration file need page migration. At the same time, the number of page migrations will be limited to avoid system performance degradation caused by migrating too many pages at one time. Only some pages that have a greater impact on system reliability will be migrated.

[0254] During the compilation period, program analysis methods are used to statically analyze cache behavior, thereby calculating the fault tolerance of each memory data. During the program running phase, pages are dynamically migrated when the risk and heat of the page change.

[0255] exist Figures 1 to 10 On the basis of the corresponding embodiments, in order to better implement the above solutions of the embodiments of the present application, the following also provides related devices for implementing the above solutions. Fig.11 , Fig.11 A schematic diagram of a structure of a memory page migration device provided in an embodiment of the present application. Fig.10 In the dynamic adjustment module shown, the memory page migration device 1100 and the dynamic adjustment module can be represented as the same module, or the memory page migration device 1100 can be a module located in the dynamic adjustment module for implementing the memory page migration function.

[0256] The memory page migration device 1100 may be located at Figure 1 In the controller shown in FIG. 1100 , the memory page migration device 1100 includes:

[0257] A memory information acquisition module 1101 is used to acquire first information of a memory page, where the first information is used to characterize the reliability of the memory page, and the first information is obtained based on static analysis of the program;

[0258] A memory node acquisition module 1102, used to acquire a target memory node of a memory page when the first information of the memory page changes;

[0259] The memory page migration module 1103 is used to migrate the memory page to the target memory node.

[0260] In a possible implementation, the first information of the memory page is obtained based on the read / write characteristics and / or cache characteristics of the data and instructions in the memory page.

[0261] In a possible implementation, the read and write characteristics of data and instructions include read and write error tolerance of data and instructions.

[0262] In a possible implementation, the cache characteristics of data and instructions include cache fault tolerance of data and instructions.

[0263] In a possible implementation, the first information of the memory page is obtained based on the heat of the memory page and the read / write characteristics and / or cache characteristics of the data and instructions in the memory page.

[0264] In a possible implementation, the program includes multiple logic blocks, each logic block corresponds to at least one memory page, and the condition for the first information of the memory page corresponding to the first logic block to change is:

[0265] The first logic block jumps when it is executed.

[0266] In a possible implementation, the memory node acquisition module 1102 is further used to:

[0267] Get the first information of the changed memory page;

[0268] Acquire second information, where the second information includes reliability information corresponding to each memory node of the non-uniform memory access NUMA;

[0269] The target memory node is determined according to the first information and the second information of the changed memory page.

[0270] In a possible implementation, the second information further includes: memory access latency information corresponding to each memory node of the NUMA, system overhead corresponding to each memory node after the changed memory page is migrated, and user demand information.

[0271] In a possible implementation, before migrating the memory page to the target memory node, the memory page migration module 1103 is further used to:

[0272] The memory node where the determined memory page is located is inconsistent with the target memory node.

[0273] In this embodiment, the operations performed by each unit in the memory page migration device 1100 are the same as those described above. Figure 3a The method described in the illustrated embodiment is similar and can be used to implement the functions of the controller in the above method embodiment, and can also achieve the beneficial effects possessed by the above method embodiment, which will not be described in detail here.

[0274] An embodiment of the present application also provides a computer-readable storage medium, including program instructions, which, when executed on a controller, causes the controller to execute any of the aforementioned method embodiments.

[0275] The embodiment of the present application also provides a computer program product. When the computer program product is run on a computer, the computer is enabled to execute any of the aforementioned method embodiments.

[0276] It is understood that the devices and methods described in the present application can also be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0277] The various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0278] The naming or numbering of the steps in this application does not mean that the steps in the method flow must be executed in the time / logical sequence indicated by the naming or numbering. The named or numbered process steps can change the execution order according to the technical purpose to be achieved, as long as the same or similar technical effects can be achieved. The division of the units in this application is a logical division. There may be other division methods when implemented in actual applications. For example, multiple units can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, and the indirect coupling or communication connection between units can be electrical or other similar forms, which are not limited in this application. In addition, the unit or subunit described as a separate component may or may not be physically separated, may or may not be a physical unit, or may be distributed in multiple circuit units, and some or all of the units can be selected according to actual needs to achieve the purpose of the present application solution.

[0279] The above is only a specific implementation mode of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. The various digital numbers involved in the embodiments of the present application are only for the convenience of description and are not used to limit the scope of the embodiments of the present application. The size of the sequence number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic.

[0280] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A memory page migration method, characterized in that: The method comprises: Acquire first information of a memory page, where the first information is used to characterize the reliability of the memory page, and the first information is obtained based on static analysis of a program; When the first information of the memory page changes, obtaining a target memory node of the memory page; Migrate the memory page to the target memory node.

2. The method according to claim 1, characterized in that The first information of the memory page is obtained based on the read / write characteristics and / or cache characteristics of the data and instructions in the memory page.

3. The method according to claim 2, characterized in that The read and write characteristics of the data and instructions include the read and write error tolerance of the data and instructions.

4. The method according to claim 2 or 3, characterized in that: The cache characteristics of the data and instructions include cache fault tolerance of the data and instructions.

5. The method according to any one of claims 1 to 4, characterized in that The first information of the memory page is obtained based on the heat of the memory page and the read / write characteristics and / or cache characteristics of the data and instructions in the memory page.

6. The method according to any one of claims 1 to 5, characterized in that The program includes multiple logic blocks, each logic block corresponds to at least one memory page, and the condition for the first information of the memory page corresponding to the first logic block to change is: The first logic block generates a jump behavior when being executed.

7. The method according to any one of claims 1 to 6, characterized in that Obtaining the target memory node of the memory page includes: Get the first information of the changed memory page; Acquire second information, where the second information includes reliability information corresponding to each memory node of the non-uniform memory access NUMA; The target memory node is determined according to the first information and the second information of the changed memory page.

8. The method according to claim 7, characterized in that The second information also includes: memory access latency information corresponding to each memory node of the NUMA, and system overhead and user demand information corresponding to each memory node when the changed memory page is migrated to the memory node.

9. The method according to any one of claims 1 to 8, characterized in that Before migrating the memory page to the target memory node, the method further includes: It is determined that the memory node where the memory page is located is inconsistent with the target memory node.

10. A memory page migration device, characterized in that: include: A memory information acquisition module, used to acquire first information of a memory page, where the first information is used to characterize the reliability of the memory page, and the first information is obtained based on static analysis of a program; A memory node acquisition module, used for acquiring a target memory node of the memory page when the first information of the memory page changes; A memory page migration module is used to migrate the memory page to the target memory node.

11. The device according to claim 10, characterized in that The first information of the memory page is obtained based on the read / write characteristics and / or cache characteristics of the data and instructions in the memory page.

12. The device according to claim 11, characterized in that The read and write characteristics of the data and instructions include the read and write error tolerance of the data and instructions.

13. The device according to claim 11 or 12, characterized in that The cache characteristics of the data and instructions include cache fault tolerance of the data and instructions.

14. The device according to any one of claims 10 to 13, characterized in that The first information of the memory page is obtained based on the heat of the memory page and the read / write characteristics and / or cache characteristics of the data and instructions in the memory page.

15. The device according to any one of claims 10 to 14, characterized in that The program includes multiple logic blocks, each logic block corresponds to at least one memory page, and the condition for the first information of the memory page corresponding to the first logic block to change is: The first logic block generates a jump behavior when being executed.

16. The device according to any one of claims 10 to 15, characterized in that The memory node acquisition module is also used for: Get the first information of the changed memory page; Acquire second information, where the second information includes reliability information corresponding to each memory node of the non-uniform memory access NUMA; The target memory node is determined according to the first information and the second information of the changed memory page.

17. The device according to claim 16, characterized in that The second information also includes: memory access latency information corresponding to each memory node of the NUMA, and system overhead and user demand information corresponding to each memory node when the changed memory page is migrated to the memory node.

18. The device according to any one of claims 10 to 17, characterized in that Before migrating the memory page to the target memory node, the memory page migration module is further used to: It is determined that the memory node where the memory page is located is inconsistent with the target memory node.

19. A controller, characterized in that: including memory and processor; The memory is used to store computer programs; The processor is configured to execute the computer program so that the control device implements the method according to any one of claims 1 to 9.

20. A computer storage medium, characterized in that The storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 9 is implemented.

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