Data reading method and device of memory, computer device and storage medium

Abstract

The application relates to the field of servers and discloses a data reading method and device of a memory, a computer device and a storage medium. The method comprises the following steps: obtaining a first address set from a reset circuit, the first address set comprising a plurality of first addresses in the memory, the first address set being dynamically generated by a system according to preset conditions or configuration; reading a plurality of first data corresponding to the plurality of first addresses of the first address set from the memory, wherein one first address corresponds to one first data; and sending the plurality of first data to a register through a second controller. Therefore, the memory data can be transmitted and stored in the register, so that a subsequent processor can directly read the first data of the memory from the register. Compared with reading from the memory, the method reduces the delay of the processor in acquiring the first data and improves the reading rate.

Description

Technical Field

[0001] This invention relates to the field of server technology, and more specifically to data reading methods, apparatus, computer equipment, and storage media for memory. Background Technology

[0002] Inside the Baseboard Manager Controller (BMC), a One-Time Programmable Read-Only Memory (OTP ROM) is used to store critical data, such as key information and configuration information. The confidentiality and integrity of this type of data are paramount, as tampering with it could lead to serious security vulnerabilities in the system. OTP ROM's non-rewritable nature means that once data is written, its value cannot be changed, but it can still be read. This characteristic makes OTP ROM an ideal choice for storing sensitive information, effectively preventing malicious modification of data.

[0003] While OTP ROMs offer advantages in terms of security, their programming and reading times are typically in the microsecond range, which is relatively long compared to the nanosecond response time of a processor. This latency causes the system to waste multiple cycles waiting for an OTP ROM response, reducing overall processing efficiency. Summary of the Invention

[0004] In view of this, the present invention provides a data reading method, apparatus, computer device, and storage medium for a memory, in order to solve the problem of how to optimize the communication efficiency between the processor and the memory in order to improve the system response speed.

[0005] In a first aspect, the present invention provides a data reading method for a memory, the method being applied to a first controller, the first controller being connected to a reset circuit, a second controller, and a memory, the method comprising:

[0006] During the system reset process, a first address set is obtained from the reset circuit. The first address set includes multiple first addresses in the memory. The first address set is dynamically generated by the system according to preset conditions or configuration.

[0007] Read multiple first data corresponding to multiple first addresses of a first address set from the memory, wherein one first address corresponds to one first data;

[0008] Multiple first data are sent to the register via the second controller.

[0009] The data reading method for a memory provided by this invention has the following advantages:

[0010] First, a first address set from the reset circuit is obtained through a first controller. Based on this first address set, multiple first data points corresponding to these first addresses are read from memory. Then, the read first data points are sent to a register via a second controller. This allows memory data to be transferred and stored in the register, enabling the processor to directly read the first data from the register later. Compared to reading directly from memory, this method reduces the processor's latency in acquiring the first data and increases the read speed. Furthermore, synchronizing the corresponding data in memory based on the first address set from the reset circuit saves register storage resources, thereby reducing hardware size and cost.

[0011] In conjunction with the first aspect, in one alternative implementation, the first controller is connected to the processor;

[0012] After sending multiple sets of first data to the register via the second controller, the process also includes:

[0013] The processor receives first programming information, which includes first programming data and a second address. The first programming data is generated by the processor performing logical operations on the second data obtained from the register and the first initial programming data. The first initial programming data is generated by the processor according to the first configuration instruction. The second data is the first data corresponding to the second address among the multiple first data stored in the register.

[0014] Based on the first programming information, the first programming data is written into the memory according to the second address.

[0015] Specifically, in this method, after synchronizing multiple first data sets into the registers, the processor sends first programming information containing a second address and first programming data. The first programming data is generated by the processor first retrieving the second data from the registers, performing logical operations with the first initial programming data generated based on the first configuration instruction, and then writing this first programming data to the second address in memory. This allows the processor to verify the data in the registers through logical operations before writing the first programming data to memory, ensuring data consistency before writing the first programming data, thus guaranteeing the security of data writing.

[0016] In conjunction with the first aspect, in another alternative implementation, after writing the first programming data to the memory, the method further includes:

[0017] Real-time acquisition of the memory's operating status;

[0018] Determine whether the memory can perform a write operation based on its operating status;

[0019] If so, then generate the first state signal;

[0020] Upon receiving the first detection command from the processor, the first status signal is sent to the processor;

[0021] The processor receives second programming information, which includes second programming data and a third address. The second programming information is sent by the processor upon receiving a first status signal. The second programming data is generated by logically operating the third data obtained by the processor from the register and the second initial programming data. The second initial programming data is generated by the processor according to the second configuration instruction. The third data is the first data corresponding to the third address among the multiple first data stored in the register.

[0022] Based on the second programming information, the second programming data is written into the memory according to the third address;

[0023] The first status signal is updated to the second status signal to indicate that the memory cannot perform a write operation.

[0024] Specifically, in this method, the operating status of the memory is acquired in real time to determine whether a write operation can be performed. If so, a first status signal is generated. Then, after receiving a first detection instruction from the processor, the first status signal is sent to the processor. The processor retrieves third data from the register, performs logical operations with the second initial programming data generated based on the second configuration instruction, generates second programming data, and sends it along with the third address to the first controller. The first controller writes the second programming data to the third address of the memory and updates the first status signal to the second status signal, indicating that the memory cannot perform a write operation. Thus, before the processor writes the second programming data to the memory, it verifies the data with the data in the register through logical operations to ensure data consistency before writing the second programming data to the memory, thereby ensuring the security of data writing. Simultaneously, by determining the operating status of the memory before receiving the second programming data, the system avoids receiving a second write operation while writing one piece of data, thus ensuring the orderliness of the memory data writing process and the security of the memory data.

[0025] In an alternative implementation, after determining that the memory cannot perform a write operation, the method further includes:

[0026] Generate a second state signal;

[0027] When a second detection command is received from the processor, a second status signal is sent to the processor.

[0028] Alternatively, after updating the first state signal to the second state signal, a third detection command sent by the processor is received;

[0029] In response to the third detection command, the second status signal is sent to the processor.

[0030] Specifically, in this method, a second status signal is generated when it is determined that the memory's operating state cannot perform a write operation. Then, upon receiving a second detection instruction from the processor, the second status signal is sent to the processor; or, after the first status signal is updated to the second status signal, the second status signal is sent to the processor in response to a third detection instruction from the processor, instructing the processor to suspend sending other programming information and wait for the memory to complete the write operation corresponding to the current programming data. This ensures the orderliness of the memory data writing process and the security of the memory data.

[0031] In a second aspect, the present invention provides a data reading method for a memory, the method being applied to a second controller, the method comprising:

[0032] During the system reset process, multiple first data are received from the first controller; the multiple first data are read from the memory by the first controller and correspond to multiple first addresses of the first address set, with one first address corresponding to one first data.

[0033] According to the preset correspondence, multiple fourth addresses corresponding to each first data in the register are determined. The preset correspondence is a correspondence between at least one first data and a fourth address in the register.

[0034] Multiple first data are stored in a register according to at least one determined fourth address.

[0035] The server data processing method provided by this invention has the following advantages:

[0036] First, multiple first data points corresponding to multiple first addresses in a first address set are read from memory by the first controller. Then, according to a preset correspondence set, the multiple first data points are stored in multiple addresses in registers. This enables the transfer and storage of memory data in registers, so that the processor can directly read the first data from the memory in the registers later. Compared with reading from memory, this method reduces the latency of the processor in obtaining the first data and improves the read speed.

[0037] In addition, by synchronizing the corresponding data in the memory based on the first address set from the reset circuit, the storage resources of the registers can be saved, thereby reducing the hardware size and cost.

[0038] In one alternative implementation, after storing the plurality of first data into the register, the method further includes:

[0039] Receive the first read instruction sent by the processor, the first read instruction including the target fourth address of the register;

[0040] Read the corresponding first data from the register according to the fourth address of the target, and use it as the first data of the target;

[0041] Send the first data of the target to the processor.

[0042] Specifically, in this method, after receiving the first read instruction from the processor, the first data is read from the register based on the fourth address in the first read instruction. The found fourth data is then fed back to the processor, thereby enabling the processor to directly read the first data from the register, thus reducing the latency of the processor acquiring the first data.

[0043] In one alternative implementation, after sending the target first data to the processor, the method further includes:

[0044] Receive a second read instruction sent by the processor, the second read instruction including the fifth address of the register;

[0045] Read the fourth data from the register based on the fifth address;

[0046] Send the fourth data to the processor;

[0047] The receiver receives the third programming data sent by the processor. The third programming data is obtained by performing logical operations on the third initial programming data and the fourth data. The third initial programming data is generated by the processor according to the third configuration instruction.

[0048] In the register, the fourth data is updated to the third programmed data.

[0049] Specifically, in this method, the fourth data corresponding to the fifth address in the second read instruction sent by the processor is read from the register. The fourth data is then fed back to the processor. The processor can perform logical operations between the third initial programming data and the fourth data, using the obtained third programming data to update the fourth data. Thus, before the processor writes the third programming data to memory, it can verify the data with the data in the register through logical operations, ensuring data consistency before writing the third programming data to both the register and memory, thereby guaranteeing data consistency and security.

[0050] Thirdly, the present invention provides a data reading device for a memory, the device being applied to a first controller, the first controller being connected to a reset circuit, a second controller, and a memory, the device comprising:

[0051] The first acquisition module is used to acquire a first address set from the reset circuit during the system reset process. The first address set includes multiple first addresses in the memory. The first address set is dynamically generated by the system according to preset conditions or configuration.

[0052] The first reading module is used to read multiple first data corresponding to multiple first addresses of a first address set from the memory, wherein one first address corresponds to one first data.

[0053] The first transmitting module is used to transmit multiple first data to the register via the second controller.

[0054] This invention provides a memory data reading device. First, a first address set is obtained from a reset circuit via a first controller. Then, multiple first data items corresponding to multiple first addresses are read from the memory based on the first address set. Finally, the read first data items are sent to a register via a second controller. This allows memory data to be transferred and stored in the register, so that the processor can directly read the first data from the register later. Compared to reading directly from the memory, this method reduces the latency of the processor acquiring the first data and improves the read speed. Furthermore, synchronizing the corresponding data in the memory based on the first address set from the reset circuit saves register storage resources and reduces costs.

[0055] Fourthly, the present invention provides a data reading device for a memory, the device being applied to a second controller, the device comprising:

[0056] The fourth receiving module is used to receive multiple first data from the first controller during the system reset process; the multiple first data are read from the memory by the first controller and correspond to multiple first addresses of the first address set, with one first address corresponding to one first data.

[0057] The second determining module is used to determine the fourth address in the register corresponding to each first data according to a preset correspondence relationship. The preset correspondence relationship is the correspondence between at least one first data and the fourth address in multiple registers.

[0058] A storage module for storing multiple first data into a register according to at least one determined fourth address.

[0059] The server data processing device provided by the present invention has the following advantages:

[0060] First, multiple first data points corresponding to multiple first addresses in a first address set are read from memory by the first controller. Then, according to a preset correspondence set, the multiple first data points are stored in multiple addresses in registers. This allows memory data to be transferred and stored in registers, so that the processor can directly read the first data from the memory in the registers later. Compared to reading from memory, this method reduces the latency of the processor acquiring the first data and improves the read speed. In addition, synchronizing the corresponding data in memory based on the first address set can save register storage resources, thereby reducing hardware size and cost.

[0061] Fifthly, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the computer instructions to perform a memory data reading method of the first aspect or any corresponding embodiment thereof.

[0062] In a sixth aspect, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to perform a data reading method of a memory according to the first aspect or any corresponding embodiment thereof. Attached Figure Description

[0063] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0064] Figure 1 This is a schematic diagram of the hardware connection relationship of a data reading method for a memory according to an embodiment of the present invention;

[0065] Figure 2 This is one of the flowcharts of a data reading method for a memory according to an embodiment of the present invention;

[0066] Figure 3 This is a second flowchart of a data reading method for a memory according to an embodiment of the present invention;

[0067] Figure 4 This is a schematic diagram illustrating the process of an OTP controller synchronizing data with a register according to an embodiment of the present invention.

[0068] Figure 5 This is the third flowchart of a data reading method for a memory according to an embodiment of the present invention;

[0069] Figure 6 This is the fourth flowchart of a data reading method for a memory according to an embodiment of the present invention;

[0070] Figure 7 This is one of the schematic diagrams of a data reading device for a memory according to an embodiment of the present invention;

[0071] Figure 8 This is a second schematic diagram of the data reading device structure of the memory according to an embodiment of the present invention;

[0072] Figure 9 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention. Detailed Implementation

[0073] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0074] According to an embodiment of the present invention, a method for reading data from a memory is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0075] Figure 1 This is a schematic diagram of the hardware connection relationship of a memory data reading method according to an embodiment of the present invention, as shown below. Figure 1 As shown, the BMC includes: a memory, a first controller, a reset circuit, a second controller, a register, and a processor.

[0076] The first controller is connected to the processor, the reset circuit, the second controller, and the memory, respectively, and the second controller is connected to the register.

[0077] Optionally, the first controller and the second controller can be connected to the processor respectively via the AHB bus (Advanced High-performance Bus). The first controller can be connected to the memory via the memory bus. The first controller can be connected to the reset circuit and the second controller respectively via read / write control lines, address bus, and data bus.

[0078] The second controller can be connected to the register via the register bus.

[0079] Optionally, the first controller can be an OTP ROM controller. The second controller can be a register controller. The memory can be an OTP ROM. The register can be a data register.

[0080] This embodiment provides a data reading method for a memory, which can be used in a first controller. Figure 2 This is one of the flowcharts of a data reading method for a memory according to an embodiment of the present invention, such as... Figure 2 As shown, the process includes the following steps:

[0081] Step S201: During the system reset process, obtain the first address set from the reset circuit.

[0082] The first address set includes multiple first addresses in memory, which are dynamically generated by the system based on preset conditions or configuration. The first data can be frequently used or important data. Once the multiple pieces of first data that need to be synchronized are determined, they can be retrieved from memory. Retrieving multiple pieces of first data requires knowing the multiple addresses storing the first data, i.e., the first address set.

[0083] One method for dynamically generating a first address set is as follows: during the operation process before system reset, the number of times each data is read by the processor is obtained, and according to preset conditions or configuration, multiple first data that have been read more than a preset value are determined, and the multiple addresses corresponding to the multiple first data in memory are used as the first address set.

[0084] Step S202: Read multiple first data corresponding to multiple first addresses of the first address set from the memory.

[0085] In this context, each first address corresponds to one first data item.

[0086] The memory consists of multiple storage cells, each of which stores a first piece of data and corresponds to a first address. Therefore, by reading the first address, the corresponding storage cell can be found, and the corresponding first data can be read from that storage cell.

[0087] Step S203: Send multiple first data to the register through the second controller.

[0088] Specifically, the first controller sends multiple first data to the second controller through the data bus between the first controller and the second controller. After receiving the multiple first data, the second controller writes the multiple first data into the corresponding address in the register through the register bus.

[0089] This embodiment provides a data reading method for a memory. A first address set is obtained from a reset circuit by a first controller. Multiple first data corresponding to multiple first addresses are read from the memory according to the first address set. Then, the read multiple first data are sent to a register by a second controller. This enables the memory data to be transferred and stored in the register so that the processor can directly read the first data from the memory in the subsequent process. Compared with reading from the memory, this method reduces the latency of the processor to obtain the first data and improves the reading speed.

[0090] In addition, by synchronizing the corresponding data in the memory based on the first address set from the reset circuit, the storage resources of the registers can be saved, thereby reducing the hardware size and cost.

[0091] In one alternative implementation, a first controller is connected to the processor to further enable the processor to write data to the memory. Figure 3 This is a second flowchart of a data reading method for a memory according to an embodiment of the present invention, such as... Figure 3 As shown, after step S203, the following steps are also included:

[0092] Step S204: Receive the first programming information sent by the processor.

[0093] The first programming information can be sent by the processor to the first controller via the AHB bus, for writing the first programming data into the memory.

[0094] The first programming information includes: first programming data and second address. The first programming data is generated by the processor performing logical operations on the second data obtained from the register and the first initial programming data. The first initial programming data is generated by the processor according to the first configuration instruction. The second data is the first data corresponding to the second address among the multiple first data stored in the register.

[0095] The first configuration instruction can be generated based on business requirements or administrator instructions, and the first initial programming data is the programming data that the business requirements or the administrator want to write to the second address in the memory. Specifically, the logical operation can be: when the data bit state of the OTP ROM is 0 (when it is not programmed), performing an OR operation on the second data and the first programming data; or, when the data bit state of the OTP ROM is 1 (when it is not programmed), performing an AND operation on the second data and the first programming data.

[0096] Step S205: Based on the first programming information, write the first programming data into the memory according to the second address.

[0097] The memory can be an OTP ROM. An OTP ROM includes multiple data bits, each of which stores data in binary form, i.e., either 0 or 1.

[0098] One specific implementation involves converting the first programming data into binary form to ensure it fits the address specified in the OTPROM. The target address to be written to is then determined, which is the second address in the OTPROM. Based on the binary form of the first programming data, the data bit state of the second address in the OTPROM is changed: for each bit, if the corresponding bit of the first programming data is 1, then that bit is set to 1; if it is 0, then that bit is set to 0.

[0099] The method provided in this embodiment, after synchronizing multiple first data sets to registers, receives first programming information sent by the processor, which includes a second address and first programming data. The first programming data is generated by the processor first retrieving second data from the registers, performing logical operations with first initial programming data generated based on first configuration instructions, and then writing this first programming data to the second address in memory. This allows the processor to verify the data in the registers through logical operations before writing the first programming data to memory, ensuring data consistency before writing the first programming data, thereby guaranteeing the security of data writing.

[0100] In this embodiment, after step S205, the following steps are also included:

[0101] Real-time acquisition of the memory's operating status.

[0102] The memory's operating status can be either idle or busy, corresponding to a write operation completed and a write operation in progress, respectively. To avoid writing data when the memory is busy, it's necessary to obtain the memory's operating status in real time. Specifically, this can be achieved by monitoring the specific timing of the memory's write operations.

[0103] Based on the operating status, determine whether the memory can perform a write operation.

[0104] The write operation is the process of storing data in memory.

[0105] Taking the acquisition of working status as an example, during the writing process, the controller can track the changes in the data line and control line to confirm whether the writing operation can be performed.

[0106] If so, then generate the first state signal.

[0107] The first status signal is used to indicate that the memory is in an idle state. Specifically, a status bit can be set in the encoding register of the first controller, and setting the status bit to 0 generates the first status signal.

[0108] Upon receiving the first detection command from the processor, the first status signal is sent to the processor.

[0109] Specifically, the first detection instruction can be to directly read the status bit set in the encoding register, and the logic signal of the status bit can be directly sent to the processor through the AHB bus.

[0110] The processor receives second programming information, which includes second programming data and a third address. The second programming information is sent by the processor upon receiving a first status signal. The second programming data is generated by logically operating the third data obtained by the processor from the register and the second initial programming data. The second initial programming data is generated by the processor according to the second configuration instruction. The third data is the first data corresponding to the third address among multiple first data stored in the register.

[0111] The second configuration instruction can be generated based on business requirements or administrator instructions, and the second initial programming data is the programming data that the business requirements or the administrator want to write to a third address in memory. Specifically, the logical operation can be: when the data bit state of the OTP ROM is 0 (when it is not programmed), performing an OR operation on the second data and the first programming data; or, when the data bit state of the OTP ROM is 1 (when it is not programmed), performing an AND operation on the third data and the second programming data.

[0112] Based on the second programming information, the second programming data is written into the memory according to the third address.

[0113] Taking writing the second programming data into the OTP ROM as an example, the state of the data bit at the third address of the OTP ROM can be directly changed. The first state signal is updated to the second state signal to indicate that the memory cannot perform a write operation. The update method can be to pull the level of the state bit set in the encoding register high, that is, change it from 0 to 1.

[0114] The method provided in this embodiment determines whether a write operation can be performed on the memory by acquiring the memory's operating status in real time. If so, a first status signal is generated. Then, after receiving a first detection instruction from the processor, the first status signal is sent to the processor. The processor obtains third data from the register, performs logical operations with the second initial programming data generated based on the second configuration instruction, generates second programming data, and then sends it along with the third address to the first controller. The first controller writes the second programming data to the third address of the memory and updates the first status signal to the second status signal, indicating that the memory cannot perform a write operation. Thus, before the processor writes the second programming data to the memory, it verifies the data with the data in the register through logical operations to ensure data consistency before writing the second programming data to the memory, thereby ensuring the security of data writing. Simultaneously, by determining the memory's operating status before receiving the second programming data, it avoids receiving a second write operation while writing one piece of data, thus ensuring the orderliness of the memory data writing process and the security of the memory data.

[0115] In another embodiment of this example, after determining that the memory cannot perform a write operation, the method further includes:

[0116] Generate a second status signal. Specifically, one method of generation includes: pulling the level of the status bit set in the encoding register high to indicate that the current memory is busy and a write operation cannot be performed, thereby generating a second status signal.

[0117] When a second detection command is received from the processor, a second status signal is sent to the processor.

[0118] The second detection instruction can be sent between the processor and the memory where other programming data needs to be written, to obtain either the first or second status signal. It can be sent via the AHB bus.

[0119] Alternatively, after updating the first state signal to the second state signal, a third detection command is sent by the receiving processor.

[0120] The third instruction can have the same content, generation method, and sending method as the second instruction.

[0121] In response to the third detection command, the second status signal is sent to the processor.

[0122] The method provided in this embodiment generates a second status signal when it is determined that the memory's operating state cannot perform a write operation. Then, upon receiving a second detection instruction from the processor, the second status signal is sent to the processor, or, after the first status signal is updated to the second status signal, the second status signal is sent to the processor in response to a third detection instruction from the processor. This instructs the processor to suspend sending other programming information and wait for the memory to complete the write operation corresponding to the current programming data, thereby ensuring the orderliness of the memory data writing process and the security of the memory data.

[0123] Optionally, the first data can be OTP data, and the first controller can be an OTP controller. Specifically, Figure 4 This is a schematic diagram illustrating the process of data synchronization from the OTP controller to the register according to an embodiment of the present invention, as shown below. Figure 4 As shown, it includes:

[0124] Step S401: System power-on initialization reset or system reset.

[0125] Specifically, a reset signal can be generated for the OTP ROM controller (i.e., the first controller) during system power-on initialization or system reset.

[0126] Step S402: Read the preset OTP ROM address that needs to be read.

[0127] That is, to obtain the first address set from the reset circuit.

[0128] Step S403: Wait for data to return from the OTP ROM.

[0129] That is, it returns multiple first data.

[0130] Step S404: Write the data into the register at the corresponding address.

[0131] That is, in step S203, multiple first data are sent to the register through the second controller.

[0132] Step S405: Determine whether all OTP ROM data has been written into the register. If yes, proceed to step S406. If no, return to step S402.

[0133] Here, all the OTP ROM data is equivalent to all the first data. The determination method can be that the second controller checks whether the corresponding write operation has been completed in the register.

[0134] Step S406: Set the OTP ROM to prepare for the end signal.

[0135] The OTP ROM is ready to end signal, which is also the first state signal.

[0136] In another embodiment, the present invention also provides a data reading method for a memory, the method being applied to a second controller, the second controller being connected to a register. Figure 5 This is a flowchart of the data reading method for a memory according to an embodiment of the present invention, as shown in the third flowchart. Figure 5 As shown, the method includes:

[0137] During the system reset process, in step S501, multiple first data are received from the first controller.

[0138] Multiple first data are read from the memory by the first controller, corresponding to multiple first addresses of the first address set, where one first address corresponds to one first data.

[0139] The first address set includes multiple first addresses in memory, which are dynamically generated by the system based on preset conditions or configuration. The first data can be frequently used or important data. Once the multiple first data items that need to be synchronized are determined, they can be retrieved from memory.

[0140] Step S502: Determine multiple fourth addresses in the register corresponding to each first data according to the preset correspondence.

[0141] Storing multiple first data items in a register requires knowing the addresses where these first data items are stored, i.e., a preset mapping relationship. This preset mapping relationship can be pre-stored in the reset circuit.

[0142] The default correspondence is a correspondence between at least one first data and a fourth address in the register.

[0143] Step S503: Store multiple first data into a register according to at least one determined fourth address.

[0144] Specifically, write operations corresponding to multiple first data can be input into the register via the register bus.

[0145] The server data processing method provided by this invention has the following advantages:

[0146] First, multiple first data points corresponding to multiple first addresses in a first address set are read from memory by the first controller. Then, according to a preset correspondence set, the multiple first data points are stored in multiple addresses in registers. This enables the transfer and storage of memory data in registers, so that the processor can directly read the first data from the memory in the registers later. Compared with reading from memory, this method reduces the latency of the processor in obtaining the first data and improves the read speed.

[0147] In addition, by synchronizing the corresponding data in the memory based on the first address set from the reset circuit, the storage resources of the registers can be saved, thereby reducing the hardware size and cost.

[0148] In one alternative implementation, to further consider the processor retrieving the first data from the memory from the register, Figure 6 This is a flowchart of the data reading method of the memory according to an embodiment of the present invention, as shown in Figure 4. Figure 6 As shown, after step S503, the following steps are also included:

[0149] Step S504: Receive the first read instruction sent by the processor.

[0150] The first read instruction includes the target fourth address of the register. The first read instruction can be sent to the second controller via the AHB bus.

[0151] Step S505: Read the corresponding first data from the register according to the target fourth address, and use it as the target first data.

[0152] The target first data is the first data corresponding to the fourth address among the multiple first data stored in the register.

[0153] Step S506: Send the target first data to the processor.

[0154] The target data can be transmitted to the processor via the data bus number in the AHB bus.

[0155] The method provided in this embodiment, upon receiving a first read instruction from the processor, reads first data from a register based on the fourth address in the first read instruction. Then, the found fourth data is fed back to the processor, thereby enabling the processor to directly read the first data from the memory register, thus reducing the latency of the processor acquiring the first data.

[0156] In an optional implementation, to further implement the data synchronization function in the register when the processor writes data to the memory, after step S506, the method further includes:

[0157] The receiver receives a second read instruction from the processor, which includes the fifth address of the register.

[0158] Before writing data into memory, the processor needs to check the third initial programming data against the corresponding data in the register to ensure the consistency of the data in the register and memory. Therefore, it is necessary to read the corresponding data in the register based on the fifth address.

[0159] Read the fourth data from the register based on the fifth address.

[0160] The fourth data point is one of several first data points.

[0161] The fourth data is sent to the processor.

[0162] The fourth data can be transmitted to the processor via the data bus number in the AHB bus.

[0163] The receiver receives the third programming data sent by the processor. The third programming data is obtained by performing logical operations on the third initial programming data and the fourth data. The third initial programming data is generated by the processor according to the third configuration instruction.

[0164] The third configuration instruction can be generated based on business requirements or administrator instructions, and the third initial programming data is the programming data that the business requirements or administrator need to write to the fifth address in memory. Specifically, the logical operation can be: when the data bit state of the OTP ROM is 0 (when it is not programmed), performing an OR operation on the fourth data and the third programming data; or, when the data bit state of the OTP ROM is 1 (when it is not programmed), performing an AND operation on the fourth data and the third programming data.

[0165] In the register, the fourth data is updated to the third programmed data.

[0166] The update method can be to directly change the state of the data bits at the fifth address.

[0167] Specifically, in this method, the fourth data corresponding to the fifth address in the second read instruction sent by the processor is read from the register. The fourth data is then fed back to the processor. The processor can perform logical operations between the third initial programming data and the fourth data, using the obtained third programming data to update the fourth data. Thus, before the processor writes the third programming data to memory, it can verify the data with the data in the register through logical operations, ensuring data consistency before writing the third programming data to both the register and memory, thereby guaranteeing data consistency and security.

[0168] In an optional implementation, after updating the fifth data to the third programmed data, the method further includes:

[0169] Monitor the operating status of registers and memory in real time to ensure data consistency between them.

[0170] During monitoring, if an abnormal register status or inconsistent data is detected, an error status signal is generated to indicate a system malfunction.

[0171] Receive error handling instructions sent by the processor and perform corresponding error recovery operations according to the instructions, including but not limited to resetting register contents, reloading data, or rolling back to a previous stable state.

[0172] After error recovery is completed, the recovered status information is sent to the processor for further decision-making and processing.

[0173] At the same time, relevant operation logs are recorded for subsequent fault analysis and system optimization.

[0174] In another embodiment, the present invention also provides a data reading device for a memory, the device being applied to a first controller, the first controller being connected to a reset circuit, a second controller, and a memory. Figure 7 This is one of the schematic diagrams of a data reading device for a memory according to an embodiment of the present invention, such as... Figure 7 As shown, the device includes:

[0175] The first acquisition module 701 is used to acquire a first address set from the reset circuit during the system reset process. The first address set includes multiple first addresses in the memory. The first address set is dynamically generated by the system according to preset conditions or configuration.

[0176] The first reading module 702 is used to read multiple first data corresponding to multiple first addresses of a first address set from the memory, wherein one first address corresponds to one first data.

[0177] The first transmitting module 703 is used to transmit multiple first data to a register via the second controller.

[0178] In an optional implementation, the first controller is connected to the processor; the device further includes:

[0179] The first receiving module is used to receive the first programming information sent by the processor.

[0180] The first programming information includes: first programming data and second address. The first programming data is generated by the processor performing logical operations on the second data obtained from the register and the first initial programming data. The first initial programming data is generated by the processor according to the first configuration instruction. The second data is the first data corresponding to the second address among the multiple first data stored in the register.

[0181] The first writing module is used to write the first programming data into the memory according to the second address based on the first programming information.

[0182] In an optional embodiment, the apparatus further includes:

[0183] The second acquisition module is used to acquire the working status of the memory in real time.

[0184] The first determining module is used to determine whether the memory can perform a write operation based on the working status.

[0185] The first generation module is used to generate a first state signal if the condition is met.

[0186] The second sending module is used to send a first status signal to the processor when it receives a first detection command sent by the processor.

[0187] The second receiving module is used to receive the second programming information sent by the processor.

[0188] The second programming information includes: second programming data and a third address. The second programming information is sent by the processor upon receiving the first status signal. The second programming data is generated by the processor performing logical operations on the third data obtained from the register and the second initial programming data. The second initial programming data is generated by the processor according to the second configuration instruction. The third data is the first data corresponding to the third address among the multiple first data stored in the register.

[0189] The second writing module is used to write the second programming data into the memory according to the third address based on the second programming information.

[0190] The first update module is used to update the first status signal to a second status signal, which indicates that the memory cannot perform a write operation.

[0191] In an optional embodiment, the apparatus further includes:

[0192] The second generation module is used to generate the second state signal.

[0193] The third sending module is used to send the second status signal to the processor when it receives the second detection command sent by the processor.

[0194] Alternatively, a third receiving module is used to receive a third detection command sent by the processor after updating the first state signal to the second state signal.

[0195] The fourth sending module is used to respond to the third detection command and send the second status signal to the processor.

[0196] The data reading device for a memory provided by the present invention has the following advantages:

[0197] First, a first address set from the reset circuit is obtained through a first controller. Based on this first address set, multiple first data points corresponding to these first addresses are read from memory. Then, the read first data points are sent to a register via a second controller. This allows memory data to be transferred and stored in the register, enabling the processor to directly read the first data from the register later. Compared to reading directly from memory, this method reduces the processor's latency in acquiring the first data and increases the read speed. Furthermore, synchronizing the corresponding data in memory based on the first address set from the reset circuit saves register storage resources, thereby reducing hardware size and cost.

[0198] In another embodiment, the present invention also provides a data reading device for a memory, the device being applied to a second controller. Figure 8 This is a second schematic diagram of the data reading device structure of the memory according to an embodiment of the present invention, as shown below. Figure 8 As shown, the device includes:

[0199] The fourth receiving module 801 is used to receive multiple first data from the first controller during the system reset process. The multiple first data are read from the memory by the first controller and correspond to multiple first addresses of the first address set, with one first address corresponding to one first data.

[0200] The second determining module 802 is used to determine the fourth address in the register corresponding to each first data according to a preset correspondence relationship. The preset correspondence relationship is the correspondence between at least one first data and the fourth address in multiple registers.

[0201] Storage module 803 is used to store a plurality of first data into a register according to at least one determined fourth address.

[0202] In an optional embodiment, the apparatus further includes:

[0203] The fifth receiving module is used to receive the first read command sent by the processor.

[0204] The first read instruction includes the target fourth address of the register.

[0205] The second reading module is used to read the corresponding first data from the register according to the fourth address of the target, and use it as the first data of the target.

[0206] The fourth data is the first data corresponding to the fourth address among the multiple first data stored in the register.

[0207] The fifth sending module is used to send the target first data to the processor.

[0208] In an optional embodiment, the apparatus further includes:

[0209] The sixth receiving module is used to receive the second read instruction sent by the processor. The second read instruction includes the fifth address of the register.

[0210] The third read module is used to read the fourth data from the register based on the fifth address.

[0211] The sixth sending module is used to send the fourth data to the processor.

[0212] The seventh receiving module is used to receive the third programming data sent by the processor.

[0213] The third programming data is obtained by performing logical operations on the third initial programming data and the fourth data. The third initial programming data is generated by the processor according to the third configuration instruction.

[0214] The second update module is used to update the fourth data in the register with the third programmed data.

[0215] The server data processing device provided by the present invention has the following advantages:

[0216] First, multiple first data points corresponding to multiple first addresses in a first address set are read from memory by the first controller. Then, according to a preset correspondence set, the multiple first data points are stored in multiple addresses in registers. This enables the transfer and storage of memory data in registers, so that the processor can directly read the first data from the memory in the registers later. Compared with reading from memory, this method reduces the latency of the processor in obtaining the first data and improves the read speed.

[0217] In addition, by synchronizing the corresponding data in the memory based on the first address set from the reset circuit, the storage resources of the registers can be saved, thereby reducing the hardware size and cost.

[0218] Further functional descriptions of each module and unit are the same as those in the corresponding embodiments, and will not be repeated here.

[0219] In this embodiment, the data reading device of the memory is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide functions.

[0220] This invention also provides a computer device having Figure 7 Or the data reading device of the memory shown in Figure 8.

[0221] Please see Figure 9 , Figure 9 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention, such as... Figure 9 As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 9 Take a processor 10 as an example.

[0222] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include an integrated circuit. The integrated circuit may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0223] The memory 20 stores instructions executable by at least one processor 10 to cause the at least one processor 10 to perform the method shown in the embodiment.

[0224] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function. The data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, which can be connected to the computer device via a network. Examples of networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0225] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of different types of memory.

[0226] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0227] This invention also provides a computer-readable storage medium. The methods according to embodiments of the invention can be implemented in hardware or firmware, or implemented as recordable on a storage medium, or implemented as computer code originally stored on a remote storage medium or a non-transitory machine-readable storage medium and subsequently stored on a local storage medium after being downloaded via a network. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of various types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the embodiments.

[0228] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and all such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A method for reading data from a memory, characterized in that, The method is applied to a first controller, which is connected to a processor, a reset circuit, a second controller, and a memory, respectively. The method includes: During system reset, a first address set is obtained from the reset circuit. The first address set includes multiple first addresses in the memory. The first address set is generated based on the following method: during the operation before system reset, the number of times each data is read by the processor is obtained, and multiple addresses in the memory corresponding to multiple first data whose number of reads is greater than a preset value are used as the first address set. From the memory, read a plurality of first data corresponding to a plurality of first addresses of the first address set, wherein one first address corresponds to one piece of first data; Sending the plurality of first data to a register via the second controller; wherein, after sending the plurality of first data to the register via the second controller, the method further includes: The processor receives first programming information, which includes first programming data and a second address. The first programming data is generated by the processor performing logical operations on second data obtained from the register and first initial programming data. The first initial programming data is generated by the processor according to a first configuration instruction. The second data is the first data corresponding to the second address among a plurality of first data stored in the register. According to the first programming information, the first programming data is written into the memory at the second address; wherein, the memory is an OTP memory.

2. The method according to claim 1, characterized in that, After writing the first programming data into the memory, the process further includes: Real-time acquisition of the operating status of the memory; Based on the operating status, determine whether the memory can perform a write operation; If so, then generate the first state signal; When a first detection command is received from the processor, the first status signal is sent to the processor. The processor receives second programming information, which includes second programming data and a third address. The second programming information is sent by the processor upon receiving the first status signal. The second programming data is generated by the processor performing logical operations on the third data obtained from the register and the second initial programming data. The second initial programming data is generated by the processor according to the second configuration instruction. The third data is the first data corresponding to the third address among the multiple first data stored in the register. According to the second programming information, the second programming data is written into the memory at the third address; The first status signal is updated to a second status signal to indicate that the memory cannot perform a write operation.

3. The method according to claim 2, characterized in that, After determining that the memory cannot perform a write operation, the process also includes: Generate the second state signal; When a second detection command is received from the processor, the second status signal is sent to the processor. Alternatively, after updating the first state signal to the second state signal, a third detection instruction sent by the processor is received; In response to the third detection command, the second status signal is sent to the processor.

4. A method for reading data from a memory, characterized in that, The method is applied to a second controller, and the method includes: During system reset, multiple first data are received from the first controller; the multiple first data are read from the memory by the first controller according to multiple first addresses of the first address set, wherein one first address corresponds to one first data, and the first address set is generated based on the following method: during the working process before system reset, the number of times each data is read by the processor is obtained, and the multiple addresses in the memory corresponding to multiple first data whose number of reads is greater than a preset value are used as the first address set; According to a preset correspondence, the fourth address corresponding to each first data in the register is determined. The preset correspondence is a correspondence between at least one first data and the fourth address in the register. According to at least one determined fourth address, multiple first data are stored in the register; After storing multiple first data into the register, the method further includes: Receive a first read instruction sent by the processor, the first read instruction including the target fourth address of the register; Read the corresponding first data from the register according to the target fourth address, and use it as the target first data; The target first data is sent to the processor; And, after sending the target first data to the processor, the method further includes: Receive a second read instruction sent by the processor, the second read instruction including the fifth address of the register; Based on the fifth address, read the fourth data from the register; The fourth data is sent to the processor; The processor receives third programming data, which is obtained by performing logical operations on third initial programming data and fourth data. The third initial programming data is generated by the processor according to a third configuration instruction. In the register, the fourth data is updated to the third programming data; wherein, the memory is an OTP memory.

5. A data reading device for a memory, characterized in that, The device is applied to a first controller, which is connected to a reset circuit, a second controller, and a memory. The device includes: The first acquisition module is used to acquire a first address set from the reset circuit during the system reset process. The first address set includes multiple first addresses in the memory. The first address set is generated based on the following method: during the operation before system reset, the number of times each data is read by the processor is acquired, and multiple addresses in the memory corresponding to multiple first data whose number of reads is greater than a preset value are used as the first address set. The first reading module is used to read multiple first data corresponding to multiple first addresses of the first address set from the memory, wherein one first address corresponds to one first data. A first sending module is configured to send the plurality of first data to a register via a second controller, and the first controller is connected to a processor. After sending the plurality of first data to the register via the second controller, the module receives first programming information sent by the processor. The first programming information includes: first programming data and a second address. The first programming data is generated by the processor performing logical operations on second data obtained from the register and first initial programming data. The first initial programming data is generated by the processor according to a first configuration instruction. The second data is the first data corresponding to the second address among the plurality of first data stored in the register. According to the first programming information, the first programming data is written into the memory according to the second address. The memory is an OTP memory.

6. A data reading device for a memory, characterized in that, The device is applied to a second controller, and the device includes: The fourth receiving module is used to receive multiple first data from the first controller during the system reset process; the multiple first data are read from the memory by the first controller according to multiple first addresses of the first address set, wherein one first address corresponds to one first data, and the first address set is generated based on the following method: during the working process before system reset, the number of times each data is read by the processor is obtained, and the multiple addresses in the memory corresponding to multiple first data whose number of reads is greater than a preset value are used as the first address set; The second determining module is used to determine the fourth address in the register corresponding to each first data according to a preset correspondence relationship, wherein the preset correspondence relationship is the correspondence between at least one first data and the fourth address in multiple registers; A storage module is configured to: store a plurality of first data into the register according to at least one determined fourth address; and after storing the plurality of first data into the register, receive a first read instruction sent by the processor, the first read instruction including a target fourth address of the register; read corresponding first data from the register according to the target fourth address as target first data; send the target first data to the processor; and after sending the target first data to the processor, receive a second read instruction sent by the processor, the second read instruction including a fifth address of the register; read fourth data from the register according to the fifth address; send the fourth data to the processor; receive third programming data sent by the processor, the third programming data being obtained by performing logical operations between third initial programming data and the fourth data, the third initial programming data being generated by the processor according to a third configuration instruction; and update the fourth data in the register with the third programming data; wherein the memory is an OTP memory.

7. A computer device, characterized in that, include: A memory and a processor are communicatively connected, the memory stores computer instructions, and the processor executes the computer instructions to perform the memory data reading method according to any one of claims 1 to 4.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a computer to perform the data reading method of the memory as described in any one of claims 1 to 4.

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