Safe pseudo-random number generator and method for high throughput of FPGA (Field Programmable Gate Array)

Abstract

The invention discloses a safe pseudo-random number generator and method for high throughput of an FPGA (Field Programmable Gate Array). According to the scheme, 12 rounds of permutation functions and modules thereof are designed on the basis of an FPGA, and input data are fully mixed through a series of linear and nonlinear operations in each round; a round constant generator of a nonlinear feedback shift register is designed, and XOR operation is performed with data at a specific position; a counter and a logic circuit are arranged to process and optimize wheel constants and increase nonlinear changes; and setting a time threshold mechanism, and carrying out regular re-seeding operation. According to the method, hardware resources are remarkably reduced and saved, meanwhile, data randomness and attack resistance are improved, the utilization rate of round constant storage resources is increased, high-throughput, efficient and high-randomness pseudo-random number generation is achieved, safety and performance balance is achieved, efficiency, unpredictability and the hardware resource utilization rate are improved, and the method is suitable for large-scale popularization and application. And the randomness and safety in long-term operation are ensured.

Description

Technical Field

[0001] The invention relates to the field of random number generation by FPGA, and in particular to a high-throughput secure pseudo-random number generator and method for FPGA. Background Art

[0002] With the rapid development of information technology, the application of random numbers has become an indispensable part of modern information systems. Random numbers play a key role in many fields, including cryptography, simulation, statistical analysis, distributed systems, and artificial intelligence training. However, the quality of random number generation directly affects the security and performance of information systems. If the random numbers are not random enough or are predictable, the system will be exploited by attackers, thereby endangering the security of the system.

[0003] Currently, random number generators are mainly divided into two categories: true random number generator (TRNG) and pseudo-random number generator (PRNG).

[0004] Although the performance of PRNG is excellent, its security is highly dependent on the quality of the seed and the complexity of the algorithm. In order to enhance the security of PRNG, many modern designs introduce hybrid random number generators (Hybrid RNG), combining the physical noise input of TRNG with the algorithmic generation capability of PRNG to strike a balance between security and efficiency.

[0005] Mohamed Gafsi et al. proposed a high-performance FPGA pseudo-random number generator (PRNG) implementation based on Lorenz chaotic mapping. A digital pseudo-random number generator (DPRNG) for high-quality key generation was developed using Lorenz chaotic mapping. The proposed DPRNG architecture consists of three modules: initial state generator (ISG), Lorenz chaotic mapping, and modulation module. The hardware design was implemented on the FPGA-Zynq platform using the Xilinx System Generator (XSG) tool, with low resource utilization.

[0006] Existing solutions, such as the Lorenz chaotic map-based pseudo-random number generator (DPRNG) proposed by Mohamed Gafsi, have performed well in throughput, hardware resource utilization, and randomness tests, but there are still some limitations and room for improvement. First, although the design improves the frequency and throughput in hardware implementation, compared with some application scenarios (such as real-time high-density data encryption or large-scale IoT device communication), the throughput of 25702 Mbps may still not be enough to meet higher performance requirements. Secondly, the complexity in hardware implementation, such as the use of floating-point operations, although it improves the accuracy of random numbers, also increases the hardware design cost and power consumption, which may not be suitable for resource-constrained embedded devices.

[0007] Therefore, the prior art lacks a secure pseudo-random number generator and method that can achieve high-efficiency, low-power consumption, high-throughput random number generation while ensuring the quality of random number generation. Summary of the invention

[0008] In order to solve the problems existing in the background technology, the present invention provides a high-throughput secure pseudo-random number generator and method for FPGA, which can achieve efficient and low-power random number generation on the basis of ensuring the quality of random number generation, and meet the diverse needs of modern information systems in the fields of communication security, embedded devices, and the Internet of Things.

[0009] The present invention relates to the field of communication security and random number generation, and in particular to the design and optimization technology of secure pseudo-random number generators in high-throughput application scenarios. Specifically, the scheme of the present invention can meet the demand for high-speed and secure random number generation in modern information systems, and is widely applicable to security scenarios such as encrypted communication, data integrity verification, identity authentication, and key generation.

[0010] The present invention processes binary numbers to generate binary random numbers, and all operations involved are binary operations.

[0011] The technical solution adopted by the present invention is: 1. A secure pseudo-random number generator for high throughput in FPGAs: The secure pseudo-random number generator is based on FPGA hardware and includes: An initial seed input module is used to input the original seed from the outside and pre-process it into an initial seed storage; A round constant generation module, used to pre-generate the round constants required by the permutation function module 12 rounds, and send them to the permutation function module; The permutation function module has an optimized permutation function F' containing a round constant, which is used to read the initial seed in the initial seed input module and store it, and then use the built-in optimized permutation function F' to perform 12 rounds of permutation operations on the initial seed to obtain the final random number output; The reseed mechanism module is used to periodically refresh the original seed to ensure randomness and security during long-term operation.

[0012] The initial seed input module includes: A register or FIFO to store the original seed; A bit selection module that reads the original seed stored in the register or FIFO and selects a portion of it; A filling and initial XOR module is used to perform XOR operation on a part of the number selected by the bit selection module and a number composed of multiple consecutive 0s with the same number of bits, and to concatenate the number composed of multiple consecutive 0s to form an initial seed.

[0013] The bit selection module comprises: a first counter for dynamically selecting bits in the original seed; a multiplexer (MUX) for selecting a binary value of a specified portion of bits as a portion of the number according to the dynamic selection of the first counter; The filling and initial XOR module includes an XOR circuit and a splicing logic circuit. The XOR circuit is used to perform an XOR operation on a part of a number with a number consisting of multiple consecutive 0s of the same number of bits. The splicing logic circuit is used to splice the number after the XOR operation of the XOR circuit with a number consisting of multiple consecutive 0s.

[0014] The round constant generation module comprises: A second counter is used to select the first round constant from the initial seed; the second counter and the first counter can be shared.

[0015] A nonlinear feedback shift register NLSFR is used to generate the round constants of the next 11 rounds according to the round constants of the first round, so as to realize the dynamic generation of the subsequent round constants, and has built-in left shift operation and XOR operation.

[0016] The permutation function module includes a logic circuit for storing registers and for performing XOR, AND, NOT operations, etc., and an optimized permutation function F' is formed in the logic circuit through hardware topology design; The reseed mechanism module utilizes a timer / counter to track a time threshold or a generation quantity threshold to control the update.

[0017] 2. A method for generating secure pseudo-random numbers for high throughput in FPGA, the method comprising: (1) Seed input stage: The original seed is stored in a register or FIFO, and after preprocessing by a bit selection module and a filling and initial XOR module, an initial seed is obtained as input data. The number of bits / bits of the original seed and the initial seed are the same and both are binary numbers; The original seed comes from an external input or a true random number generator TRNG, and is used to initialize the state of the pseudo-random number generator.

[0018] (2) Round constant generation stage: The role of the round constant is to enhance the randomness, security, and anti-attack capabilities of the random number generator by introducing dynamic, nonlinear, and unique changes, and to ensure the independence and complexity between each round of operations.

[0019] According to the initial seed, a counter is used in combination with a nonlinear feedback shift register NLSFR to pre-generate dynamic round constants for the permutation function execution stage through shifting and XOR operations; During the generation process, dynamically generated round constants are pre-stored to reduce runtime computation requirements.

[0020] (3) Permutation function execution phase: A register is set to store an input initial seed, and an optimized permutation function F' implemented by a logic circuit and containing a round constant is used to process the initial seed. The optimized permutation function F' includes 12 rounds of permutation operations. After each 12 rounds of permutation operations are performed, a final random number is output as a secure pseudo-random number result; (4) Replanting mechanism stage: By setting a time threshold or a generation quantity threshold, the original seed is refreshed periodically through a timer / counter according to the time threshold or the generation quantity threshold, that is, returning to step (1) and then repeating steps (1) to (3) for a loop process, and continuously updating the output of the final random number.

[0021] The step (1) is specifically as follows: first, a counter of the bit selection module is used to select a number of consecutive digits / bits from the original seed stored in the register or FIFO on the low-order side and the high-order side to form a preliminary binary number, and then a filling and initial XOR module is used to perform an XOR operation on a binary number consisting of consecutive 0s with the same number of digits / bit as the preliminary binary number and the preliminary binary number, and then the number of consecutive 0s / bits is spliced ​​at the end to form a binary number with the same number of digits as the original seed as the initial seed, which is used for subsequent input into the optimized permutation function F'.

[0022] The step (2) is specifically as follows: (21) First, a counter is used to select a preset binary number of several digits from the initial seed as the round constant rc1 for optimizing the first round of the permutation function F'; (22) Then the round constant rc of the nth round is n Use the nonlinear feedback shift register NLSFR to dynamically generate the next round of round constants rc n+1 , expressed as: rc n+1 [K-1:0] = {rc n [K-2:0], rc n [A] ^ rc n [B] ^ rc n [C] ^ rc n [D]} Among them, ^ represents XOR operation, {} represents binary number concatenation, rc n [62:0] represents the round constant rc n From the lowest bit 0 to the 62nd bit, that is, from the lowest bit to the second-to-last bit, that is, from the rightmost bit to the second-to-last left bit; K represents the total number of bits of each round constant, A, B, C, D represent four pre-set fixed bits, rc n [A], rc n [B] rc n [C], rc n [D] represents the wheel constant rc n The values ​​at the fixed bit positions A, B, C, D, which are all less than K, are used to perform XOR operations on the round constants; (23) Finally, the above process (22) is repeated to generate the round constants corresponding to each round in all the optimized permutation functions F'.

[0023] The fixed digits A, B, C, and D in the above-mentioned rounds of constant generation processing remain unchanged.

[0024] The round constant generation of the present invention uses a nonlinear feedback shift register including two basic operations, a left shift or a right shift and an XOR operation.

[0025] The optimized permutation function F' includes 12 rounds of permutation function operations.

[0026] The round constant of the Iota step in each permutation operation of the optimized permutation function F' corresponds to the round constant obtained in step (2), that is, the round constant of the Iota step in the i-th permutation operation of the optimized permutation function F' corresponds to the i-th round constant obtained in step (2). The initial seed is input into the optimized permutation function F' and the final random number is obtained after 12 consecutive permutation operations.

[0027] Each round of permutation operation of the optimized permutation function F' includes five steps performed sequentially in the logic circuit, the five steps are respectively a Theta step, a Rho step, a Pi step, a Chi step and an Iota step; First, the Theta step is performed to calculate the even parity of each column of the input binary data and perform an XOR operation with each state bit value in it to achieve global information diffusion; Then, the Rho step is performed to perform a cyclic shift process on each state bit value according to a predefined offset to increase the obfuscation of the state; Then, the Pi step is performed to rearrange the bit values ​​of the bit states on the same surface, dispersing the local information to the global information; Next, the Chi step is performed to process the bits on the same line through nonlinear Boolean transformation to enhance the nonlinear complexity of the state; Finally, the Iota step is performed to perform an even XOR operation on the round constant and the specific bit, so as to introduce randomness and uniqueness of the round.

[0028] The above five steps work together to ensure sufficient confusion and diffusion of the state, providing high security for subsequent rounds.

[0029] Each round of permutation operation includes the above five steps, and a total of 12 rounds are performed, that is, the five steps are repeated 12 times. By combining linear and nonlinear operations in the round permutation function, the input data is fully obfuscated to ensure high randomness and security of the output.

[0030] The value of each bit of the initial seed is used as a state bit value, and the state bit values ​​of each bit of the initial seed are distributed in a three-dimensional arrangement manner along the three axes of x, y, and z in a plurality of cubes to form three-dimensional arrangement structure data.

[0031] The three-dimensional arrangement structure data is divided into three types of slices: horizontal slice plane, vertical slice slice, and longitudinal slice sheet, and three types of strips: horizontal strip row, vertical strip column, and longitudinal strip lane. Each slice is composed of state bit values ​​corresponding to all cubes in a layer on the same plane, and each strip is composed of state bit values ​​corresponding to a column of cubes on the same straight line.

[0032] The horizontal slice plane is composed of the state bit values ​​corresponding to all cubes located on the xz plane, the vertical slice slice is composed of the state bit values ​​corresponding to all cubes located on the xy plane, and the longitudinal slice sheet is composed of the state bit values ​​corresponding to all cubes located on the yz plane; the horizontal bar row is composed of the state bit values ​​corresponding to all cubes located on the x-axis line, the vertical bar column is composed of the state bit values ​​corresponding to all cubes located on the y-axis line, and the vertical bar lane is composed of the state bit values ​​corresponding to all cubes located on the z-axis line.

[0033] The final random number is obtained after 12 rounds of permutation operations are performed continuously on the three-dimensional arrangement structure data.

[0034] In each round of permutation operation, the following process is followed: The Theta step processes and replaces each state bit value in the three-dimensional arrangement data structure according to the following formula: s'[x][y][z]=s[x][y][z]^∑ y'' s[x-1][y''][z]^∑ y'' s[x+1][y''][z-1] y''=y+△y Wherein, s'[x][y][z] represents the state bit value of the coordinates (x, y, z) in the three-dimensional arrangement structure data after the Theta step, and s[x][y][z] represents the state bit value of the coordinates (x, y, z) in the three-dimensional arrangement structure data before the Theta step; y'' represents the y coordinate of the state bit values ​​of the two adjacent columns of the vertical bar column under the current calculated state bit value s[x][y][z] and its three-dimensional arrangement; ^ represents an exclusive-or operation, and △y represents the step value of the adjacent y coordinates; The operation of the Theta step is essentially to perform an XOR operation on all state bit values ​​s[x][y][z] and the parity check values ​​of the two adjacent columns to obtain a new state bit value.

[0035] The Rho step processes and replaces each state bit value in the three-dimensional arrangement data structure processed by the Theta step according to the following formula: s''[x][y][z]=s'[x][y][z-(t+1)(t+2) / 2] Wherein, t represents an intermediate variable used to calculate the bit value offset; s''[x][y][z] represents the state bit value of the coordinates (x, y, z) in the three-dimensional arrangement structure data after the Rho step; The Rho step operation is to translate all state bit values ​​s'[x][y][z] by (t+1)(t+2) / 2 units in the z-axis direction. The Rho step operation fixes the x-axis and the y-axis and can be regarded as a cyclic shift inside the 25 vertical lanes.

[0036] The Pi step is to process and replace each state bit value located on the same vertical slice in the three-dimensional arrangement data structure processed by the Rho step according to the following formula: p'[x][y]=p[x'][y']

[0037] Wherein, p'[x][y] represents the state bit value of the coordinates (x, y) on the vertical slice slice located on the same xy plane in the three-dimensional arrangement structure data after the Pi step processing, p[x][y] represents the state bit value of the coordinates (x, y) on the vertical slice slice located on the same xy plane in the three-dimensional arrangement structure data before the Pi step processing, and x', y' represent the new horizontal and vertical position coordinates of the state bit value in the state matrix; The operation of the Pi step is to fix the z-axis and is regarded as a bit permutation on 25 vertical slices, and the permutation restriction is given by the following conditions.

[0038] The Chi step is to process and replace the state bit value of each bit located in the same horizontal row in the three-dimensional arrangement data structure processed by the Pi step according to the following formula: q'[x]= q[x]^((q[x+1]^1)&q[x+2]) Among them, q'[x] represents the state bit value of coordinate x on the horizontal bar row located on the same x-axis line in the three-dimensional arrangement structure data after processing in the Chi step, q'[x] represents the state bit value of coordinate x on the horizontal bar row located on the same x-axis line in the three-dimensional arrangement structure data before processing in the Chi step, ^ represents XOR operation, and & represents AND operation.

[0039] The operation of the Chi step is to fix the y-axis and the z-axis, and is regarded as a bit operation on all horizontal rows, including XOR, AND and NOT operations.

[0040] The Iota step is to process and replace the state bit value of each vertical lane located at the center of the three-dimensional arrangement data structure processed by the Chi step according to the following formula: I'[0][0][z]=I[0][0][z]^RC i Among them, i represents the number of rounds of permutation operation, RC iRepresents the round constant of the current i-th round, where I'[0][0][z] represents the state bit value of the coordinate z on the centermost vertical lane in the three-dimensional arrangement structure data after the Iota step, and z is an even number; I[0][0][z] represents the state bit value of the coordinate z on the centermost vertical lane in the three-dimensional arrangement structure data before the Iota step, and the value range of z is from 0 to 62.

[0041] The optimized replacement function F' of the present invention is an encrypted hash function based on the Keccak algorithm, which adopts a unique sponge structure and completes the generation of the message digest in two stages of absorption and extrusion.

[0042] First, in the absorption phase, the input message is divided into blocks, each block is XORed with the first r bits of the current state, and then the state is updated through the permutation function; in the extrusion phase, the output summary is extracted from the first r bits of the state, and the state is updated through the permutation function if it is insufficient. The state feature consists of the absorption rate part r and the capacity part c. The absorption rate part r is responsible for processing input and output, and the capacity part c provides security. In addition, the multiple rounds of nonlinear operations of the permutation function ensure strong resistance to collision and pre-image attacks. Compared with traditional processing, it has higher flexibility and security, and is suitable for a variety of application scenarios, including cryptography and data integrity verification.

[0043] The existing permutation function F in the prior art includes 24 rounds of operations each time it runs, resulting in low throughput and difficulty in meeting high performance requirements.

[0044] Moreover, the existing permutation function F has two major problems during operation: first, the round constant (64-bit long data) is generated during runtime, resulting in high consumption of computing resources; second, the round constant is fixed and is the same each time the F function is executed, which may make the behavior of the algorithm easier to be analyzed and predicted by attackers, thereby reducing security.

[0045] To solve these problems, Figure 3 As shown, the present invention proposes an optimization scheme to improve coordination in many aspects: On the one hand, the solution of the present invention is to optimize the permutation function to F', and reduce the number of running rounds from 24 to 12 rounds. On the basis of ensuring security, it can significantly improve the throughput of the algorithm by reducing the computational complexity, making it more suitable for scenarios with higher performance requirements.

[0046] On the other hand, the present invention adopts the processing mechanism of the nonlinear feedback shift register NLSFR to generate round constants in advance based on the initial seed of the random number in the process of generating round constants.

[0047] In this way, the generation of round constants can be completed before running, thus reducing the computing resource consumption during running. At the same time, simple shift and XOR operations are used to generate dynamically changing round constants, ensuring that the round constants of each round are different. This processing method not only improves the efficiency of round constant generation, but also enhances the unpredictability and anti-attack ability of the algorithm, achieving a good balance between security and performance.

[0048] On the other hand, in order to solve the problem that only 7 bits are involved in the XOR operation in the existing permutation function F round constant processing, resulting in a waste of storage resources, and the problem that the S box is not used and the nonlinear change is small, resulting in insufficient randomness of the output data, the present invention also improves the lota step of the round constant processing, not only combining only 12 pre-generated round constants, but also selecting 32 bits in the round constant and 32 bits of the local number of data for XOR operation each time, which increases unpredictability and computational complexity. This improvement also greatly improves the utilization efficiency of the round constant storage resources, enhances the security of the algorithm and the randomness of the output results, and solves the above-mentioned resource waste and randomness problems.

[0049] In a specific implementation, the present invention can also optimize the execution of the optimized permutation function F' by pipeline acceleration to improve the throughput of the pseudo-random number generator (PRNG). Since the optimized permutation function F' has a total of 12 rounds of operations, by dividing it into a multi-stage pipeline design, multiple rounds of constant operations can be performed within one clock cycle, and 2-level, 3-level, 4-level, 6-level or 12-level acceleration can be achieved according to requirements, which can further significantly improve throughput and reduce latency while maintaining processing integrity and security.

[0050] Therefore, the solution of the present invention adopts multiple optimization techniques to significantly improve the performance and security of the pseudo-random number generator (PRNG). The specific beneficial effects include: 1) By making a lot of modifications to the hash function, a new 12-round permutation function optimized permutation function F' is designed for the pseudo-random number generator (PRNG). The input 1600-bit seed is fully obfuscated through linear and nonlinear operations to ensure high randomness and security of the output data. The output randomness is guaranteed while improving the throughput, achieving a balance between security and performance.

[0051] 2) Establish a round constant generator based on nonlinear feedback shift register: Use nonlinear feedback shift register (NLSFR) to pre-generate round constants, and use simple shifts and XOR operations with specific data positions to reduce the computational complexity of round constant generation. At the same time, it ensures that the round constants of each round are different, thereby improving the randomness and unpredictability of the output while reducing hardware resource consumption.

[0052] 3) Optimized round constant generation and storage: Add nonlinear changes, select 32 bits in the round constant each time to perform XOR operation with the original data, further enhance the complexity and unpredictability of the output, further improve the randomness and anti-attack ability of the output data, and improve the utilization rate of the round constant storage resources.

[0053] 4) Time threshold mechanism: Regularly perform reseeding operations to refresh the seeds to ensure the continuity and security of output randomness during long-term operation.

[0054] 5) Multi-stage pipeline acceleration: The throughput of PRNG is improved by introducing pipeline technology. According to the 12-round design of the optimized permutation function F', the 12-round permutation function is efficiently parallelized, supporting 2-level, 3-level, 4-level, 6-level and 12-level pipeline acceleration, so that multiple rounds of constants can be executed within one clock cycle, which significantly improves the overall performance of the system. It only takes 4 clock cycles to complete the generation of 1600-bit random numbers, which significantly improves the throughput.

[0055] 6) High throughput: In the 12 rounds of F' function operation, by optimizing the calculation process and hardware resource allocation, efficient and highly random pseudo-random number generation is achieved while reducing the calculation consumption. After testing, in a 200MHz FPGA environment, the throughput reaches 80Gbps, meeting the high performance requirements.

[0056] In summary, these technical means achieve a balance between security and performance, and significantly improve the efficiency, unpredictability and hardware resource utilization of random number generation. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 A basic flow chart of the method and system processing of the present invention; Figure 2 is the flow chart of the permutation function of round i; Figure 3 Improved renderings for the wheel constant generator and wheel constants; Figure 4 This is a performance comparison chart of pipelines with different numbers of stages; Figure 5 This is the overall design diagram of the PRNG scheme; Figure 6 It is a schematic diagram of the geometric representation of the state characteristics of the round permutation function in the scheme; Figure 7 Schematic diagram of the classification of specific arrangements of state characteristics of the round permutation function in the scheme. DETAILED DESCRIPTION

[0058] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0059] The overall design process of the solution of the present invention is as follows Figure 5 As shown in the figure, first, for the input 1600-bit seed, 12 rounds of permutation functions are designed. Each round uses a series of linear and nonlinear operations to fully confuse the input data, making the output data highly random. Secondly, a round constant generator based on NLSFR (nonlinear feedback shift register) is designed. By performing XOR operations with data at specific positions, the unpredictability of the output is further enhanced, and hardware resources are significantly saved. In addition, the Iota function for round constant processing is optimized, and nonlinear changes are added, which further improves the randomness and anti-attack capabilities of the data. In order to ensure randomness in long-term operation, a time threshold mechanism is also designed to periodically reseed the PRNG to refresh the seed data and ensure the randomness and security of the output results.

[0060] The secure pseudo-random number generator specifically implemented is based on FPGA hardware, including an initial seed input module, a round constant generation module, a permutation function module and a reseed mechanism module: the FPGA-based hardware composition and each step in the method are in a corresponding relationship.

[0061] The initial seed input module is used to input the original seed x[1599:0] of 1600 bits from the outside and pre-process it into initial seed storage.

[0062] The initial seed input module includes: A register or FIFO to store the 1600-bit raw seed.

[0063] A bit selection module reads the 1600-bit original seed stored in the register or FIFO and selects a portion of 576 bits as input. The bit selection module implements dynamic selection through an 11-bit counter.

[0064] The above-mentioned bit selection module includes: An 11-bit first counter, used to dynamically select bits in the original seed; A multiplexer (MUX) is used to select a binary value of a specified part of bits as a part number according to the dynamic selection of the first counter.

[0065] The initial seed input module also includes a padding and initial XOR module, which is used to perform an XOR operation on the 576-bit data of a part of the number selected by the bit selection module and a number composed of multiple consecutive 0s of 576 bits of the same number of bits, and to splice a number composed of multiple consecutive 0s of 1024 bits to form a 1600-bit initial seed.

[0066] The padding and initial XOR module includes an XOR circuit and a splicing logic circuit. The XOR circuit is used to perform an XOR operation on a part of a 576-bit number with a number consisting of multiple consecutive 0s of 576 bits of the same number of bits. The splicing logic circuit is used to splice the 576-bit number after the XOR operation of the XOR circuit with a number consisting of multiple consecutive 0s of 1024 bits.

[0067] The round constant generation module is used to pre-generate the 64-bit round constants required for 12 rounds of the permutation function module and send them to the permutation function module; The round constant generation module includes: A 11-bit second counter is used to select the first round 64-bit round constant from the initial seed. In a specific implementation, the second counter can be reused with the 11-bit first counter of the first step, that is, the same counter is used.

[0068] A nonlinear feedback shift register NLSFR is used to generate the round constants of the next 11 rounds based on the 64-bit round constant of the first round, realizing the dynamic generation of the subsequent round constants, with built-in left shift operation and XOR operation. XOR operation logic: used to implement rc n+1 [K-1:0] = {rc n [K-2:0], rc n [A] ^ rc n [B] ^ rc n [C] ^ rc n [D]} operation.

[0069] The permutation function module contains an optimized permutation function F' including the round constant generated by the round constant generation module, and is used to read the initial seed in the initial seed input module and store it, and then use the built-in optimized permutation function F' to perform 12 rounds of permutation operations on the initial seed to obtain the final random number output; The permutation function module includes a register for storing 1600 bits and a logic circuit for performing operations such as XOR, AND, and NOT. The optimized permutation function F' is constructed in the logic circuit through hardware topology design.

[0070] The reseed mechanism module is used to periodically refresh the original seed to ensure randomness and security during long-term operation. The reseed mechanism module uses a timer / counter to track the time threshold or the generation quantity threshold to control the update.

[0071] The following is a description of the implementation process of the solution of the present invention. Figure 1 As shown, including the sequential connection of each step and detailed sub-step logic description: (1) Seed input stage: The random number generation process starts with a 1600-bit initial seed. The 1600-bit original seed generated by external input or true random number generator TRNG is stored in a register or FIFO. After preprocessing by the bit selection module and the padding and initial XOR module, the initial seed is obtained as the input data. The number of bits / bit of the original seed and the initial seed is the same and both are binary numbers.

[0072] Step (1) is to first use a counter of the bit selection module in combination with a multiplexer (MUX) to select a number of consecutive digits / bits from the original seeds of a number of digits / bits stored in the register or FIFO on the low-order side and the high-order side to form a preliminary binary number, and then use the filling and initial XOR modules to perform an XOR operation (XOR operation on each digit) on a binary number consisting of consecutive 0s with the same number of digits / bits as the preliminary binary number, and then splice the consecutive digits / bits of 0 at the end to make the number of digits the same as the original seed. The binary number with the same number of digits as the original seed is used as the initial seed for subsequent input into the optimized permutation function F'.

[0073] (2) Round constant generation stage: According to the random initial seed, a counter is used in combination with a nonlinear feedback shift register NLSFR to pre-generate dynamic round constants for the permutation function execution phase through shifting and XOR operations, specifically generating multiple round constants through shifting and XOR operations.

[0074] (21) First, a round constant for optimizing the first round of the permutation function F' is selected from an initial seed by a counter as a binary number of preset digits, which is used as the round constant rc1 for optimizing the first round of the permutation function F'; (22) Then the round constant rc of the nth round is n Use the nonlinear feedback shift register NLSFR to dynamically generate the next round of round constants rc n+1 , expressed as: rc n+1 [K-1:0] = {rc n [K-2:0], rc n [A] ^ rc n [B] ^ rc n [C] ^ rc n [D]} Among them, ^ represents XOR operation, {} represents binary number concatenation, rc n [62:0] represents the round constant rc nFrom the lowest bit 0 to the 62nd bit, that is, from the lowest bit to the second-to-last bit, that is, from the rightmost bit to the second-to-last left bit; K represents the total number of bits of each round constant, A, B, C, D represent four pre-set fixed bits, rc n [A], rc n [B] rc n [C], rc n [D] represents the wheel constant rc n The values ​​at the fixed bit positions A, B, C, D, which are all less than K, are used to perform XOR operations on the round constants; (23) Finally, the above process (22) is repeated to generate the round constants corresponding to each round in all the optimized permutation functions F'.

[0075] In a specific implementation, the fixed bits A, B, C, and D in the above-mentioned round constant generation process remain unchanged.

[0076] (3) Permutation function execution phase: A register is set to store the input initial seed, and the initial seed is processed by an optimized permutation function F' implemented by a logic circuit and containing the round constants obtained in the round constant generation phase. The optimized permutation function F' includes 12 rounds of permutation operations, which greatly reduces the number of rounds to 12 compared to the traditional 24 rounds. After each 12 rounds of permutation operations are executed, a final random number with a length of 1600 bits is output as a secure pseudo-random number result.

[0077] like Figure 2 As shown, each round of permutation operation for optimizing the permutation function F' includes five steps performed sequentially in the logic circuit, namely, the Theta step, the Rho step, the Pi step, the Chi step and the Iota step. Each round of permutation operation includes the following steps: Theta step (θ): Diffusion of input information to ensure the relevance of global data.

[0078] Rho step (ρ): Circularly shift the bits to increase the obfuscation of the data.

[0079] Pi step (π): Rearrange the bits to further enhance the obfuscation effect.

[0080] Chi step (χ): performs nonlinear Boolean transformations, enhancing randomness.

[0081] Iota step (ι): Introduce dynamically generated round constants, XOR with specific bits in the state, to increase uniqueness and unpredictability. This step uses the round constants generated in the round constant generation phase.

[0082] In the specific implementation, the secure pseudo-random number generator and method are used to generate several random numbers per second. Since a total of 12 rounds of permutation functions need to be executed, and each round is independent of each other and contains five sub-steps, the scheme uses a pipeline method to decompose and parallelize these 12 rounds of operations, so that multiple rounds of operations can be performed simultaneously in the same clock cycle.

[0083] That is, the previous random number to be generated is processed in the first calculation module of the logic circuit, and the next random number to be generated is processed in the second calculation module of the logic circuit; the next random number to be generated enters the first calculation module after the second calculation module of the logic circuit completes the operation, and the second calculation module continues to process the next random number to be generated of the next random number to be generated.

[0084] (4) Replanting mechanism stage: By setting a time threshold or a generation quantity threshold, when the time reaches the time threshold or the generated random number reaches the generation quantity threshold, the original seed generated by the external input or the true random number generator TRNG, which the pseudo-random number generator relies on, is regularly updated through the timer / counter according to the time threshold or the generation quantity threshold, so as to ensure the security and unpredictability of the generated random number, that is, return to step (1) and then repeat steps (1) to (3) for loop processing, continuously update the output of the final random number, and ensure the randomness, continuity and security of the output of the final random number during long-term operation.

[0085] The solution of the present invention has been verified through specific implementation tests, and the final random number obtained has good quality. Compared with the random numbers obtained by other cumbersome methods, the random number quality is close to or higher.

[0086] Embodiments of the present invention are as follows: The main calculation process of the pseudo-random number generator (PRNG) of the present invention is as follows: Figure 1 As shown, Figure 1 In the above formula, r is called bitrate and c is called capacity, which are both specified parameters. r + c = 1600. In the present invention, r is selected as 576 and c is selected as 1024. c (capacity) determines the security of the algorithm. The larger c is, the stronger the anti-collision and anti-attack capabilities are. The security level of the SHA-3 algorithm is about c / 2.

[0087] The first step is to obtain an initial seed by externally inputting a 1600-bit original seed.

[0088] An original seed of 1600 bits is input from the outside and stored in a register or FIFO, which is recorded as x[1599:0]. 1599 and 0 represent the highest bit and the lowest bit, respectively, which are the leftmost bit and the rightmost bit of the binary number, respectively. [1599:0] represents the continuous bit structure from the lowest bit to the highest bit. Since r is selected as 576, this embodiment needs to select 576 bits from 1600 bits as input.

[0089] (11) First, an 11-bit first counter is used in combination with a multiplexer MUX to select 576 bits from the 1600-bit seed. The specific method is as follows: the initial value of the counter is 11'b 001 1111 1111, where 11'b is the hardware description source and 001 1111 1111 is the count value, which is 511. At this time, {x[511:0], x[1599:1536]}, a total of 576 bits, are selected as input, that is, 576 bits are selected from the current value of the counter in the low direction. If it is less than 576 bits, it is supplemented from the highest bit to form a total input of 576 bits.

[0090] In the above process, the value of the counter increases by 1 in each clock cycle. When the value of the counter is 11'b110 00111111, 110 0011 1111 is 1599. At this time, the value of the counter already corresponds to the highest bit of the 1600-bit original seed. If it continues to increase, it will cause an overflow. Therefore, in the next clock cycle, the value of the counter is reset to 11'b000 0000 0000, which corresponds to the lowest bit of the 1600-bit original seed.

[0091] (12) The XOR circuit in the padding and initial XOR module is used to perform an XOR operation on the 576 bits selected as input and 576 bits of 0. Then, the splicing logic circuit in the padding and initial XOR module is used to splice 1024 bits of 0 (corresponding to c is 1024) at the end to form a total of 1600 bits of input data, which is input into the optimized permutation function F'.

[0092] The second step is to generate round constants. The traditional SHA-3 algorithm usually performs 24 rounds of permutation functions, each round requires a 64-bit round constant, so a total of 24 64-bit round constants are required. These 24 round constants are directly specified by the algorithm and remain unchanged, so there are risks to security and randomness.

[0093] This embodiment pregenerates round constants based on the seed of the random number. The permutation function designed by the present invention has 12 rounds in total, so 12 round constants are required in total.

[0094] First, the first round constant is also selected from the 1600-bit seed through the same 11-bit counter in the first step. The specific method is that the initial value of the counter is 11'b001 1111 1111, which is 511. At this time, x[575:512], a total of 64 bits, is selected as the first round round constant, that is, 64 bits are selected from the current value of the counter plus 1 in the high-order direction. If it is less than 64 bits, it is supplemented from the lowest bit to form a total of 64 bits of the first round round constant, expressed as rc1[63:0]. The second round constant rc2 is generated by the first round constant rc1, and the third round constant rc3 is generated by the second round constant rc2, and so on.

[0095] The specific generation method is as follows Figure 3 As shown, taking rc1 to generate rc2 as an example, the nonlinear feedback shift register NLSFR is used to generate a dynamic round constant, which specifically includes two operations - shift (left shift) and XOR, that is, rc2[63:0] = {rc1[62:0], rc1

[63] ^ rc1

[60] ^ rc1

[52] ^ rc1

[45] }, where ^ represents the XOR operation, and, represents binary number concatenation.

[0096] It should be noted that the round constant generation of the present invention uses a nonlinear feedback shift register including two basic operations. The design of using left shift and selecting rc1

[63] , rc1

[60] , rc1

[52] , rc1

[45] for XOR operation is only a special case. However, in actual processing implementation, other operations that perform the same operation but have different shift directions or XOR bit selections should also be regarded as the same round constant generation method.

[0097] The third step is to perform 12 rounds of permutation function operations on the 1600-bit input data obtained in the first step to obtain the same 1600-bit random number output. The input and output of each round of permutation operation are both 1600 bits. The output of the first round of permutation function is used as the input of the second round of permutation function, and the output of the second round of permutation function is used as the input of the third round of permutation function, and so on. The number of inputs and outputs of each round of permutation operation is called the state number, and each bit is called the state bit value. For example, the input number of the first round of permutation operation is S0, the input number of the second round of permutation operation is S1, and so on.

[0098] The value of each bit of the initial input data is used as a state bit value and also as a cube; the state bit values ​​of each bit of the initial input data are distributed in a three-dimensional arrangement of multiple cubes along mutually orthogonal x, y, and z axes to form a three-dimensional arrangement structure data, that is, the cubes are closely arranged along the x, y, and z axes, and each cube represents bit data.

[0099] Specifically, first distribute on the xy plane where the x and y axes are located, and then expand along the z axis; when distributing on each xy plane, first distribute along the x axis where the x axis is located, and then expand along the y axis; when distributing on each x axis, first distribute along the x axis positive direction at the center of the x axis, and then distribute along the x axis negative direction. The x-axis and y-axis serial numbers are both symmetrically distributed with the center position as 0, and the z-axis serial numbers are sorted in sequence along the z axis direction.

[0100] According to a specific arrangement division method, the three-dimensional arrangement structure data is divided into three slices: horizontal slice plane, vertical slice slice, and longitudinal slice sheet, and three strips: horizontal strip row, vertical strip column, and vertical strip lane. Each slice is composed of the state bit values ​​corresponding to all cubes in a layer on the same plane, and each strip is composed of the state bit values ​​corresponding to a column of cubes on the same straight line.

[0101] The horizontal slice plane is composed of the state bit values ​​corresponding to all cubes located on the xz plane, the vertical slice slice is composed of the state bit values ​​corresponding to all cubes located on the xy plane, and the longitudinal slice sheet is composed of the state bit values ​​corresponding to all cubes located on the yz plane; the horizontal bar row is composed of the state bit values ​​corresponding to all cubes located on the x-axis line, the vertical bar column is composed of the state bit values ​​corresponding to all cubes located on the y-axis line, and the vertical bar lane is composed of the state bit values ​​corresponding to all cubes located on the z-axis line.

[0102] In the specific implementation, its 1600-bit solid geometry representation is as follows Figure 6 As shown in the figure, each cube represents 1 bit of data. According to the specific arrangement, the specific slices and strips are as follows Figure 7 shown.

[0103] The final random number is obtained after 12 rounds of permutation operations are performed continuously on the three-dimensional arrangement structure data.

[0104] In the specific implementation, each round of permutation function includes five operations, namely, Theta step (θ), Rho step (ρ), Pi step (π), Chi step (χ) and Iota step (ι). The five operations are performed sequentially, that is, the output of the Theta step (θ) is used as the input of the Rho step (ρ), the output of the Rho step (ρ) is used as the input of the Pi step (π), and so on.

[0105] In each round of permutation function: (31) Theta step is to process each state bit value in the three-dimensional arrangement data structure according to the following formula and assign a value to replace its own value: The Theta step processes and replaces each state bit value in the three-dimensional arrangement data structure according to the following formula: s'[x][y][z]=s[x][y][z]^∑ y'' s[x-1][y''][z] ^∑ y'' s[x+1][y''][z-1] y''=y+△y Wherein, s'[x][y][z] represents the state bit value of the coordinates (x, y, z) in the three-dimensional arrangement structure data after the Theta step, and s[x][y][z] represents the state bit value of the coordinates (x, y, z) in the three-dimensional arrangement structure data before the Theta step; y'' represents the y coordinate of the state bit values ​​of the two adjacent columns of the vertical bar column under the current calculated state bit value s[x][y][z] and its three-dimensional arrangement; ^ represents an exclusive-or operation, and △y represents a preset adjacent y coordinate step value; In a specific implementation, if x-1<0 or x+1>4, the actual situation may be to calculate (x-1)mod 5, where mod represents the modulo operation. For example, when x-1 is -1, (x-1)mod 5 = 4. The purpose of taking the modulo of the calculated coordinates is to ensure that they are always within the range of 0-4 and always meaningful.

[0106] (32) The Rho step is to process each state bit value in the three-dimensional arrangement data structure processed by the Theta step according to the following formula and assign a value to replace its own value: ρ:s''[x][y][z]=s'[x][y][z-(t+1)(t+2) / 2] Wherein, t represents an intermediate variable used to calculate the bit value offset; s''[x][y][z] represents the state bit value of the coordinates (x, y, z) in the three-dimensional arrangement structure data after the Rho step; The intermediate variable t satisfies: 0≤t≤24 and in GF(5) 2×2 or if x=y=0, t=-1 Among them, GF(5) 2×2 represents a 2×2 matrix space over the finite field GF(5), where all elements and operations are defined over the finite field GF(5), and in means belonging to; (33) The Pi step is to process each state bit value on the same vertical slice in the three-dimensional arrangement data structure processed by the Rho step according to the following formula and assign a value to replace its own value: π: p'[x][y]=p[x'][y']

[0107] Among them, p'[x][y] represents the state bit value of the coordinates (x, y) on the vertical slice slice located on the same xy plane in the three-dimensional arrangement structure data after processing in the Pi step, p[x][y] represents the state bit value of the coordinates (x, y) on the vertical slice slice located on the same xy plane in the three-dimensional arrangement structure data before processing in the Pi step, and x', y' represent the new horizontal and vertical position coordinates of the state bit value in the state matrix, that is, the target position after the state bit value is remapped from the original position (x, y).

[0108] (34) The Chi step is to process the state bit value of each bit in the same horizontal row in the three-dimensional arrangement data structure after the Pi step according to the following formula and assign a value to replace its own value: χ: q'[x]= q[x]^((q[x+1]^1)&q[x+2]) Among them, q'[x] represents the state bit value of coordinate x on the horizontal bar row located on the same x-axis line in the three-dimensional arrangement structure data after processing in the Chi step, and q'[x] represents the state bit value of coordinate x on the horizontal bar row located on the same x-axis line in the three-dimensional arrangement structure data before processing in the Chi step.

[0109] (35) The Iota step is to process the state bit value of each vertical lane located at the center of the three-dimensional arrangement data structure processed by the Chi step according to the following formula and assign a value to replace its own value: ι: I'[0][0][z]=I[0][0][z]^RC i Among them, i represents the number of rounds of permutation operation, RC i Represents the round constant of the current i-th round, where I'[0][0][z] represents the state bit value of the coordinate z on the centermost vertical lane in the three-dimensional arrangement structure data after the Iota step, and z is an even number, and I[0][0][z] represents the state bit value of the coordinate z on the centermost vertical lane in the three-dimensional arrangement structure data before the Iota step.

[0110] The Iota step operation is performed in lanes. In the prior art, when z is 0, 1, 3, 7, 15, 31, 63, s[0][0][z] and RC i [z] performs XOR operation. The round constant is 64 bits, but only 7 bits are actually XORed with the original data. This may result in limited state changes, reduce the entropy and unpredictability of random numbers, and affect the quality and security of pseudo-random numbers.

[0111] The present invention sets the ι operation of the Iota step to be equal to the round constant RC when z is an even number. i Perform an XOR operation on the value of the even bit z of I[0][0][z] and the round constant RC i The corresponding even-numbered bits z are XORed each time, so that each time the 32 bits in the round constant are XORed with the 32 bits of I[0][0][z], the round key is reused, which increases unpredictability and complexity and increases the randomness of the operation.

[0112] The above description is for the five permutation operations included in one round of permutation function. By performing 12 rounds of permutation operations, a 1600-bit random number will be output.

[0113] In the specific implementation process, in order to optimize the performance of the pseudo-random number generator modified based on SHA-3, a multi-stage pipeline design was adopted. Since the design contains 12 rounds of permutation functions, by introducing pipeline processing, multiple rounds of operations can be performed in one clock cycle, effectively improving throughput.

[0114] To evaluate the performance of different pipeline stages, comparative experiments were conducted with no pipeline, 2-stage, 3-stage, 4-stage, and 6-stage pipelines. The test results are shown in the figure. Figure 4 The experiment is based on the Verilog language and implemented on Vivado 2024.2 for AMD Virtex-7FPGA (VC709 Connectivity Kit). The throughput, LUT resource usage, and LUT / throughput ratio are compared.

[0115] from Figure 4 It can be seen that under the 3-stage pipeline design, 12 rounds of permutation functions can be efficiently executed in parallel, so that the generation of 1600-bit pseudo-random numbers only requires 4 clock cycles, which significantly improves the random number generation rate. At the same time, a good balance is achieved between throughput and resource consumption, so the present invention selects the 3-stage pipeline as the final implementation solution to achieve a better balance between performance and resource utilization.

[0116] It can be seen that this optimization solution can significantly improve throughput and reduce latency, while maintaining the integrity and security of the F' function and meeting the needs of high-performance application scenarios.

[0117] Table 1 design Board Technology Clock frequency Throughput On-chip resources (slices) Throughput / Frequency [1] ZY 28nm 138.3MHz 15.37Mbps 46573 0.11bit / circle [2] XC2VP30 90nm 373MHz 46.63Gbps 12556 125bit / circle [3] ZY 28nm 156.813MHz 19.60Gbps 10867 124.9bit / circle The present invention Virtex 7 28nm 200MHz 80Gbps 15341 400bit / circle After testing of a specific embodiment, in an FPGA operating environment, based on a clock frequency of 200 MHz, a throughput of up to 80 Gbps was achieved. As shown in Table 1, the comparison results of other research works show that the throughput of the present invention is significantly higher than that of other design schemes, and the hardware resource overhead is low, using a total of 15,341 slices.

[0118] [1][2][3] in Table 1 are from: [1] Yu F, Li L, He B, et al. Pseudorandom number generator based on a5D hyperchaotic four-wing memristive system and its FPGA implementation[J]. The European Physical Journal Special Topics, 2021, 230(7): 1763-1772. [2] Iyer N, Anandmohan PV, Poornaiah DV, et al. Efficient hardwarearchitectures for AES on FPGA[C] / / International Conference on ComputationalIntelligence and Information Technology. Berlin, Heidelberg: Springer BerlinHeidelberg, 2011: 249-257. [3] Gafsi M, Abbassi N, Amdouni R, et al. Hardware implementation of a strong pseudo-random numbers generator with an application to image encryption[C] / / 2022 IEEE 9th International Conference on Sciences of Electronics, Technologies of Information and Telecommunications (SETIT). IEEE, 2022: 510-515. It can be seen from this implementation that the present invention significantly improves hardware efficiency while ensuring randomness and security, and meets the demand for high-performance random number generation.

[0119] The above specific implementations are used to explain the present invention, rather than to limit the present invention. Any modifications and changes made to the present invention within the spirit of the present invention and the protection scope of the claims shall fall within the protection scope of the present invention. The above description is only a preferred implementation of the present invention, so any equivalent changes or modifications made according to the structure, features and principles described in the scope of the patent application of the present invention are included in the scope of the patent application of the present invention.

Claims

1. A secure pseudo-random number generator for high throughput in FPGA, characterized in that: The secure pseudo-random number generator is based on FPGA hardware and includes: An initial seed input module is used to input the original seed from the outside and pre-process it into an initial seed storage; A round constant generation module, used to pre-generate the round constants required by the permutation function module 12 rounds, and send them to the permutation function module; The permutation function module has an optimized permutation function F' containing a round constant, which is used to read the initial seed in the initial seed input module and store it, and then use the built-in optimized permutation function F' to perform 12 rounds of permutation operations on the initial seed to obtain the final random number output; The reseed mechanism module is used to periodically refresh the original seed to ensure randomness and security during long-term operation.

2. The secure pseudo-random number generator for FPGA high throughput according to claim 1, characterized in that: The initial seed input module includes: A register or FIFO to store the original seed; A bit selection module that reads the original seed stored in the register or FIFO and selects a portion of it; A filling and initial XOR module is used to perform XOR operation on a part of the number selected by the bit selection module and a number composed of multiple consecutive 0s with the same number of bits, and to concatenate the number composed of multiple consecutive 0s to form an initial seed.

3. The secure pseudo-random number generator for FPGA high throughput according to claim 2, characterized in that: The bit selection module comprises: a first counter for dynamically selecting bits in the original seed; a multiplexer for selecting a binary value of a specified portion of bits according to the first counter; The filling and initial XOR module includes an XOR circuit and a splicing logic circuit. The XOR circuit is used to perform an XOR operation on a part of a number with a number consisting of multiple consecutive 0s of the same number of bits. The splicing logic circuit is used to splice the number after the XOR operation of the XOR circuit with a number consisting of multiple consecutive 0s.

4. The secure pseudo-random number generator for FPGA high throughput according to claim 1, characterized in that: The round constant generation module comprises: a second counter for selecting a first round constant from an initial seed; A nonlinear feedback shift register is used to generate round constants for the next 11 rounds according to the round constants of the first round, and has built-in left shift operation and XOR operation.

5. The secure pseudo-random number generator for FPGA high throughput according to claim 1, characterized in that: The substitution function module includes a logic circuit for storing registers and for performing XOR, AND, NOT operations; the reseeding mechanism module uses a timer / counter to track a time threshold or a generation quantity threshold to control the update.

6. A method for generating secure pseudo-random numbers for FPGA with high throughput based on the secure pseudo-random number generator for FPGA with high throughput according to any one of claims 1 to 5, characterized in that: The method comprises: (1) Seed input stage: The original seed is stored in a register or FIFO, and after preprocessing by a bit selection module and a filling and initial XOR module, an initial seed is obtained as input data. The number of bits / bits of the original seed and the initial seed are the same and both are binary numbers; (2) Round constant generation stage: According to the initial seed, a nonlinear feedback shift register NLSFR is used to pre-generate round constants for the permutation function execution phase; (3) Permutation function execution phase: A register is set to store an input initial seed, and an optimized permutation function F' implemented by a logic circuit and containing a round constant is used to process the initial seed. The optimized permutation function F' includes 12 rounds of permutation operations. After each 12 rounds of permutation operations are performed, a final random number is output as a result; (4) Replanting mechanism stage: By setting a time threshold or a generation quantity threshold, the original seed is refreshed periodically through a timer / counter according to the time threshold or the generation quantity threshold, and the process returns to step (1) and then repeats steps (1) to (3) for a loop process, thereby continuously updating the output of the final random number.

7. The method for generating secure pseudo-random numbers for FPGA with high throughput according to claim 6, characterized in that: The step (1) is specifically as follows: first, a counter of a bit selection module is used to select a number of consecutive bits on the low-order side and the high-order side from the original seed stored in the register or FIFO to form a preliminary binary number, and then a filling and initial XOR module is used to perform an XOR operation on a binary number consisting of consecutive 0s with the same number of bits as the preliminary binary number, and then the consecutive 0s are concatenated at the end to form a binary number with the same number of bits as the original seed as the initial seed, which is then input into the optimized permutation function F'.

8. The method for generating secure pseudo-random numbers for FPGA with high throughput according to claim 6, characterized in that: The step (2) is specifically as follows: (21) First, a counter is used to select a preset binary number of several digits from the initial seed as the round constant rc1 for optimizing the first round of the permutation function F'; (22) Then the round constant rc of the nth round is n Use the nonlinear feedback shift register NLSFR to dynamically generate the next round of round constants rc n+1 , expressed as: rc n+1 [K-1:0] = {rc n [K-2:0], rc n [A]^rc n [B]^rc n [C]^rc n [D]} Among them, ^ represents the XOR operation, rc n [62:0] represents the round constant rc n From the lowest bit 0 to the 62nd bit; K represents the total number of bits of each round constant, A, B, C, D represent four pre-set fixed bits, rc n [A], rc n [B] rc n [C] , rc n [D] represents the wheel constant rc n The values ​​at the fixed positions A, B, C, D; (23) Finally, the above process (22) is repeated to generate the round constants corresponding to each round in all the optimized permutation functions F'.

9. The method for generating secure pseudo-random numbers for FPGA with high throughput according to claim 6, characterized in that: The round constant in the i-th round permutation operation of the optimized permutation function F' corresponds to the i-th round constant obtained in step (2).

10. The method for generating secure pseudo-random numbers for FPGA with high throughput according to claim 6, characterized in that: Each round of permutation operation of the optimized permutation function F' includes five steps performed sequentially in the logic circuit, the five steps are respectively a Theta step, a Rho step, a Pi step, a Chi step and an Iota step; First, the Theta step is performed to calculate the even parity of each column of the input binary data and perform an XOR operation on each bit; Then, the Rho step is performed to perform a cyclic shift on each bit according to a predefined offset; Then the Pi step is performed to rearrange the bits on the same face; Next, the Chi step is performed to process the bits on the same line through nonlinear Boolean transformation; Finally, the Iota step is performed to perform an even XOR operation on the round constant and the specific bit.

11. The method for generating secure pseudo-random numbers for FPGA with high throughput according to claim 6, characterized in that: The value of each bit of the initial seed is used as a state bit value, and the state bit values ​​of each bit of the initial seed are distributed in a three-dimensional arrangement of multiple cubes along the three axes of x, y, and z to form three-dimensional arrangement structure data; the three-dimensional arrangement structure data is divided into three types of slices, namely, horizontal slices plane, vertical slices slice, and longitudinal slices sheet, and three types of strips, namely, horizontal strips row, vertical strips column, and vertical strips lane, each slice is composed of state bit values ​​corresponding to all cubes in a layer on the same plane, and each strip is composed of state bit values ​​corresponding to a column of cubes on the same straight line; the final random number is obtained after 12 rounds of permutation operations are performed continuously and sequentially on the three-dimensional arrangement structure data.

12. The method for generating secure pseudo-random numbers for FPGA with high throughput according to claim 6, characterized in that: In each round of permutation operation: The Theta step processes and replaces each state bit value in the three-dimensional arrangement data structure according to the following formula: s'[x][y][z]=s[x][y][z] ^∑ y'' s[x-1][y''][z] ^∑ y'' s[x+1][y''][z-1] y''=y+△y Wherein, s'[x][y][z] represents the state bit value of the coordinates (x, y, z) in the three-dimensional arrangement structure data after the Theta step, and s[x][y][z] represents the state bit value of the coordinates (x, y, z) in the three-dimensional arrangement structure data before the Theta step; y'' represents the y coordinate of the state bit values ​​of the two adjacent columns of the vertical bar column under the current calculated state bit value s[x][y][z] and its three-dimensional arrangement; ^ represents an exclusive-or operation, and △y represents the step value of the adjacent y coordinates; The Rho step processes and replaces each state bit value in the three-dimensional arrangement data structure processed by the Theta step according to the following formula: s''[x][y][z]=s'[x][y][z-(t+1)(t+2) / 2] Wherein, t represents an intermediate variable used to calculate the bit value offset; s''[x][y][z] represents the state bit value of the coordinates (x, y, z) in the three-dimensional arrangement structure data after the Rho step; The Pi step is to process and replace each state bit value located on the same vertical slice in the three-dimensional arrangement data structure processed by the Rho step according to the following formula: p'[x][y]=p[x'][y'] Wherein, p'[x][y] represents the state bit value of the coordinates (x, y) on the vertical slice slice located on the same xy plane in the three-dimensional arrangement structure data after the Pi step processing, p[x][y] represents the state bit value of the coordinates (x, y) on the vertical slice slice located on the same xy plane in the three-dimensional arrangement structure data before the Pi step processing, and x', y' represent the new horizontal and vertical position coordinates of the state bit value in the state matrix; The Chi step is to process and replace the state bit value of each bit located in the same horizontal row in the three-dimensional arrangement data structure processed by the Pi step according to the following formula: q'[x]= q[x]^((q[x+1]^1)&q[x+2]) Wherein, q'[x] represents the state bit value of the coordinate x on the horizontal bar row located on the same x-axis line in the three-dimensional arrangement structure data after the Chi step processing, q'[x] represents the state bit value of the coordinate x on the horizontal bar row located on the same x-axis line in the three-dimensional arrangement structure data before the Chi step processing, ^ represents an exclusive-or operation, and & represents an and operation; The Iota step is to process and replace the state bit value of each vertical lane located at the center of the three-dimensional arrangement data structure processed by the Chi step according to the following formula: I'[0][0][z]=I[0][0][z]^RC i Among them, i represents the number of rounds of permutation operation, RC i Represents the round constant of the current i-th round, where I'[0][0][z] represents the state bit value of the coordinate z on the centermost vertical lane in the three-dimensional arrangement structure data after the Iota step, and z is an even number, and I[0][0][z] represents the state bit value of the coordinate z on the centermost vertical lane in the three-dimensional arrangement structure data before the Iota step.

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