Memory Management Method and Memory Controller

Abstract

The present disclosure provides a memory management method and its controller. The method includes: obtaining mapping table data to be stored; determining the size of an array storage group according to the total number of multiple chip enable pins, where the array storage group includes multiple physical pages corresponding to a number of chip enable pins less than the total number; setting multiple array storage groups arranged consecutively based on the word line order, chip enable pin order, and plane order; and storing the mapping table data into the multiple array storage groups, where the check pages of two adjacent array storage groups correspond to different chip enable pins. Through the technical solution of the present disclosure, the storage distribution uniformity of the mapping table data can be improved, the parallel efficiency of data reading can be ensured, and the reliability of data protection can be maintained at the same time.

Description

Technical Field

[0001] The present disclosure relates to the field of storage technologies, and in particular, to a memory management method and a controller for a storage device configured with a rewritable non-volatile memory module. Background Art

[0002] In modern storage technologies, rewritable non-volatile memories (NAND Flash) have been widely used in storage devices such as solid state drives (SSDs).

[0003] In the existing solid state drive architecture, the mapping table is responsible for mapping logical addresses to physical addresses to locate the correct data storage location. The correctness of the mapping table is crucial for data reading of the solid state drive. To enhance the protection ability of the mapping table, in addition to LDPC (Low Density Parity Check) protection, a redundant array of independent disks error checking and correcting code (RAID ECC) mechanism is also required. This mechanism dispersedly stores the mapping table data in multiple channels and stores the parity code encoded by ECC in the last plane corresponding to the last channel. However, this method will centrally store the parity code in the last plane of the last channel. When writing mapping table data, if a power failure occurs, dummy pages will be supplemented before the last plane of the last channel, resulting in the effective data being stored only in the chips corresponding to the previous channels, thereby affecting the reading speed of the mapping table data. Summary of the Invention

[0004] Aiming at the problem in the prior art that the parity code of the mapping table data is centrally stored in the last plane of the last channel, resulting in the need to supplement dummy pages during a power failure and affecting the data reading speed, the present disclosure provides a memory management method and a controller. By optimizing the storage distribution strategy of the mapping table data, the parity pages can be evenly distributed among different chip enable pins, thereby improving the reading efficiency of the mapping table data while ensuring the data protection ability.

[0005] One or more embodiments of the present disclosure provide a memory management method applicable to a storage device configured with a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of chips, and each of the plurality of chips corresponds to a chip enable pin. Each chip includes P planes. The method includes: obtaining mapping table data to be stored; determining the size of an array storage group according to the total number N of the plurality of chip enable pins, where the array storage group includes a plurality of physical pages corresponding to M chip enable pins, where M is less than N and greater than 1, and M is equal to N minus a predetermined value; setting a plurality of consecutively arranged array storage groups based on the word line order, the chip enable pin order, and the plane order, where the plurality of physical pages of each array storage group respectively correspond to different planes of the M chip enable pins; and storing the mapping table data in the plurality of array storage groups, where the plurality of physical pages of each array storage group include a plurality of data pages and a parity page, where the plurality of data pages are used to store partial mapping table data corresponding to the array storage group, and the parity page is used to store parity data corresponding to the partial mapping table data, where the parity pages of two adjacent array storage groups respectively correspond to different chip enable pins.

[0006] In one or more embodiments of the present disclosure, the step of setting the plurality of consecutively arranged array storage groups based on the word line order, the chip enable pin order, and the plane order includes: selecting a first array storage group to be set according to the serial number order of the plurality of array storage groups; selecting an available first word line based on the word line order; selecting one or more available first chip enable pins from the plurality of chip enable pins corresponding to the first word line based on the chip enable pin order; if the number of the one or more first chip enable pins is equal to M: obtaining a plurality of first physical pages corresponding to the plurality of planes in each first chip enable pin; and setting the plurality of first physical pages as the plurality of physical pages of the first array storage group.

[0007] In one or more embodiments of the present disclosure, the step of setting the plurality of array storage groups arranged in succession based on the string line order, the chip enable pin order, and the plane order further includes: if the number of one or more first chip enable pins selected in the first string line is less than M: selecting an available second string line after the first string line; based on the chip enable pin order, selecting one or more available second chip enable pins from the plurality of chip enable pins corresponding to the second string line, wherein the total number of the one or more first chip enable pins and the one or more second chip enable pins is M; obtaining a plurality of first physical pages corresponding to the plurality of planes in each first chip enable pin, and obtaining a plurality of second physical pages corresponding to the plurality of planes in each second chip enable pin; and setting the plurality of first physical pages and the plurality of second physical pages as the plurality of physical pages of the first array storage group.

[0008] In one or more embodiments of the present disclosure, the parity page of each array storage group is the last one of the plurality of physical pages of the array storage group.

[0009] In one or more embodiments of the present disclosure, if N is an even number, there is a remainder when M is used as a divisor of N.

[0010] In one or more embodiments of the present disclosure, the predetermined value is 1.

[0011] In one or more embodiments of the present disclosure, the chip enable pin following the last chip enable pin of the i-th string line is the first chip enable pin of the (i + 1)-th string line, wherein the plurality of physical pages of each array storage group correspond to the plurality of chip enable pins of the same string line or the plurality of chip enable pins of adjacent string lines, and each string line includes N P physical pages.

[0012] In one or more embodiments of the present disclosure, the method further includes: if a target chip fails, reconstructing target partial mapping table data stored in the target chip according to the partial mapping table data stored in other chips except the target chip and the corresponding parity data.

[0013] In one or more embodiments of the present disclosure, the plane order is the order from the 0-th plane to the (P - 1)-th plane within the same chip enable pin.

[0014] One or more embodiments of the present disclosure provide a memory controller for controlling a storage device configured with a rewritable non-volatile memory module. The memory controller includes: a memory interface control circuit for electrically connecting to the rewritable non-volatile memory module, the rewritable non-volatile memory module including a plurality of chips, each of the plurality of chips corresponding to a chip enable pin, and each chip including P planes; and a processor electrically connected to the memory interface control circuit, wherein the processor is further electrically connected to a connection interface circuit of the storage device to electrically connect to a host system. Wherein, the processor is configured to: acquire mapping table data to be stored; determine the size of an array storage group according to the total number N of chip enable pins, wherein the array storage group includes a plurality of physical pages corresponding to M chip enable pins, where M is less than N and greater than 1, and M is equal to N minus a predetermined value; set a plurality of successively arranged array storage groups based on the word line order, the chip enable pin order, and the plane order, wherein the plurality of physical pages of each array storage group respectively correspond to different planes of the M chip enable pins; and store the mapping table data into the plurality of array storage groups, wherein the plurality of physical pages of each array storage group include a plurality of data pages and a parity page, wherein the plurality of data pages are used to store partial mapping table data corresponding to the array storage group, and the parity page is used to store parity data corresponding to the partial mapping table data, wherein the parity pages of two adjacent array storage groups respectively correspond to different chip enable pins.

[0015] Based on the above, the memory management method and its controller provided by the present disclosure optimize the size setting and distribution method of the array storage group, so that the mapping table data and its parity page can be evenly distributed among different chip enable pins, effectively avoiding the problem of concentrated data storage. At the same time, on the premise of maintaining the data protection strength, this method can ensure the parallel reading efficiency of the mapping table data even in the case of power failure, thereby improving the overall performance of the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings are included to provide a further understanding of the present invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and, together with the description, serve to explain the principles of the present invention.

[0017] Figure 1 A block diagram of a host system and a storage device shown according to an embodiment of the present invention;

[0018] Figure 2 A flowchart of a memory management method shown according to an embodiment of the present disclosure;

[0019] Figure 3Schematic diagram of setting an array storage group via a traditional method;

[0020] Figure 4 Schematic diagram of setting an array storage group via the provided memory management method as shown in an embodiment of the present disclosure.

[0021] Explanation of reference numerals in the accompanying drawings

[0022] 10: Host system

[0023] 20: Storage device

[0024] 110: Processor (second processor)

[0025] 120: Host memory

[0026] 130: Data transmission interface circuit

[0027] 210: Memory controller

[0028] 211: Processor (first processor)

[0029] 212: Data management circuit

[0030] 213: Memory interface control circuit

[0031] 214: Buffer memory

[0032] 220: Rewritable non-volatile memory module

[0033] 230: Connection interface circuit

[0034] S210 - S240: Steps

[0035] CE0 - CE3: Chip enable pins

[0036] PL0, PL1: Planes

[0037] PG000 - PG231: Physical pages

[0038] SG0 - SG2: String lines

[0039] REG01 - REG03, REG11 - REG14: Array storage groups Detailed implementation manners

[0040] Reference will now be made in detail to the exemplary embodiments of the present invention, examples of the exemplary embodiments are illustrated in the accompanying drawings. Whenever possible, the same component symbols are used in the drawings and the description to represent the same or similar parts.

[0041] Figure 1A block diagram of a host system and a storage device according to an embodiment of the present invention is shown. Please refer to Figure 1 , the host system 10 is, for example, a personal computer, a notebook computer, or a server. The host system 10 includes a processor 110 (also referred to as a second processor), a host memory 120, and a data transfer interface circuit 130. In this embodiment, the processor 110 is coupled (also referred to as electrically connected) to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 are electrically connected to each other by a system bus. In this embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 may be disposed on the motherboard of the host system 10.

[0042] The storage device 20 includes a memory controller 210, a rewritable non-volatile memory module 220, a connection interface circuit 230, and a random access memory 240. Among them, the memory controller 210 includes a processor 211 (also referred to as a first processor), a data management circuit 212, and a memory interface control circuit 213.

[0043] In this embodiment, the host system 10 accesses data by being electrically connected to the storage device 20 through the connection interface circuit 230 of the data transfer interface circuit 130 of the storage device 20. For example, the host system 10 can store data in the storage device 20 or read data from the storage device 20 via the data transfer interface circuit 130.

[0044] In this embodiment, the number of data transfer interface circuits 130 may be one or more. Through the data transfer interface circuit 130, the motherboard can be electrically connected to the storage device 20 via a wired or wireless manner. The storage device 20 may be, for example, a USB flash drive, a memory card, a solid state drive (SSD), or a wireless memory storage device. The wireless memory storage device may be, for example, a near field communication (NFC) memory storage device, a wireless fidelity (WiFi) memory storage device, a Bluetooth memory storage device, or a low energy Bluetooth memory storage device (e.g., iBeacon), etc., which are memory storage devices based on various wireless communication technologies. In addition, the motherboard can also be electrically connected to various I / O devices such as a global positioning system (GPS) module, a network interface card, a wireless transmission device, a keyboard, a screen, a speaker, etc. via a system bus.

[0045] In this embodiment, the data transfer interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the peripheral component interconnect express (PCI Express) standard. Moreover, data is transferred between the data transfer interface circuit 130 and the connection interface circuit 230 by using the non-volatile memory express (NVMe) communication protocol.

[0046] In addition, in another embodiment, the connection interface circuit 230 may be encapsulated in a chip with the memory controller 210, or the connection interface circuit 230 is disposed outside a chip including the memory controller 210.

[0047] In this embodiment, the host memory 120 is used to temporarily store the instructions or data executed by the processor 110. For example, in this embodiment, the host memory 120 and the random access memory 240 may be a dynamic random access memory (DRAM), a static random access memory (SRAM), etc. However, it must be understood that the present invention is not limited thereto, and the host memory 120 and the random access memory 240 may also be other suitable memories.

[0048] The memory controller 210 is configured to execute multiple logic gates or control instructions implemented in the form of hardware or firmware, and perform operations such as writing, reading, and erasing data in the rewritable non-volatile memory module 220 according to the instructions of the host system 10.

[0049] More specifically, the processor 211 in the memory controller 210 is hardware with computing capabilities, which is used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed by multiple control instructions / program codes, and when the storage device 20 operates, these control instructions / program codes will be executed to perform operations such as writing, reading, and erasing data. In addition, in this embodiment, the control instructions / program codes can be further executed to perform specific garbage collection operations to implement the memory management method for different working states of the storage device provided by the present invention. The control instructions / program codes corresponding to the memory management method can be further implemented as circuit units in the form of hardware to implement the memory management method provided by the present invention.

[0050] It is worth mentioning that, in this embodiment, the processor 110 and the processor 211 are, for example, a Central Processing Unit (CPU), a micro-processor, or other programmable processing units (Microprocessor), a Digital Signal Processor (DSP), a programmable controller, an Application Specific Integrated Circuits (ASIC), a Programmable Logic Device (PLD), or other similar circuit components. The present invention is not limited thereto.

[0051] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by each component of the memory controller 210 can also be regarded as the operations performed by the memory controller 210.

[0052] Among them, the data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213, and the connection interface circuit 230. The data management circuit 212 is used to accept the instructions of the processor 211 to perform data transmission. For example, read data from the host system 10 (such as the host memory 120) via the connection interface circuit 230, and write the read data into the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (such as performing a write operation according to a write instruction from the host system 10). Another example is to read data from one or more physical units of the rewritable non-volatile memory module 220 (the data can be read from one or more storage units in one or more physical units), and write the read data into the host system 10 (such as the host memory 120) via the connection interface circuit 230 (such as performing a read operation according to a read instruction from the host system 10). In another embodiment, the data management circuit 212 can also be integrated into the processor 211.

[0053] The memory interface control circuit 213 is used to accept the instructions of the processor 211 and cooperate with the data management circuit 212 to perform write (also known as programming), read, or erase operations on the rewritable non-volatile memory module 220.

[0054] In one embodiment, the memory interface control circuit 213 includes a plurality of chip enable pin control circuits. These chip enable pin control circuits respectively correspond to the chip enable pins (Chip Enable pin, also abbreviated as CE) of a plurality of chips in the rewritable non-volatile memory module 220, and are used to control the enabling and disabling of the corresponding chips. In this way, the memory interface control circuit 213 can achieve selective access to different chips.

[0055] In addition, the data to be written into the rewritable non-volatile memory module 220 will be converted into a format acceptable to the rewritable non-volatile memory module 220 via the memory interface control circuit 213. Specifically, if the processor 211 wants to access the rewritable non-volatile memory module 220, the processor 211 will send a corresponding instruction sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform the corresponding operation. For example, these instruction sequences can include a write instruction sequence for indicating writing data, a read instruction sequence for indicating reading data, an erase instruction sequence for indicating erasing data, and corresponding instruction sequences for indicating various memory operations. These instruction sequences can include one or more signals, or data on the bus. These signals or data can include instruction codes or program codes. For example, in the read instruction sequence, information such as a read identification code, a memory address, and a physical address will be included.

[0056] In addition, the memory controller 210 establishes a logical-to-physical address mapping table and a physical-to-logical address mapping table to record the mapping relationship between the logical addresses of logical units (e.g., logical blocks, logical pages) allocated to the rewritable non-volatile memory module 220 and the physical addresses (physical addresses) of physical units (e.g., physical erase units / physical blocks, physical pages). In other words, the memory controller 210 can look up the physical unit mapped by a logical unit (e.g., look up the physical page mapped by a logical page; look up the physical address mapped by a logical address) through the logical-to-physical address mapping table (also referred to as the logical-to-physical mapping table), and the memory controller 210 can look up the logical unit mapped by a physical unit (e.g., look up the logical page mapped by a physical page; look up the logical address mapped by a physical address) through the physical-to-logical address mapping table (also referred to as the physical-to-logical mapping table).

[0057] In one embodiment, the memory controller 210 further includes a buffer memory 214. The buffer memory 214 is electrically connected to the processor 211 for temporarily storing data and instructions from the host system 10, data from the rewritable non-volatile memory module 220, or other system data for managing the storage device 20. In addition, the buffer memory 214 can also be used to store various mapping tables (e.g., the logical-to-physical address mapping table and the physical-to-logical address mapping table) so that the processor 211 can quickly access the data, instructions, or system data from the buffer memory 214.

[0058] In one embodiment, to ensure the reliability of the mapping table data, before the memory controller 210 writes the mapping table data to the rewritable non-volatile memory module 220, the memory controller 210 performs a redundant array of independent disks error checking and correcting code (RAID ECC) protection mechanism on the mapping table data. Specifically, the memory controller 210 generates corresponding check pages based on the mapping table data and distributes and stores the mapping table data and the check pages in different chips of the rewritable non-volatile memory module 220. In this way, even if a certain chip fails, the memory controller 210 can still reconstruct the mapping table data stored in the failed chip according to the mapping table data and the corresponding check pages stored in other chips.

[0059] In one embodiment, the buffer memory 214 is divided into multiple cache regions, including a mapping table cache region dedicated to temporarily storing mapping table data to be encoded and a parity data cache region for temporarily storing encoded parity data. This regional division helps improve the processing efficiency of the mapping table data.

[0060] The rewritable non-volatile memory module 220 is electrically connected to the memory controller 210 (memory interface control circuit 213) and is used to store user data sent by the host system 10.

[0061] In this embodiment, each memory die (chip) in the multiple memory dies of the rewritable non-volatile memory module 220 has multiple planes (for example, each chip enable pin corresponds to P planes), and each plane has multiple physical blocks. Each physical block includes multiple physical programming units (also called physical pages). Each physical page has multiple memory cells (also called physical bytes or bytes), and each memory cell corresponds to a physical address. The physical address is used to record the physical location of the data stored in the memory cell. It should be noted that the present invention is not limited to the size of each physical page and logical page.

[0062] Figure 2 It is a flowchart of a memory management method shown according to an embodiment of the present disclosure.

[0063] Refer to Figure 2 , in step S210, the memory controller 210 obtains the mapping table data to be stored. Specifically, the memory controller 210 can obtain the mapping table data to be stored from the buffer memory 214. The mapping table data includes a logical-to-physical address mapping table and a physical-to-logical address mapping table. However, this memory management method can also be applied to other types of mapping tables or various system data that need to be properly protected.

[0064] Next, in step S220, the memory controller 210 determines the size of the array storage group according to the total number N of multiple chip enable pins (CE). The array storage group includes multiple physical pages corresponding to M chip enable pins, where M is less than N and greater than 1, and M is equal to N minus a predetermined value. In one embodiment, the predetermined value can be set according to requirements, for example, 1. The setting of this predetermined value is to enable multiple continuously arranged array storage groups to be staggered so that the parity pages of adjacent array storage groups do not belong to the same chip enable pin.

[0065] It should be noted that in order to enable multiple consecutively arranged array storage groups to be interleaved, when the total number N of chip enable pins (CE) is even, there is a remainder when the number of M chip enable pins corresponding to the array storage group is used as a divisor of N, that is, N cannot be divided evenly by M, so as to make the array storage groups as interleaved as possible.

[0066] In step S230, the memory controller 210 sets a plurality of consecutively arranged array storage groups based on the word line order, the chip enable pin order, and the plane order. The memory controller 210 makes the plurality of physical pages of each array storage group respectively correspond to different planes of the M chip enable pins. The plane order is the order from the 0th plane to the (P - 1)th plane within the same chip enable pin.

[0067] For example, in one embodiment, the memory controller 210 sets a plurality of consecutively arranged array storage groups based on the word line order, the chip enable pin order, and the plane order. Specifically, the memory controller 210 first selects the first array storage group to be set according to the serial number order of the plurality of array storage groups. Such a serial number order can ensure the orderly progress of the setting process of the array storage groups.

[0068] In another embodiment, the memory controller 210 selects an available first word line from the rewritable non-volatile memory module 220 based on the word line order. Subsequently, the memory controller 210 selects one or more available first chip enable pins from the plurality of chip enable pins corresponding to the first word line based on the chip enable pin order. Among them, the chip enable pin order can be the order from the smaller number to the larger number.

[0069] In another embodiment, when the memory controller 210 detects that the number of the selected one or more first chip enable pins is equal to M, the memory controller 210 performs the following operations: First, the memory controller 210 obtains a plurality of first physical pages corresponding to the plurality of planes in each first chip enable pin. Then, the memory controller 210 sets the plurality of first physical pages as the plurality of physical pages of the first array storage group. In this way, the memory controller 210 can complete the setting of the array storage group within a single word line.

[0070] In another embodiment, if the memory controller 210 detects that the number of one or more first chip enable pins selected in the first string line is less than M (for example, the corresponding remaining space of the current first string line cannot set a complete array storage group), the memory controller 210 will perform the following steps: First, the memory controller 210 selects an available second string line sorted after the first string line (obtaining other spaces from the next string line to make up for the insufficient space of the first string line). Then, the memory controller 210 selects one or more available second chip enable pins from the multiple chip enable pins corresponding to the second string line based on the chip enable pin order. Among them, the memory controller 210 ensures that the total number of the one or more first chip enable pins and the one or more second chip enable pins is M.

[0071] Next, the memory controller 210 will obtain multiple first physical pages corresponding to the multiple planes in each first chip enable pin, and at the same time obtain multiple second physical pages corresponding to the multiple planes in each second chip enable pin. Finally, the memory controller 210 sets the multiple first physical pages and the multiple second physical pages as the multiple physical pages of the first array storage group. In this way, the memory controller 210 can complete the setting of the array storage group within the range of spanning adjacent string lines.

[0072] Through the above embodiments, the memory management method provided by the present disclosure can flexibly set the array storage group within a single string line or within the range of spanning adjacent string lines according to the actual situation.

[0073] In step S240, the memory controller 210 stores the mapping table data into the multiple array storage groups. Specifically, the multiple physical pages of each array storage group include multiple data pages and a parity page, where the multiple data pages are used to store partial mapping table data corresponding to the array storage group, and the parity page is used to store parity data corresponding to the partial mapping table data. It should be noted that the parity pages of two adjacent array storage groups correspond to different chip enable pins.

[0074] Through the memory management method of the present disclosure, uniform distributed storage of the mapping table data can be achieved, effectively avoiding the problem of reduced reading efficiency that may be caused by centralized storage of parity pages in the traditional method.

[0075] In one embodiment, the process by which the memory controller 210 generates parity data for the mapping table data is as follows.

[0076] Specifically, the memory controller 210 first divides the partial mapping table data to be stored into multiple data units. Then, based on the error correction code algorithm of redundant array of independent disks, the memory controller 210 performs exclusive OR (XOR) operations on these data units to generate corresponding parity data. Among them, the size of the parity data is the same as that of a single data unit, and the parity data contains redundant information for recovering the partial mapping table data.

[0077] In another embodiment, before writing the generated parity data into the parity page, the memory controller 210 first performs encoding processing on the parity data. Specifically, the memory controller 210 uses error correction code encoding technology, such as Low Density Parity Check (LDPC), to encode the parity data to improve the reliability of the parity data itself. Through this dual protection mechanism, even if part of the parity data itself is incorrect, the memory controller 210 can still recover the correct parity data through the error correction code, thereby ensuring the reliability of the mapping table data.

[0078] Figure 3 Schematic diagram for setting an array storage group via a traditional method. In one embodiment, please refer to Figure 3 , which shows a traditional array storage group setting method.

[0079] In this embodiment, the configuration of the array storage group by the memory controller 210 has the following characteristics: the total number of chip enable pins is 4 (N = 4), and each array storage group corresponds to 4 chip enable pins (M = 4 = N).

[0080] Specifically, each string line (e.g., SG0, SG1, SG2) contains 4 chip enable pins (CE0, CE1, CE2, CE3), and each chip enable pin corresponds to 2 planes (PL0, PL1). The memory controller 210 fixedly sets the parity page of each array storage group (e.g., REG01, REG02, REG03) in the physical page of the last chip enable pin CE3. For example, in the string line SG0, the parity page of the array storage group REG01 is set in the physical page PG031 of the chip enable pin CE3.

[0081] In another embodiment, when adopting this traditional method, the memory controller 210 sets the array storage groups in the following order: First, in the string line SG0, the memory controller 210 sets the physical pages corresponding to the chip enable pins CE0 to CE2 (from physical page PG000 to PG021, also known as data pages) as the data pages of the array storage group REG01, and sets the physical page PG031 corresponding to the chip enable pin CE3 as the parity page of the array storage group REG01. Then, in the string line SG1, the memory controller 210 sets the array storage group REG02 in the same way, and so on.

[0082] However, this traditional setting method has the following technical defects:

[0083] In one embodiment, since the parity page is always fixed in the last chip enable pin CE3, when an abnormal situation such as power failure occurs, the memory controller 210 needs to supplement virtual pages at positions before the chip enable pin CE3. This results in the effective mapping table data being concentrated in the previous chip enable pins (such as CE0, CE1), while the subsequent chip enable pins (such as CE2, CE3) mainly store virtual pages or parity pages.

[0084] In another embodiment, this unbalanced data distribution will cause a significant reduction in the reading efficiency. Because when the memory controller 210 needs to read the mapping table data, it cannot make full use of the parallel reading capabilities of multiple chip enable pins, but is forced to concentrate a large number of reading operations on a few of the previous chip enable pins, resulting in a reading performance bottleneck.

[0085] These technical defects highlight the limitations of the traditional array storage group setting method in practical applications and also illustrate the necessity of developing new storage management methods.

[0086] Figure 4 Schematic diagram for setting an array storage group via the provided memory management method as shown in an embodiment according to the present disclosure. In one embodiment, please refer to Figure 4 , which shows an improved array storage group configuration method provided by the present disclosure.

[0087] In this embodiment, the memory controller 210 adopts an innovative configuration strategy: the total number of chip enable pins is 4 (N = 4), but each array storage group corresponds to only 3 (N minus a predetermined value of 1) chip enable pins ( ).

[0088] For example, the configuration method of the memory controller 210 for the array storage groups REG11 to REG14 is specifically as follows:

[0089] The configuration method of the array storage group REG11 is as follows: The memory controller 210 sets the physical pages (from PG000 to PG021) corresponding to the chip enable pins CE0, CE1, and CE2 in the string line SG0 as components of the array storage group REG11, where the physical page PG021 is set as the parity page.

[0090] In one embodiment, when the memory controller 210 configures the distribution of physical pages of the array storage group, it can adopt two methods: The first method is to correspond all the physical pages of the array storage group to multiple chip enable pins of the same string line; The second method is to allocate the physical pages of the array storage group to multiple chip enable pins of adjacent string lines. The memory controller 210 can select an appropriate method to configure the array storage group according to the actual storage situation.

[0091] Specifically, the memory controller 210 will consider the storage capacity of each string line. Since each chip enable pin corresponds to P planes and there are N chip enable pins on the string line, each string line includes N ×P physical pages. For example, when N is 4 and P is 2, each string line can contain 8 physical pages. The memory controller 210 will plan the distribution of the array storage group based on this fixed storage capacity to ensure that the allocation of physical pages does not exceed the capacity limit of the string line.

[0092] Returning to the configuration of the array storage group REG12, the configuration method of the array storage group REG12 is as follows: The memory controller 210 spans the string lines SG0 and SG1, and sets the physical pages (from PG030 to PG111) corresponding to the chip enable pin CE3 in the string line SG0 and the chip enable pins CE0 and CE1 in the string line SG1 as components of the array storage group REG12, where the physical page PG111 is set as the parity page.

[0093] More specifically, when the memory controller 210 sets the array storage group REG12, it performs the following detailed steps:

[0094] First, after completing the setting of REG11, the memory controller 210 selects the array storage group REG12 as the array storage group to be set according to the sequence number order of the array storage groups. Then, the memory controller 210 selects the available string line SG0 as the first string line based on the string line order.

[0095] Then, based on the chip enable pin sequence, the memory controller 210 selects from among the multiple chip enable pins corresponding to the string line SG0. Since the chip enable pins CE0, CE1, and CE2 have been occupied by the array storage group REG11, the memory controller 210 can only select the chip enable pin CE3 as the first chip enable pin. At this time, the memory controller 210 detects that the number of the first chip enable pins selected in the string line SG0 (1) is less than M (M = 3).

[0096] Therefore, the memory controller 210 selects the string line SG1 after the string line SG0 as the second string line. The memory controller 210 continues to select available second chip enable pins from among the multiple chip enable pins corresponding to the string line SG1 based on the chip enable pin sequence. Specifically, the memory controller 210 selects the chip enable pins CE0 and CE1 as the second chip enable pins, such that the total number of the first chip enable pin (CE3) and the second chip enable pins (CE0, CE1) is M (M = 3).

[0097] Next, the memory controller 210 obtains multiple first physical pages corresponding to multiple planes in the first chip enable pin CE3 (i.e., PG030, PG031), and obtains multiple second physical pages corresponding to multiple planes in the second chip enable pins CE0 and CE1 (i.e., PG100, PG101, PG110, PG111). Finally, the memory controller 210 uniformly sets these first physical pages and second physical pages as the multiple physical pages of the array storage group REG12, and sets the physical page PG111 as the parity page.

[0098] And so on, the configuration method of the array storage group REG13 is: the memory controller 210 crosses the string lines SG1 and SG2, and sets the physical pages corresponding to the chip enable pins CE2, CE3 in the string line SG1 and the chip enable pin CE0 in the string line SG2 (from the physical page PG120 to PG201) as the components of the array storage group REG13, where the physical page PG201 is set as the parity page.

[0099] The configuration method of the array storage group REG14 is: the memory controller 210 sets the physical pages corresponding to the chip enable pins CE1, CE2, CE3 in the string line SG2 (using the remaining available physical pages PG210 - PG231) as the components of the array storage group REG14, where the physical page PG231 is set as the parity page.

[0100] It is worth mentioning that this innovative configuration method has the following advantages: First, since the check page positions of each array storage group are different, even when virtual pages need to be replenished in the event of a power outage, the valid mapping table data can still be scattered and stored in different chip enable pins. For example, the check page of array storage group REG11 is located at chip enable pin CE2, the check page of REG12 is located at chip enable pin CE1, the check page of array storage group REG13 is located at chip enable pin CE0, and the check page of array storage group REG14 is located at chip enable pin CE3.

[0101] Second, by restricting the range of each array storage group to M (M = 3) chip enable pins, the memory controller 210 can prevent data within the same array storage group from being stored in the same chip enable pins corresponding to different word strings, ensuring that even if a certain chip fails, not too much data within the same array storage group will be lost, thus improving data reliability. For example, if the range of the array storage group is 5, the physical pages within SG0 and SG1 corresponding to CE0 will both store data belonging to the same array storage group. When the chip corresponding to CE0 malfunctions, a large amount of data will be lost, making it impossible to correct the data again.

[0102] Finally, this cross-word string configuration method enables the memory controller 210 to fully utilize the parallel reading capabilities of multiple chip enable pins, significantly improving the reading efficiency of the mapping table data.

[0103] In one embodiment, the memory controller 210 adopts a cross-word string continuous configuration when managing the arrangement order of the chip enable pins. Specifically, when the memory controller 210 finishes accessing the last chip enable pin of the i-th word string, it will automatically switch to the first chip enable pin of the (i + 1)-th word string, thereby achieving continuous access to the chip enable pins.

[0104] Through the above configuration method, the memory management method provided by the present disclosure can achieve flexible distributed storage of the mapping table data while ensuring the effective utilization of the storage space. Whether within a single word string or across adjacent word strings, the memory controller 210 can effectively manage and allocate physical page resources.

[0105] In one embodiment, when configuring each array storage group, the memory controller 210 adopts a specific check page layout strategy. Specifically, the memory controller 210 sets the check page of each array storage group as the last physical page among the multiple physical pages of that array storage group.

[0106] In another embodiment, when the memory controller 210 sets the check page position of the array storage group, it will perform the following operation steps: First, the memory controller 210 will confirm the total number of physical pages included in the array storage group, where these physical pages include data pages for storing mapping table data and check pages for storing check data. Then, the memory controller 210 designates the physical page with the largest serial number as the check page of the array storage group. For example, if an array storage group contains M physical pages, the Mth physical page will be designated as the check page, and the first to (M - 1)th physical pages will be used as data pages.

[0107] Through this fixed check page layout strategy, the memory controller 210 can quickly locate the position where the check data is stored during data recovery. This layout not only simplifies the data management operation of the memory controller 210, but also improves the access efficiency of the check data. In addition, due to the determinacy of the check page position, the memory controller 210 can perform the write and recovery operations of the mapping table data more efficiently.

[0108] In another embodiment, the memory controller 210 can adopt a round-robin check page allocation strategy. Specifically, the memory controller 210 cycles based on the numbering order of the chip enable pins, and sequentially designates the physical pages in different chip enable pins as check pages.

[0109] For example, the memory controller 210 can perform the following check page allocation steps: For the first array storage group, the memory controller 210 selects the last physical page in its corresponding last chip enable pin as the check page; for the second array storage group, the memory controller 210 selects the last physical page in its corresponding first chip enable pin as the check page; for the third array storage group, the memory controller 210 selects the last physical page in its corresponding second chip enable pin as the check page.

[0110] Through this round-robin check page allocation strategy, the memory controller 210 not only ensures that the check pages of adjacent array storage groups are not located in the same chip enable pin, but also realizes the balanced distribution of the check pages among the chip enable pins. In addition, the regularity of this allocation strategy also facilitates the memory controller 210 to quickly locate and access the check page position.

[0111] In one embodiment, the memory controller 210 has a mapping table data reconstruction function. Specifically, when the memory controller 210 detects that the target chip fails, it will trigger the mapping table data reconstruction mechanism.

[0112] In another embodiment, the memory controller 210 performs the specific steps of mapping table data reconstruction as follows: First, the memory controller 210 identifies the array storage group containing the target chip. Since multiple physical pages of each array storage group are respectively mapped to M different chip enable pins, the memory controller 210 can determine which array storage groups are affected by the target chip failure.

[0113] Then, for each affected array storage group, the memory controller 210 performs a data reconstruction operation respectively. Specifically, the memory controller 210 first reads the complete mapping table data from the chips in the array storage group that have not failed. At the same time, the memory controller 210 reads the parity data from the corresponding parity page.

[0114] In another embodiment, based on the error correction code algorithm of redundant array of independent disks, the memory controller 210 performs an exclusive OR (XOR) operation using the unimpaired mapping table data and the parity data to reconstruct the target partial mapping table data stored in the target chip. For example, if the array storage group contains three data pages (D1, D2, D3) and one parity page (P), and D2 is stored in the failed target chip, the memory controller 210 can reconstruct D2 by calculating to reconstruct D2.

[0115] In another embodiment, after completing the data reconstruction, the memory controller 210 performs a data verification step. Specifically, the memory controller 210 ensures the accuracy of the reconstructed mapping table data by recalculating the parity code of the reconstructed data and comparing it with the original parity data. If the verification passes, the memory controller 210 temporarily stores the reconstructed mapping table data in the buffer memory 214 for subsequent use.

[0116] Through the above mapping table data reconstruction mechanism, the memory management method provided by the present disclosure not only realizes reliable data storage, but also ensures the data recovery ability in case of chip failure, thereby improving the reliability and stability of the storage system. Even if a certain chip fails, the memory controller 210 can still reconstruct and recover the critical mapping table data through the data and parity information in other chips.

[0117] This embodiment also provides a computer program product, including computer-readable code or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor, the processor executes the steps of the above-mentioned memory management method. This computer program product can be specifically implemented in the form of hardware, firmware, software, or a combination thereof. In an alternative embodiment, the computer program product is specifically embodied as a computer storage medium. In another alternative embodiment, the computer program product is specifically embodied as a software product, such as a Software Development Kit (SDK), etc.

[0118] Based on the above, the memory management method and its memory controller provided by the present disclosure have the following advantages:

[0119] By determining the size of the array storage group according to the total number of multiple chip enable pins, where the array storage group includes multiple physical pages corresponding to a number of chip enable pins less than the total number, it can effectively avoid concentrating the check pages in the last chip enable pin, thereby improving the storage distribution uniformity of the mapping table data.

[0120] By setting multiple sequentially arranged array storage groups based on the word line order, chip enable pin order, and plane order, such that the multiple physical pages of each array storage group respectively correspond to different planes of different chip enable pins, it can ensure the uniform distribution of the mapping table data in the physical storage space and avoid the read bottleneck caused by concentrated data storage.

[0121] By corresponding the check pages of two adjacent array storage groups to different chip enable pins, even when virtual pages need to be supplemented in the case of power failure, it can ensure that the valid data is dispersed and stored in different chips, thereby maintaining a high parallel read efficiency without affecting the protection strength of the mapping table data.

[0122] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, applicable to a storage device configured with a rewritable non-volatile memory module, the rewritable non-volatile memory module including a plurality of chips, each of the plurality of chips corresponding to a chip enable pin, and each chip including P planes, characterized in that, The method includes: Obtaining mapping table data to be stored; Determining a fixed size of each array storage group according to the total number N of multiple chip enable pins, where the array storage group includes multiple physical pages corresponding to M chip enable pins, where M is less than N and greater than 1, and M is equal to N minus a predetermined value; Setting multiple consecutively arranged array storage groups based on the string line order, the chip enable pin order, and the plane order, where the multiple physical pages of each array storage group respectively correspond to different planes of the M chip enable pins; and Storing the mapping table data into the multiple array storage groups, where the multiple physical pages of each array storage group include multiple data pages and a parity page, where the multiple data pages are used to store partial mapping table data corresponding to the array storage group, and the parity page is used to store parity data corresponding to the partial mapping table data, where the parity page of each array storage group has a predetermined fixed position within the array storage group, where the parity pages of two adjacent array storage groups respectively correspond to different chip enable pins.

2. The memory management method according to claim 1, wherein The step of setting the multiple consecutively arranged array storage groups based on the string line order, the chip enable pin order, and the plane order includes: Selecting a first array storage group to be set according to the serial number order of the multiple array storage groups; Selecting an available first string line based on the string line order; Selecting one or more available first chip enable pins from the multiple chip enable pins corresponding to the first string line based on the chip enable pin order; If the number of the one or more first chip enable pins is equal to M: Obtaining multiple first physical pages corresponding to the P planes in each first chip enable pin; and Setting the multiple first physical pages as the multiple physical pages of the first array storage group.

3. The memory management method according to claim 2, wherein The step of setting the multiple consecutively arranged array storage groups based on the string line order, the chip enable pin order, and the plane order further includes: If the number of the one or more first chip enable pins selected in the first string line is less than M: Selecting an available second string line sorted after the first string line; Selecting one or more available second chip enable pins from the multiple chip enable pins corresponding to the second string line based on the chip enable pin order, where the total number of the one or more first chip enable pins and the one or more second chip enable pins is M; Obtaining multiple first physical pages corresponding to the P planes in each first chip enable pin, and obtaining multiple second physical pages corresponding to the P planes in each second chip enable pin; and Setting the multiple first physical pages and the multiple second physical pages as the multiple physical pages of the first array storage group.

4. The memory management method according to claim 1, wherein, The parity page of each array storage group is the last one of the multiple physical pages of the array storage group.

5. The memory management method according to claim 1, wherein If N is even, there is a remainder when M is used as a divisor of N.

6. The memory management method according to claim 1, wherein The predetermined value is 1.

7. The memory management method according to claim 1, wherein The chip enable pin following the last chip enable pin of the i-th string line is the first chip enable pin of the (i + 1)-th string line, where multiple physical pages of each array storage group correspond to multiple chip enable pins of the same string line or multiple chip enable pins of adjacent string lines. where each string line includes N P entity pages.

8. The memory management method according to claim 1, wherein The method further includes: If a target chip fails, reconstruct the target partial mapping table data stored in the target chip according to the partial mapping table data stored in other chips except the target chip and the corresponding check data.

9. A memory controller for controlling a storage device configured with a rewritable non-volatile memory module, characterized in that, The memory controller includes: A memory interface control circuit for electrically connecting to the rewritable non-volatile memory module, the rewritable non-volatile memory module including multiple chips, each of the multiple chips corresponding to a chip enable pin, and each chip including P planes; and A processor electrically connected to the memory interface control circuit, wherein the processor is further electrically connected to the connection interface circuit of the storage device to electrically connect to the host system. Wherein the processor is configured to: Obtain the mapping table data to be stored; Determine the fixed size of each array storage group according to the total number N of chip enable pins, where the array storage group includes multiple physical pages corresponding to M chip enable pins, where M is less than N and greater than 1, and M is equal to N minus a predetermined value; Set multiple array storage groups arranged in succession based on the string line order, the chip enable pin order, and the plane order, where the multiple physical pages of each array storage group respectively correspond to different planes of the M chip enable pins; and Store the mapping table data into the multiple array storage groups, where the multiple physical pages of each array storage group include multiple data pages and a check page, where the multiple data pages are used to store the partial mapping table data corresponding to the array storage group, and the check page is used to store the check data corresponding to the partial mapping table data, where the check page of each array storage group has a predetermined fixed position within the array storage group. The check pages of two adjacent array storage groups respectively correspond to different chip enable pins.

10. The memory controller according to claim 9, wherein The step of setting the multiple array storage groups arranged in succession based on the string line order, the chip enable pin order, and the plane order includes: Select the first array storage group to be set according to the serial number order of the multiple array storage groups; Select an available first string line based on the string line order; Select one or more available first chip enable pins from the multiple chip enable pins corresponding to the first string line based on the chip enable pin order; If the number of the one or more first chip enable pins is equal to M: Obtain multiple first physical pages corresponding to the P planes in each first chip enable pin; and Set the multiple first physical pages as the multiple physical pages of the first array storage group.

11. The memory controller according to claim 10, wherein, The step of setting the multiple array storage groups arranged in succession based on the string line order, the chip enable pin order, and the plane order further includes: If the number of the one or more first chip enable pins selected in the first string line is less than M: Select an available second string line sorted after the first string line; Based on the chip enable pin order, select one or more available second chip enable pins from the multiple chip enable pins corresponding to the second string line, wherein the total number of the one or more first chip enable pins and the one or more second chip enable pins is M; Obtain multiple first physical pages corresponding to the P planes in each first chip enable pin, and obtain multiple second physical pages corresponding to the P planes in each second chip enable pin; and Set the multiple first physical pages and the multiple second physical pages as the multiple physical pages of the first array storage group.

12. The memory controller according to claim 9, wherein The parity page of each array storage group is the last one of the multiple physical pages of the array storage group.

13. The memory controller according to claim 9, wherein If N is an even number, there is a remainder when M is used as a divisor of N.

14. The memory controller according to claim 9, wherein The predetermined value is 1.

15. The memory controller according to claim 9, wherein The chip enable pin following the last chip enable pin of the i-th string line is the first chip enable pin of the (i + 1)-th string line, wherein the multiple physical pages of each array storage group correspond to the multiple chip enable pins of the same string line or correspond to the multiple chip enable pins of adjacent string lines, where each string line includes N P entity pages.

16. The memory controller according to claim 9, wherein The processor is further configured to: If a target chip fails, reconstruct the target partial mapping table data stored in the target chip according to the partial mapping table data stored in other chips except the target chip and the corresponding parity data.

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