Controller and instruction scheduling method for a storage device

Abstract

The application discloses a controller and instruction scheduling method of a storage device. The controller and instruction scheduling method introduces dynamic priority arbitration through a priority configuration table, so that various CA instructions sent to a CA bus are more evenly distributed, and a certain type of instruction is no longer sent in a cluster. Thus, the CA instructions on the CA bus and the data transmission on a DQ bus can be better parallel executed, so as to improve the bandwidth utilization of the DQ bus.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and in particular to a controller and instruction scheduling method for a storage device. Background Technology

[0002] Currently, many storage devices, such as USB flash drives, SD cards, CF cards, SSDs, eMMC embedded storage cards, and UFS devices, use flash memory (especially NAND flash memory) as their primary storage medium, and this is gradually becoming the mainstream form. Compared to traditional magnetic media storage, this represents a significant performance leap. The traditional flash interface protocols (ONFi or Toggle) used in these storage devices transmit commands / addresses and data using the same bus. As the data transfer rate of the flash interface increases, the command / address transfer rate remains unchanged, leading to a greater proportion of command / address transfer time and thus creating a bottleneck in improving the data transfer bandwidth of the flash interface.

[0003] To address the challenges of improving traditional flash memory interfaces, new flash memory interface protocols (such as Separate Command Address, or SCA) separate command / address and data transmission, placing them on two different transmission buses. Specifically, CA commands are transmitted on the Command and Address (CA) bus, while DQ commands (data to be written to or read from the flash memory storage medium) are transmitted on the Data (DATA, also called DQ) bus.

[0004] As the transmission rate of the DQ bus increases, the time required for storage devices to read a unit of data also decreases. However, because the CA bus is a low-speed signal with a maximum operating frequency limit, the time required for CA instructions on the CA bus cannot be shortened by increasing the frequency. When the transmission time on the DQ bus is less than the time required for a CA instruction on the CA bus, data transmission on the DQ bus will become idle because it needs to wait for the execution of CA instructions on the CA bus. Figure 1 As shown, data transmission G needs to wait for instructions A / B / C / D / G to finish executing before it can begin; during the execution of instruction G, the DQ bus is idle, resulting in a waste of DQ bus bandwidth. Summary of the Invention

[0005] In view of this, embodiments of the present disclosure provide a controller for a storage device and an instruction scheduling method to solve the above problems.

[0006] According to a first aspect of the present disclosure, a controller for a storage device is provided. The controller is coupled to a plurality of flash memory chips via a CA bus and a DQ bus in a first channel. The first channel further includes a CA control unit coupled to the CA bus and a DQ control unit coupled to the DQ bus. The controller includes:

[0007] The instruction cache unit caches CA instructions and DQ instructions adapted to the multiple flash memory chips one-to-one through multiple instruction queues;

[0008] The priority configuration table maintenance unit is used to store multiple priority configuration tables corresponding to multiple scenarios. The priority configuration table stores the initial quota and priority balance of the CA instructions used in the corresponding scenario. The priority configuration table maintenance unit also sets the initial value of the priority balance in each priority configuration table to the initial quota. When all priority balances in the priority configuration table are equal to zero, all priority balances are reset to the initial quota.

[0009] The arbitration unit is used to obtain the current scenario of the controller for multiple CA commands to be arbitrated, obtain the priority balance of each CA command in the current scenario from the priority balance table, select the CA command with the largest priority balance as the preferred CA command of the CA control unit, and subtract 1 from the priority balance corresponding to the CA command with the largest priority balance.

[0010] In some embodiments, the plurality of scenarios include: random read, random write, sequential read, and sequential write.

[0011] In some embodiments, in each of the plurality of scenarios, a CA instruction sequence needs to be executed to complete a read data operation or write data operation on the flash memory chip. Then, the priority configuration table maintenance unit sets the initial quota of each CA instruction in the priority configuration table of the corresponding scenario according to the number of each CA instruction in the corresponding CA instruction sequence of the corresponding scenario.

[0012] In some embodiments, the system further includes a command parser for converting received host commands into CA and DQ instructions adapted to the plurality of flash memory chips and caching them into the plurality of instruction queues.

[0013] In some embodiments, the system further includes firmware for determining the current scenario of the controller based on received host commands.

[0014] In some embodiments, the priority configuration table maintenance unit further adjusts the initial quota in each priority configuration table based on the bandwidth utilization of the DQ bus over a past period.

[0015] In some embodiments, the arbitration unit further determines whether each CA instruction can be executed in parallel with the currently executing DQ instruction for the multiple CA instructions to be arbitrated.

[0016] According to a second aspect of the present disclosure, a storage device is provided, comprising: a controller coupled to a flash memory storage medium, the flash memory storage medium being composed of flash memory chips, and the controller being any of the controllers described above.

[0017] According to a third aspect of the present disclosure, an instruction scheduling method is provided for a controller of a storage device, the controller being coupled to a plurality of flash memory chips via a CA bus and a DQ bus in a first channel, the first channel further comprising a CA control unit coupled to the CA bus and a DQ control unit coupled to the DQ bus, the instruction scheduling method comprising:

[0018] Multiple instructions are retrieved from multiple instruction queues, each of which corresponds to an instruction cache adapted to multiple flash memory chips under the first channel;

[0019] The current scene of the controller is obtained, and a priority configuration table is selected according to the current scene. Multiple priority configuration tables correspond to multiple scenes.

[0020] Retrieve the priority balance of each CA instruction to be arbitrated from the selected priority configuration table;

[0021] The priority balances of each CA instruction to be arbitrated are compared, and the CA instruction with the largest priority balance is selected as the preferred CA instruction by the CA control unit.

[0022] Subtract 1 from the priority balance corresponding to the CA instruction with the largest priority balance in the selected priority configuration table; and

[0023] If the priority balance of each CA instruction in the priority configuration table is 0, then the priority balance of each CA instruction will be reset to the initial limit.

[0024] In some embodiments, the instruction scheduling method further includes: adjusting the initial quota in each priority configuration table based on the bandwidth utilization of the DQ bus over a past period of time.

[0025] The embodiments disclosed herein introduce dynamic priority arbitration through a priority configuration table, which makes the various CA instructions sent to the CA bus more evenly distributed, rather than being sent in clusters of a certain instruction type. This allows the CA instructions on the CA bus and the data transmission on the DQ bus to be executed in parallel better, thereby improving the bandwidth utilization of the DQ bus. Attached Figure Description

[0026] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0027] Figure 1 This is a schematic diagram showing the CA bus and DQ bus executing CA instructions and DQ instructions respectively;

[0028] Figure 2 This is a schematic block diagram of the host system;

[0029] Figure 3 This is a schematic diagram of the structure of the controller of the storage device provided in the embodiments of this disclosure;

[0030] Figure 4A and Figure 4B An example of the priority configuration table structure is provided;

[0031] Figure 5 An example of a priority configuration table for random reads designed according to embodiments of this disclosure is provided;

[0032] Figure 6 An example of a priority configuration table for sequential writes designed according to embodiments of this disclosure is provided;

[0033] Figure 7 Example diagrams are given showing the execution of random read CA and DQ instructions on the CA bus and DQ bus, respectively.

[0034] Figure 8 A flowchart of the instruction scheduling method provided in the embodiments of this disclosure is given. Detailed Implementation

[0035] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.

[0036] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0037] Unless the context explicitly requires it, the terms "comprising," "including," and similar terms throughout the specification and claims should be interpreted as encompassing rather than exclusive or exhaustive; that is, meaning "including but not limited to." In the description of this invention, it should be understood that terms such as "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0038] Figure 2 This is a schematic block diagram of an exemplary host system 100. The host system 100 is, for example, a personal computer, a laptop, or a server.

[0039] Host system 100 includes host device 110 (e.g., a computer system including a main processor and memory) and storage devices. Host device 110 can issue host commands to the storage devices, causing the storage devices to manage data stored in the storage devices according to the commands. For example, host device 110 can communicatively connect to the storage devices (e.g., via host interface 121) and issue various commands to the storage devices (e.g., READ, WRITE, UNMAP, REASSIGNBLOCK, TRIM, etc.). The storage devices can store, update, read, and / or otherwise manage host data according to the address range prompted by the command. Once a command is executed, the storage devices can transmit a response to host device 110, indicating that the command has been successfully completed.

[0040] The storage device consists of a controller 120 and a storage medium 130. The controller 120 parses host commands, translates them into instructions adapted to the storage medium 130, executes the instructions, and feeds back the results to the host device 110. The controller 120 consists of various hardware and software components. The hardware includes, for example, a (micro)processor, cache units such as SRAM and DRAM, and interface circuits. The software includes, for example, a series of software programs that perform management functions, including but not limited to data read / write, bad block management, wear leveling, garbage collection, power-off recovery, and write balancing techniques.

[0041] Storage medium 130 is used to store data. There are multiple channels (e.g., CH0 and CH1) between controller 120 and storage medium 130, through which controller 120 and storage medium 130 exchange data.

[0042] Currently, the mainstream storage medium 130 is flash memory (especially NAND flash memory). Typically, each channel (e.g., CH0 or CH1 in the diagram) is coupled to N (N can be 2, 4, 8, etc.) flash memory chips, and the controller 120 needs to operate the corresponding flash memory chips through each channel. When the SCA protocol is used as the flash memory interface protocol, each channel includes two buses: a DQ bus and a CA bus. The controller 120 executes DQ instructions through the DQ bus to write or read data from the flash memory chips, and executes CA instructions through the CA bus to perform command / address operations on the flash memory chips.

[0043] Referring to the background technology, in order to make full use of the transmission bandwidth of the DQ bus, it is necessary to make the CA command execute as much as possible during the data transmission of the DQ bus. Figure 3 A schematic diagram of the improved controller 120 based on this idea, provided in an embodiment of this disclosure, is given.

[0044] like Figure 3 As shown, the controller 120 includes a host interface 201, a command parser 202, an instruction cache unit 203, an arbitration unit 204, a data path 205, a priority configuration table maintenance unit 206, a CA control unit 207, and a DQ control unit 208. For ease of description, only those passing through the same channel (e.g., ...) are shown in the figure. Figure 1 The flash memory chips DIE0 to DIEn are coupled to the controller 120 via CH0. The channel includes a CA control unit 207, a DQ control unit 208, a CA bus 11, and a DQ bus 12. The CA control unit 207 is coupled to the flash memory chips DIE0 to DIEn via the CA bus 11, and the DQ control unit 208 is coupled to the flash memory chips DIE0 to DIEn via the DQ bus 12.

[0045] The host interface 201 is used to receive host commands from the host device 110 and to transmit data with the host device 110. Host commands include, for example, write commands to write data to the flash memory storage medium 130, read commands to read data from the flash memory storage medium, query commands to check the execution status of write or read commands, and so on. The interface protocol used by the host interface 201 determines the various command types and formats. For example, when using UPIU (UFS Protocol Information Units) as the interface protocol, the transmitted UPIU packet consists of multiple parts, including a header and a payload. The header provides information such as the interaction type, length, and attributes, while the payload provides the specific content of the command or data.

[0046] Command parser 202 parses the received host commands, converts them into instructions adapted to the flash memory chips, and stores the instructions in the instruction cache unit 203. Different flash memory chips support different instruction sets; for example, different flash memory chip products have different instruction formats for write data operations. Therefore, command parser 202 is needed to convert the received host commands. Command parser 202 can convert one host command into multiple instructions adapted to the flash memory chips, or it can convert multiple host commands into multiple instructions adapted to the flash memory chips. This embodiment does not impose specific limitations on the correspondence between the number of host commands and the number of instructions adapted to the flash memory chips.

[0047] The command parser 202, based on the SCA protocol, divides the instructions that operate on the flash memory chip via the CA bus 11 and DQ bus 12 into CA instructions and DQ instructions, and caches the CA and DQ instructions in the instruction cache unit 203. CA instructions are generally operation instructions related to the configuration of the flash memory chip, such as instructions to read the status of the flash memory chip or instructions to modify the status of registers on the flash memory chip. DQ instructions are generally instructions for actual data transfer between the flash memory chip and the flash memory chip, such as writing data to or reading data from the flash memory chip.

[0048] In some embodiments, the instruction cache unit 203 includes a plurality of first-in-first-out instruction queues corresponding to a plurality of flash memory chips. Each instruction queue stores CA instructions and DQ instructions for the same flash memory chip. The figure shows (n+1) instruction queues corresponding to flash memory chips DIE0 to DIEn respectively.

[0049] Arbitration unit 204 monitors the operating status of CA control unit 207 and DQ control unit 208. If CA control unit 207 is idle, it retrieves CA instructions from multiple instruction queues. If multiple CA instructions are retrieved, they need to be arbitrated, and the selected CA instruction is sent to CA execution unit 207 for execution. If DQ control unit 207 is idle, it selects a DQ instruction following a similar process and sends it to DQ control unit 208 via data path 205 for data transmission. Here, data path 205 is similar to a data buffer unit. Data to be written to the flash memory chip is first placed in data path 205 and then retrieved by DQ control unit 208. Data read from the flash memory chip is first placed in data path 205 by DQ control unit 208 and then transmitted to host device 110.

[0050] The arbitration performed by arbitration unit 204 must ensure that the selected CA or DQ instruction can be executed in parallel with the currently executing DQ or CA instruction. Due to SCA protocol limitations, some DQ and CA instructions cannot be executed in parallel. Therefore, arbitration unit 204 needs to detect and eliminate certain instructions that conflict with the currently executing CA or DQ instruction, thereby ensuring that the CA or DQ instruction sent to the CA control unit or DQ control unit can be executed in parallel with the currently executing DQ or CA instruction. For example, if the CA instruction is a DQ-relate instruction, it will conflict with a DQ data transmission command on the same LUN (Logical Unit Number), and these two commands cannot be executed simultaneously.

[0051] However, if there are multiple CA instructions that can be executed in parallel with the currently executing DQ instruction, the arbitration unit 204 typically makes arbitration based on the priority of the CA instructions. In traditional processing, the priority of each CA instruction is fixed. However, in this embodiment, the arbitration unit 204 refers to the priority configuration table in the priority configuration table maintenance unit 206 for arbitration. The priority configuration table has the data format shown in 4A. Since users' hard drive usage is mostly regular, generally divided into random read, random write, sequential read, and sequential write scenarios, the CA instruction sequence used to complete reading or writing data from the flash memory chip differs in these scenarios. Therefore, a sequence of CA instructions is used as shown in 4A. Figure 4A The priority configuration table shown provides priority quota query information for different CA instructions in different scenarios. Specifically, each instruction type in each scenario has an initial quota, and the priority balance of each instruction type is counted. Initially, the priority balance equals the initial quota. When the priority balance is 0, the priority is the lowest. When arbitration unit 204 refers to the priority configuration table for arbitration, it first retrieves the priority balance of the instruction type corresponding to each CA instruction to be arbitrated in the current scenario. Then, it compares the priority balances of each CA instruction to be arbitrated, selects the CA instruction corresponding to the highest priority balance as the preferred instruction sent to CA execution unit 207, and decrements the corresponding priority balance by 1 after arbitration or the preferred instruction is executed. The priority configuration table maintenance unit also resets all priority balances to the initial quota when all priority balances in the priority configuration table are equal to zero.

[0052] It should be noted that the arbitration unit 204 needs to obtain the current scenario of the controller in order to determine the priority configuration table for the current scenario adaptation. Therefore, the controller 120 should also include a functional module for determining the current scenario of the controller based on the currently received host commands or other information. This functional module can be implemented as firmware (but is not limited to this).

[0053] It should also be pointed out that, although Figure 4A Multiple priority configuration tables are provided, each stored according to a specific scenario. Each priority configuration table corresponds to a corresponding scenario. However, it can also be stored according to... Figure 4B The organization priority configuration table is shown.

[0054] The embodiments of this disclosure will be explained below using random read and continuous write scenarios as examples.

[0055] In random read scenarios, the data that the host needs to acquire is randomly stored in different flash memory chips. To complete the data read operation, a basically identical CA instruction sequence is executed, which includes:

[0056] Read status, used to determine whether the flash memory chip is ready and whether a read operation command can be sent;

[0057] Read, i.e., sending a read operation command.

[0058] Read status: Reads the N flash memory status to determine if it is ready.

[0059] DATA OUT: Sends a command to prepare the NAND flash memory for data transfer.

[0060] Read transfer: Performs data transfer.

[0061] The first four CA instructions are executed by the CA line, and the fifth is the DQ instruction for data transmission on the DQ bus (which requires sending start and end commands on the CA bus). For the same flash memory chip, the above CA instruction sequence must be executed sequentially.

[0062] Figure 5 An example of a priority configuration table for random reads designed according to an embodiment of this disclosure is provided. According to this example, if the arbitration unit 204 is currently arbitrating the three CA commands—Read status, data out, and Read—Read status and data out have the same priority, while Read has the lowest priority.

[0063] In a continuous write scenario, completing a write operation requires sending four Program Pages, four Program Confirms, and seven Read Status commands. Therefore, in this priority configuration table, the initial quotas for these CA commands are configured as 4 / 4 / 7, respectively. Figure 6An example of a priority configuration table for continuous writes designed according to an embodiment of this disclosure is provided. According to this example, if the arbitration unit 204 is currently arbitrating the three CA commands—Program page, Program confirm, and Read status—then Program page has the highest priority, and Read status has the same priority as Program confirm.

[0064] In the example above, the initial quota of a CA instruction in the priority configuration table is set according to the number of each CA instruction in the CA instruction sequence corresponding to the read / write operation in random read and sequential write scenarios. That is, the initial quota of each CA instruction in the priority configuration table is equal to the number of CA instructions in the CA instruction sequence corresponding to the read / write operation, or it can be set as a multiple. This setting method can be extended to scenarios involving both random write and sequential read. Ultimately, a similar result can be obtained. Figure 7 The execution effect Figure 7 A schematic diagram is given showing the execution of random read CA and DQ instructions on the CA and DQ buses, respectively. Figure 7 It can be seen that the CA command, Read status, Read, and DATA OUT, which mark the start or end of DQ transmission, are executed alternately. The CA commands executed on the CA bus can basically be executed in parallel with the data transmission on the DQ bus, thus the bandwidth utilization of the DQ bus is relatively high.

[0065] It should be understood that the initial quota of each instruction in the priority configuration table plays a key role in the execution order of CA instructions on the CA bus. In order to better maintain this quota, the priority configuration table maintenance unit 206 can also count the bandwidth utilization of the DQ bus over a period of time. When the bandwidth utilization is poor, the initial quota in the priority configuration table is adjusted to improve the bandwidth utilization of the subsequent DQ bus.

[0066] Accordingly, this disclosure also provides an instruction scheduling method, which can be used in the controller of a storage device to implement arbitration logic for distributing CA instructions to a CA control unit. The controller is coupled to multiple flash memory chips through a first channel. This instruction scheduling method can be implemented as one or more combinations of software programs, firmware, and hardware logic. A flowchart of the instruction scheduling method is shown below. Figure 8 As shown.

[0067] In step S801, multiple CA instructions to be arbitrated are received.

[0068] In step S802, a priority configuration table is selected based on the current scenario.

[0069] In step S803, the priority balance of each CA instruction is retrieved from the selected priority configuration table.

[0070] In step S804, the priority balances of each CA instruction are compared, and the CA instruction with the largest priority balance is selected as the preferred CA instruction.

[0071] In step S805, the priority balance corresponding to the CA instruction with the largest priority balance in the selected priority configuration table is reduced by 1.

[0072] In step S806, when the priority balance of each CA instruction in the priority configuration table is 0, the priority balance of each CA instruction is reset to the initial amount.

[0073] According to this embodiment, the design is first as follows: Figure 4A The diagram shows multiple priority configuration tables corresponding to multiple scenarios. Each priority configuration table stores the initial quota and priority balance of CA instructions for the corresponding scenario. Then, for multiple CA instructions to be arbitrated, a priority configuration table is selected according to the current scenario. The priority balance of each CA instruction to be arbitrated is obtained from the selected priority configuration table, and the priority balances of the multiple CA instructions to be arbitrated are compared. The CA instruction with the largest priority balance is the preferred CA instruction. If this instruction can be executed in parallel with the DQ instruction currently being executed by the DQ control unit in the controller, it can be sent to the CA control unit in the controller for execution. Then, the priority balance corresponding to this CA instruction in the selected priority configuration table is reduced by 1. When the priority balance of all CA instructions in a certain priority configuration table is 0, the priority balance of all CA instructions in that priority configuration table is reset to the initial quota.

[0074] As a preferred embodiment, the instruction scheduling method further includes: setting the initial quota corresponding to each CA instruction in multiple priority configuration tables according to the number of each CA instruction in the CA instruction sequence corresponding to the read / write operation in each scenario.

[0075] As a preferred embodiment, the instruction scheduling method further includes: calculating the bandwidth utilization rate of the DQ bus over a period of time, and when the bandwidth utilization rate is poor, adjusting the initial quota in the priority configuration table to improve the bandwidth utilization rate of the subsequent DQ bus.

[0076] In summary, the storage device controller and the instruction scheduling method applied to the controller provided in this disclosure introduce dynamic priority arbitration through a priority configuration table, and through the initial quota design of the priority configuration table, the various CA instructions sent to the CA bus are more evenly distributed, rather than being sent in clusters of a certain instruction type. This allows for better parallel execution of CA instructions on the CA bus and data transmission on the DQ bus in SCA mode, thereby improving the bandwidth utilization of the DQ bus.

[0077] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A controller for a storage device, the controller being coupled to a plurality of flash memory chips via a CA bus and a DQ bus in a first channel, the first channel further comprising a CA control unit coupled to the CA bus and a DQ control unit coupled to the DQ bus, the controller comprising: The instruction cache unit caches CA instructions and DQ instructions adapted to the multiple flash memory chips one-to-one through multiple instruction queues; The priority configuration table maintenance unit is used to store multiple priority configuration tables corresponding to multiple scenarios. The priority configuration table stores the initial quota and priority balance of CA instructions used in the corresponding scenario. The priority configuration table maintenance unit also sets the initial value of the priority balance in each priority configuration table to the initial quota. When all priority balances in the priority configuration table are equal to zero, all priority balances are reset to the initial quota. The priority balance of a CA instruction in the corresponding scenario is used to represent the priority of the CA instruction in that scenario, while the initial quota is the initial value set for the CA instruction according to the scenario and instruction type. The arbitration unit is used to obtain the current scenario of the controller for multiple CA commands to be arbitrated, obtain the priority balance of each CA command in the current scenario from the priority balance table, select the CA command with the largest priority balance as the preferred CA command of the CA control unit, and subtract 1 from the priority balance corresponding to the CA command with the largest priority balance.

2. The controller according to claim 1, wherein, The multiple scenarios include: random read, random write, continuous read, and continuous write.

3. The controller according to claim 1, wherein, In each of the multiple scenarios, a CA instruction sequence needs to be executed to complete a read data operation or a write data operation on the flash memory chip. Then, the priority configuration table maintenance unit sets the initial quota of each CA instruction in the priority configuration table of the corresponding scenario according to the number of each CA instruction in the corresponding CA instruction sequence of the corresponding scenario.

4. The controller according to claim 1, further comprising: A command parser is used to convert received host commands into CA and DQ instructions adapted to the multiple flash memory chips and cache them into the multiple instruction queues.

5. The controller according to claim 1, further comprising: Firmware is used to determine the current scenario of the controller based on received host commands.

6. The controller according to claim 1, wherein, The priority configuration table maintenance unit also adjusts the initial quota in each priority configuration table based on the bandwidth utilization of the DQ bus over a period of time.

7. The controller according to claim 1, wherein, For the multiple CA instructions to be arbitrated, the arbitration unit also determines whether each CA instruction can be executed in parallel with the currently executing DQ instruction.

8. A storage device, comprising: A coupled controller and a flash memory storage medium, the flash memory storage medium being composed of flash memory chips, and the controller being the controller according to any one of claims 1 to 7.

9. An instruction scheduling method for a controller of a storage device, the controller being coupled to a plurality of flash memory chips via a CA bus and a DQ bus in a first channel, the first channel further comprising a CA control unit coupled to the CA bus and a DQ control unit coupled to the DQ bus, the instruction scheduling method comprising: Multiple instructions are retrieved from multiple instruction queues, each of which corresponds to an instruction cache adapted to multiple flash memory chips under the first channel; The current scene of the controller is obtained, and a priority configuration table is selected according to the current scene. Multiple priority configuration tables correspond to multiple scenes. Retrieve the priority balance of each CA instruction to be arbitrated from the selected priority configuration table; The priority balances of each CA instruction to be arbitrated are compared, and the CA instruction with the largest priority balance is selected as the preferred CA instruction by the CA control unit. Subtract 1 from the priority balance corresponding to the CA instruction with the largest priority balance in the selected priority configuration table; and When the priority balance of each CA instruction in the priority configuration table is 0, the priority balance of each CA instruction is reset to the initial limit. The priority balance of each CA instruction in the corresponding scenario indicates the priority of the CA instruction in that scenario, while the initial limit is the initial value set for the CA instruction according to the scenario and instruction type.

10. The instruction scheduling method according to claim 9, further comprising: The initial quota in each priority configuration table is adjusted based on the bandwidth utilization of the DQ bus over a past period.

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