Bus relay device and interconnection system supporting simultaneous response to multi-instruction transmission

Abstract

The invention provides a bus relay device and an interconnection system supporting simultaneous response to multi-instruction transmission, the bus relay device is used for connecting slave equipment and an interconnection bus, and comprises an instruction processing unit and a cache unit; the instruction processing unit is used for separating and integrating a plurality of received instructions and transmitting the processed instructions to the cache unit; and the cache unit is used for determining direct read-write operation in the cache unit according to the processed instruction, or sending the processed instruction to the slave device for read-write operation. According to the invention, the read-write instructions are separated and integrated, so that the read-write operations are mutually independent and processed in parallel, and the number of read-write access times with an equal relationship is reduced to one, so that repeated read-write is avoided, and the time for processing the instructions is saved; the cache unit supports multi-read and multi-write, read-write instructions from a plurality of master devices can be queried at the same time, and the time for accessing the slave devices is effectively shortened.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a bus relay device and an interconnection system that support simultaneous response to multiple instruction transmissions. Background Art

[0002] With the development of integrated circuit manufacturing technology, there are usually many master and slave devices in the system on chip, and the devices are interconnected and communicated through the on-chip bus. When the master devices such as microprocessors and microcontrollers access the slave devices such as memory and peripherals, they often face conflicts between the instructions of multiple master devices. For example, multiple master devices access the same slave device at the same time. Since the slave device can only respond to one read and write instruction at a time, the remaining master devices that failed in the competition will enter a waiting state. Even if there are multiple master devices accessing the same address, they need to access the slave devices one by one, and the access resources cannot be shared. The limited resource competition caused by this has become one of the important factors affecting system performance.

[0003] In a multi-master and multi-slave system, when multiple master devices issue instructions at the same time, the common practice of the on-chip bus is to first classify the instructions of the master device according to the access address, and shield the instructions accessing the same slave device according to the master device's priority (QoS) information, and finally poll / fixed priority arbitration for the instructions of the remaining master devices. The master device that successfully competes sends the instruction to the slave device for reading and writing, and the remaining master devices need to wait for the slave device to be idle, and repeat the above process until the competition is successful. As the number of master devices increases, the waiting time of the master device with lower priority increases due to the limited response capability of the slave device, and the following problems exist: the data required by the low-priority master device has been read out by the other master devices, and it still needs to wait; the high-priority master device has just written the data of the same address, and the low-priority master device is still waiting in line to read the slave device; two master devices write the same address at the same time, and queue up to issue two write operations, resulting in repeated writes, etc. The above problems are ultimately due to the fact that the bus does not have the ability to process multiple instructions at the same time, so the access is limited by the response capability of the slave device, resulting in low system efficiency and high power consumption.

[0004] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0005] The purpose of the present invention is to provide a bus relay device so that the on-chip bus has the ability to process multiple read and write instructions simultaneously, and separate and integrate the read and write instructions from multiple hosts, thereby minimizing the number of accesses to slave devices, avoiding access conflicts, and saving access time.

[0006] In order to solve the above problems, in a first aspect, a bus relay device supporting simultaneous response to multiple instruction transmissions is provided, the bus relay device being used to connect a slave device and an interconnect bus; the bus relay device comprising an instruction processing unit and a cache unit; The instruction processing unit is used to separate and integrate the received multiple instructions and transmit the processed instructions to the cache unit; The cache unit is used to determine, according to the processed instructions, whether to directly perform read and write operations in the cache unit, or to send the processed instructions to the slave device for read and write operations.

[0007] The solution of the present invention separates and integrates read and write instructions through the instruction processing unit, so that the read and write operations are independent of each other and processed in parallel, and the number of read and write accesses with equal relationship is reduced to one, thereby avoiding repeated reading and writing and saving instruction processing time; at the same time, because the cache unit supports multiple reads and multiple writes, the read and write instructions from multiple master devices can be queried at the same time. In the most ideal situation, the cache returns all read data and stores all write data, eliminating the contention waiting time and reducing the access time of the slave device.

[0008] The instruction processing unit is used to separate the received multiple instructions into read instructions and write instructions, and integrate the read instructions and the write instructions respectively; the integration processing includes merging multiple read instructions with the same read address into one read instruction, and merging multiple write instructions with the same write address into one write instruction. The read and write instructions from multiple master devices are separated, and repeated accesses are merged, which greatly reduces the number of accesses and shortens the waiting time of the master device.

[0009] The integration process of the instruction processing unit further includes: merging the corresponding read instructions with continuous read addresses in the merged read instructions into one read instruction again, and merging the corresponding write instructions with continuous write addresses in the merged write instructions into one write instruction again, so as to further reduce the number of accesses and shorten the waiting time of the master device.

[0010] The instruction processing unit is used to separate the received multiple instructions into read instructions and write instructions, and match the addresses of the read instructions and the write instructions. If the addresses are equal, the corresponding write data is directly returned as read data through the bus relay device. Only the cache writing is required, and the reading process is omitted, further improving the access efficiency of the master device to the bus.

[0011] The cache unit is used to search in the cache unit according to the received read instruction, directly perform a read operation in the cache unit on the hit read instruction and then return, and send the miss read instruction to the slave device for read operation and then return; the cache unit is used to classify the received write instruction, directly perform a write operation in the cache unit on the corresponding write instruction if the write data is cacheable write data and then return, and send the corresponding write instruction if the write data is non-cacheable write data to the slave device for write operation and then return. The cache unit is attached to allow the read and write instructions not to be sent to the slave device, so that the read and write operations of the master device are likely to be integrated and released in advance, reducing the access time; the cache that supports multiple writes and multiple reads can enable the bus to have the ability to receive multiple read and write instructions.

[0012] The cache unit includes a cache table information unit, a cache maintenance unit and a cache storage unit; the cache storage unit is used to store data, the cache maintenance unit is used to allocate cache addresses, and the cache table information unit is used to record the physical address of data and the cache address in correspondence. It can perform temporary access to data and realize the reasonable allocation of cache resources.

[0013] When the bus is idle or the cache storage unit is about to be full, the cache maintenance unit writes the valid data in the cache storage unit into the slave device, and waits for the slave device to be idle to initiate writing, fully coordinate bus resources, and reduce unnecessary queuing time.

[0014] It also includes an arbitration unit; the arbitration unit is used to arbitrate according to priority and queue and send the processed instructions to the slave device before sending them to the slave device for read and write operations.

[0015] The write instruction is classified according to the special identification bit.

[0016] On the other hand, the present application also provides a bus interconnection system device, including a plurality of master devices and a plurality of slave devices connected via an interconnection bus; A bus relay device as described in any one of the first aspects is arranged on the slave device side of the interconnected bus, and the bus relay device corresponds to each of the slave devices one by one, and is used to realize the access between each of the slave devices and the multiple master devices. The bus relay device is highly compatible with the existing bus interconnection system, can be conveniently placed in the bus interconnection system, can fully coordinate bus resources, and improve the access efficiency of the master device to the bus.

[0017] Compared with the prior art, the beneficial effects of the present invention mainly include the following: 1) it can respond to multiple read and write instructions at the same time, reducing the waiting time of the master device; 2) it has the function of instruction integration, which can reduce the number of accesses for repeated accesses and reduce power consumption; 3) the device has a cache, allowing read and write instructions not to be sent to the slave device, reducing the access time, waiting for the slave device to be idle before initiating the write, fully coordinating bus resources, and reducing unnecessary queuing time. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 A schematic diagram of a bus relay device is provided for the present invention.

[0020] Figure 2 A working flow chart of a bus relay device is provided for the present invention.

[0021] Figure 3 A schematic diagram of the system architecture of a bus interconnection system is provided for the present invention. DETAILED DESCRIPTION

[0022] The above and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or back, etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and not to limit the present invention.

[0023] The following will describe the various embodiments of the present application in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present application, many technical details are provided in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solution claimed in the present application can be implemented.

[0024] The steps in the following embodiments do not correspond one to one with the summary of the invention.

[0025] Embodiment 1: Figure 1 A schematic diagram of a bus relay device is provided for the present invention. Figure 2 A working flow chart of a bus relay device is provided for the present invention.

[0026] refer to Figure 1-2As shown, the present invention first provides a bus relay device that supports simultaneous response to multiple instruction transmissions. The bus relay device is arranged on the slave device side of the bus, and is used to connect the slave device and the interconnection bus; the bus relay device includes an instruction processing unit and a cache unit, and the cache unit includes a cache table information unit, a cache maintenance unit, and a cache storage unit. The instruction processing unit is used to separate and integrate multiple received instructions, and transmit the processed instructions to the cache unit; the cache unit is used to determine whether to directly perform read and write operations in the cache unit according to the processed instructions, or to send the processed instructions to the slave device for read and write operations.

[0027] It can be understood that in a multi-master and multi-slave bus interconnection system (i.e., a bus interconnection system with multiple master devices and multiple slave devices), one of the slave devices may be accessed by multiple master devices at the same time, that is, multiple instructions are received at the same time. Instructions can generally be divided into read instructions and write instructions, wherein the read instruction carries the storage address of the data to be read (i.e., the read address), and the write instruction carries the data to be written and the storage address where the data to be written is to be stored (i.e., the write address).

[0028] refer to Figure 1-2 As shown, when the bus relay device receives multiple instructions (i.e., instructions 1 to n, corresponding to master devices 1 to master devices n, respectively), the instruction processing unit will separate and integrate the instructions. Specifically, the instruction processing unit will first separate the multiple instructions into two types: read instructions and write instructions, and then integrate the read instructions and write instructions respectively. The integration process includes merging instructions with the same address (including read address and write address) into one. Taking the read instruction as an example, for the separated multiple read instructions, the read address of each read instruction is compared and the corresponding read instructions with the same read address range are merged into one, so as to reduce the number of instructions. Similarly, for the separated multiple write instructions, the write address of each write instruction is compared and the corresponding write instructions with the same write address range are merged into one. Further, for the above-mentioned merged instructions, the instructions with continuous merged addresses can be merged into one again to further reduce the number of instructions. It can be understood that after separation and integration by the instruction processing unit, the number of instructions can be effectively reduced. It can also match the addresses of all read instructions and write instructions. If the read address is equal to the write address, the corresponding write data can be directly returned as the required read data through the bus relay device; in order to improve the subsequent cache hit, the write data can be written into the cache for subsequent read instruction query. Finally, refer to Figure 2 , that is, it can reduce n instructions to x read instructions and y write instructions (x+y <n)。

[0029] The instruction processing unit transmits the processed instructions (x read instructions and y write instructions) to the cache unit, which specifically includes a cache table information unit, a cache maintenance unit and a cache storage unit; among which, the cache storage unit is responsible for data storage, and the cache table information unit is used to record the physical address and cache address of the data, which is maintained by the cache maintenance unit.

[0030] The cache unit supports multiple reads and multiple writes. When the cache unit receives a processed instruction, for a read instruction, the cache unit first searches the cache unit according to the received read instruction, directly performs a read operation on the hit read instruction in the cache unit and returns it, and sends a miss read instruction to the slave device for a read operation and returns it. Specifically, x read instructions query the physical address stored in the cache table information unit at the same time to determine whether the access address generates a hit. If a hit occurs (such as Figure 2 As shown, if there are j read instructions that generate hits), the cache storage unit is queried according to the cache address corresponding to the physical address, and the data therein is returned to the corresponding master device; if no hit is generated (such as Figure 2 As shown in the figure, xj read instructions miss), then a slave device access is required. For the xj miss read instructions, arbitration will be performed according to the priority, and finally queued and sent to the slave device for read operation and returned to the corresponding master device through the bus relay device. It can be understood that the situation of no hit usually occurs when the device is just used. As the frequency of use increases, the probability of cache hit will also increase.

[0031] Considering that writing data directly to the slave device is inefficient, in order to reduce the data written to the slave device, the write data can be pre-classified into at least two categories: one is the data that can be written to the cache storage unit, called cacheable write data, and the other is the data that must be written to the slave device (such as register configuration), called non-cached write data. The difference between cacheable write data and non-cached write data can be confirmed by some preset rules or flags, such as using special identification bits (such as USER of AXI) for identification.

[0032] Then, when the cache unit receives the processed write instruction, the cache unit can classify the received write instruction, directly write the corresponding write instruction of the write data that is cacheable write data in the cache unit and then return it, and send the corresponding write instruction of the write data that is non-cacheable write data to the slave device for write operation and then return it. Figure 2 , the cacheable write data and non-cacheable write data in the y write instructions can be determined based on the special identification bit. For cacheable write data, it can be directly stored in the cache storage unit. For details, refer to Figure 2, the corresponding write instruction (k) is assigned a cache address by the cache maintenance unit, and the cache address is stored in the cache table information unit together with the actual physical address. The cacheable write data is stored in the cache storage unit according to the cache address. For non-cached write data, since it needs to be written to the slave device, the remaining write instructions (yk) are arbitrated according to the priority and finally queued and sent to the slave device for write access.

[0033] After being processed by the bus relay device, the original n instructions that need to be queued for arbitration are finally simplified to only xj read instructions and yk write instructions that are queued for arbitration at the slave end.

[0034] In this device, multiple read instructions with equal read addresses are merged into one, which only triggers one cache read access or slave device read access; multiple write instructions with equal write addresses are merged into one, which also only triggers one cache write access or slave device write access (under the same address, the write operation that must be written to the slave device will overwrite the cacheable write operation, and further, since the write instruction with the lowest priority is written last, only one write operation with the lowest priority is triggered); further, instructions with consecutive merged addresses can be merged into one again to further reduce read and write operations.

[0035] In this device, when the slave device is idle or the remaining cache space is small, the cache maintenance unit can also initiate a write operation to the slave device to actually write the data to the slave device. The data after writing will be overwritten in the subsequent write operation initiated by the master device to realize the allocation of cache resources.

[0036] Embodiment 2 Figure 3 The present invention provides a system architecture diagram of a bus interconnection system. The present invention also provides a bus interconnection system, including multiple master devices and multiple slave devices, the master devices and the slave devices are connected through a bus; the above-mentioned bus relay device is arranged on the slave device side of the interconnection bus, the bus relay device and the slave device correspond one-to-one, and is used to realize the access of each of the slave devices and the multiple master devices.

[0037] Based on the traditional bus distribution arbitration, this bus interconnection system adds a bus relay device. Through the instruction processing unit and cache unit of the bus relay device, it can ensure that the bus distributes instructions while supporting the reception and response of multiple read and write instructions, thereby reducing the number of accesses to slave devices and increasing the access efficiency of master devices.

[0038] like Figure 3As shown in the figure, when multiple master devices (master device 1 to master device n) issue read and write instructions, they are distributed to the bus relay devices at the corresponding slave device end according to the address range after passing through their respective bus control devices. The bus relay devices separate and integrate the received instructions and process them separately. When the data and response are ready, the bus relay devices and bus control devices return them to the master device to complete the access.

[0039] In order to facilitate the description, some common English nouns or letters used in the present invention are only used for exemplary reference rather than restrictive interpretation or specific usage, and the protection scope of the present invention should not be limited by their possible Chinese translations or specific letters.

[0040] It should also be noted that, in this document, relational terms such as "first" and "second" are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

Claims

1. A bus relay device supporting simultaneous response to multiple instruction transmissions, characterized in that: The bus relay device is used to connect the slave device and the interconnect bus; the bus relay device includes an instruction processing unit and a cache unit; The instruction processing unit is used to separate and integrate the received multiple instructions and transmit the processed instructions to the cache unit; The cache unit is used to determine, according to the processed instructions, whether to directly perform read and write operations in the cache unit, or to send the processed instructions to the slave device for read and write operations.

2. A bus relay device supporting simultaneous response to multiple instruction transmissions according to claim 1, characterized in that: The instruction processing unit is used to separate the received multiple instructions into read instructions and write instructions, and integrate and process the read instructions and the write instructions respectively; The integration process includes merging multiple read instructions with the same read address into one read instruction, and merging multiple write instructions with the same write address into one write instruction.

3. A bus relay device supporting simultaneous response to multiple instruction transmissions according to claim 2, characterized in that: The integration processing of the instruction processing unit also includes: merging corresponding read instructions with continuous read addresses in the merged read instructions into one read instruction again, and merging corresponding write instructions with continuous write addresses in the merged write instructions into one write instruction again.

4. A bus relay device supporting simultaneous response to multiple instruction transmissions according to claim 1, characterized in that: The instruction processing unit is used to separate the received multiple instructions into read instructions and write instructions, and match the addresses of the read instructions and the write instructions. If the addresses are equal, the corresponding write data is directly returned as read data through the bus relay device.

5. A bus relay device supporting simultaneous response to multiple instruction transmissions according to claim 2 or 3, characterized in that: The cache unit is used to search in the cache unit according to the received read instruction, directly perform a read operation on the hit read instruction in the cache unit and then return, and send the miss read instruction to the slave device for read operation and then return; The cache unit is used to determine the category of the received write instructions, directly perform a write operation in the cache unit on the corresponding write instructions whose write data is cacheable write data and then return it, and send the corresponding write instructions whose write data is non-cacheable write data to the slave device for write operation and then return it.

6. A bus relay device supporting simultaneous response to multiple instruction transmissions according to claim 5, characterized in that: The cache unit includes a cache table information unit, a cache maintenance unit and a cache storage unit; The cache storage unit is used to store data, the cache maintenance unit is used to allocate cache addresses, and the cache table information unit is used to record the correspondence between the physical address of the data and the cache address.

7. A bus relay device supporting simultaneous response to multiple instruction transmissions according to claim 6, characterized in that: When the bus is idle or the cache storage unit is almost full, the cache maintenance unit writes valid data in the cache storage unit into the slave device.

8. A bus relay device supporting simultaneous response to multiple instruction transmissions according to claim 1, characterized in that: Also includes an arbitration unit; The arbitration unit is used to perform arbitration according to the priority and queue the processed instructions before sending them to the slave device for reading and writing operations.

9. A bus relay device supporting simultaneous response to multiple instruction transmissions according to claim 5, characterized in that: The write instruction is classified according to the special identification bit.

10. A bus interconnection system device, characterized in that: including a plurality of master devices and a plurality of slave devices connected via an interconnect bus; A bus relay device as described in any one of claims 1 to 9 is arranged on the slave device side of the interconnected bus, and the bus relay device corresponds to each of the slave devices one by one, and is used to realize access between each of the slave devices and the multiple master devices.

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