Non-volatile memory, memory system, and control method of non-volatile memory

Abstract

This embodiment provides a nonvolatile memory capable of high-speed compression, a memory system, and a control method for a nonvolatile memory. According to this embodiment, the nonvolatile memory includes a memory chip and an instruction processing unit. Upon receiving a first instruction for compression from a controller, the instruction processing unit stores data read from a first location on the memory chip in the memory, transmits validity determination information for determining whether the data is valid to the controller, and upon receiving a second instruction for compression and validity determination information specifying valid data from the controller, writes valid data from the data stored in the memory to a second location on the memory chip.

Description

[0001] [ CROSS-REFERENCE TO RELATED APPLICATIONS ]

[0002] This application claims the benefit of priority based on Japanese Patent Application No. 2020-148337 (filing date: September 3, 2020), the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present embodiment relates to a non-volatile memory, a memory system, and a control method of the non-volatile memory. Background Art

[0004] An SSD (Solid State Drive) is an example of a memory system. An SSD includes non-volatile memory, such as NAND (Not-And) flash memory. Non-volatile memory, for example, includes multiple blocks. Each block can be a unit of erased data. To continue operation, the SSD performs compaction, gathering multiple valid data fragments stored in multiple blocks of the non-volatile memory and writing the gathered valid data back to at least one block of the non-volatile memory. Compaction organizes the blocks of the non-volatile memory. Summary of the Invention

[0005] This embodiment provides a nonvolatile memory, a memory system, and a compression method capable of performing compression at high speed.

[0006] According to this embodiment, a nonvolatile memory includes a memory chip and a command processing unit. The command processing unit controls data writing or reading from the memory chip according to commands received from a controller. Upon receiving a first command from the controller for compressing the memory chip, the command processing unit stores data read from a first location in the memory chip in the memory and sends validation determination information to the controller for determining whether the data is valid. Upon receiving a second command from the controller for compressing the memory chip and validation determination information specifying valid data, the command processing unit writes valid data from the data stored in the memory to a second location in the memory chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a block diagram showing an example of the configuration of a memory system including the nonvolatile memory according to this embodiment.

[0008] Figure 2 This is a diagram for explaining the outline of compression.

[0009] Figure 3This is a diagram showing an example of usage of a storage device included in the controller of the memory system according to this embodiment.

[0010] Figure 4 This is a block diagram showing an example of cooperation between the processor and the instruction processing unit according to this embodiment.

[0011] Figure 5 This is a block diagram showing an example of the configuration of the nonvolatile memory according to this embodiment.

[0012] Figure 6 This is a diagram showing an example of the relationship between pages and frames in the memory chip of this embodiment.

[0013] Figure 7 This is a diagram illustrating changes in frames read from two memory planes according to the compressed read command of this embodiment.

[0014] Figure 8 This is a diagram illustrating changes in frames written to two memory planes according to a compression write command according to this embodiment.

[0015] Figure 9 This is a diagram showing an example of valid frame determination performed by the memory system of this embodiment.

[0016] Figure 10 This is a diagram showing an example of a command sent from a controller to a command processing unit for reading during compression.

[0017] Figure 11 This is a diagram showing an example of a command sent from the controller to the command processing unit for writing during compression.

[0018] Figure 12 This is a diagram showing an example of cooperation between the controller and the command processing unit according to this embodiment.

[0019] Figure 13 This is a flowchart showing an example of processing executed by the command processing unit and the controller in this embodiment.

[0020] Figure 14 This is a diagram showing an example of a method for manufacturing the nonvolatile memory according to this embodiment.

[0021] Figure 15 This is a block diagram showing an example of the configuration of a memory system of a comparative example.

[0022] Figure 16 This is a diagram showing an example of data conversion when the memory system of this embodiment receives a write command and a read command from a host device.

[0023] Figure 17FIG. 1 is a diagram showing an example of data conversion during compression performed by a memory system of a comparative example.

[0024] Figure 18 This is a diagram showing an example of data conversion during compression performed by the memory system of this embodiment. DETAILED DESCRIPTION

[0025] Hereinafter, the present embodiment will be described with reference to the accompanying drawings. In the following description, substantially the same functions and components are denoted by the same reference numerals, and repeated descriptions are only performed when necessary. In addition, the numerical values ​​and the number of components described in the present embodiment are examples and can be appropriately changed.

[0026] In this embodiment, the nonvolatile memory includes a command processing unit and a memory cell array. The command processing unit performs compression according to a command received from a controller. In this embodiment, compression can be referred to as garbage collection.

[0027] Figure 1 1 is a block diagram showing an example of the configuration of a memory system 1 including nonvolatile memories NM00 to NM33 according to the present embodiment.

[0028] Memory system 1 is, for example, an SSD. Memory system 1 can be any of a variety of storage devices, including a hard disk drive (HDD), a USB (Universal Serial Bus) memory, a memory card, a hybrid storage system including a hard disk drive and an SSD, an optical disk device, and the like. Memory system 1 is capable of communicating with a host device (e.g., an external information processing device) 2.

[0029] The memory system 1 includes a nonvolatile memory device NMM and a controller 3 .

[0030] The nonvolatile memory device NMM includes nonvolatile memories NM00 ˜ NM33 .

[0031] The controller 3 controls data writing to the nonvolatile memory device NMM and data reading from the nonvolatile memory device NMM. More specifically, the controller 3 controls the nonvolatile memories NM00 to NM33 according to instructions received from the host device 2.

[0032] Controller 3 includes a host interface unit 4, a storage device such as SRAM (Static Random Access Memory) 5, a processor 6, a DMAC (Direct Memory Access Controller) 7, and memory interface units MI0-MI3. The host interface unit 4, SRAM 5, processor 6, DMAC 7, and memory interface units MI0-MI3 of controller 3 can mutually transmit and receive data, information, signals, commands, requests, messages, instructions, and responses via a bus.

[0033] First, nonvolatile memories NM00 to NM33 and their components will be described.

[0034] The nonvolatile memories NM00 to NM33 are nonvolatile semiconductor memories having a three-dimensional structure. However, the nonvolatile memories NM00 to NM33 may be other types of memories that require compression.

[0035] Specifically, the nonvolatile memories NM00 to NM33 may be, for example, NAND flash memories. Alternatively, the nonvolatile memories NM00 to NM33 may be, for example, NOR (Not Or) flash memories, MRAM (Magnetoresistive Random Access Memory), PRAM (Phase Change Random Access Memory), ReRAM (Resistive Random Access Memory), FeRAM (Ferroelectric Random Access Memory), or any other nonvolatile semiconductor memory.

[0036] Nonvolatile memories NM00 through NM33 are grouped into banks bk0 through bk3, which are further grouped into channels ch0 through ch3. Bank bk0 corresponds to nonvolatile memories NM00, NM10, NM20, and NM30. Bank bk1 corresponds to nonvolatile memories NM01, NM11, NM21, and NM31. Bank bk2 corresponds to nonvolatile memories NM02, NM12, NM22, and NM32. Bank bk3 corresponds to nonvolatile memories NM03, NM13, NM23, and NM33.

[0037] The nonvolatile memories NM00 to NM03 are each connected to the memory bus MB0. The nonvolatile memories NM00 to NM03 correspond to the channel ch0.

[0038] Nonvolatile memory NM00 includes a command processing unit CP00 and a memory chip (e.g., an array chip) MC00. Memory chip MC00 is an example of a memory device. Nonvolatile memory NM01 includes a command processing unit CP01 and a memory chip MC01. Nonvolatile memory NM02 includes a command processing unit CP02 and a memory chip MC02. Nonvolatile memory NM03 includes a command processing unit CP03 and a memory chip MC03.

[0039] Each of the memory chips MC00 to MC03 has a memory cell array. Each of the memory chips MC00 to MC03 may be, for example, a NAND flash memory die. Storing data in a nonvolatile state in the memory cells of the memory chips MC00 to MC03 may be referred to as "programming," for example.

[0040] The command processing unit CP00 is an example of a control unit that controls the memory chip MC00. The command processing unit CP00 is formed of, for example, a CMOS (Complementary Metal Oxide Semiconductor).

[0041] The command processing unit CP00 receives a command from the controller 3 via the memory bus MB0 and controls the memory chip MC00 according to the command.

[0042] The command processing unit CP00 cooperates with the controller 3 to assist in the compression of the memory chip MC00 .

[0043] Specifically, the command processing unit CP00 receives, for example, a write command, a write destination physical address, and write data from the controller 3, and writes the write data to the location specified by the write destination physical address in the memory chip MC00. The command processing unit CP00 receives, for example, a read command and a read destination physical address from the controller 3, and reads the read data from the location specified by the read destination physical address in the memory chip MC00, and sends the read data to the controller 3.

[0044] Similarly, each of the command processing units CP01 to CP03 receives a command from the controller 3 via the memory bus MB0 and controls each of the memory chips MC01 to MC03 according to the command.

[0045] The nonvolatile memories NM10 to NM13 are each connected to the memory bus MB1. The nonvolatile memories NM10 to NM13 correspond to the channel ch1.

[0046] Nonvolatile memory NM10 includes a command processing unit CP10 and a memory chip MC10. Nonvolatile memory NM11 includes a command processing unit CP11 and a memory chip MC11. Nonvolatile memory NM12 includes a command processing unit CP12 and a memory chip MC12. Nonvolatile memory NM13 includes a command processing unit CP13 and a memory chip MC13.

[0047] Each of the command processing units CP10 to CP13 receives a command from the controller 3 via the memory bus MB1 and controls each of the memory chips MC10 to MC13 according to the command.

[0048] The nonvolatile memories NM20 to NM23 are each connected to the memory bus MB2 and correspond to the channel ch2.

[0049] Nonvolatile memory NM20 includes a command processing unit CP20 and a memory chip MC20. Nonvolatile memory NM21 includes a command processing unit CP21 and a memory chip MC21. Nonvolatile memory NM22 includes a command processing unit CP22 and a memory chip MC22. Nonvolatile memory NM23 includes a command processing unit CP23 and a memory chip MC23.

[0050] Each of the command processing units CP20 to CP23 receives a command from the controller 3 via the memory bus MB2 and controls each of the memory chips MC20 to MC23 according to the command.

[0051] The nonvolatile memories NM30 to NM33 are each connected to the memory bus MB3. The nonvolatile memories NM30 to NM333 correspond to the channel ch3.

[0052] Nonvolatile memory NM30 includes a command processing unit CP30 and a memory chip MC30. Nonvolatile memory NM31 includes a command processing unit CP31 and a memory chip MC31. Nonvolatile memory NM32 includes a command processing unit CP32 and a memory chip MC32. Nonvolatile memory NM33 includes a command processing unit CP33 and a memory chip MC33.

[0053] Each of the command processing units CP30 to CP33 receives a command from the controller 3 via the memory bus MB3 and controls each of the memory chips MC30 to MC33 according to the command.

[0054] In order to simplify the description, the following description will be given using the nonvolatile memory NM00 among the nonvolatile memories NM00 to NM33.

[0055] In order to simplify the description below, the memory buses MB0 to MB3 will be described and explained only when necessary.

[0056] In this embodiment, the command processing unit CP00 performs error correction processing. During compression, the command processing unit CP00 extracts validity determination information (hereinafter referred to as the redundant portion) used to determine whether data is valid, and writes only data determined to be valid (hereinafter referred to as valid data) to erased blocks in the memory chip MC00.

[0057] In this embodiment, the redundant portion includes a logical address. The redundant portion may be, for example, metadata of the data corresponding to the redundant portion. Metadata refers to, for example, various attribute information about the data.

[0058] Specifically, the command processing unit CP00 receives a compression read command and a physical address of a read destination from the processor 6 via the memory interface unit MI0. Here, the compression read command is an instruction for reading data from a block to be compressed (hereinafter referred to as an original block). Upon receiving the compression read command and the physical address of the read destination, the command processing unit CP00 reads data from the location specified by the physical address of the read destination in the memory chip MC00. The command processing unit CP00 performs error correction processing on the read data.

[0059] If a data error cannot be corrected, the command processing unit CP00 sends the data and redundant portion to the processor 6 via the memory interface unit MI0. In this case, the correction unit CR0 of the memory interface unit MI0 performs error correction processing on the data and redundant portion. The processor 6 determines whether the data is valid or invalid based on the error-corrected data and redundant portion, the address translation table AT, and the physical address of the read destination. The processor 6 then sends a command (a write command in this embodiment) to write valid data to the write destination block (hereinafter referred to as the destination block) in the non-volatile memories NM00-NM33 via the memory interface unit MI0, along with the write destination physical address, valid data, and the redundant portion corresponding to the valid data.

[0060] The command processing unit CP00 receives a write command, a write destination physical address, valid data, and a redundant portion from the processor 6 via the memory interface unit MI0. Upon receiving the write command, the write destination physical address, valid data, and redundant portion, the command processing unit CP00 writes the valid data and redundant portion to the location specified by the write destination physical address in any of the memory chips MC00 to MC33.

[0061] If the data error can be corrected, the command processing unit CP00 sends a redundant portion (redundant portion data output) appended to the data and including the logical address to the processor 6 via the memory interface unit MI0. In this case, the command processing unit CP00 does not send the data to the processor 6 via the memory interface unit MI0. The processor 6 determines whether the data is valid or invalid based on the received redundant portion, the address translation table AT, and the physical address of the read destination. The processor 6 then sends a compression write command (compression programming command), the physical address of the write destination, and the redundant portion corresponding to the valid data to the command processing unit CP00 via the memory interface unit MI0. Here, the compression write command is a command for writing valid data to the destination block.

[0062] The command processing unit CP00 receives a compression write command, a write destination physical address, and a redundant portion (data input for the redundant portion) from the processor 6 via the memory interface unit MI0. Upon receiving the compression write command, the write destination physical address, and the redundant portion, the command processing unit CP00 writes the data corresponding to the redundant portion and the redundant portion to the location specified by the write destination physical address in the memory chip MC00.

[0063] In the present embodiment, the process executed when the command processing unit CP00 receives a compression write command from the processor 6 via the memory interface unit MI0 is called compression write.

[0064] When receiving an erase command and a physical address of an erase destination corresponding to an original block from the processor 6 via the memory interface unit MI0 , the command processing unit CP00 erases the location specified by the physical address of the erase destination in the memory chip MC00 .

[0065] Next, the controller 3 and its components will be described.

[0066] For example, during compression, the controller 3 issues a compression read command and a compression write command to any one of the nonvolatile memories NM00 to NM33.

[0067] The host interface unit 4 receives data, information, signals, commands, requests, messages, instructions, responses, etc. from the host device 2 in accordance with a prescribed standard. In addition, the host interface unit 4 transmits data, information, signals, commands, requests, messages, instructions, responses, etc. to the host device 2.

[0068] The prescribed standard may be, for example, the NVMe (Non-Volatile Memory Express) standard, the PCIe (Peripheral Component Interconnect Express) standard, the SATA (Serial Advanced Technology Attachment) standard, or the SAS (Serial Attached Small Computer System Interface) standard.

[0069] The SRAM 5 stores, for example, the firmware FW1 and the address translation table AT. Alternatively, other memories such as DRAM (Dynamic Random Access Memory) may be used in place of the SRAM 5. Furthermore, the controller 3 may include both the SRAM 5 and the DRAM.

[0070] The firmware FW1 is an example of software executed by the processor 6. The firmware FW1 includes, for example, code and data. When executed by the processor 6, the firmware FW1 causes any of the command processing units CP00 to CP33 included in the nonvolatile memories NM00 to NM33 to perform compression.

[0071] The address translation table AT associates the logical addresses and physical addresses of data stored in nonvolatile memories NM00-NM33. The address translation table AT can also be referred to as a lookup table. For example, the logical address can be an LBA (Logical Block Addressing). The physical address can be a PBA (Physical Block Addressing).

[0072] For example, the DMAC 7 transfers data stored in a memory included in the host device 2 or data stored in a memory included in the memory system 1 to another memory according to an instruction from the processor 6 .

[0073] Memory interface units MI0-MI3 each correspond to channels ch0-ch3. Writing to or reading from nonvolatile memories NM00-NM03 via memory interface unit MI0, writing to or reading from nonvolatile memories NM10-NM13 via memory interface unit MI1, writing to or reading from nonvolatile memories NM20-NM23 via memory interface unit MI2, and writing to or reading from nonvolatile memories NM30-NM33 via memory interface unit MI3 can be performed in parallel. In other words, controller 3 can perform writing to or reading from multiple channels ch0-ch3 in parallel. Memory interface units MI0-MI3 each include correction units CR0-CR3.

[0074] Correction units CR0-CR3 perform error detection and error correction processing, for example using ECC (Error Correcting Code), on data received from nonvolatile memories NM00-NM03, NM10-NM13, NM20-NM23, and NM30-NM33, respectively. Correction units CR0-CR3 perform higher error correction capabilities, such as soft bit correction, than command processing units CP00-CP33.

[0075] In addition, the soft bit correction may be executed by the processor 6 instead of the correction units CR0 to CR3. The controller 3 may include a dedicated device or circuit for executing the soft bit correction.

[0076] In this embodiment, soft bit correction refers to performing error detection and error correction using likelihood information such as log likelihood ratios (LLRs), which represent the probability of a 0 or 1. For example, LDPC (Low-Density Parity-Check) codes are used as error correction codes. In soft bit correction, for example, soft bit information obtained through soft bit reading from memory interface units MI0 to MI3 is used to calculate LLR values, and the calculated LLR values ​​are used. Soft bit reading, for example, involves reading data from a memory cell using the same read voltage used for hard bit reading and two or more read voltages set at predetermined steps relative to the read voltage used for hard bit reading. Soft bit information can be a combination of multiple data points obtained through soft bit reading, or data obtained by performing a logical operation on these multiple data points.

[0077] The processor 6 executes various controls according to the firmware FW1.

[0078] The processor 6 is, for example, any one of various processing devices such as a CPU (Central Processing Unit), an MPU (Micro-Processing Unit), a DSP (Digital Signal Processor), or a GPU (Graphics Processing Unit).

[0079] For example, when the memory system 1 is activated, the processor 6 reads the firmware FW1 and the address translation table AT from at least one of the nonvolatile memories NM00 to NM33 via at least one of the memory interfaces MI0 to MI3 and stores the firmware FW1 and the address translation table AT in the SRAM 5 .

[0080] For example, when the memory system 1 is stopped, the processor 6 writes the address translation table AT stored in the SRAM 5 into at least one of the nonvolatile memories NM00 to NM33 via at least one of the memory interface units MI0 to MI3 .

[0081] In this embodiment, the processor 6 sends a command for executing compression (e.g., a compressed read command, a compressed move command, a compressed write command, an erase command, etc.) to at least one of the command processing units CP00-CP33 via at least one of the memory interface units MI0-MI3. If at least one of the command processing units CP00-CP33 cannot correct an error during compression, the processor 6 executes compression on behalf of at least one of the command processing units CP00-CP33.

[0082] The operation of the processor 6 during compression in this embodiment will be described in detail.

[0083] The processor 6 selects an original block to be compressed from the nonvolatile memories NM00 to NM33 based on the address translation table AT stored in the SRAM 5 .

[0084] For example, the processor 6 may select a block having the number of invalid data equal to or greater than a first threshold value from among the blocks of the memory chips MC00 to MC33 as the original block.

[0085] For example, the processor 6 may select, from among the blocks of the memory chips MC00 to MC33 , a block having an invalid data ratio equal to or greater than a second threshold value as the original block.

[0086] For example, the processor 6 may select a predetermined number of blocks having a total invalid data count equal to or greater than a third threshold value from among the blocks of the memory chips MC00 to MC33 as original blocks.

[0087] For example, the processor 6 may select a predetermined number of blocks having the highest invalid data ratio from among the blocks of the memory chips MC00 to MC33 as original blocks.

[0088] The following description assumes that the processor 6 selects a block of the nonvolatile memory NM00 as an original block.

[0089] In order to read the data stored in the original block, the processor 6 sends a compression read command and a physical address of a read destination to the command processing unit CP00 via the memory interface unit MI0.

[0090] When the instruction processing unit CP00 cannot correct the error, the processor 6 first receives the data and redundant part corrected by the correction unit CR0 from the instruction processing unit CP00 via the memory interface unit MI0. Then, the processor 6 saves the data and redundant part corrected by the correction unit CR0 in the SRAM5. Next, based on the address translation table AT, the logical address contained in the redundant part, and the physical address of the read destination, the processor 6 determines whether the data corresponding to the redundant part stored in the SRAM5 is valid data. Next, the processor 6 selects a destination block from the free blocks. Next, in order to write valid data to the destination block in the memory chips MC00 to MC33, the processor 6 sends the compressed write instruction, the physical address of the write destination, and the valid data to at least one of the instruction processing units CP00 to CP33 via at least one of the memory interface units MI0 to MI3.

[0091] If the command processing unit CP00 is able to correct the data error, the processor 6 first receives the redundant portion from the command processing unit CP00 via the memory interface unit MI0. Next, based on the address translation table AT stored in the SRAM 5, the physical address of the read destination, and the logical address contained in the redundant portion, the processor 6 determines whether the data corresponding to the redundant portion stored in the command processing unit CP00 is valid data. Next, the processor 6 selects a destination block from the free blocks in the memory chip MC00. Next, the processor 6 sends the compression write command, the physical address of the write destination, and the redundant portion corresponding to the valid data to the command processing unit CP00 via the memory interface unit MI0.

[0092] After sending the compression write command, the processor 6 sends an erase command for erasing the original block and the physical address of the erase destination to the command processing unit CP00 via the memory interface unit MI0. Furthermore, the processor 6 uses the physical address of the write destination to update the physical address of the read destination associated with the logical address of the valid data in the address translation table AT stored in the SRAM 5. The processor 6 manages the erased original block as a free block.

[0093] Figure 2This is a diagram for explaining the outline of compression.

[0094] Each of the memory chips MC00 to MC33 includes a plurality of blocks. The memory system 1 manages the blocks in which no data has been written among the plurality of blocks as free blocks. When a write instruction, a logical address of a write destination, and data are received from the host device 2, the memory system 1 obtains the physical address of the write destination according to the logical address of the write destination, and writes the data to the location specified by the physical address of the write destination. As the memory system 1 writes data to the block, the amount of invalid data in the block increases, and the valid data in the block is fragmented. For example, the memory system 1 writes (moves) valid data in an original block whose ratio or amount of invalid data is greater than a specified value to a destination block selected from the free blocks. When the movement of valid data from the original block to the destination block is completed, the memory system 1 manages the original block as a free block and erases the free block at a specified time. Thus, the memory system 1 can continue the write process according to the write instruction received from the host device 2.

[0095] Figure 3 This is a diagram showing an example of the use of the SRAM 5 according to this embodiment.

[0096] At least a portion of the SRAM 5 is used as a cache memory 5 a for storing the code of the firmware FW1 .

[0097] At least a portion of the SRAM 5 is used as a cache memory 5 b for storing data of the firmware FW1 .

[0098] At least a portion of the SRAM 5 is used as a read cache memory 5 c for storing data read from any of the nonvolatile memories NM00 to NM33 via any of the memory interface units MI0 to MI3 .

[0099] At least a portion of the SRAM 5 is used as a cache memory 5d for storing the address translation table AT.

[0100] At least a portion of the SRAM 5 is used as a write buffer memory 5 e for storing data written to any of the nonvolatile memories NM00 to NM33 via any of the memory interface units MI0 to MI3 .

[0101] During compression, at least a portion of the SRAM 5 is used as a compression read memory 5f for storing redundant parts received from any of the command processing units CP00 to CP33 via any of the memory interfaces MI0 to MI3, etc. The compression read memory 5f is, for example, a buffer memory.

[0102] During compression, at least a portion of the SRAM 5 is used as a compression write memory 5g for storing redundant data sent to any of the command processing units CP00 to CP33 via any of the memory interfaces MI0 to MI3. The compression write memory 5g is, for example, a buffer memory.

[0103] Figure 4 This is a block diagram showing an example of cooperation between the processor 6 and the command processing unit CP00 according to this embodiment.

[0104] In the case of performing compression on the nonvolatile memory NM00, the processor 6 selects an original block from the memory chip MC00 based on the address translation table AT.

[0105] In order to read the data stored in the original block, the processor 6 sends a compression read command and a physical address of a read destination to the command processing unit CP00 via the memory interface unit MI0.

[0106] When receiving the compressed read command and the physical address of the read destination, the command processing part CP00 reads the data and the redundant part from the location specified by the physical address of the read destination in the memory chip MC00 .

[0107] The command processing unit CP00 performs error correction processing on the read data and the redundant portion.

[0108] In this embodiment, the compression operation switches between a case where the command processing unit CP00 cannot correct errors in the data and redundant portion and a case where the errors can be corrected.

[0109] First, the operation when the command processing unit CP00 cannot correct errors in the read data and redundant portion will be described.

[0110] When errors cannot be corrected for the data and the redundant portion, the command processing portion CP00 transmits the data and the redundant portion to the memory interface portion MI0.

[0111] The correction unit CR0 of the memory interface unit MI0 performs error correction processing on the data and redundant portion received from the command processing unit CP00 , and then transmits the error-corrected data and redundant portion to the processor 6 .

[0112] The processor 6 receives the error-corrected data and the redundant portion from the memory interface unit MI0 and stores the received data and the redundant portion in the SRAM 5 .

[0113] The processor 6 determines whether the data stored in the SRAM 5 is valid data based on the address translation table AT, the logical address included in the redundant portion, and the physical address of the read destination.

[0114] Processor 6 selects a destination block from the free blocks.

[0115] In order to write valid data to the destination block, the processor 6 sends the compressed write instruction, the physical address of the write destination corresponding to the destination block, the valid data, and the redundant part to at least one of the instruction processing units CP00~CP33 via at least one of the memory interface units MI0~MI3.

[0116] When at least one of the instruction processing units CP00~CP33 receives a compressed write instruction, a physical address of a write destination, valid data, and a redundant part from the processor 6 via at least one of the memory interface units MI0~MI3, the valid data and the redundant part are written to the location specified by the physical address of the write destination.

[0117] Next, the operation of the command processing unit CP00 in the case where errors in the read data and redundant portion can be corrected will be described.

[0118] If errors in the data and the redundant portion can be corrected, the command processing unit CP00 transmits the redundant portion added to the data to the processor 6 via the memory interface unit MI0. In this case, the command processing unit CP00 does not transmit the data to the processor 6.

[0119] When receiving the redundant portion from the command processing unit CP00 via the memory interface unit MI0 , the processor 6 stores the redundant portion in the SRAM 5 .

[0120] The processor 6 determines whether the data corresponding to the redundant portion stored in the command processing unit CP00 is valid data based on the address translation table AT, the logical address included in the redundant portion, and the physical address of the read destination.

[0121] The processor 6 selects a destination block from the free blocks of the memory chip MC00.

[0122] To write valid data to a destination block in the memory chip MC00 , the processor 6 sends a compression write command, a physical address of a write destination corresponding to the destination block, and a redundant portion to the command processing unit CP00 via the memory interface unit MI0 .

[0123] When receiving a compression write instruction, a physical address of a write destination, and a redundant part from the processor 6 via the memory interface unit MI0, the instruction processing unit CP00 writes the valid data and the redundant part corresponding to the received redundant part to the location specified by the physical address of the write destination in the memory chip MC00.

[0124] After sending the compression write command, the processor 6 sends an erase command for erasing the original block and the physical address of the erase destination corresponding to the original block to the command processing unit CP00 via the memory interface unit MI0.

[0125] When receiving an erase command and a physical address of an erase destination from the processor 6 via the memory interface unit MI0 , the command processing unit CP00 erases the location specified by the physical address of the erase destination in the memory chip MC00 .

[0126] The processor 6 uses the physical address of the write destination to update the physical address of the read destination associated with the logical address corresponding to the valid data in the address translation table AT stored in the SRAM 5. The processor 6 manages the erased original block as a free block.

[0127] Figure 5 1 is a block diagram showing an example of the configuration of the nonvolatile memory NM00 according to this embodiment. The nonvolatile memories NM01 to NM33 may have the same configuration as that of the nonvolatile memory NM00.

[0128] The nonvolatile memory NM00 includes a command processing unit CP00 and a memory chip MC00.

[0129] The command processing unit CP00 is connected to the controller 3 via the memory bus MB0 and the power supply line PL. The command processing unit CP00 includes control circuits CPA and CPB. Each component of the control circuits CPA and CPB may be formed by an electronic circuit.

[0130] The control circuit CPA is connected to the controller 3. The control circuit CPB is connected to the input / output (I / O) section of the memory chip MC00.

[0131] The control circuit CPA and the control circuit CPB are connected via a control bus 22 and a data bus 23 .

[0132] The control circuit CPA includes an interface unit 8 , an interface control unit 9 , a command control unit 10 , a data buffer control unit 11 , a memory 12 , a randomization processing unit 13 , and an error correction processing unit 14 .

[0133] The interface unit 8 is connected to the controller 3 via the memory bus MB0 , and is also connected to the control bus 22 and the data bus 23 .

[0134] The interface control unit 9 , the command control unit 10 , the data buffer control unit 11 , the memory 12 , the randomization processing unit 13 , and the error correction processing unit 14 are connected to a control bus 22 .

[0135] The memory 12 , the randomization processing unit 13 , and the error correction processing unit 14 are connected to a data bus 23 .

[0136] The interface unit 8 receives data, information, signals, commands, requests, messages, instructions, responses, etc. from the controller 3 . In addition, the interface unit 8 sends data, information, signals, commands, requests, messages, instructions, responses, etc. to the controller 3 .

[0137] The interface control unit 9 controls the interface unit 8 .

[0138] The command control unit 10 interprets a command or request received from the controller 3 via the interface unit 8 and controls various components of the command processing unit CP00 according to the command or request.

[0139] The memory 12 temporarily stores data received from the controller 3 and data read from the memory chip MC00. The memory 12 is, for example, a buffer memory or a cache memory. The memory 12 can also be, for example, an SRAM, a DRAM, or a register. The memory 12 can be a volatile memory or a non-volatile memory.

[0140] The data buffer control unit 11 manages the use (eg, the area in use or the free area) of the memory 12. The data buffer control unit 11 manages the correspondence between the areas of the memory 12 and the data to be written to the memory chip MC00.

[0141] The randomization processing unit 13 randomizes the data to be written to the memory chip MC00. Here, randomization refers to randomly arranging the data pattern based on the randomization key so that data with the same pattern is not continuously included. This randomization prevents bit errors. Hereinafter, the randomized data is referred to as randomized data.

[0142] The randomization processing unit 13 derandomizes the randomized data read from the memory chip MC00. Derandomization here means obtaining the original data before randomization from the randomized data based on the randomization key.

[0143] The error correction processing unit 14 encodes the data written into the memory chip MC00. In this embodiment, the encoding adds a parity check portion to the randomized data and the redundant portion.

[0144] The error correction processing unit 14 decodes the randomized data and redundant portion read from the memory chip MC00 and performs error correction processing. Specifically, the error correction processing unit 14 performs hard bit correction, for example, which has a lower error correction capability than the correction units CR0 to CR3.

[0145] In this embodiment, hard bit correction refers to performing error detection and error correction on the read data using hard bit read by the command processing unit CP00. Error correction codes such as Bose-Chaudhuri-Hochwengem (BCH) codes or RS (Reed-Solomon) codes are used. Hard bit read, for example, involves reading data from a memory cell using a reference read voltage or a voltage offset from the reference read voltage by a predetermined voltage.

[0146] The control circuit CPB includes a power supply control unit 15 , an address register 16 a , a command register 16 b , a status register 16 c , a memory control unit 17 , a row decoder 18 , a column decoder 19 , a data cache 20 , and a sense amplifier 21 .

[0147] The power supply control unit 15 is connected to the controller 3 via a power supply line PL. The power supply control unit 15 controls the power supply to the memory chip MC00, the address register 16a, the command register 16b, the status register 16c, the memory control unit 17, the row decoder 18, the column decoder 19, the data cache memory 20, and the sense amplifier 21. The address register 16a, the command register 16b, the status register 16c, and the memory control unit 17 are connected to a control bus 22. The column decoder 19 is connected to a data bus 23. The row decoder 18, the column decoder 19, the data cache memory 20, and the sense amplifier 21 are connected to the memory control unit 17. The column decoder 19 controls the column gates of the memory chip MC00 according to the column address. The power supply control unit 15, the row decoder 18, and the sense amplifier 21 are connected to the input and output units of the memory chip MC00. The row decoder 18 selects and drives the word lines and select gate lines of the memory chip MC00 according to the column address. More specifically, row decoder 18 controls the potentials of the electrode layer, drain select gate, and source select gate of the memory cell array in memory chip MC00. Sense amplifier 21 is connected to the bit line of memory chip MC00, reads the potential of the bit line, and amplifies the read potential.

[0148] The following describes Figure 5 The nonvolatile memory NM00 is executed when receiving a write command (program command) from the controller 3 via the memory bus MB0.

[0149] The command control unit 10 receives a write command, a physical address of a write destination, and a randomization key from the controller 3 via the memory bus MB0 , the interface unit 8 , and the control bus 22 .

[0150] Furthermore, the command control unit 10 stores the data to be written and the redundant portion received from the controller 3 via the memory bus MB0 by the interface unit 8 in the memory 12 via the data bus 23 .

[0151] The command control unit 10 uses the randomization processor 13 and the randomization key to randomize the data stored in the memory 12 as the write target, and stores the randomized data in the memory 12. Alternatively, the command control unit 10 may use another memory such as the data cache memory 20 instead of the memory 12 to randomize the data.

[0152] The instruction control unit 10 uses the error correction processing unit 14 to generate a parity check unit for the randomized data and the redundant unit stored in the memory 12, and stores the parity check unit in the memory 12. Alternatively, the instruction control unit 10 may use another memory such as the data cache memory 20 instead of the memory 12 to perform error correction processing on the randomized data and the redundant unit.

[0153] The command control unit 10 transmits a write command, a row address, and a column address to the memory control unit 17 via the control bus 22 .

[0154] The instruction control unit 10 stores the randomized data, the redundant portion, and the parity portion stored in the memory 12 in the data cache memory 20 via the data bus 23 .

[0155] The memory control unit 17 receives a write command, a row address, and a column address from the command control unit 10 via the control bus 22 .

[0156] The memory control unit 17 stores the row address and the column address in the address register 16 a and stores the write command in the command register 16 b .

[0157] The memory control unit 17 controls the row decoder 18 according to the row address of the address register 16a. The memory control unit 17 controls the column decoder 19 according to the column address of the address register 16a. The memory control unit 17 then amplifies the randomized data, redundant portion, and parity portion stored in the data cache memory 20 using the sense amplifier 21 and writes (programs) them into the memory chip MC00.

[0158] The memory control unit 17 stores a status indicating the writing result in the status register 16 c.

[0159] The command control unit 10 transmits the status stored in the status register 16 c to the controller 3 via the control bus 22 , the interface unit 8 , and the memory bus MB0 .

[0160] Next, explain Figure 5The nonvolatile memory NM00 is executed when receiving a read instruction from the controller 3 via the memory bus MB0.

[0161] The command control unit 10 receives a read command, a physical address of a read destination, and a randomization key from the controller 3 via the memory bus MB0 , the interface unit 8 , and the control bus 22 .

[0162] The command control unit 10 sends a read command, a row address, and a column address to the memory control unit 17 via the control bus 22 .

[0163] The memory control unit 17 receives a read command, a row address, and a column address from the command control unit 10 via the control bus 22 .

[0164] The memory control unit 17 stores the row address and the column address in the address register 16 a and stores the read command in the command register 16 b .

[0165] The memory control unit 17 controls the row decoder 18 according to the row address of the address register 16a. The memory control unit 17 controls the column decoder 19 according to the column address of the address register 16a. The memory control unit 17 then reads the randomized data, redundant portion, and parity portion from the memory chip MC00 and stores them in the data cache 20.

[0166] The instruction control unit 10 stores the randomized data, the redundant portion, and the parity portion stored in the data cache memory 20 in the memory 12 via the data bus 23 .

[0167] The memory control unit 17 stores a status indicating the read result in the status register 16 c.

[0168] The command control unit 10 uses the error correction processing unit 14 to perform error correction processing on the randomized data, redundant portion, and parity portion stored in the memory 12 , and stores the randomized data and redundant portion after error correction in the memory 12 .

[0169] The command control unit 10 derandomizes the randomized data stored in the memory 12 using the randomization processor 13 and the randomization key, and stores the derandomized data in the memory 12 .

[0170] The command control unit 10 transmits the derandomized data and the redundant portion to the controller 3 via the data bus 23 , the interface unit 8 , and the memory bus MB0 .

[0171] The command control unit 10 transmits the status stored in the status register 16 c to the controller 3 via the control bus 22 , the interface unit 8 , and the memory bus MB0 .

[0172] Next, explain Figure 5 The nonvolatile memory NM00 executes a compression read process when receiving a compression read instruction from the controller 3 via the memory bus MB0.

[0173] The command control unit 10 includes a processing unit 10a. The memory 12 includes a compression read buffer 12a and a compression write buffer 12b.

[0174] The processing unit 10 a receives a compression read command, a physical address of a read destination, and a randomization key from the controller 3 via the memory bus MB0 , the interface unit 8 , and the control bus 22 .

[0175] The processing unit 10 a sends the compression read command, the row address, and the column address to the memory control unit 17 via the control bus 22 .

[0176] The memory control unit 17 receives the compression read command, the row address, and the column address from the processing unit 10 a via the control bus 22 .

[0177] The memory control unit 17 stores the row address and the column address in the address register 16 a , and stores the compression read command in the command register 16 b .

[0178] The memory control unit 17 controls the row decoder 18 according to the row address of the address register 16a. The memory control unit 17 controls the column decoder 19 according to the column address of the address register 16a. The memory control unit 17 then reads the randomized data, redundant portion, and parity portion from the memory chip MC00 and stores the randomized data, redundant portion, and parity portion in the data cache memory 20.

[0179] The processing unit 10 a stores the randomized data, the redundant portion, and the parity portion stored in the data cache memory 20 in the memory 12 via the data bus 23 .

[0180] The memory control unit 17 stores a status indicating the compressed read result in the status register 16 c.

[0181] The processing unit 10a uses the error correction processing unit 14 to perform error correction processing on the randomized data, redundant portion, and parity portion stored in the memory 12. Here, the error correction processing unit 14 may perform error correction on the randomized data and redundant portion.

[0182] In this case, the processing unit 10 a stores the randomized data and the redundant portion after error correction in the memory 12 .

[0183] The processing unit 10 a derandomizes the randomized data stored in the memory 12 using the randomization processing unit 13 and the randomization key, and stores the derandomized data in the memory 12 .

[0184] The processing unit 10 a transmits the redundant part stored in the memory 12 to the controller 3 via the data bus 23 , the interface unit 8 , and the memory bus MB0 .

[0185] Furthermore, the processing unit 10 a transmits the status stored in the status register 16 c to the controller 3 via the control bus 22 , the interface unit 8 , and the memory bus MB0 .

[0186] The processing unit 10 a stores the derandomized data, the redundant portion, and the parity portion in the compression read buffer 12 a .

[0187] Next, explain Figure 5 The nonvolatile memory NM00 performs compression movement when receiving a compression movement instruction from the controller 3 via the memory bus MB0.

[0188] The processing unit 10 a receives a compression move instruction and a redundant portion corresponding to valid data from the controller 3 via the memory bus MB0 , the interface unit 8 , and the control bus 22 .

[0189] The processing unit 10a stores the valid data corresponding to the received redundant part among the data, redundant part, and parity part stored in the compression read buffer 12a, and the received redundant part, valid data, and parity part of the redundant part in the compression write buffer 12b.

[0190] This compression move is repeatedly executed until the number of valid data stored in the compression write buffer memory 12b reaches a predetermined number or more.

[0191] Next, explain Figure 5 The nonvolatile memory NM00 performs compression writing when receiving a compression writing instruction from the controller 3 via the memory bus MB0.

[0192] The processing unit 10 a receives a compression write command, a physical address of a write destination, a redundant portion, and a randomization key from the controller 3 via the memory bus MB0 , the interface unit 8 , and the control bus 22 .

[0193] The processing unit 10 a randomizes the valid data stored in the compression write buffer 12 b using the randomization processing unit 13 and the randomization key, and stores the randomized data in the compression write buffer 12 b .

[0194] The processing unit 10 a uses the error correction processing unit 14 to generate a parity portion for the randomized data and the redundant portion stored in the compression write buffer 12 b , and stores the parity portion in the compression write buffer 12 b .

[0195] The processing unit 10 a sends the compression write command, the row address, and the column address to the memory control unit 17 via the control bus 22 .

[0196] The processing unit 10 a stores the randomized data, the redundant portion, and the parity portion stored in the compressed write buffer 12 b in the data cache 20 via the data bus 23 .

[0197] The memory control unit 17 receives the compression write command, the row address, and the column address from the command control unit 10 via the control bus 22 .

[0198] The memory control unit 17 stores the row address and the column address in the address register 16 a , and stores the compression write command in the command register 16 b .

[0199] The memory control unit 17 controls the row decoder 18 according to the row address of the address register 16a. The memory control unit 17 controls the column decoder 19 according to the column address of the address register 16a. The memory control unit 17 then amplifies the randomized data, redundant portion, and parity portion stored in the data cache memory 20 using the sense amplifier 21 and writes them to the memory chip MC00.

[0200] The memory control unit 17 stores a status indicating the compression writing result in the status register 16 c.

[0201] The processing unit 10 a transmits the status stored in the status register 16 c to the controller 3 via the control bus 22 , the interface unit 8 , and the memory bus MB0 .

[0202] Figure 6 This is a diagram showing an example of the relationship between pages and frames F0 to F3 in the memory chip MC00 according to the present embodiment.

[0203] Memory chip MC00 includes multiple memory planes PL0 and PL1. Memory plane PL0 includes blocks B0, B2, ..., Bk, and page register PR0. Memory plane PL1 includes blocks B1, B3, ..., Bk+1, and page register PR1. The following description uses block B2 as a representative example, but blocks B1, B3, Bk+1, and B2 are also similar.

[0204] Block B2 includes a plurality of pages and includes a plurality of word lines WL0 to WLm and a plurality of memory cells connected to each of the plurality of word lines WL0 to WLm.

[0205] In this embodiment, a storage cell is a TLC (Triple Level Cell) capable of storing 3 bits of information, or a QLC (Quad Level Cell) capable of storing 4 bits of information. In addition, the storage cell may also be an SLC (Single Level Cell), an MLC (Multi Level Cell), or a cell capable of storing more than 5 bits of information. Figure 6 In the example, the figure shows a case where the storage unit is TLC.

[0206] Hereinafter, a group of memory cells collectively selected during data writing and reading is referred to as a "memory cell group." Furthermore, a collection of 1-bit data written to or read from each of the plurality of memory cells in a memory cell group is referred to as a "page."

[0207] The multiple memory cells connected to the word line WL0 correspond to the memory cell group MCG0. Similarly, the multiple memory cells connected to the word lines WL1 to WLm correspond to the memory cell groups MCG1 to MCGm, respectively. The 3-bit data stored by the TLC are, from the lowest bit, a lower bit, a middle bit, and an upper bit. The set of lower bits stored in the memory cell group MCG0 is a lower page, the set of middle bits stored in the memory cell group MCG0 is a middle page, and the set of upper bits stored in the memory cell group MCG0 is an upper page. The memory cell groups MCG1 to MCGm also include a lower page, a middle page, and an upper page, just like the memory cell group MCG0.

[0208] The lower page corresponding to word line WL0 can store 4 frames using the lower bits of memory cell group MCG0. The middle page corresponding to word line WL0 can store 4 frames F0 to F3 using the middle bits of memory cell group MCG0. The upper page corresponding to word line WL0 can store 4 frames using the upper bits of memory cell group MCG0. Figure 6 , four frames F0 to F3 stored in a middle page corresponding to word line WL0 are shown as an example.

[0209] The number of frames that can be stored using any one of the lower page, the middle page, and the upper page may be changed, and may be, for example, 1 to 3 or 5 or more.

[0210] Frame F0 includes data D, a redundant portion P, and a parity portion Par.

[0211] The data D is, for example, user data or randomized data.

[0212] The redundant portion P includes the logical address LA of the data D.

[0213] The parity part Par includes information for detecting and correcting errors generated in the data D and the redundant part P.

[0214] Furthermore, frames F1 to F3 may include the same information as frame F0.

[0215] Figure 7 1 and 2 are diagrams illustrating changes in frames Fr0a and Fr1a read from memory planes PL0 and PL1 according to the compressed read command of this embodiment.

[0216] The processing unit 10a executes compressed reading of a frame Fr0a from the memory plane PL0. The frame Fr0a includes randomized data Dr, a redundant portion R, and a parity portion Par. The read frame Fr0a may contain an error.

[0217] The error correction processing unit 14 performs error correction processing on the randomized data Dr and the redundant portion R of the frame Fr0a to generate a frame Fr0b.

[0218] The error correction processing unit 14 generates a frame Fr0c obtained by deleting the parity portion Par from the frame Fr0b.

[0219] The randomization processing unit 13 derandomizes the randomized data Dr of the frame Fr0c to generate a frame Fr0d including data D and a redundant portion R.

[0220] The processing unit 10a stores the frame Fr0d in the compressed read buffer memory 12a.

[0221] Furthermore, the frame Fr1a read from the memory plane PL1 changes to frames Fr1b to Fr1d in the same manner as the frame Fr0a.

[0222] Figure 8 This is a diagram illustrating changes in frames Fr0d and Fr1d written to the memory planes PL0 and PL1 according to the compression write command of this embodiment.

[0223] The processing unit 10a reads the frame Fr0d stored in the compressed write buffer memory 12b. The frame Fr0d includes data D and a redundant portion R.

[0224] The randomization processing unit 13 performs randomization on the data D of the frame Fr0d to generate a frame Fr0c including the randomized data Dr and the redundant portion R.

[0225] The error correction processing unit 14 adds the parity portion Par to the randomized data Dr and the redundant portion R of the frame Fr0c to generate a frame Fr0b.

[0226] The processing unit 10 a executes a process for writing the frame Fr0 b into the memory plane PL0 .

[0227] The frame Fr0b written to the memory plane PL0 may contain an error. Figure 8 It is recorded as frame Fr0a.

[0228] Furthermore, the frame Fr1d written to the memory plane PL1 changes to the frames Fr1c to Fr1a similarly to the frame Fr0d.

[0229] Figure 9 1 is a diagram showing an example of valid frame determination executed by the memory system 1 according to the present embodiment.

[0230] The command processing unit CP00 reads frames F0 to F3 stored in the lower page, frames F4 to F7 stored in the middle page, and frames F8 to F11 stored in the upper page from the original page of the memory plane PL0 of the memory chip MC00 to be compressed.

[0231] In addition, the command processing unit CP00 reads frames F12 to F15 stored in the lower page, frames F6 to F19 stored in the middle page, and frames F20 to F23 stored in the upper page from the original page of the memory plane PL1 of the memory chip in parallel with frames F0 to F11.

[0232] Redundant sections R0-R3 are read from the lower pages of the original page of memory plane PL0. Redundant sections R4-R7 are read from the middle pages of the original page of memory plane PL0. Redundant sections R8-R11 are read from the upper pages of the original page of memory plane PL0.

[0233] Redundant sections R12-R15 are read from the lower pages of the original page on memory plane PL1. Redundant sections R16-R19 are read from the middle pages of the original page on memory plane PL1. Redundant sections R20-R23 are read from the upper pages of the original page on memory plane PL1.

[0234] The command processing unit CP00 sends the redundant units R0 to R23 to the controller 3 .

[0235] In this embodiment, multiple redundant parts can be collectively transmitted from the command processing unit CP00 to the controller 3. For example, in memory plane PL0, redundant parts R0 to R3 included in the lower page, redundant parts R4 to R7 included in the middle page, and redundant parts R8 to R11 included in the upper page are sequentially transmitted from the command processing unit CP00 to the controller 3. In other words, redundant parts R0 to R11 are collectively transmitted from the command processing unit CP00 to the controller 3. For example, in memory plane PL1, redundant parts R12 to R15 included in the lower page, redundant parts R16 to R19 included in the middle page, and redundant parts R20 to R23 included in the upper page are sequentially transmitted from the command processing unit CP00 to the controller 3. In other words, redundant parts R12 to R23 are collectively transmitted from the command processing unit CP00 to the controller 3. This can increase the transmission speed.

[0236] The controller 3 determines whether each of the frames F0 to F23 is valid or invalid based on the address translation table AT, the redundant parts R0 to R23 , and the physical address of the original page.

[0237] exist Figure 9 In the example, frames F1, F3, F5, F9 to F11, F14, F15, and F20 to F23, which include redundant portions R1, R3, R5, R9 to R11, R14, R15, and R20 to R23, are valid. Furthermore, frames F0, F2, F4, F6 to F8, F12, F13, and F16 to F19, which include redundant portions R0, R2, R4, R6 to R8, R12, R13, and R16 to R19, are invalid.

[0238] The controller 3 sends the redundant parts R1, R3, R5, R9 to R11, R14, R15, R20 to R23 corresponding to the frames F1, F3, F5, F9 to F11, F14, F15, F20 to F23 determined to be valid to the command processing unit CP00.

[0239] In this embodiment, a plurality of redundant units may be collectively transmitted from the controller 3 to the command processing unit CP00. This can increase the transmission speed.

[0240] During compression writing, the command processing unit CP00 writes the received frames F1, F3, F5, F9 to F11, F14, F15, F20 to F23 including the redundant parts R1, R3, R5, R9 to R11, R14, R15, R20 to R23 to the destination page.

[0241] Figure 10 1 is a diagram showing an example of a command sent from the controller 3 to the command processing unit CP00 for reading during compression.

[0242] First, the command processing unit CP00 receives a Set Feature command CMD1 for setting parameter values, a LUN (Logical Unit Number) address, a feature address, a parameter value, and a busy signal indicating the end of the command from the controller 3. The LUN address specifies any device included in the non-volatile memories NM00 to NM33. The feature address specifies the parameter. The command processing unit CP00 sets the parameter value for the device specified by the LUN address and the parameter specified by the feature address. The command processing unit CP00 can repeatedly (continuously) receive the Set Feature command CMD1 until the busy signal is signaled, and repeatedly (continuously) execute the parameter set.

[0243] In this embodiment, the characteristic address and parameter values ​​of the characteristic command CMD1 are set, for example, to "change a specified non-volatile memory to compression mode or return it to normal operation mode" (mode change). For example, the command processing unit CP00 changes the non-volatile memory NM00 from normal operation mode to compression mode based on the LUN address, characteristic address, and parameter values.

[0244] Furthermore, to change the voltage value information used when executing the compressed read command or the compressed write command, the characteristic address and parameter value added by the characteristic setting command CMD1 are used.

[0245] The instruction processing unit CP00 receives from the controller 3 an address input instruction CMD2a with a randomized key, a column address of the memory plane PL0, a row address of the memory plane PL0, a randomized key of the memory plane PL0, a memory plane switching instruction CMD2b, a busy signal indicating the end of the instruction, an address input instruction CMD2a with a randomized key, a column address of the memory plane PL1, a row address of the memory plane PL1, a randomized key of the memory plane PL1, a compressed read instruction CMD2c, and a busy signal indicating the end of the instruction.

[0246] Then, command processing unit CP00 reads the frame stored at the location corresponding to the column address of memory plane PL0 and the row address of memory plane PL0. Command processing unit CP00 then performs error correction processing on the read frame and derandomizes the randomized data contained in the error-corrected frame using the randomization key of memory plane PL0.

[0247] Furthermore, command processing unit CP00 reads the frame stored at the location corresponding to the column address of memory plane PL1 and the row address of memory plane PL1. Command processing unit CP00 then performs error correction processing on the read frame and derandomizes the randomized data contained in the error-corrected frame using the randomization key of memory plane PL1.

[0248] Furthermore, if error correction cannot be performed on the read frame, the command processing unit CP00 sends the read frame to the controller 3 , and the controller 3 performs error correction processing with higher error correction capability than the command processing unit CP00 on the frame and performs compression.

[0249] If error correction is possible for the read frame, the command processing unit CP00 receives an address input command CMD3a for outputting the redundant portion of the frame, a column address, a row address, a data output (data output start) command CMD3b, and a trigger signal indicating the end of the command from the controller 3. Upon receiving the data output command CMD3b, the command processing unit CP00 transmits the redundant portion corresponding to the column address and row address to the controller 3 without transmitting the data to the controller 3. Alternatively, the command processing unit CP00 may repeatedly (continuously) receive the address input command CMD3a until the trigger signal, and repeatedly (continuously) transmit the redundant portion to the controller 3.

[0250] The command processing unit CP00 receives, from the controller 3, a set feature command CMD1 for terminating compressed read, a LUN address, a feature address, a parameter value, and a busy signal indicating the end of the command. The command processing unit CP00 sets parameter values ​​for the device specified by the LUN address and the parameter specified by the feature address. For example, the command processing unit CP00 switches the non-volatile memory NM00 from compressed mode to normal operation mode based on the LUN address, feature address, and parameter value. The command processing unit CP00 may also repeatedly (continuously) receive the set feature command CMD1 until the busy signal is received, and repeatedly (continuously) terminate the compressed read.

[0251] Figure 11 1 is a diagram showing an example of a command sent from the controller 3 to the command processing unit CP00 for writing during compression.

[0252] The command processing unit CP00 first receives a setting feature command CMD1 for setting parameter values, a LUN address, a feature address, a parameter value, and a busy signal indicating the end of the command from the controller 3. The LUN address specifies any one of the devices included in the non-volatile memories NM00 to NM33. The command processing unit CP00 sets the parameter value for the device specified by the LUN address and the parameter specified by the feature address. For example, the command processing unit CP00 changes the non-volatile memory NM00 from the normal operation mode to the compressed mode based on the LUN address, the feature address, and the parameter value. The command processing unit CP00 may also repeatedly (continuously) receive the command CMD1 until the busy signal is received, and repeatedly (continuously) execute the parameter set.

[0253] The instruction processing unit CP00 receives from the controller 3 a redundant part and an address input instruction CMD2ar with a randomized key for writing in compression, a column address of the memory plane PL0, a row address of the memory plane PL0, a redundant part of the memory plane PL0, a randomized key of the memory plane PL0, a memory plane switching instruction CMD2b, a busy signal indicating the end of the instruction, a redundant part and an address input instruction CMD2ar with a randomized key, a column address of the memory plane PL1, a row address of the memory plane PL1, a redundant part of the memory plane PL1, a randomized key of the memory plane PL1, a compression write instruction CMD2d, and a busy signal indicating the end of the instruction.

[0254] Then, command processing unit CP00 randomizes the received frame data containing the redundant portion of memory plane PL0 using the randomization key of memory plane PL0, generating a frame by adding a parity check portion to the randomized data and the redundant portion of memory plane PL0. Command processing unit CP00 then writes the generated frame to the location corresponding to the column address of memory plane PL0 and the row address of memory plane PL0.

[0255] Furthermore, command processing unit CP00 randomizes the received frame data including the redundant portion of memory plane PL1 using the randomization key, generating a frame by adding a parity portion to the randomized data and the redundant portion of memory plane PL1. Command processing unit CP00 then writes the generated frame to a location corresponding to the column address of memory plane PL1 and the row address of memory plane PL1.

[0256] When receiving the status inquiry from the controller 3 , the command processing unit CP00 transmits a status indicating whether the compression writing has been completed to the controller 3 .

[0257] The command processing unit CP00 receives, from the controller 3, a set feature command CMD1 for terminating compression writing, a LUN address, a feature address, a parameter value, and a busy signal indicating the end of the command. The command processing unit CP00 sets parameter values ​​for the device specified by the LUN address and the parameter specified by the feature address. For example, the command processing unit CP00 switches the non-volatile memory NM00 from compression mode to normal operation mode based on the LUN address, feature address, and parameter value. The command processing unit CP00 may also repeatedly (continuously) receive the set feature command CMD1 until the busy signal is received, and repeatedly (continuously) terminate the compression writing.

[0258] Figure 12 1 is a diagram showing an example of cooperation between the controller 3 and the command processing unit CP00 according to the present embodiment.

[0259] exist Figure 12In FIG, the time during which the command processing unit CP00 executes the compressed read is represented by tR, and the time during which the command processing unit CP00 executes the compressed write is represented by tProg.

[0260] The controller 3 sends the physical address, the randomization key, and the compressed read command CMD2c to the command processing unit CP00 (data input).

[0261] When receiving the physical address, randomization key and compressed read command CMD2c from the controller 3, the command processing unit CP00 reads a frame from the location indicated by the physical address in the memory chip MC00 and derandomizes the randomized data contained in the read frame using the randomization key.

[0262] The controller 3 waits for the compression reading process to be performed by the command processing unit CP00, and inquires about the status of the command processing unit CP00 (for example, polling) to check the status of the compression reading.

[0263] When the compression reading of the command processing unit CP00 is completed, the controller 3 sends a data output command CMD3 b for acquiring a physical address and a redundant portion to the command processing unit CP00 .

[0264] When receiving the physical address and the data output command CMD3 b from the controller 3 , the command processing unit CP00 transmits the redundant portion corresponding to the physical address to the controller 3 (data output of the redundant portion).

[0265] The controller 3 receives the redundant part from the command processing part CP00.

[0266] The controller 3 determines whether the frame corresponding to the redundant portion is a valid frame based on the redundant portion, the address translation table AT, and the physical address received from the command processing unit CP00.

[0267] Based on the judgment result of whether it is a valid frame, the controller 3 sends a compression move instruction for moving the valid frame stored in the compression read buffer memory 12a of the instruction processing unit CP00 to the compression write buffer memory 12b of the instruction processing unit CP00, as well as valid specific information (such as a logical address or a redundant part) to the instruction processing unit CP00.

[0268] The command processing unit CP00 moves the valid frame stored in the compression read buffer 12 a to the compression write buffer 12 b based on the compression read command and validity identification information from the controller 3 .

[0269] The physical address, randomization key and compressed read instruction CMD2c are sent from the controller 3 to the instruction processing unit CP00 to move the valid data from the compressed read buffer memory 12a to the compressed write buffer memory 12b. This process is repeated until the compressed write buffer memory 12b stores the valid data in the amount that can be stored by one word line.

[0270] When it is determined that the compressed write buffer memory 12b stores the number of valid frames that can be stored in one word line, the controller 3 sends the physical address, redundant part, randomization key and compressed write instruction CMD2d to the instruction processing unit CP00 (data input of redundant part and randomization key).

[0271] Upon receiving the physical address, redundant portion, randomization key, and compression write command CMD2d from the controller 3, the command processing unit CP00 randomizes the data using the randomization key. The command processing unit CP00 then adds a parity check unit to the randomized data and redundant portion. The command processing unit CP00 generates a frame containing the randomized data, redundant portion, and parity check unit. The command processing unit CP00 then writes the generated frame to the location specified by the physical address.

[0272] The controller 3 waits for the compression writing process of the command processing unit CP00, inquires about the status of the command processing unit CP00 (for example, polls), and checks the compression writing status.

[0273] The controller 3 detects the end of the compression writing based on the status check result.

[0274] Figure 13 This is a flowchart showing an example of processing executed by the command processing unit CP00 and the controller 3 according to the present embodiment.

[0275] In this Figure 13 In the description, the case where the memory chip MC00 includes TLC memory cells is taken as an example.

[0276] The controller 3 sends the compressed read command and the physical address to the command processing unit CP00. The command processing unit CP00 receives the compressed read command and the physical address from the controller 3 (S1301).

[0277] In accordance with the compressed read command, the command processing unit CP00 reads the frames stored in the pages specified by the physical addresses in the original blocks from the two memory planes PL0 and PL1 of the memory chip MC00 using a multiplane sequential read method ( S1302 ).

[0278] Specifically, upon receiving the compression read command, the command processing unit CP00 executes a read of 3 [pages / word line: lower page / middle page / upper page]×2 [memory planes] and stores the read frame in the memory 12 .

[0279] The command processing unit CP00 executes error correction processing on the frame stored in the memory 12 ( S1303 ).

[0280] The command processing unit CP00 determines whether the error correction of the frame is successful (S1304).

[0281] When error correction of the frame fails, the command processing unit CP00 transmits the frame including the data and the redundant portion to the controller 3 ( S1305 a ).

[0282] The controller 3 performs error correction processing on the frame received from the command processing unit CP00 ( S1305 b ).

[0283] The controller 3 determines whether the frame received from the command processing unit CP00 is a valid frame based on the error-corrected frame, the address translation table AT, and the physical address of the read destination ( S1305 c ).

[0284] Then, the controller 3 sends, to the command processing unit CP00 , for example, a write command, a physical address, valid data, a redundant portion, and a randomization key for writing a valid frame into a destination block in the nonvolatile memories NM00 to NM33 ( S1305 d ).

[0285] The command processing unit CP00 receives the write command, the physical address, the redundant portion, and the randomization key from the controller 3 ( S1305 e ).

[0286] The command processing unit CP00 performs data randomization and addition of a parity check unit using a randomization key on the valid frame including valid data and a redundant unit received from the controller 3 ( S1305 f ).

[0287] The command processing unit CP00 writes the valid frame including the randomized data, the redundant part, and the parity part into the page specified by the physical address (S1305g). Then, the process proceeds to S1301.

[0288] If the error correction of the frame is successful, the command processing unit CP00 derandomizes the randomized data of the frame stored in the memory 12 and stores the frame including the derandomized data and the redundant portion in the memory 12 ( S1306 ).

[0289] The command processing unit CP00 transmits the redundant portion of the frame including the derandomized data to the controller 3 (data output: S1307 ).

[0290] Specifically, for example, when the data size of the redundant part is 16 bytes, the instruction processing unit CP00 outputs data of 16 [bytes] redundant part × 4 [frames] × 3 [pages / word lines: lower page / middle page / upper page] × 2 [memory planes] = 384 [bytes] to the controller 3.

[0291] The command processing unit CP00 moves the frame including the derandomized data and the redundant portion stored in the memory 12 to the compressed read buffer 12a (S1308). The command processing unit CP00 moves the frame stored in, for example, a latch circuit of the memory 12 to the compressed read buffer 12a, thereby enabling the reception of a read command from the host device 2.

[0292] The controller 3 determines whether the frame including the redundant portion received from the command processing unit CP00 is a valid frame based on the logical address, the address translation table AT, and the physical address included in the redundant portion received from the command processing unit CP00 ( S1309 ).

[0293] The controller 3 sends the compression movement command and the validity identification information to the command processing unit CP00. The command processing unit CP00 receives the compression movement command and the validity identification information from the controller 3 (S1310).

[0294] Upon receiving the compression move command and the validity identification information, the command processing unit CP00 moves the valid frames specified by the validity identification information from among the frames stored in the compression read buffer 12a to the compression write buffer 12b in a filled state (S1311). For example, the command processing unit CP00 determines that a frame containing a redundant portion corresponding to the validity identification information is a valid frame.

[0295] The controller 3 determines whether the number of valid frames stored in the compression write buffer memory 12b is equal to or greater than a predetermined value (S1312).

[0296] Specifically, the controller 3 determines whether 4 [frames]×3 [pages / word line: lower page / middle page / upper page]×2 [memory planes]=24 valid frames are stored in the compression write buffer memory 12 b .

[0297] If the number of valid frames stored in the compressed write buffer memory 12b is not greater than a predetermined value, the command processing unit CP00 enters a waiting state until a new compressed read command is received from the controller 3. When the command processing unit CP00 receives a new compressed read command from the controller 3, the processing in S1301 and subsequent steps is executed.

[0298] When the number of valid frames stored in the compression write buffer 12b is greater than a predetermined value, the controller 3 sends a compression write command, a physical address, a redundant portion, and a randomization key (data input) to the command processing unit CP00. The command processing unit CP00 receives the compression write command, the physical address, the redundant portion, and the randomization key from the controller 3 (S1313).

[0299] The command processing unit CP00 randomizes the data and adds a parity check unit to the valid frame stored in the compressed write buffer 12b using the randomization key (S1314).

[0300] The command processing unit CP00 writes a valid frame including randomized data, a redundant portion, and a parity portion to a page specified by a physical address in a destination block using a multiplane page write method for the two memory planes PL0 and PL1 ( S1315 ).

[0301] Specifically, the command processing unit CP00 writes 4 [frames] × 3 [pages / word lines: lower page / middle page / upper page] × 2 [memory planes] = 24 valid frames into the two memory planes PL0 and PL1 using a multiplane sequential write method.

[0302] Figure 14 1 is a diagram showing an example of a method for manufacturing the nonvolatile memory NM00 according to this embodiment.

[0303] In this embodiment, the peripheral circuit PC includes a command processing unit CP00. The peripheral circuit PC is produced using, for example, CMOS.

[0304] The memory chip MC00 includes a NAND memory cell array, which may also have a three-dimensional structure.

[0305] The peripheral circuit PC and memory chip MC00 are manufactured from separate silicon wafers. The peripheral circuit PC and memory chip MC00 are then bonded together to create nonvolatile memory NM00. More specifically, the electrodes of the peripheral circuit PC are connected to the electrodes of the memory chip MC00 to create nonvolatile memory NM00.

[0306] The manufacturing process of the peripheral circuit is more advanced than that of the memory cell. When the peripheral circuit and the memory cell are manufactured from the same silicon wafer, the technology level of the peripheral circuit manufacturing process must be consistent with that of the memory cell manufacturing process.

[0307] In contrast, in this embodiment, the peripheral circuit PC can be designed and manufactured using a more advanced technology than that of the memory chip MC00, thereby enabling miniaturization, speed improvement, and high integration of the nonvolatile memory NM00.

[0308] Therefore, in this embodiment, compared with the case where the peripheral circuit and the memory cell are manufactured from the same silicon wafer, the functionality of the peripheral circuit PC can be enhanced.

[0309] Furthermore, in this embodiment, compared with the case where the peripheral circuit and the memory cell are manufactured from the same silicon wafer, the storage capacity of the memory 12 and the like of the peripheral circuit PC can be increased.

[0310] Furthermore, in this embodiment, compared with the case where peripheral circuits and memory cells are manufactured from the same silicon wafer, the reuse rate of functional blocks and circuit blocks can be improved.

[0311] Hereinafter, examples of effects obtained by the memory system 1 of the present embodiment will be described by comparing the memory system 1 of the present embodiment with a memory system of a comparative example.

[0312] Figure 15 2 is a block diagram showing an example of the configuration of a memory system 24 according to a comparative example.

[0313] The memory system 24 of the comparative example is capable of communicating with the host device 2 , and includes nonvolatile memories NM40 to NM73 and a controller 26 .

[0314] The nonvolatile memories NM40 to NM73 differ from the nonvolatile memories NM00 to NM33 in that they do not include the command processing units CP00 to CP33 .

[0315] Nonvolatile memories NM40 to NM43 are each connected to memory bus MB0. Nonvolatile memories NM50 to NM53 are each connected to memory bus MB1. Nonvolatile memories NM60 to NM63 are each connected to memory bus MB2. Nonvolatile memories NM70 to NM73 are each connected to memory bus MB3.

[0316] The controller 26 controls the nonvolatile memories NM40 to NM73 .

[0317] The controller 26 includes a host interface unit 4 , a storage device such as an SRAM 25 , a processor 6 , a DMAC 7 , and memory interface units MI0 to MI3 .

[0318] The SRAM 25 stores, for example, the firmware FW2 and the address translation table AT.

[0319] The firmware FW2 is executed by the processor 6 to cause the processor 6 to implement various controls including compression.

[0320] The processor 6 executes the firmware FW2 and transmits a read command and a physical address of a read destination to the nonvolatile memory NM40 including the original block via the memory interface unit MI0 and the memory bus MB0.

[0321] The processor 6 receives a frame including data and a redundant portion from a location specified by a read destination physical address in the nonvolatile memory NM40 via the memory bus MB0 and the memory interface unit MI0 , and stores the received frame in the SRAM 25 .

[0322] The processor 6 determines whether the frame stored in the SRAM 25 is a valid frame based on the address translation table AT, the physical address of the read destination, and the redundant portion.

[0323] The processor 6 sends the write command, the physical address of the write destination, and the valid frame stored in the SRAM 25 to the nonvolatile memory NM50 including the destination block.

[0324] Furthermore, the processor 6 sends an erase command for erasing the original block and the physical address of the erase destination to the nonvolatile memory NM40 including the original block via the memory interface unit MI0 and the memory bus MB0. Thus, the original block is erased. The processor 6 then manages the original block as a free block.

[0325] The time required to read / write data from one nonvolatile memory is longer than that of an HDD. In the memory system 24 of the comparative example, multiple nonvolatile memories NM40 to NM73 are installed to increase the parallelism of internal processing, thereby achieving faster reading / writing than an HDD.

[0326] The memory system 24 of the comparative example performs compression as described above. If the memory system 24 of the comparative example does not have DRAM installed, or if the DRAM of the memory system 24 of the comparative example is small, the controller 26 may include, for example, an SRAM 25 for temporary storage. However, installing an SRAM 25 of sufficient size in the memory system 24 of the comparative example for compression results in increased costs. Therefore, in the memory system 24 of the comparative example, the buffer size that can be used for compression is limited. In the memory system 24 of the comparative example with a limited buffer size, it is difficult to increase the parallelism of internal processing, and processing must be performed serially. In this case, from the perspective of the host device 2, the processing speed of the memory system 24 of the comparative example is slow.

[0327] like Figure 15 As shown, the memory system 24 of the comparative example includes 16 nonvolatile memories NM40 to NM73, four memory buses MB0 to MB3, and four channels ch4 to ch7. In the SRAM 25 of the memory system 24 of the comparative example, it is assumed that the read buffer memory, which temporarily stores data read from any of the nonvolatile memories NM40 to NM73 during compression, is limited to 516 kilobytes, and the write buffer memory, which temporarily stores data to be written to any of the nonvolatile memories NM40 to NM73 during compression, is limited to 192 kilobytes. Thus, in the memory system 24 of the comparative example, the write buffer memory, which temporarily stores data to be written to any of the nonvolatile memories NM40 to NM73 during compression, is limited to 192 kilobytes. This allows for parallel execution of 4 [number of nonvolatile memories] × 1 [number of memory planes] of writes during compression. In the hardware configuration of the comparative example memory system 24, when the buffer memory size is sufficient, the comparative example memory system 24 can perform 16 [number of non-volatile memories] × 2 [number of memory planes] writes in parallel during compression. When comparing the write performance in these two compressions in the comparative example memory system 24, the number of chips that can write in parallel when the write buffer memory size is limited is 1 / 4 the number of chips that can write in parallel when the write buffer memory size is not limited. Furthermore, in the comparative example memory system 24, the number of memory planes that can be written in parallel when the write buffer memory size is limited is 1 / 2 the number of memory planes that can be written in parallel when the write buffer memory size is not limited. Therefore, the compression performance of the comparative example memory system 24 with a limited write buffer memory size is 1 / 8 the compression performance when the write buffer memory size is not limited.

[0328] As described above, if the size of the SRAM 25 is limited, compression of the memory system 24 of the comparative example takes time, and the write performance score (eg, global random write) of the memory system 24 of the comparative example becomes low.

[0329] In contrast, in the memory system 1 of this embodiment, when the command processing units CP00 to CP33 can perform error correction on the data and the redundant portion during compression, the controller 3 receives the redundant portion but does not receive the data from the command processing units CP00 to CP33.

[0330] Therefore, in the memory system 1 of this embodiment, even if the size of the SRAM 5 is limited, the area used for compression can be reduced and the nonvolatile memories NM00 to NM33 can be operated in parallel. Therefore, in this embodiment, compression can be accelerated.

[0331] Figure 16 1 is a diagram showing an example of data conversion when the memory system 1 of this embodiment receives a write command and a read command from the host device 2. In addition, the data conversion when the memory system 24 of the comparative example receives a write command and a read command from the host device 2 is also similar to the example of FIG. Figure 16 same.

[0332] The controller 3 receives, for example, a write command, a logical address, and data D from the host device 2 .

[0333] When receiving a write instruction, the controller 3 converts the logical address into a physical address using the address translation table AT.

[0334] The controller 3 adds a redundant portion R including a logical address to the data D, thereby generating a frame Fr0d.

[0335] The controller 3 randomizes the data D of the frame Fr0d to generate a frame Fr0c including the randomized data Dr and the redundant portion R.

[0336] The controller 3 generates a frame Fr0b by adding the parity portion Par to the frame Fr0c, and writes the frame Fr0b to the position (page) indicated by the physical address in the nonvolatile memory NM00.

[0337] The controller 3 receives, for example, a read instruction and a logical address from the host device 2 .

[0338] When receiving a read instruction, the controller 3 converts the logical address into a physical address using the address translation table AT.

[0339] The controller 3 reads the frame Fr0a from the position (page) specified by the physical address in the nonvolatile memory NM00. An error may occur in the frame Fr0a.

[0340] The controller 3 performs error correction processing on the frame Fr0a read from the nonvolatile memory NM00, deletes the parity portion Par from the frame Fr0a, and generates a frame Fr0c.

[0341] The controller 3 derandomizes the randomized data Dr included in the frame Fr0c to generate a frame Fr0d including data D and a redundant portion R.

[0342] The controller 3 transmits the data D included in the frame Fr0d to the host device 2 .

[0343] Figure 17 2 is a diagram showing an example of data conversion during compression performed by the memory system 24 of the comparative example. Figure 17, the case where the original block and the destination block exist in the nonvolatile memory NM 40 is exemplified. However, the original block and the destination block may be contained in different nonvolatile memories.

[0344] The controller 26 reads the frame Fr0a stored in the original block from the nonvolatile memory NM40. An error may occur in the frame Fr0a read from the nonvolatile memory NM40.

[0345] The controller 26 performs error correction processing on the frame Fr0a read from the nonvolatile memory NM40, deletes the parity portion Par, and generates a frame Fr0c.

[0346] The controller 26 derandomizes the randomized data Dr included in the frame Fr0c, and generates a frame Fr0d including the derandomized data D and the redundant portion R.

[0347] The controller 26 determines whether the data D in the frame Fr0d is valid data based on the logical address included in the redundant portion R, the physical address of the read destination, and the address conversion table AT.

[0348] When the data D is valid data, the controller 26 randomizes the data D of the frame Fr0d to generate a frame Fr0c including the randomized data Dr and the redundant portion R.

[0349] The controller 26 adds the parity portion Par to the frame Fr0c to generate a frame Fr0b.

[0350] The controller 26 writes the frame Fr0b to the location specified by the physical address of the write destination.

[0351] When the data D is valid data, the controller 26 updates the physical address corresponding to the logical address included in the redundant portion R in the address translation table AT to the physical address of the write destination.

[0352] Thus, in the memory system 24 of the comparative example, during compression, a frame Fr0a including randomized data Dr, a redundant portion R, and a parity portion Par is transmitted from the nonvolatile memory NM40 to the controller 26. Furthermore, in the memory system 24 of the comparative example, during compression, a frame Fr0b including randomized data Dr, a redundant portion R, and a parity portion Par is transmitted from the controller 26 to the nonvolatile memory NM40.

[0353] Figure 18 This is a diagram showing an example of data conversion during compression performed by the memory system 1 of this embodiment. Figure 18 , a case where the original block and the destination block are arranged in the nonvolatile memory NM00 is illustrated.

[0354] The controller 3 sends the compressed read command, the physical address of the read destination, and the randomization key to the command processing unit CP00.

[0355] The command processing unit CP00 reads the frame Fr0a stored in the nonvolatile memory NM00 at a location specified by the physical address of the read destination. An error may occur in the frame Fr0a read from the nonvolatile memory NM00.

[0356] The command processing unit CP00 performs error correction processing on the frame Fr0a read from the nonvolatile memory NM00, deletes the parity portion Par from the frame Fr0a, and generates a frame Fr0c.

[0357] The command processing unit CP00 derandomizes the randomized data Dr of the frame Fr0c using the randomization key, and generates a frame Fr0d including the data D and the redundant portion R.

[0358] The command processing unit CP00 transmits the redundant portion R of the frame Fr0d to the controller 3 (data output).

[0359] The controller 3 determines whether the data D in the frame Fr0d stored in the command processing unit CP00 is valid data based on the logical address contained in the redundant portion R received from the command processing unit CP00, the address translation table AT, and the physical address of the read destination. For example, the controller 3 determines whether an association is established between the logical address contained in the redundant portion R in the address translation table AT and the physical address of the read destination. If an association is established between the logical address contained in the redundant portion R in the address translation table AT and the physical address of the read destination, the controller 3 determines that the data D in the frame Fr0d is valid data. Conversely, if an association is not established between the logical address contained in the redundant portion R in the address translation table AT and the physical address of the read destination, the controller 3 determines that the data D in the frame Fr0d is invalid data.

[0360] When determining that the data D included in the frame Fr0d stored in the command processing unit CP00 is valid data, the controller 3 sends a compression write command, a physical address of a write destination, and a redundant unit R to the command processing unit CP00 (data input).

[0361] The command processing unit CP00 receives a compression write command, a physical address of a write destination, a redundant portion R, and a randomization key from the controller 3 .

[0362] The command processing unit CP00 randomizes the data D of the received frame Fr0d including the redundant portion R using the randomization key, and generates a frame Fr0c including the randomized data Dr and the redundant portion R.

[0363] The command processing unit CP00 generates a frame Fr0b obtained by adding a parity portion Par to the randomized data Dr and the redundant portion R of the frame Fr0c.

[0364] The command processing unit CP00 writes the frame Fr0b to the location specified by the physical address of the write destination in the memory chip MC00.

[0365] When determining that the data D included in the frame Fr0d is valid data, the controller 3 updates the address translation table AT so that the logical address included in the redundant portion R is associated with the physical address of the write destination.

[0366] When the command processing unit CP00 can perform error correction on the frame during compression, the command processing unit CP00 does not send the data D to the controller 3 but sends the redundant part R to the controller 3 and receives the redundant part R corresponding to the valid data from the controller 3 .

[0367] The memory system 1 restricts frame movement to the nonvolatile memory NM00. If the command processing unit CP00 can perform error correction on the data D and the redundant portion R, the nonvolatile memory NM00 sends the redundant portion R to the controller 3 without sending the data D to the controller 3. The data D contained in the frame is guaranteed to be within the command processing unit CP00. The controller 3 collects the redundant portion R from the nonvolatile memory NM00. If the command processing unit CP00 can perform error correction, the controller 3 does not need to allocate the data D contained in the frame to the SRAM 5. After moving valid data from the original block to the destination block, the controller 3 updates the relationship between the physical address and the logical address in the address translation table AT.

[0368] In the embodiment described above, the size of the temporary storage SRAM 5 for compression included in the controller 3 can be made smaller than the SRAM 25 of the memory system 24 of the comparative example. Specifically, the size of the temporary storage SRAM 5 of the controller 3 can be set to be approximately 1 / 300 or less of the size of the SRAM 25 of the controller 26.

[0369] In memory system 1, even when controller 3 does not have DRAM, performance degradation due to the size limitation of SRAM 5 can be avoided, and compression can be performed with the maximum parallelism of the number of non-volatile memories NM00 to NM33 installed. In other words, even when controller 3 does not have DRAM, memory system 1 can perform compression with the same performance as when controller 3 has DRAM installed.

[0370] During compression, the memory system 1 moves data from the original block to the destination block within each of the nonvolatile memories NM00 to NM33 even if the data is not sent from the command processing units CP00 to CP33 to the controller 3 .

[0371] The size of data sent and received between the controller 3 of the memory system 1 and the non-volatile memories NM00 to NM33 during compression is smaller than the size of data sent and received between the controller 26 of the memory system 24 of the comparative example and the non-volatile memories NM40 to NM73 during compression. Therefore, the amount of communication between the controller 3 of the memory system 1 and the non-volatile memories NM00 to NM33 can be reduced. Therefore, in the memory system 1 of this embodiment, the compression processing time can be shortened compared to the memory system 24 of the comparative example. By shortening the compression processing time, in this embodiment, random writes to the non-volatile memories NM00 to NM33 can be prevented from being hindered by compression. Therefore, the random write performance of the memory system 1 of this embodiment is higher than that of the memory system 24 of the comparative example.

[0372] During compression, the controller 3 of the memory system 1 of this embodiment first sends a compression read command to the command processing unit CP00, and then sends a compression write command to the command processing unit CP00. The compression read command and the compression write command are described below.

[0373] First, the compressed read instruction is described.

[0374] As an example of determining whether data in an original block to be compressed is valid or invalid, this embodiment uses the example of reading all data in an original block and determining whether the read data is valid or invalid.

[0375] The compression read command is a command for extracting a redundant portion R from the command processing unit CP00 during compression. The redundant portion R is validity determination information required for the controller 3 to determine valid data.

[0376] The command processing unit CP00 executes the first to fourth compression read processes according to the compression read command.

[0377] The first compressed read process is as follows: randomized data and a redundant portion are read from the memory chip MC00 , and the read randomized data is stored in the memory 12 of the command processing unit CP00 .

[0378] The second compression read process is as follows: error correction processing is performed on the randomized data and redundant portion stored in the memory 12 , whether error correction is possible is determined, and the randomized data and redundant portion after error correction are stored in the memory 12 .

[0379] The third compression reading process is as follows: using the randomization key received from the controller 3 , randomized data after error correction stored in the memory 12 is derandomized, and the derandomized data is stored in the memory 12 .

[0380] The fourth compression read process is as follows: for example, when a request to output data of the redundant part R is received from the controller 3 , the redundant part R is sent to the controller 3 .

[0381] In the memory system 24 of the comparative example, for example, when reading from the nonvolatile memory NM40, the controller 26 sends a read command and a physical address to the nonvolatile memory NM40. If the nonvolatile memory NM40 is a QLC, the physical address specifies any one of the lower, middle, upper, and first pages. Therefore, to read data from the lower, middle, upper, and first pages, the controller 26 must send four read commands to the nonvolatile memory NM40.

[0382] In contrast, in this embodiment, when the memory chip MC00 is QLC, the command processing unit CP00 performs all 15 levels of sensing upon receiving a compressed read command, reading data from four pages (lower page, middle page, upper page, and first page). Therefore, in this embodiment, the execution speed of commands can be increased. Furthermore, when the nonvolatile memory NM00 is composed of two memory planes PL0 and PL1, the command processing unit CP00 can execute compressed read commands on both memory planes PL0 and PL1 in parallel.

[0383] In this embodiment, the controller 3 determines the validity of the data and the page address of the block to which the data should be moved. To determine the validity and the move destination, the command processing unit CP00 sends the redundant portion to the controller 3. However, if the command processing unit CP00 can perform error correction on the data, the command processing unit CP00 does not send the data to the controller 3.

[0384] Assume that the controller 26 of the memory system 24 of the comparative example can output data from the nonvolatile memory NM40 to the controller 26 in, for example, 20 nanoseconds in response to a data output instruction. Furthermore, assume that the memory system 24 of the comparative example requires a wait time of, for example, 300 nanoseconds until the data can be output from the nonvolatile memory NM40 to the controller 26 in response to the data output instruction. In this case, the time required for the memory system 24 of the comparative example to fetch 4 [frames / page] × 4 [lower page / middle page / upper page / first page] = 16 [frames] of redundant portions and data from one word line is (300 nanoseconds + 20 nanoseconds) × 16 = 5.12 milliseconds.

[0385] In contrast, in the memory system 1 of this embodiment, addresses are continuously generated within the command processing unit CP00. In this case, the time required to fetch redundant data (4 [frames / page] × 4 [lower page / middle page / upper page / first page] = 16 frames) from a single word line is 300 nanoseconds + 20 nanoseconds × 16 = 0.64 milliseconds.

[0386] As described above, during compression, the memory system 1 of this embodiment continuously generates read addresses from the addresses representing the original blocks in the command processing unit CP00. The command processing unit CP00 then continuously reads data based on the generated addresses. Consequently, the memory system 1 of this embodiment can transfer data at a speed approximately eight times that of the memory system 24 of the comparative example, for example.

[0387] Next, the compression write command will be described.

[0388] The compression write command is a command for causing the command processing unit CP00 to write a valid frame into the memory chip MC00 during compression.

[0389] The command processing unit CP00 executes the first to fourth compression write processes according to the compression write command.

[0390] The first compression write process is as follows: a redundant portion including data identification information such as a logical address (position information), a randomization key, and a physical address of a write destination are received from the controller 3 .

[0391] The second compression write process is a process of performing randomization so as to level the data 0 and 1 using the randomization key.

[0392] The third compression write process is a process (for example, encoding process) of generating the randomized data and the parity check portion required for error correction of the redundant portion.

[0393] The fourth compression write process is a process of writing data to a designated location in the memory chip MC00.

[0394] Regarding the data transfer amount in the data input of the memory system 24 of the comparative example, for example, when the memory chip is TLC and the data size of each page is 18,000 bytes, based on 18,000 [bytes / page] × 3 [page / word line: lower page / middle page / upper page] × 2 [memory surface], it is obtained as 108,000 bytes.

[0395] In contrast, regarding the data transfer amount in the data input of this embodiment, for example, when the memory chip MC00 is TLC and the data size of the redundant part of each frame is 16 bytes, the result is 384 bytes based on 16 [number of bytes of the redundant part / frame] × 4 [frame / page] × 3 [page / word line: lower page / middle page / upper page] × 2 [memory surface].

[0396] Therefore, in this embodiment, the amount of data transfer in data input can be reduced to approximately 1 / 281 of the memory system 24 of the comparative example.

[0397] In this embodiment, when non-volatile memories NM00-NM33 are QLC, the command processing unit CP00 can also continuously transmit the redundant portion of one word line, that is, 16 redundant portions (4 [frames] × 4 [pages / word line: lower page / middle page / upper page / first page]) to the controller 3. For example, when the command processing unit CP00 sends the 16-byte redundant portion to the controller 3 in accordance with the random data output command, it may take 300 nanoseconds. In contrast, when the command processing unit CP00 continuously transmits the redundant portion of one word line, the data can be transmitted in approximately 20 nanoseconds. Therefore, by continuously transmitting the redundant portion of one word line from the command processing unit CP00 to the controller 3, the transmission efficiency can be reduced to approximately 6% compared to when using the random data output command.

[0398] The present embodiment is provided as an example and is not intended to limit the scope of the invention. The present embodiment can be implemented in various other ways and can be omitted, replaced, or modified without departing from the scope of the invention. The present embodiment or its variations are included within the scope or spirit of the invention and are included within the scope of the invention described in the claims and their equivalents.

[0399] [Explanation of Symbols]

[0400] 1 Memory System

[0401] 2 Host device

[0402] 3 Controller

[0403] NMM Non-volatile memory device

[0404] 4 Host interface

[0405] 5 SRAM

[0406] 6 processors

[0407] 7 DMAC

[0408] MI0~MI3 memory interface

[0409] CR0~CR3 calibration unit

[0410] MB0~MB3 memory bus

[0411] NM00~NM33 non-volatile memory

[0412] CP00~CP33 instruction processing unit

[0413] MC00~MC33 memory chips

[0414] FW1 firmware

[0415] AT address translation table

[0416] 10a Processing Unit

[0417] 12a Compressed read buffer

[0418] 12b compressed write buffer

[0419] B0~Bk+1 blocks

[0420] MCG0~MCGm storage unit group

[0421] F1~F3 frames

[0422] D data

[0423] P Redundant part

[0424] Par parity check unit

[0425] LA logical address.

Claims

1. A non-volatile memory, characterized in that have: a memory cell array comprising a plurality of nonvolatile memory cells; and an instruction processing unit, comprising a buffer, for controlling writing or reading data to or from the memory cell array according to instructions received from a controller; and The instruction processing unit is: When receiving a first position of the memory cell array and a first command from the controller, first data based on data read from the first position is stored in the buffer, When receiving a second position of the memory cell array and a second command from the controller, second data based on the data read from the second position is stored in the buffer. sending first validity determination information for determining whether the first data is valid and second validity determination information for determining whether the second data is valid to the controller, When receiving a third instruction and validity-specifying information indicating that the second data is valid data from the controller, third data based on the second data stored in the buffer is written to a third position of the memory cell array; The third data is a valid frame.

2. The non-volatile memory according to claim 1, wherein The command processing unit is configured to write the fourth data into the fourth position when receiving the fourth position and fourth data of the memory cell array and a write command from the controller.

3. The non-volatile memory according to claim 1 or 2, characterized in that The command processing unit reads the first validity determination information from the storage cell array when receiving the first command from the controller.

4. The non-volatile memory according to claim 1 or 2, characterized in that The instruction processing unit is: performing error correction processing based on the data read from the first position, When error correction based on the data read from the first position is successful, the first validity determination information is sent to the controller; When error correction based on the data read from the first location fails, the data read from the first location and the first validity determination information are transmitted to the controller.

5. The non-volatile memory according to claim 1 or 2, characterized in that The instruction processing unit is: When the first location, the first randomization key, and the first instruction are received from the controller, the fifth data based on the data read from the first location is derandomized using the first randomization key. When the second randomization key, the valid identification information, and the third command are received from the controller, the third data is generated using the second randomization key for the second data.

6. The nonvolatile memory according to claim 1 or 2, wherein: The first validity determination information includes a first logical address, which is a logical address of the data read from the first position. The second validity determination information includes a second logical address, which is a logical address of the data read from the second position. The valid identification information includes the second logical address.

7. The nonvolatile memory according to claim 1 or 2, wherein: The writing of the third data to the third location by the command processing unit includes: Upon receiving the valid identification information and the fourth instruction, the second data is moved from the first area included in the buffer to the second area included in the buffer, When the third command and the third location are received, the third data based on the second data moved to the second area is written to the third location.

8. A memory system, characterized in that have: The nonvolatile memory according to any one of claims 1 to 7, and the controller; and The controller is: sending the first command and the second command to the nonvolatile memory, receiving the first validity determination information and the second validity determination information from the nonvolatile memory, Based on the first validity judgment information, determine whether the first data is valid, Based on the second validity judgment information, determine whether the second data is valid, When it is determined that the first data is invalid and the second data is valid, the third command and the validity specifying information are sent to the nonvolatile memory.

9. A method for controlling a nonvolatile memory, wherein the nonvolatile memory comprises a memory cell array including a plurality of nonvolatile memory cells, and the method comprises: When receiving the first position of the memory cell array and the first instruction, first data is read from the first position. When receiving the second position of the memory cell array and the second instruction, reading the second data from the second position, Sending first validity determination information for determining whether the first data is valid, and second validity determination information for determining whether the second data is valid, When receiving a third instruction and valid identification information indicating that the second data is valid data, third data based on the second data is written into a third position of the memory cell array. The third data is a valid frame.

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