A multi-bit in-memory computing array structure and an electronic device

Abstract

The present invention discloses a multi-bit in-memory computing array structure and an electronic device. The structure includes a plurality of voltage-controlled delay circuits arranged in a rectangular pattern. Each voltage-controlled delay circuit has an input terminal, an output terminal, a voltage control terminal, and at least one control terminal. When the control terminal signal is 0, the reference signal generates a delay one through the corresponding input terminal and output terminal. When the control terminal signal is 1, the reference signal generates a delay two through the corresponding input terminal and output terminal. The delay two is the sum of the delay one and a delay adjustment amount, and the delay adjustment amount is linearly and positively correlated with the corresponding voltage control terminal signal. The in-memory computing array structure represents the multiplication and accumulation calculation results of multiple bit input values and multiple bit weight values through the delay adjustment amounts generated by combining multiple columns of voltage-controlled delay circuits in a row form. The present invention realizes the multiplication and accumulation in-memory computing of multi-bit inputs and multi-bit weights, and can provide a large system-level inference accuracy and efficiency.

Description

Technical Field

[0001] The present invention relates to a computing array structure in the field of integrated circuit design technology, and in particular to a multi-bit in-memory computing array structure, and also relates to an electronic device. Background Art

[0002] In traditional computing architectures, data needs to be repeatedly moved between the memory and the processor, resulting in the "memory wall" problem, which limits the computing speed and energy efficiency. Computing In Memory (CIM) breaks the von Neumann architecture of traditional computers and embeds the computing circuit in the memory, integrating storage and computing, thereby greatly reducing data migration and memory access consumption.

[0003] Current non-volatile in-memory computing technology solutions support Binary Neural Networks (BNNs) or Binary Weight Networks (BWNs), which reduce the storage requirement to a certain extent and improve energy efficiency. However, BNNs and BWNs are only applicable to simple networks, which usually only support single-bit input and weight multiplication and Multiply And Accumulate (MAC) in-memory computing. Therefore, when applied to complex applications, they can only provide limited system-level inference accuracy, restricting the further development of AI technology. Summary of the Invention

[0004] To solve the technical problem that the existing in-memory computing array structure only supports single-bit input and weight multiplication in-memory computing and can only provide limited system-level inference accuracy, the present invention provides a multi-bit in-memory computing array structure and an electronic device.

[0005] The present invention is implemented by the following technical solutions: A multi-bit in-memory computing array structure, which includes:

[0006] A plurality of voltage-controlled delay circuits arranged in a rectangular pattern, where the columns correspond to a row of bit input values and the rows correspond to a column of bit weight values; each voltage-controlled delay circuit has an input terminal, an output terminal, a voltage control terminal, and at least one control terminal; in each row, the output terminal of each voltage-controlled delay circuit is connected to the input terminal of the next column; the same control terminal of each column is connected and receives the corresponding bit weight value, and the voltage control terminals of each row are connected and receive the corresponding bit input value; when the control terminal signal is 0, the reference signal generates a delay one through the corresponding input terminal and output terminal; when the control terminal signal is 1, the reference signal generates a delay two through the corresponding input terminal and output terminal; the delay two is the sum of the delay one and a delay adjustment amount, and the delay adjustment amount is linearly and positively correlated with the corresponding voltage control terminal signal; each voltage-controlled delay circuit includes a high-bit voltage-controlled delay unit and a low-bit voltage-controlled delay unit; each voltage-controlled delay unit has the input terminal, the output terminal, the voltage control terminal, and two control terminals with opposite signals: control terminal one and control terminal two; in each column, the output terminal of the high-bit voltage-controlled delay unit is connected to the input terminal of the high-bit voltage-controlled delay unit of the next column, and the output terminal of the low-bit voltage-controlled delay unit is connected to the input terminal of the low-bit voltage-controlled delay unit of the next column; in each voltage-controlled delay circuit, control terminal one of the high-bit voltage-controlled delay unit is connected to control terminal one of the low-bit voltage-controlled delay unit, and control terminal two of the high-bit voltage-controlled delay unit is connected to control terminal two of the low-bit voltage-controlled delay unit;

[0007] A storage array; control terminal one of each row of voltage-controlled delay circuits is connected to the local bit line LBL of the storage array, and control terminal two is connected to the local bit line LBLB;

[0008] Among them, the accumulation of the delay adjustment amounts of multiple columns of voltage-controlled delay circuits represents the multiplication and accumulation calculation result of multiple bit input values and multiple bit weight values; the calculation array structure realizes the multiplication and accumulation calculation in the following way:

[0009] (1) Take the sum of four times the delay adjustment amount generated by the high-bit voltage-controlled delay unit of each column and the delay adjustment amount generated by the low-bit voltage-controlled delay unit as the total adjustment amount;

[0010] (2) Take the number of unit adjustment amounts contained in the total adjustment amount as the multiplication and accumulation result of multiple bit input values and a single bit weight value;

[0011] (3) Corresponding to multiple bit weight values through multiple rows of voltage-controlled delay circuits, add multiple total adjustment amounts according to the weight ratio to obtain the multiplication calculation result of multiple bit input values and multiple bit weight values;

[0012] (4) The total adjustment amount generated by combining multiple rows of voltage-controlled delay circuits in a column form represents the multiplication and accumulation calculation result of multiple bit input values and multiple bit weight values.

[0013] The present invention characterizes the calculation result by the rising edge delay adjustment amount of the reference signal. Since the rising edge delay adjustment amount can be accumulated, when it is necessary to implement multiply-accumulate calculations with multi-bit inputs and multi-bit weights, only multi-column multi-bit data in-memory computing arrays need to be combined in a row form, and the reference signal output by each voltage-controlled delay circuit in the previous column is received by the corresponding voltage-controlled delay circuit in the next column. Thus, the calculation result of the bit position in the previous column can be passed to the calculation result of the corresponding bit position in the next column. The number of columns of the voltage-controlled delay circuits determines the maximum number of accumulation terms that this structure can perform, and also determines the number of groups of multi-bit multiply-accumulate operations that this structure can perform simultaneously. This computing array structure can provide high system-level inference accuracy and efficiency, and solves the problem that current non-volatile in-memory computing circuits usually only support multiply-accumulate in-memory calculations with single-bit inputs and weights, and can only provide limited system-level inference accuracy.

[0014] Further, each voltage-controlled delay unit includes:

[0015] An input control circuit, which is used to generate an input voltage analog quantity of the voltage-controlled terminal according to the signals of the first control terminal and the second control terminal;

[0016] A trigger circuit, which is connected to the input control circuit and is used to output a delay adjustment amount of the reference signal pulse width according to the input terminal signal;

[0017] An inverter circuit, which is connected to the trigger circuit and is used to shape the waveform output by the trigger circuit and has the output terminal.

[0018] Still further, the trigger circuit includes NMOS transistors N1 to N3 and PMOS transistor P1; the gate of N1 is connected to the reference signal, the source is grounded, and the drain is connected to node X1; the gate of N2 is connected to the reference signal, the source is connected to node X1, and the drain is connected to node X2; the gate of N3 is connected to node X2, the source is connected to node X1, and the drain is connected to node X3; the gate of P1 is connected to the reference signal, the source is connected to node X2, and the drain is connected to the power supply VDD; the gates of N1, N2, and P1 are used as the input terminal;

[0019] The input control circuit includes NMOS transistors N4 and N5; the gate of N4 is used as the first control terminal and is connected to the local bit line LBL, the source is connected to node X3, and the drain is used as the voltage-controlled terminal; the gate of N5 is used as the second control terminal and is connected to the local bit line LBLB, the source is grounded, and the drain is connected to node X3;

[0020] The inverter circuit includes NMOS transistor N6 and PMOS transistor P2; the gate of N6 is connected to node X2, the source is grounded, and the drain is used as the output terminal; the gate of P2 is connected to node X2, the source is used as the output terminal, and the drain is connected to the power supply VDD.

[0021] Furthermore, the in-memory computing array structure further includes:

[0022] A quantization module, which is used to convert the pulse width of the reference signal output by any voltage-controlled delay circuit in the last column from a time analog quantity to a binary digital signal;

[0023] A digital shift adder module, which is used to amplify the quantization result of the high-bit voltage-controlled delay unit by four times and add it to the quantization result of the low-bit voltage-controlled delay unit to obtain the multiplication result of the single-bit input value and the single-bit weight value, and perform weighted summation of the multiplication results of different bit positions according to the weights to obtain the multiply-accumulate calculation result of the multi-bit input value and the multi-bit weight value.

[0024] As a further improvement of the above solution, the reference signal is a rectangular wave reference signal; when the signal at the first control end is 0 and the signal at the second control end is 1, the first delay is a fixed value t0 and is not affected by the voltage at the voltage-controlled end; when the signal at the first control end is 1 and the signal at the second control end is 0, the second delay is t0 + kΔt;

[0025] where k is the binary value of the signal at the voltage-controlled end, and Δt is the unit adjustment amount, representing the minimum adjustment amount of the voltage-controlled delay circuit to the reference signal; the computing array structure calculates the multiply-accumulate calculation result of multiple-bit input values and multiple-bit weight values through the number of unit adjustment amounts Δt contained in the delay adjustment amount.

[0026] Furthermore, the number of both the bit input values and the bit weight values is four; the in-memory computing array structure further includes:

[0027] An input signal column channel module, which is used to divide the four-bit input values into high-bit two-bit signals and low-bit two-bit signals, respectively control the output voltages of the input column channel 1 of the high-bit voltage-controlled delay unit and the input column channel 2 of the low-bit voltage-controlled delay unit, and the output voltage value is determined by the corresponding two-bit signal.

[0028] As a further improvement of the above solution, the in-memory computing array structure further includes:

[0029] A storage array, which includes a plurality of storage units arranged in a rectangular pattern, is used to store multiple-bit weight values, and supports the switching between the standard read-write mode and the multi-bit multiply-accumulate calculation mode; in the multi-bit multiply-accumulate calculation mode, the computing array structure realizes the multiply-accumulate calculation of multiple-bit input values and multiple-bit weight values; the first storage node and the second storage node of each storage unit are respectively connected to the local bit line LBL and LBLB.

[0030] Furthermore, the in-memory computing array structure further includes:

[0031] A local read / write module, which is used to transmit read / write signals through a horizontal word line HWL and global bit lines GBL / GBLB in a standard read / write mode to complete the read / write operations on the storage unit; the local read / write module includes NMOS transistors N7 and N8; the gate of N7 is connected to the horizontal word line HWL, the drain is connected to the local bit line LBL, and the source is connected to the global bit line GBL; the gate of N8 is connected to the horizontal word line HWL, the drain is connected to the local bit line LBLB, and the source is connected to the global bit line GBLB; when the horizontal word line HWL and the word line WL of the nth row of storage units are turned on, the write signal is first transmitted to the local bit lines LBL / LBLB through the global bit lines GBL / GBLB, and then the data is written into the nth row of storage units, where n is any row number of the storage units.

[0032] The present invention also provides an electronic device, which includes a memory and a processor; the memory includes the multi-bit in-memory computing array structure described in any one of the above.

[0033] Compared with the existing in-memory computing array structures and electronic devices, the multi-bit in-memory computing array structure and electronic device of the present invention have the following beneficial effects:

[0034] In this multi-bit in-memory computing array structure, the calculation result is characterized by the rising edge delay adjustment amount of the reference signal. Since the rising edge delay adjustment amount can be accumulated, when it is necessary to implement multiply-accumulate calculations with multi-bit inputs and multi-bit weights, only multi-column multi-bit data in-memory computing arrays need to be combined in a row form, and the signals output by the voltage-controlled delay circuits in the previous column are used as the inputs of the corresponding voltage-controlled delay circuits in the next column. Furthermore, the calculation results of the bit positions in the previous column can be passed to the calculation results of the corresponding bit positions in the next column. The number of columns of the voltage-controlled delay circuits determines the maximum number of accumulation terms that this structure can perform, and also determines the number of groups of multi-bit multiply-accumulate that this structure can perform simultaneously. This computing array structure can provide a large system-level inference accuracy and efficiency, and solves the problem that the current non-volatile in-memory computing circuits usually only support multiply-accumulate in-memory computing with single-bit inputs and weights, and can only provide limited system-level inference accuracy. Description of the Drawings

[0035] Figure 1 It is a schematic structural diagram of the multi-bit in-memory computing array structure according to Embodiment 1 of the present invention;

[0036] Figure 2 is Figure 1 a schematic structural diagram of the storage array and the local read / write module of the multi-bit in-memory computing array structure in

[0037] Figure 3 is Figure 1 a circuit diagram of the voltage-controlled delay unit of the multi-bit in-memory computing array structure in

[0038] Figure 4 The symbol diagram of the voltage-controlled delay unit in Figure 3 ;

[0039] Figure 5 The framework diagram of the storage array, local read / write module, and voltage-controlled delay circuit of the multi-bit in-memory computing array structure in Figure 1 ;

[0040] Figure 6 The calculation schematic diagram of four-bit input and four-bit weight in Embodiment 1 of the present invention;

[0041] Figure 7 The simulation diagram when the input values are 0V, 0.17V, 0.32V, 0.47V and the delay adjustment amount is 6p in Embodiment 1 of the present invention;

[0042] Figure 8 The simulation diagram when the input values are 0V, 0.175V, 0.338V, 0.576V and the delay adjustment amount is different in Embodiment 1 of the present invention;

[0043] Figure 9 The simulation diagram when INPUT = 503ps, t0 = 26ps, and Δt = 6ps in Embodiment 1 of the present invention;

[0044] Figure 10 The first Monte Carlo simulation diagram with different delay adjustment amounts in Embodiment 1 of the present invention;

[0045] Figure 11 The second Monte Carlo simulation diagram with different delay adjustment amounts in Embodiment 1 of the present invention;

[0046] Figure 12 The third Monte Carlo simulation diagram with different delay adjustment amounts in Embodiment 1 of the present invention;

[0047] Figure 13 The fourth Monte Carlo simulation diagram with different delay adjustment amounts in Embodiment 1 of the present invention. Specific Embodiments

[0048] In order to make the objectives, technical solutions, and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0049] Embodiment 1

[0050] Please refer to Figures 1 to 5, this embodiment provides a multi-bit in-memory computing array structure. The core structure of this in-memory computing array structure is multiple voltage-controlled delay circuits. In this embodiment, the in-memory computing array structure further includes a storage array, a quantization module, a digital shift adder module, an input signal column channel module, and a local read / write module. In some other embodiments, the in-memory computing array structure may further include some other modules or circuits, which can be set according to actual needs.

[0051] The multiple voltage-controlled delay circuits are arranged in a rectangular layout, that is, the voltage-controlled delay circuits are arranged in a matrix array, which is similar to the storage array. The columns of the matrix array correspond to a row of bit input values, and its rows correspond to a column of bit weight values. That is, the multiple voltage-controlled delay circuits in each column respectively correspond to multiple bit input values, and the multiple voltage-controlled delay circuits in each row respectively correspond to multiple bit weight values. Each voltage-controlled delay circuit has an input terminal, an output terminal, a voltage control terminal, and at least one control terminal. In each row, the output terminal of each voltage-controlled delay circuit is connected to the input terminal of the next column. The same control terminal in each column is connected and receives the corresponding bit weight value, and the voltage control terminals in each row are connected and receive the corresponding bit input values. When the control terminal signal is 0, the reference signal generates a delay one through the corresponding input terminal and output terminal. When the control terminal signal is 1, the reference signal generates a delay two through the corresponding input terminal and output terminal. The delay two is the sum of the delay one and the delay adjustment amount, and the delay adjustment amount is linearly positively correlated with the corresponding voltage control terminal signal. Among them, the in-memory computing array structure accumulates the delay adjustment amounts of multiple columns of voltage-controlled delay circuits to represent the multiplication and accumulation calculation results of multiple bit input values and multiple bit weight values.

[0052] Please continue to refer to Figure 2 , the storage array includes multiple memory cells arranged in a rectangular layout and is used to store multiple bit weight values. The storage array can be set in multiple groups, and each group is used to store a bit weight value. The memory cell is preferably 6T-SRAM in this embodiment. The storage array is used to switch between the standard read / write mode and the multi-bit multiplication and accumulation calculation mode. In the multi-bit multiplication and accumulation calculation mode, the in-memory computing array structure realizes the multiplication and accumulation calculation of multiple bit input values and multiple bit weight values. The first storage node and the second storage node of the memory cell are respectively connected to the local bit line LBL and LBLB.

[0053] In some embodiments including this embodiment, the reference signal is a rectangular wave reference signal. When the signal at control terminal one is 0 and the signal at control terminal two is 1, delay one is not affected by the voltage value of the voltage-controlled terminal and is defined as t0. When the signal at control terminal one is 1 and the signal at control terminal two is 0, when the voltage-controlled terminal signal is 00, delay two is t0 + 0Δt, when the voltage-controlled terminal signal is 01, delay two is t0 + 1Δt, when the voltage-controlled terminal signal is 10, delay two is t0 + 2Δt, and when the voltage-controlled terminal signal is 11, delay two is t0 + 3Δt. Define Δt as the unit adjustment amount, which is the minimum adjustment amount of the voltage-controlled delay circuit for the reference signal. The in-memory computing array structure calculates the multiply-accumulate calculation result of multiple bit input values and multiple bit weight values through the number of unit adjustment amounts contained in the delay adjustment amount.

[0054] Please continue to refer to Figure 3 , Figure 4 and Figure 5 , in this embodiment, each voltage-controlled delay circuit includes two voltage-controlled delay units, which are a high-bit voltage-controlled delay unit and a low-bit voltage-controlled delay unit respectively. Each voltage-controlled delay unit has an input terminal IN, an output terminal OUT, a voltage-controlled terminal (Vin, A for the high-bit voltage-controlled delay unit and B for the low-bit voltage-controlled delay unit), and two control terminals with opposite signals: control terminal one C and control terminal two CB. The delay adjustment amount of the voltage-controlled delay unit is jointly determined by the stored weight and the voltage value of the input signal, and can realize the multiplication calculation of 2-bit input and 1-bit weight. In the multi-bit in-memory computing mode, multiple voltage-controlled delay units delay the rising edge of the input rectangular wave reference signal, and the voltage-controlled delay units are connected in series step by step, and can realize the multiply-accumulate calculation of multi-bit input and multi-bit weight.

[0055] The output terminal OUT of each high-bit voltage-controlled delay unit is connected to the input terminal IN of the high-bit voltage-controlled delay unit in the next column. The control terminal of the high-bit voltage-controlled delay unit is only connected to the control terminal of the low-bit voltage-controlled delay unit, and is not connected to the control terminal of the high-bit voltage-controlled delay unit in the next row. The output terminal OUT of each low-bit voltage-controlled delay unit is connected to the input terminal IN of the low-bit voltage-controlled delay unit in the next column. The low-bit voltage-controlled delay unit is only connected to the control terminal of the high-bit voltage-controlled delay unit, and is not connected to the control terminal of the low-bit voltage-controlled delay unit in the next row. In each voltage-controlled delay circuit, control terminal one C of the high-bit voltage-controlled delay unit is connected to control terminal one C of the low-bit voltage-controlled delay unit, and control terminal two CB of the high-bit voltage-controlled delay unit is connected to control terminal two CB of the low-bit voltage-controlled delay unit. Control terminal one of each row of voltage-controlled delay circuits is connected to the local bit line LBL of the memory array, and control terminal two is connected to the local bit line LBLB of the memory array. The number of delay adjustment amounts of the high-bit voltage-controlled delay unit for the rising edge of the reference signal and the number of delay adjustment amounts of the low-bit voltage-controlled delay circuit for the rising edge of the reference signal are the multiplication calculation results of the corresponding 2-bit input and 1-bit weight.

[0056] The computing array structure of this embodiment realizes multiply-accumulate calculation in the following manner:

[0057] (1) Take the sum of four times the delay adjustment amount generated by the high-bit voltage-controlled delay units in each column and the delay adjustment amount generated by the low-bit voltage-controlled delay units as the total adjustment amount;

[0058] (2) Take the number of unit adjustment amounts contained in the total adjustment amount as the multiply-accumulate result of multiple-bit input values and single-bit weight values;

[0059] (3) Corresponding to multiple-bit weight values through multiple rows of voltage-controlled delay circuits, add multiple total adjustment amounts according to the weight ratio to obtain the multiplication calculation result of multiple-bit input values and multiple-bit weight values;

[0060] (4) The total adjustment amount generated by combining multiple rows of voltage-controlled delay circuits in a column form represents the multiply-accumulate calculation result of multiple-bit input values and multiple-bit weight values.

[0061] Here, each column can implement the multiplication calculation of multi-bit inputs and multi-bit weights. The operations implemented by different columns are the multiplication calculations of another set of multi-bit input and multi-bit weight values. The multiply-accumulate result of multi-bit inputs and multi-bit weight values is achieved through the cascading of multiple columns. The voltage-controlled input voltages of the voltage-controlled delay circuits in the same column are the same, both being A and B, but the input controls C and CB of the voltage-controlled delay units in the same column are different and are the data weights of the corresponding bit positions respectively. This means that the final outputs of different groups of voltage-controlled delay units are used to represent the multiplication calculation results of the data inputs and data weights of the corresponding bit positions. The number of Δt contained in the sum of four times the time adjustment amount of the high-bit voltage-controlled delay unit for the rising edge of the reference signal and the time adjustment amount of the low-bit voltage-controlled delay circuit for the rising edge of the reference signal is the multiplication calculation result of the bit input and the weight. The Δt in the above text is the unit adjustment amount, that is, the minimum adjustment amount of the voltage-controlled delay circuit for the reference signal.

[0062] As a design approach, each voltage-controlled delay unit in this embodiment includes an input control circuit, a trigger circuit, and an inverter circuit. In other embodiments, the structure of the voltage-controlled delay unit can be adaptively adjusted. The input control circuit is used to generate the analog value of the input voltage at the voltage control terminal, and has a control terminal C, a control terminal CB, and a voltage control terminal Vin. The trigger circuit is connected to the input control circuit and is used to output the delay adjustment amount of the reference signal pulse width, and has an input terminal IN. The inverter circuit is connected to the trigger circuit and is used to shape the waveform output by the trigger circuit, and has an output terminal OUT. C and CB are connected to the LBL and LBLB of the storage array. The output of the input control circuit is connected to the trigger circuit, the output of the trigger circuit is connected to the input of the inverter, the input of the trigger circuit is a rectangular wave reference signal IN, and the output port of the inverter is the output port OUT of the voltage-controlled delay circuit.

[0063] The trigger circuit is a Schmitt trigger circuit, which includes NMOS transistors N1 to N3 and PMOS transistor P1. The gate of N1 is connected to the reference signal, the source is grounded, and the drain is connected to node X1; the gate of N2 is connected to the reference signal, the source is connected to node X1, and the drain is connected to node X2. The gate of N3 is connected to node X2, the source is connected to node X1, and the drain is connected to node X3. The gate of P1 is connected to the reference signal, the source is connected to node X2, and the drain is connected to the power supply VDD. Among them, the gates of N1, N2, and P1 are used as the input terminals.

[0064] The input control circuit includes NMOS transistors N4 and N5. The gate of N4 is used as the control terminal C and is connected to the local bit line LBL, the source is connected to node X3, and the drain is used as the voltage control terminal. The gate of N5 is used as the control terminal CB and is connected to the local bit line LBLB, the source is grounded, and the drain is connected to node X3. When the input control C is 0, the voltage-controlled delay circuit delays the rising edge time of the reference signal by t0; when the input control C is 1, the voltage-controlled delay circuit adjusts the rising edge time of the reference signal on the basis of the rising edge time delay t0 of the reference signal, and the adjustment strategy is: the delay time of the rising edge of the reference signal is linearly positively correlated with the voltage control input Vin.

[0065] The inverter circuit includes NMOS transistor N6 and PMOS transistor P2. The gate of N6 is connected to node X2, the source is grounded, and the drain is used as the output terminal. The gate of P2 is connected to node X2, the source is used as the output terminal, and the drain is connected to the power supply VDD. That is, the drain of N6 is connected to the source of P2 and is used as the output terminal OUT.

[0066] The functions of the voltage-controlled delay unit are as follows:

[0067] When C = 0 and CB = 1 (the inverse signal of C), the delay of the voltage-controlled delay circuit is not affected by the voltage value of the voltage-controlled port. After the rectangular wave is delayed by the voltage-controlled delay circuit, the rising-edge delay is t0.

[0068] When C = 1 and CB = 0, the following situations exist:

[0069] V in = V 00 When it is, the rising-edge delay is t0 + 0Δt,

[0070] V in = V 01 When it is, the rising-edge delay is t0 + 1Δt,

[0071] V in = V 10 When it is, the rising-edge delay is t0 + 2Δt,

[0072] V in = V 11 When it is, the rising-edge delay is t0 + 3Δt.

[0073] That is: when the signal of the first control terminal is 0 and the signal of the second control terminal is 1, the first delay is a fixed value t0 and is not affected by the voltage of the voltage-controlled terminal. When the signal of the first control terminal is 1 and the signal of the second control terminal is 0, the second delay is t0 + kΔt. k is the binary value of the voltage-controlled terminal signal, and Δt is the unit adjustment amount, representing the minimum adjustment amount of the voltage-controlled delay circuit to the reference signal. The calculation array structure of this embodiment calculates the multiplication and accumulation calculation result of multiple bit input values and multiple bit weight values by delaying the number of unit adjustment amounts Δt included in the adjustment amount.

[0074] Table 1 Function table of the voltage-controlled delay unit

[0075]

[0076] The quantization module is used to convert the pulse width of the reference signal output by any voltage-controlled delay circuit in the last column from a time analog quantity to a binary digital signal. The quantization module quantizes the pulse width of the reference signal output by any voltage-controlled delay circuit in the last column and converts the pulse width from a time analog quantity to a binary digital signal. In this embodiment, the quantization module is a TDC quantization module, and the time-to-digital converter quantizes the rising-edge delay time output by the last column of the array, converts the time quantity to a binary code, and the quantized data can be the multiplication and accumulation results of multi-bit inputs and multi-bit weights of 32 columns (which can be changed according to needs).

[0077] The digital shift adder module is used to multiply the quantization result of the high-bit voltage-controlled delay unit by four and add it to the quantization result of the low-bit voltage-controlled delay unit to obtain the multiplication result of the single-bit input value and the single-bit weight value, and sum the multiplication results of different bit positions with weights to obtain the multiply-accumulate calculation result of the multi-bit input value and the multi-bit weight value. It is used to multiply the quantization result of the high-bit voltage-controlled delay unit by four and add it to the quantization result of the corresponding low-bit voltage-controlled delay unit to obtain the multiplication calculation result of the input and weight of the corresponding bit position. The digital shift adder module is also used to sum the multiplication calculation results of the input and weight of different bit positions according to the bit position relationship to obtain the multiply-accumulate calculation result of the multi-bit input value and the multi-bit weight value.

[0078] The local read / write module is used to complete the read / write operation of the memory cell by transmitting read / write signals through the horizontal word line HWL and the global bit line GBL / GBLB in the standard read / write mode. The local read / write module includes a seventh NMOS transistor N7 and an eighth NMOS transistor N8. The gate of the seventh NMOS transistor N7 is connected to the horizontal word line HWL, the drain is connected to the local bit line LBL, and the source is connected to the global bit line GBL. The gate of the eighth NMOS transistor N8 is connected to the horizontal word line HWL, the drain is connected to the local bit line LBLB, and the source is connected to the global bit line GBLB. When the horizontal word line HWL and the word line WL of the nth row of memory cells are turned on, the write signal is first transmitted to the local bit line LBL / LBLB through the global bit line GBL / GBLB, and then the data is written into the nth row of memory cells, where n is any row number of the memory cells.

[0079] Taking this embodiment as an example, the number of bit input values and bit weight values is four, that is, the multiply-accumulate result of the four-bit input IN3IN2IN1IN0 and the four-bit weight W3W2W1W0 is realized. The four groups of voltage-controlled delay units correspond to four bit positions respectively. Therefore, the multiplication calculation results of the data input and data weight of four bit positions can be obtained through the four groups of voltage-controlled delay units. Then, by adding the multiplication calculation results from the high-bit position to the low-bit position according to the weight ratio of 8 / 4 / 2 / 1, the multiplication calculation result of the four-bit input IN3IN2IN1IN0 and the four-bit weight W3W2W1W0 can be obtained.

[0080] The input signal column channel module is used to divide the four-bit input values IN3IN2IN1IN0 into a high-bit two-bit signal IN3IN2 and a low-bit two-bit signal IN1IN0. The high-bit two-bit signal IN3IN2 and the low-bit two-bit signal IN1IN0 respectively control the output voltages of the input column channel one connected to the high-bit voltage-controlled delay unit and the input column channel two connected to the low-bit voltage-controlled delay unit, and the voltage values are determined by the corresponding two-bit signals.

[0081] Please refer to Figures 6 - 13, this embodiment can achieve the multiplication calculation of four-bit input IN3IN2IN1IN0 and four-bit weight W3W2W1W0. Its core lies in characterizing the calculation result through the rising-edge delay adjustment amount of the reference signal. Since the rising-edge delay adjustment amount can be accumulated, when it is necessary to implement the multiply-accumulate calculation of four-bit input IN3IN2IN1IN0 and four-bit weight W3W2W1W0, only need to combine the multi-bit data in-memory computing arrays in column form, and the reference signals output by each voltage-controlled delay circuit in the previous column are received by the corresponding voltage-controlled delay circuits in the next column. Here, the correspondence means that they both correspond to the same bit and are both high-bit delay circuits or low-bit delay circuits. For example, there is a correspondence between the high-bit delay circuit corresponding to the second bit in the previous column and the high-bit delay circuit corresponding to the second bit in the next column. Furthermore, the calculation result of the bit in the previous column can be passed to the calculation result of the corresponding bit in the next column. The multi-bit data in-memory computing array provided by this embodiment supports forming a multi-bit data in-memory computing array structure through a combination form to achieve the multiply-accumulate calculation of four-bit input IN3IN2IN1IN0 and four-bit weight W3W2W1W0, which can provide a relatively large system-level inference accuracy and efficiency, and solves the problem that the current non-volatile in-memory computing circuits usually only support the multiply-accumulate in-memory calculation of single-bit input and weight, and can only provide limited system-level inference accuracy.

[0082] In Figure 8 , VIN are 0, 175mv, 338mv, 576mv respectively, and the corresponding delays are 26p, 32p, 38p, 44p respectively. In Figure 9 , INPUT = 503ps, t0 = 26ps, Δt = 6 ps, OUT7 = 649ps, OUT6 = 637ps, OUT5 = 625ps, OUT4 = 637ps, OUT3 = 643ps, OUT2 = 643ps, OUT1 = 631ps, OUT0 = 631ps, then there are: [(649 - 503) - 4t0] / Δt = 7; [(637 - 503) - 4t0] / Δt = 5; [(625 - 503) - 4t0] / Δt = 3; [(637 - 503) - 4t0] / Δt = 5; [(643 - 503) - 4t0] / Δt = 6; [(643 - 503) - 4t0] / Δt = 6; [(631 - 503) - 4t0] / Δt = 4; [(631 - 503) - 4t0] / Δt = 4. In Figures 10 - 13 , std are 2p, 2.5p, 3.1p, 4.2p respectively, and the Monte Carlo runs about 100 times, with the fluctuation below 5ps, and the fluctuation is very small.

[0083] Exemplarily, the control inputs of the four voltage-controlled delay units corresponding to the same bit position in the four columns are 1, 0, 1, and 1 respectively, and the input voltages of the four voltage-controlled delay units are as follows: A1 = V 11 , A2 = V 10 , A3 = V 00 , A4 = V 01 . Then the theoretical quantization result of the TDC is 3×1 + 2×0 + 0×1 + 1×1 = 4. Among them, after passing through the first column of voltage-controlled delay circuits, the rising edge of the rectangular wave is delayed by t0 + 3Δt; after passing through the second column of voltage-controlled delay circuits, the rising edge of the rectangular wave is delayed by t0 + 0Δt; after passing through the third column of voltage-controlled delay circuits, the rising edge of the rectangular wave is delayed by t0 + 0Δt; after passing through the fourth column of voltage-controlled delay circuits, the rising edge of the rectangular wave is delayed by t0 + Δt, and the total delay is 4t0 + 4Δt.

[0084] Just convert the rising delay amount of the rectangular wave in the last column into a binary number (the number of unit pulse delay adjustments Δt it contains), and then subtract this binary number from the binary number set according to the initial rising edge time of the rectangular wave to obtain the result of the 2-bit × 1-bit multiply-accumulate in the four columns in the above example.

[0085] In this embodiment, the multiply-accumulate process of the multi-bit data in-memory computing array structure is described, which shows that the multiplication calculation result in the previous column can be accumulated into the multiplication calculation result in the next column. Further, in the multi-bit data in-memory computing array structure, the number of columns of the multi-bit data in-memory computing array determines the maximum number of accumulation terms that this structure can perform, and the number of rows of the multi-bit data in-memory computing array determines the number of groups of four-bit multiply-accumulate that this structure can perform simultaneously. For example, in this embodiment, there are 4 multi-bit data in-memory computing arrays in each column, indicating that 4 groups of multi-bit multiply-accumulate calculations can be performed in parallel, and there are 32 columns in the multi-bit data in-memory computing array in total, indicating that the multiplication calculation results of up to 32 multi-bit terms can be accumulated.

[0086] Compared with the existing in-memory computing array structure, the multi-bit in-memory computing array structure and electronic device in this embodiment have the following beneficial effects:

[0087] The multi-bit in-memory computing array structure characterizes the calculation result by adjusting the rising edge delay of the reference signal. Since the rising edge delay adjustment amount can be accumulated, when implementing the multiply-accumulate calculation of multi-bit input and multi-bit weights, only need to combine multiple columns of multi-bit data in-memory computing arrays in a row form, and use the signals output by the voltage-controlled delay circuits in the previous column as the inputs of the corresponding voltage-controlled delay circuits in the next column. Furthermore, the calculation result of the bit position in the previous column can be passed to the calculation result of the corresponding bit position in the next column. The number of columns of the voltage-controlled delay circuits determines the maximum number of accumulation terms that this structure can perform, and also determines the number of groups of multi-bit multiply-accumulate that this structure can perform simultaneously. This computing array structure can provide high system-level inference accuracy and efficiency, and solves the problem that current non-volatile in-memory computing circuits usually only support the multiply-accumulate in-memory computing of single-bit input and weights, and can only provide limited system-level inference accuracy.

[0088] Embodiment 2

[0089] This embodiment provides a static random access memory (SRAM). This memory uses the multi-bit in-memory computing array structure in Embodiment 1 to implement the multiply-accumulate calculation of multi-bit input and multi-bit weights, and can implement the multiply-accumulate calculation of four-bit input and four-bit weights.

[0090] Based on the multi-bit in-memory computing array structure in Embodiment 1, the in-memory computing of SRAM in this embodiment directly completes the multiply-accumulate operation within the storage unit, reduces data movement, and significantly reduces power consumption. SRAM can simultaneously process the multiply-accumulate operations of multiple inputs and weights, greatly improving the computing efficiency, and is particularly suitable for application scenarios requiring high throughput. The read and write speeds of SRAM are much higher than those of DRAM and flash memory, and can achieve low-latency multiply-accumulate calculations, which are suitable for applications with high real-time requirements, such as edge computing and Internet of Things devices. SRAM can be integrated with other computing units (such as CPU, GPU) on the same chip to form an efficient in-memory computing architecture.

[0091] The SRAM in this embodiment is applicable to artificial intelligence and machine learning. The inference and training processes of neural networks involve a large number of multiply-accumulate operations, and the in-memory computing of SRAM can significantly accelerate these operations and improve the overall performance. The multi-bit input and weights enable SRAM to support from simple linear models to complex deep neural networks. The in-memory computing of the SRAM in this embodiment reduces the complex interface between the memory and the processor in the traditional computing architecture, and simplifies the system design. By reducing data movement and simplifying the architecture, SRAM can reduce the overall cost and power consumption of the system.

[0092] Embodiment 3

[0093] This embodiment provides an electronic device, which includes a memory and a processor. Among them, the memory includes the multi-bit in-memory computing array structure of Embodiment 1. Compared with existing electronic devices, this electronic device can significantly improve computing efficiency, reduce power consumption, and support high-precision computing. It has broad application prospects in fields such as artificial intelligence and edge computing. Although it faces some technical challenges, its advantages make it an important technical direction for in-memory computing.

[0094] Embodiment 4

[0095] This embodiment provides a computer device, which includes a memory, a processor, and a computer program stored on the memory and executable on the processor. Among them, the memory is the static random access memory in Embodiment 2.

[0096] This computer device can take various forms. It can either be an embedded chip or module, or a general-purpose data processing device, such as a smart terminal capable of executing programs, a tablet computer, a laptop computer, a desktop computer, a rack-mounted server, a blade server, a tower server, or a cabinet server (including an independent server or a server cluster composed of multiple servers), etc.

[0097] The computer device of this embodiment at least includes, but is not limited to, a memory and a processor that can communicate with each other through a system bus. The memory (i.e., the readable storage medium) includes flash memory, a hard disk, a multimedia card, a card-type memory (such as an SD or DX memory, etc.), a random access memory (RAM), a static random access memory (SRAM), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), a programmable read-only memory (PROM), a magnetic memory, a magnetic disk, an optical disk, etc. In some embodiments, the memory can be an internal storage unit of the computer device, such as the hard disk or memory of the computer device.

[0098] In some embodiments, the processor can be a central processing unit (CPU), a graphics processing unit (GPU), a controller, a microcontroller, a microprocessor, or other data processing chips. The processor is generally used to control the overall operation of the computer device. In this embodiment, the processor is used to run the program code stored in the memory or process data.

[0099] Embodiment 5

[0100] This embodiment provides an artificial intelligence chip, which includes the multi-bit in-memory computing array structure in Embodiment 1. It has a standard read / write mode and a multi-bit multiply-accumulate calculation mode. In the standard read / write mode, the read / write operations of data in the storage array can be realized. In the multi-bit multiply-accumulate calculation mode, the chip can realize the operation of multiplying and accumulating multiple-bit input values and multiple-bit weight values. In this way, the chip can efficiently process artificial intelligence tasks, is not prone to problems such as excessive energy consumption and latency, avoids the "memory wall", and greatly reduces the data migration and memory access consumption of the memory. The artificial intelligence chip in this embodiment has multi-bit input (IN) and output (OUT) multiply-accumulation, which is beneficial to promoting the realization of artificial intelligence chips with high inference accuracy.

[0101] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A multi-bit in-memory computing array structure, characterized in that: It includes: A plurality of voltage-controlled delay circuits are arranged in a rectangular shape, wherein a column corresponds to a row of bit input values, and a row corresponds to a column of bit weight values; each voltage-controlled delay circuit has an input terminal, an output terminal, a voltage-controlled terminal, and at least one control terminal; in each row, the output terminal of each voltage-controlled delay circuit is connected to the input terminal of the next column; The same control end of each column is connected and receives the corresponding bit weight value, and the voltage control end of each row is connected and receives the corresponding bit input value; when the control end signal is 0, the reference signal generates a delay of one through the corresponding input end and output end; when the control end signal is 1, the reference signal generates a delay of two through the corresponding input end and output end; the delay of two is the sum of the delay of one and the delay adjustment amount, and the delay adjustment amount is linearly positively correlated with the corresponding voltage control end signal; each voltage control delay circuit includes a high voltage control delay unit and a low voltage control delay unit ... The control delay unit has the input end, the output end, the voltage control end, and two control ends with opposite signals: control end 1 and control end 2; in each column, the output end of the high-order voltage-controlled delay unit is connected to the input end of the high-order voltage-controlled delay unit in the next column, and the output end of the low-order voltage-controlled delay unit is connected to the input end of the low-order voltage-controlled delay unit in the next column; in each voltage-controlled delay circuit, the control end 1 of the high-order voltage-controlled delay unit is connected to the control end 1 of the low-order voltage-controlled delay unit, and the control end 2 of the high-order voltage-controlled delay unit is connected to the control end 2 of the low-order voltage-controlled delay unit; A memory array; a control terminal 1 of each row of the voltage-controlled delay circuit is connected to a local bit line LBL of the memory array, and a control terminal 2 is connected to a local bit line LBLB; Among them, the delay adjustment amounts of multiple columns of voltage-controlled delay circuits are accumulated to represent the multiplication and accumulation calculation results of multiple bit input values ​​and multiple bit weight values; the calculation array structure implements the multiplication and accumulation calculation in the following manner: (1) The sum of four times the delay adjustment amount generated by the high-order voltage-controlled delay unit in each column and the delay adjustment amount generated by the low-order voltage-controlled delay unit is taken as the total adjustment amount; (2) taking the number of unit adjustment amounts contained in the total adjustment amount as the multiplication and accumulation result of the multiple bit input values ​​and the single bit weight value; (3) using multiple rows of voltage-controlled delay circuits corresponding to multiple bit weight values, adding multiple total adjustment amounts according to the weight ratio to obtain a multiplication result of multiple bit input values ​​and multiple bit weight values; (4) The total adjustment amount generated by combining multiple rows of voltage-controlled delay circuits in column form represents the multiplication and accumulation calculation results of multiple bit input values ​​and multiple bit weight values.

2. The multi-bit in-memory computing array structure according to claim 1, characterized in that: Each voltage-controlled delay unit includes: An input control circuit, used for generating an input voltage analog quantity of the voltage control terminal according to signals of the control terminal 1 and the control terminal 2; A trigger circuit connected to the input control circuit and configured to output a delay adjustment amount of a reference signal pulse width according to an input terminal signal; An inverter circuit is connected to the trigger circuit, is used for shaping the waveform output by the trigger circuit, and has the output end.

3. The multi-bit in-memory computing array structure as claimed in claim 2, characterized in that: The trigger circuit includes NMOS tubes N1-N3 and PMOS tube P1; the gate of N1 is connected to the reference signal, the source is grounded, and the drain is connected to node X1; the gate of N2 is connected to the reference signal, the source is connected to node X1, and the drain is connected to node X2; the gate of N3 is connected to node X2, the source is connected to node X1, and the drain is connected to node X3; the gate of P1 is connected to the reference signal, the source is connected to node X2, and the drain is connected to the power supply VDD; the gates of N1, N2, and P1 serve as the input terminals; The input control circuit includes NMOS transistors N4 and N5; the gate of N4 serves as the control terminal 1 and is connected to the local bit line LBL, the source is connected to the node X3, and the drain serves as the voltage control terminal; the gate of N5 serves as the control terminal 2 and is connected to the local bit line LBLB, the source is grounded, and the drain is connected to the node X3; The inverter circuit includes an NMOS tube N6 and a PMOS tube P2; the gate of N6 is connected to the node X2, the source is grounded, and the drain is used as the output terminal; the gate of P2 is connected to the node X2, the source is used as the output terminal, and the drain is connected to the power supply VDD.

4. The multi-bit in-memory computing array structure according to claim 1, wherein: The in-memory computing array structure also includes: A quantization module, which is used to convert the pulse width of the reference signal output by the last column of arbitrary voltage-controlled delay circuits from a time analog quantity into a binary digital signal; A digital shift adder module is used to amplify the quantization result of the high-bit voltage-controlled delay unit by four times and add it to the quantization result of the low-bit voltage-controlled delay unit to obtain the multiplication result of the single-bit input value and the single-bit weight value, and to weight the multiplication results of different bits according to the weights to obtain the multiplication and accumulation calculation results of the multi-bit input value and the multi-bit weight value.

5. The multi-bit in-memory computing array structure according to claim 1, characterized in that: The reference signal is a rectangular wave reference signal; when the control terminal 1 signal is 0 and the control terminal 2 signal is 1, the delay 1 is a fixed value t0 and is not affected by the voltage of the voltage control terminal; when the control terminal 1 signal is 1 and the control terminal 2 signal is 0, the delay 2 is t0 +k Δt; Among them, k is the binary value of the voltage-controlled end signal, Δt is the unit adjustment amount, which represents the minimum adjustment amount of the voltage-controlled delay circuit to the reference signal; the calculation array structure calculates the multiplication and accumulation results of multiple bit input values ​​and multiple bit weight values ​​through the number of unit adjustment amounts Δt contained in the delay adjustment amount.

6. The multi-bit in-memory computing array structure according to claim 1, characterized in that: The number of the bit input values ​​and the number of the bit weight values ​​are both four; The in-memory computing array structure also includes: An input signal column channel module is used to divide the four-bit input values ​​into a high-order two-bit signal and a low-order two-bit signal, and respectively control the output voltage of the input column channel one of the high-order voltage-controlled delay unit and the input column channel two of the low-order voltage-controlled delay unit, and the output voltage value is determined by the corresponding two-bit signal.

7. The multi-bit in-memory computing array structure according to claim 1, characterized in that: The in-memory computing array structure also includes: A storage array includes a plurality of storage cells arranged in a rectangular shape, which are used to store a plurality of bit weight values ​​and support switching between a standard read / write mode and a multi-bit multiplication-accumulation calculation mode; in the multi-bit multiplication-accumulation calculation mode, the calculation array structure realizes multiplication-accumulation calculation of a plurality of bit input values ​​and a plurality of bit weight values; a first storage node and a second storage node of each storage cell are respectively connected to a local bit line LBL and a local bit line LBLB.

8. The multi-bit in-memory computing array structure according to claim 7, characterized in that: The in-memory computing array structure also includes: A local read / write module is used to transmit read / write signals through a horizontal word line HWL and a global bit line GBL / GBLB in a standard read / write mode to complete the read / write operations on the storage unit; the local read / write module includes NMOS tubes N7 and N8; the gate of N7 is connected to the horizontal word line HWL, the drain is connected to a local bit line LBL, and the source is connected to the global bit line GBL; the gate of N8 is connected to the horizontal word line HWL, the drain is connected to a local bit line LBLB, and the source is connected to the global bit line GBLB; when the horizontal word line HWL and the word line WL of the n-th row storage unit are turned on, the write signal is first transmitted to the local bit line LBL / LBLB through the global bit line GBL / GBLB, and then the data is written into the n-th row storage unit, where n is an arbitrary number of rows of storage units.

9. An electronic device comprising a memory and a processor; characterized in that: The memory includes a multi-bit in-memory computing array structure as described in any one of claims 1-8.

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