Simulation simplification method of reflow soldering packaging process

Abstract

The invention provides a simulation simplification method for a reflow soldering packaging process. The simulation simplification method comprises the following steps: acquiring parameters of a plurality of components in a packaging structure and establishing a geometric model corresponding to each component; establishing an equivalent geometric model corresponding to each component; delimiting an equivalent area according to the density in the equivalent geometric model, performing material thermal equivalence on a part in the equivalent area, and generating an equivalent material model corresponding to the equivalent geometric model; establishing an equivalent simplified geometric model according to the equivalent geometric model and the equivalent material model corresponding to the equivalent geometric model; and establishing a simulation model according to the plurality of equivalent simplified geometric models. According to the invention, the problems of low simulation efficiency and large resource consumption of a simulation method of a reflow soldering packaging process in the prior art are solved.

Description

Technical Field

[0001] The present invention relates to the field of microelectronic packaging technology, and in particular to a simulation simplification method for a reflow soldering packaging process. Background Art

[0002] In the current electronic packaging field, as the integration of integrated circuits continues to increase, 2.5D packaging technology has been widely used due to its unique advantages. However, as a key step in 2.5D packaging, the reflow process faces many challenges in quality prediction.

[0003] Traditional methods for predicting the quality of reflow soldering processes mainly rely on experience and actual process experiments. However, with the increasing complexity of packaging structures and the sharp increase in scale, the accuracy and completeness of this method are gradually no longer guaranteed. Many uncertain factors in the experimental process and the limitation of experimental costs make it difficult to comprehensively and accurately predict the quality of the reflow soldering process.

[0004] In order to overcome this problem, a method based on finite element simulation came into being. This method can perform numerical simulation of the entire reflow process, thereby providing more accurate simulation predictions. However, with the continuous increase in packaging scale and complexity, simulation time and resource consumption also increase. For 2.5D packaging, a packaging form with complex structure and large scale, relying on detailed modeling to realize reflow process simulation will consume a lot of time and computing resources, and it is difficult to integrate into the fast-paced process production line iteration. At the same time, this also increases the cost of computing resources, which has an adverse impact on the production efficiency of the enterprise.

[0005] In addition, the existing reflow simplification methods for models and materials in 2.5D packaging are incomplete. Most methods only optimize the process flow of the simulation, but do not involve the simplification and equivalence of the detailed model. This results in a large amount of detailed information still needing to be processed during the simulation process, reducing the efficiency of the simulation. In addition, in the existing equivalent methods, the metal wiring layer of the rewiring layer on the interposer is generally simply equivalent to a copper plate, while the PI (Polyimide) dielectric material between the wiring is ignored. Although this simplification method reduces the complexity of the model, it will also cause deviations between the stress simulation and the warpage simulation and the actual process results, affecting the accuracy of the simulation.

[0006] In summary, the simulation method of the reflow soldering packaging process in the prior art has the problems of low simulation efficiency and high resource consumption. Summary of the invention

[0007] The purpose of the present invention is to provide a simplified simulation method for a reflow soldering packaging process, so as to solve the problems of low simulation efficiency and high resource consumption in the simulation method for the reflow soldering packaging process in the prior art.

[0008] In order to achieve the above-mentioned object of the present invention, an embodiment of the present invention provides a simulation simplification method of a reflow soldering packaging process, which includes the following steps: Obtaining parameters of multiple components in the package structure and establishing a geometric model corresponding to each component; Establishing an equivalent geometric model corresponding to each component; Delineating an equivalent region according to the density in the equivalent geometric model, performing material thermal equivalence on the part within the equivalent region, and generating an equivalent material model corresponding to the equivalent geometric model; Establish an equivalent simplified geometric model according to the equivalent geometric model and the corresponding equivalent material model; The simulation model is established based on multiple equivalent simplified geometric models.

[0009] As a further improvement of an embodiment of the present invention, in the process of “obtaining parameters of multiple components in the packaging structure and establishing a geometric model corresponding to each component”, the geometric model is established by using Space Claim software.

[0010] As a further improvement of an embodiment of the present invention, the plurality of components include: EMC molding compound, chip, ABF substrate, solder joint, silicon interposer, and redistribution layer.

[0011] As a further improvement of an embodiment of the present invention, the process of establishing an equivalent geometric model corresponding to each component specifically includes: When establishing the equivalent geometric model corresponding to the silicon interposer, the sidewall barrier layer of the through silicon via is ignored, the through silicon via is equivalent to a single copper conductor structure, and the silicon interposer is divided into regions according to the density of the through silicon via.

[0012] As a further improvement of an embodiment of the present invention, the process of establishing an equivalent geometric model corresponding to each component further includes: When establishing an equivalent geometric model corresponding to the redistribution layer, the equivalent regions are divided according to the wiring density based on the layout information, and each region includes a metal conductor and a filling medium.

[0013] As a further improvement of an embodiment of the present invention, the solder joints include C2 solder joints and C4 solder joints, the chips include a main control chip, an HBM chip, and a dummy layer chip, and the process of establishing an equivalent geometric model corresponding to each component further includes: When establishing the equivalent geometric model corresponding to the C2 solder joint and the C4 solder joint, the C2 solder joint and the C4 solder joint array are respectively equivalent to a hexahedral cubic block model, wherein the C2 solder joint connects the main control chip, the HBM chip, the dummy layer chip and the silicon interposer, and the C4 solder joint connects the silicon interposer and the ABF substrate.

[0014] As a further improvement of an embodiment of the present invention, the specific method of thermal equivalence of the material includes: When performing material thermal equivalence on the silicon interposer, the through silicon via and the surrounding silicon material are regarded as an integral component, and the longitudinal Young's modulus, transverse Young's modulus, longitudinal Poisson's ratio, transverse Poisson's ratio and thermal expansion coefficient are calculated based on the elastic mechanics method. Then, the material thermal equivalence is performed based on the above parameters.

[0015] As a further improvement of an embodiment of the present invention, the specific method of thermal equivalence of the material includes: When performing material thermal equivalence on the redistribution layer, the equivalent elastic modulus, Poisson's ratio and thermal expansion coefficient are calculated using an orthotropic composite material model based on the volume ratio of the metal conductor and the dielectric material, and then the material thermal equivalence is performed based on the aforementioned parameters.

[0016] As a further improvement of an embodiment of the present invention, the specific method of thermal equivalence of the material includes: When performing material thermal equivalence on solder joints, the equivalent Young's modulus, Poisson's ratio and thermal expansion coefficient are calculated by a linear weighted method based on the volume fraction of the solder joint and the filling material, and then the material thermal equivalence is performed based on the aforementioned parameters.

[0017] Compared with the prior art, the present invention has the following beneficial effects: The simulation model established by determining the thermal parameters of the equivalent material area through density can meet the calculation accuracy of reflow soldering and reduce the resource occupation of the model. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A flowchart of a simulation simplification method for a reflow soldering packaging process provided by an embodiment of the present invention; Figure 2 is a schematic diagram of a simplified geometric model partition of an intermediate layer in one embodiment of the present invention; Figure 3 is a schematic diagram of a simplified geometric model partition of a small solder joint in one embodiment of the present invention; Figure 4 3 is a comparison diagram of the warpage simulation results of a simulation model (b) established based on an equivalent simplified geometric model and a detailed modeling model (a) according to an embodiment of the present invention. DETAILED DESCRIPTION

[0019] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0020] It should be noted that, unless otherwise specified, all technical and scientific terms used in this application have the same meanings as commonly understood by ordinary technicians in the technical field to which this application belongs.

[0021] In the present invention, unless otherwise specified, the directional words used, such as "up, down, top, bottom", usually refer to the directions shown in the drawings, or to the components themselves in the vertical, perpendicular or gravity directions; similarly, for ease of understanding and description, "inside and outside" refer to the inside and outside relative to the outline of each component itself, but the above-mentioned directional words are not used to limit the present invention.

[0022] In order to solve the problems of low simulation efficiency and high resource consumption in the simulation method of the reflow soldering packaging process in the prior art, the present invention provides a simplified simulation method of the reflow soldering packaging process.

[0023] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments. Example

[0024] like Figure 1 As shown, a simulation simplification method for a reflow soldering packaging process provided by an embodiment of the present invention includes the following steps: S1: Obtain parameters of multiple components in the packaging structure and establish a geometric model corresponding to each component; S2: Establishing an equivalent geometric model corresponding to each component; S3: Delineating an equivalent region according to the density in the equivalent geometric model, performing material thermal equivalence on the part within the equivalent region, and generating an equivalent material model corresponding to the equivalent geometric model; S4: establishing an equivalent simplified geometric model according to the equivalent geometric model and the corresponding equivalent material model; S5: Establish a simulation model based on multiple equivalent simplified geometric models.

[0025] In this embodiment, the reflow soldering package is a 2.5D package, which is an advanced heterogeneous integration technology between traditional 2D planar packaging and 3D stacked packaging. Its core feature is to achieve high-density interconnection of multiple chips (such as logic chips, memory chips, etc.) through a silicon interposer, while optimizing signal transmission efficiency and power consumption by using through silicon vias (TSV) and redistribution layers (RDL).

[0026] It should be noted that in the present invention, the "geometric model" is the physical model of the object in space, also known as the original model. The "equivalent geometric model" only considers the division of density on the geometric model. The "equivalent material model" performs material equivalence in this divided area.

[0027] In the present invention, the basic principle of the simulation simplification method of the reflow soldering packaging process is: first, a packaging structure is selected, which usually includes multiple components, and the parameters of the multiple components in the packaging structure are analyzed. The purpose of analyzing the parameters is to establish a geometric model of each component; then, an equivalent geometric model corresponding to each component is established, and the equivalent geometric model of each component is the division of the density of the component on its geometric model; then, equivalent areas are delineated according to the density in the equivalent geometric model, and different equivalent areas are divided into different densities; the part in each equivalent area is subjected to material thermal equivalence and an equivalent material model corresponding to the equivalent geometric model is generated; then, an equivalent simplified geometric model is established based on the equivalent geometric model and the corresponding equivalent material model; finally, a simulation model is established based on multiple equivalent simplified geometric models.

[0028] Establishment of equivalent geometric model: In the step of establishing the equivalent simplified geometric model of each component of the 2.5D package structure, first, according to the layout information, the Space Claim software in Ansys Workbench is used to perform three-dimensional modeling of the 2.5D package structure to be simulated to establish a geometric model. Layout information refers to the physical layout data generated from the chip and package design stage, which is used to describe the precise geometric shape, spatial position, material properties and connection relationship of each component in the package structure.

[0029] The components selected for building the geometric model include: EMC plastic packaging material, chips (including: main control chip, dummy layer chip and HBM chip), ABF substrate, solder balls (C2 solder joints and C4 solder joints), silicon interposer, and redistribution layer. Name the built geometric model for easy reference in subsequent operations.

[0030] The process of establishing an equivalent geometric model includes the following situations: 1) For the through silicon via (TSV) in the interposer, since the thickness of its sidewall barrier layer (silicon dioxide) is much larger than the surrounding silicon material and the surrounding copper filling, this component is ignored in the modeling of the material equivalent model and the equivalent geometric model, and the TSV is treated as a single copper conductor. The silicon interposer is divided into regions according to the density of the through silicon via, and then the material equivalent treatment is performed on each divided region; 2) For the redistribution layer, the redistribution layer (RDL) in the 2.5D package is a key component on the interposer, which is used to achieve high-density electrical interconnection between the chip and the substrate. RDL is composed of multiple layers of metal wires and dielectric materials, and a fine wiring network is formed through photolithography and electroplating processes. Due to the complexity of wiring, the wiring layer is generally equivalent to a single layer of metal. In this example, in order to ensure the accuracy of the simulation, the wiring layer is divided into the same area (including metal and filling resin medium) according to the layout information, and the material is equivalent to the partition; 3) For the C2 and C4 solder joint arrays (BGA) located above and below the interposer, since the purpose of the reflow process is to form solder joint bonding, the solder joints are not volume-equivalent or divided into equivalent geometric model regions. However, since the 2.5D package structure in this example is complex and contains tens of thousands of large and small solder joints, if a completely detailed model is directly made based on the layout, the meshing density and complexity of the finite element simulation will be greatly increased. Although the stress and deformation of the solder joints in the actual process can be more accurately characterized, the computing resources and time costs cannot be balanced. Therefore, in this embodiment, the solder joint structure is equivalent to a hexahedral cubic block model, and the parts connected are: main control chip-interposer, HBM-interposer, dummy layer-interposer, and interposer-ABF substrate.

[0031] Establishment of equivalent material models and equivalent simplified geometric models of each component of the packaging structure: 1) For the material equivalence of the silicon interposer, the mechanical analysis method of composite material properties is used to treat the silicon via (copper) and the silicon material surrounding it as an equivalent material model of the entire component. The entire equivalent material model is regarded as an isotropic material and the equivalent Young's modulus and Poisson's ratio of the divided area are obtained by the method of elastic mechanics. According to the analysis method of elastic mechanics, the equivalent longitudinal Young's modulus E can be obtained. V for: ; Among them, E Cu and E Si are the elastic moduli of copper and silicon, v Cu and v Si are the Poisson's ratios of copper and silicon, V Cu and V Si are the volume ratios of copper and silicon, respectively.

[0032] Equivalent transverse Young's modulus E l for: ; in: ; ; ; .

[0033] Equivalent longitudinal Poisson's ratio v 12 for: .

[0034] Equivalent transverse Poisson's ratio v 23 for: .

[0035] The equivalent shear modulus is: .

[0036] The longitudinal equivalent thermal expansion coefficient α1 is: .

[0037] The lateral equivalent thermal expansion coefficient α2 is: .

[0038] Based on the parameters obtained from the above calculations, the thermal equivalence of the silicon interposer material can be performed and an equivalent material model can be established. Then, based on the equivalent material model of the interposer and the equivalent geometric model established previously, a simplified geometric model of the interposer can be established.

[0039] A schematic diagram of the simplified geometric model partitioning of the interposer can be found in Figure 2 shown.

[0040] 2) As for the equivalence of the redistribution layer, since the redistribution layer is composed of copper transmission lines and the PI surrounding it, the redistribution layer cannot be equivalent to a single metal or dielectric. In this embodiment, the representative volume fraction equivalent method is adopted to perform the equivalent of the layer, and the equivalent mechanical properties of the composite material with orthogonal anisotropic characteristics are obtained. The equivalent formula based on the composite material theory is expressed as follows: ; ; ; ; ; ; Among them, V m and V f Represent the volume percentage of PID and copper respectively; E m 、v m and α mThey represent the elastic modulus, Poisson's ratio and thermal expansion coefficient (CTE) of PID respectively; symbols E1, v 12 and α1 represent the equivalent elastic modulus, Poisson’s ratio and thermal expansion coefficient of RDL (redistribution layer) in the thickness direction, respectively; while E2, v 23 and α2 represent the equivalent elastic modulus, Poisson’s ratio and thermal expansion coefficient of RDL in the plane direction. f1 , ν 12 and α f1 are the elastic modulus, Poisson's ratio and thermal expansion coefficient of the copper wire in the direction perpendicular to the upper surface of the RDL; and E f2 , ν 23 and α f2 It represents the elastic modulus, Poisson's ratio and thermal expansion coefficient of the copper conductor in the transverse direction. Compared with the volume percentage method, the representative volume method considered in this example can obtain more accurate alternative mechanical properties.

[0041] Based on the parameters obtained by the above calculations, the thermal equivalence of the material of the redistribution layer can be performed and an equivalent material model can be established. Then, according to the equivalent material model of the redistribution layer and the equivalent geometric model established previously, a simplified geometric model of the redistribution layer can be established.

[0042] 3) For the equivalence at the solder joint level, since the interposer and the chip (main control chip, HBM, dummy chip) are bonded by small solder joints (C2 bumps), their volume and proportion in the lower filling layer are small, and based on process experience, it is inferred that the stress peak and stress concentration points of the solder joints are mainly concentrated near the edge of the chip. Therefore, a reasonable equivalent method is used to equate the designated area inside the chip to a uniform material layer, while the solder joints near the edge of the chip are still modeled using simplified six-sided cubes. As for the large solder joints (C4 bumps) under the interposer, they are also modeled using simplified six-sided cubes instead of uniform material layer equivalence due to their large volume and sparseness. The method for uniform material layer equivalence of small solder joints in this embodiment is as follows: The equivalent Young's modulus (E) of the small solder joint filling layer is expressed as: ; Among them, E f and c f are Young's modulus and volume fraction of small solder joints respectively; E m and c m are Young’s modulus and volume fraction of filler in the filling layer of small solder joints, respectively; The equivalent Poisson's ratio (v) of the small solder joint filling layer is expressed as: ; Among them, Kf and v f are the bulk modulus and Poisson’s ratio of the small solder joint, K m and v m are the bulk modulus and Poisson’s ratio of the filler in the filling layer of the small solder joint, respectively; The equivalent thermal expansion coefficient (α) of the small solder joint filling layer is expressed as: ; where α f and α m They are the thermal expansion coefficients of the small solder joint and the filler in the small solder joint filling layer, respectively.

[0043] Based on the parameters obtained from the above calculations, the thermal equivalence of the materials of large solder joints and small solder joints can be performed and an equivalent material model can be established. Then, based on the equivalent material model of the large solder joints and small solder joints and the equivalent geometric model established previously, a simplified geometric model of the large solder joints and small solder joints can be established.

[0044] Data output and analysis processing: 1) When creating an equivalent model, the area will be divided according to density. The area division of the interposer is as follows: Figure 2 As shown in Figure 2, the area of ​​the small solder joints on the interposer is divided as follows: Figure 3 shown.

[0045] 2) After demarcating the equivalent area according to density, perform material thermal parameter equivalence on parts within the equivalent area. According to the material equivalence method for the interposer, redistribution layer and small solder joint area mentioned above, the equivalent Young's modulus, Poisson's ratio and thermal expansion coefficient of each area are obtained. Taking the TSV equivalence of the interposer as an example, the above equivalence method is used to perform regional material equivalence. Since the TSV density in each area is the same, all blocks are equivalent to the same material. The equivalent material results and the thermal parameter properties of the original material are shown in Table 1 below: Table 1 Equivalent thermal parameter coefficients of each region

[0046] From this, we can see that since the volume fraction of copper is very small and silicon dioxide is ignored, after material equivalence, the material parameters of copper and silicon are very close.

[0047] 3) The steady-state thermal simulation and stress warpage simulation of the reflow process are carried out on the detailed BGA model in the 2.5D package after material equivalent simplification and geometric model simplification. The boundary condition settings are the same as those of the equivalent model. The warpage of the solder joints of the two models is as follows: Figure 4As shown, (a) is the reflow soldering simulation warpage distribution diagram after detailed modeling of the 2.5D packaging structure, and (b) is the packaging structure simulation warpage distribution diagram after replacing the equivalent simplified model mentioned in this embodiment. By comparison, it can be seen that the warpage distribution trend before and after the equivalent is consistent, and the maximum warpage range is concentrated at the junction of the main control chip and the HBM chip. By comparing the stress equivalence and the warpage, it can be intuitively seen that the equivalent model has a good effect. Therefore, the error of the simulation model result determined by the thermal parameters determined by the density of the equivalent material area and the thermal parameters modeling using the detailed structure meets the requirements, fully meets the calculation accuracy of the reflow soldering, and greatly simplifies the detailed model.

[0048] In summary, the embodiments of the present invention achieve the following technical effects: The simulation model established by determining the thermal parameters of the equivalent material area through density can meet the calculation accuracy of reflow soldering and reduce the resource occupation of the model.

[0049] Obviously, the above-described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0050] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0051] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein.

[0052] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A simulation simplification method for a reflow soldering packaging process, characterized in that: The following steps are involved: Obtaining parameters of multiple components in the package structure and establishing a geometric model corresponding to each component; Establishing an equivalent geometric model corresponding to each component; Delineating an equivalent region according to the density in the equivalent geometric model, performing material thermal equivalence on the part within the equivalent region, and generating an equivalent material model corresponding to the equivalent geometric model; Establish an equivalent simplified geometric model according to the equivalent geometric model and the corresponding equivalent material model; A simulation model is established based on multiple equivalent simplified geometric models.

2. The simulation simplification method of the reflow soldering packaging process according to claim 1, characterized in that: In the process of "obtaining parameters of multiple components in the package structure and establishing a geometric model corresponding to each component", the geometric model is established through Space Claim software.

3. The simulation simplification method of the reflow soldering packaging process according to claim 2, characterized in that: The multiple components include: EMC plastic packaging material, chip, ABF substrate, solder joints, silicon interposer, and redistribution layer.

4. The simulation simplification method of the reflow soldering packaging process according to claim 3, characterized in that: The process of establishing an equivalent geometric model corresponding to each component specifically includes: When establishing the equivalent geometric model corresponding to the silicon interposer, the TSV sidewall barrier layer is ignored, the TSV is equivalent to a single copper conductor structure, and the silicon interposer is divided into regions according to the TSV density.

5. The simulation simplification method of the reflow soldering packaging process according to claim 3, characterized in that: The process of establishing an equivalent geometric model corresponding to each component also includes: When establishing an equivalent geometric model corresponding to the redistribution layer, the equivalent regions are divided according to the wiring density based on the layout information, and each region includes a metal conductor and a filling medium.

6. The simulation simplification method of the reflow soldering packaging process according to claim 3, characterized in that: The solder joints include C2 solder joints and C4 solder joints, the chips include a main control chip, an HBM chip, and a dummy layer chip, and the process of establishing an equivalent geometric model corresponding to each component further includes: When establishing the equivalent geometric model corresponding to the C2 solder joint and the C4 solder joint, the C2 solder joint and the C4 solder joint array are respectively equivalent to a hexahedral cubic block model, wherein the C2 solder joint connects the main control chip, the HBM chip, the dummy layer chip and the silicon interposer, and the C4 solder joint connects the silicon interposer and the ABF substrate.

7. The simulation simplification method of the reflow soldering packaging process according to claim 1, characterized in that: The specific method of thermal equivalence of the material includes: When performing material thermal equivalence on the silicon interposer, the through silicon via and the surrounding silicon material are regarded as an integral component, and the longitudinal Young's modulus, transverse Young's modulus, longitudinal Poisson's ratio, transverse Poisson's ratio and thermal expansion coefficient are calculated based on the elastic mechanics method. Then, the material thermal equivalence is performed based on the above parameters.

8. The simulation simplification method of the reflow soldering packaging process according to claim 1, characterized in that: The specific method of thermal equivalence of the material includes: When performing material thermal equivalence on the redistribution layer, the equivalent elastic modulus, Poisson's ratio and thermal expansion coefficient are calculated using an orthotropic composite material model based on the volume ratio of the metal conductor and the dielectric material, and then the material thermal equivalence is performed based on the aforementioned parameters.

9. The simulation simplification method of the reflow soldering packaging process according to claim 1, characterized in that: The specific method of thermal equivalence of the material includes: When performing material thermal equivalence on solder joints, the equivalent Young's modulus, Poisson's ratio and thermal expansion coefficient are calculated by a linear weighted method based on the volume fraction of the solder joint and the filling material, and then the material thermal equivalence is performed based on the aforementioned parameters.

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