Parameterized capacitance extraction method and device, equipment and storage medium
The parasitic capacitance parameters are extracted through the deep symbol learning model, which solves the problems of low extraction accuracy and high computational complexity in the prior art, and achieves more efficient and accurate parasitic capacitance parameters extraction.
Patent Information
- Application Number
- CN202411868695.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-18
- Publication Date
- 2025-05-02
AI Technical Summary
The prior art has problems of low accuracy and high computational complexity when extracting parasitic capacitance parameters, especially when dealing with complex circuits and high-density integrated circuits.
The deep symbol learning model is adopted to parameterize the layout data of the two-dimensional capacitor structure, and the deep symbol learning model is trained to predict parasitic capacitance parameters and saved to the parasitic capacitance library.
It realizes more accurate extraction of parasitic capacitance parameters, reduces approximate errors in traditional methods, improves computing efficiency, and is especially suitable for complex integrated circuit designs.
Smart Images
Figure CN119918486A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuit technology, and in particular to a method, device, equipment and storage medium for extracting parameterized capacitance. Background Art
[0002] As the complexity of integrated circuit (IC) design continues to increase, especially in high-frequency and high-speed circuits, the impact of parasitic effects on circuit performance is becoming increasingly significant. Components such as parasitic capacitance, parasitic resistance and parasitic inductance in the circuit have an important impact on signal transmission, timing, power consumption and electromagnetic compatibility. Parasitic capacitance is formed by the interaction of electric fields between different metal layers and wires in the circuit, which usually causes signal delays, increased power consumption, and even signal interference.
[0003] Traditional parasitic capacitance extraction methods usually rely on physical models or empirical formulas. Although these methods are effective in some cases, they are often not accurate enough when dealing with complex circuits and high-density integrated circuits, and the calculation complexity is high. Therefore, how to accurately and efficiently extract parasitic capacitance parameters and optimize them has become a major challenge in modern integrated circuit design.
[0004] In summary, the problems existing in the prior art need to be solved urgently. Summary of the invention
[0005] The present invention provides a method, device, equipment and storage medium for extracting parameterized capacitance, so as to solve the defects in the prior art and extract the parasitic capacitance parameters more accurately.
[0006] The present invention provides a method for extracting parameterized capacitance, comprising:
[0007] parameterizing layout data including a two-dimensional capacitor structure;
[0008] Input the parameterized layout data into the capacitance extraction model to obtain the predicted parasitic capacitance parameters;
[0009] Saving the predicted parasitic capacitance parameters in a parasitic capacitance library;
[0010] The capacitance extraction model is trained by the following steps:
[0011] Build deep symbolic learning models;
[0012] Acquire training sample data, wherein the training sample data includes electromagnetic parameters and operation formulas corresponding to the electromagnetic parameters;
[0013] The electromagnetic parameters and the operation formulas corresponding to the electromagnetic parameters are input into the deep symbolic learning model for training, wherein the electromagnetic parameters are used as input and the operation formulas corresponding to the electromagnetic parameters are used as output.
[0014] According to a method for extracting a parameterized capacitor provided by the present invention, the step of parameterizing layout data containing a two-dimensional capacitor structure specifically includes:
[0015] Extracting parameters of the two-bit capacitor structure;
[0016] The layout data is converted into vector data using the parameters as vector elements.
[0017] According to a parameterized capacitor extraction method provided by the present invention, the predicted parasitic capacitor parameters include a predicted capacitor expression and a predicted parasitic capacitor value, and the step of inputting the parameterized layout data into a capacitor extraction model to obtain the predicted parasitic capacitor parameters specifically includes:
[0018] The parameterized layout data is input into the capacitance extraction model to obtain a predicted capacitance expression;
[0019] The parasitic capacitance value is determined according to the predicted capacitance expression.
[0020] According to a method for extracting parameterized capacitance provided by the present invention, the deep symbolic learning model adopts a Transformer architecture, maps input mathematical parameters to corresponding mathematical expressions through end-to-end training, and uses gradient descent and back propagation algorithms to optimize model parameters to minimize the difference between predicted output and true output.
[0021] According to a method for extracting parameterized capacitance provided by the present invention, the step of inputting the electromagnetic parameters and the operation formulas corresponding to the electromagnetic parameters into the deep symbolic learning model for training specifically includes:
[0022] Defining a loss function of the deep symbolic learning model, wherein the loss function is used to measure the difference between the predicted output and the true output;
[0023] The electromagnetic parameters and the operation formulas corresponding to the electromagnetic parameters are input into the deep symbolic learning model for training to minimize the loss function.
[0024] According to a method for extracting parameterized capacitance provided by the present invention, the step of obtaining training sample data specifically includes:
[0025] Get layout training data;
[0026] A data enhancement operation is performed on the layout training data, wherein the data enhancement operation includes geometric transformation, noise addition and color disturbance.
[0027] According to a method for extracting parameterized capacitance provided by the present invention, after the step of saving the predicted parasitic capacitance parameters in a parasitic capacitance library, the method further includes:
[0028] Acquiring a target parasitic capacitance parameter in the parasitic capacitance library;
[0029] Based on the target parasitic capacitance parameters, circuit simulation is performed.
[0030] The present invention also provides a device for extracting parameterized capacitance, comprising:
[0031] A layout parameterization module, used for parameterizing layout data including a two-dimensional capacitor structure;
[0032] A parameter prediction module is used to input the parameterized layout data into the capacitance extraction model to obtain the predicted parasitic capacitance parameters;
[0033] A parameter saving module, used for saving the predicted parasitic capacitance parameters into a parasitic capacitance library;
[0034] The capacitance extraction model is trained by the following steps:
[0035] Build deep symbolic learning models;
[0036] Acquire training sample data, wherein the training sample data includes electromagnetic parameters and operation formulas corresponding to the electromagnetic parameters;
[0037] The electromagnetic parameters and the operation formulas corresponding to the electromagnetic parameters are input into the deep symbolic learning model for training, wherein the electromagnetic parameters are used as input and the operation formulas corresponding to the electromagnetic parameters are used as output.
[0038] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, a method for extracting parameterized capacitance as described above is implemented.
[0039] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the method for extracting a parameterized capacitor as described in any one of the above is implemented.
[0040] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the method for extracting parameterized capacitance as described above is implemented.
[0041] The present invention provides a method, device, equipment and storage medium for extracting parameterized capacitance, which parameterizes the layout data containing a two-dimensional capacitance structure; inputs the parameterized layout data into a capacitance extraction model to obtain predicted parasitic capacitance parameters; and saves the predicted parasitic capacitance parameters into a parasitic capacitance library. The present invention can accurately capture the changing law of parasitic capacitance in the circuit through a deep symbolic learning model. Compared with the traditional physical modeling method, it can more accurately extract parasitic capacitance parameters and reduce the approximate error in the traditional method. The use of a deep learning model for capacitance extraction can avoid the cumbersome physical model calculation process and significantly improve the computational efficiency of parasitic capacitance extraction. In particular, for complex integrated circuit designs, the capacitance extraction task can be completed in a relatively short time. BRIEF DESCRIPTION OF THE DRAWINGS
[0042] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0043] Figure 1 It is a schematic diagram of the process of extracting the parameterized capacitance provided by the present invention;
[0044] Figure 2 It is a structural schematic diagram of a device for extracting parameterized capacitance provided by the present invention;
[0045] Figure 3 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION
[0046] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0047] In order to solve the problems in the prior art, the present invention proposes a method for extracting parameterized capacitance to more accurately extract parasitic capacitance parameters. The following describes the method for extracting parameterized capacitance. Figure 1 As shown, including but not limited to the following steps:
[0048] Step 110: parameterize the layout data including the two-dimensional capacitor structure.
[0049] In step 110, first, layout data containing a two-dimensional capacitor structure is obtained. The data generally comes from an integrated circuit design tool or an electronic design automation (EDA) system. The two-dimensional capacitor structure generally includes electrodes, metal layers, dielectric materials, and the geometric relationship between them. The layout data includes all geometric information related to the capacitor, such as the shape, area, spacing, etc. of the electrode.
[0050] For the parameterization step of the layout data, it is first necessary to extract the layout data to obtain the relevant geometric features of the capacitor structure. These features include but are not limited to: the layout of the metal layer, the spacing of the wires, the size and shape of the electrodes, etc. Then, these feature data are converted into a form suitable for input into the machine learning model. For example, a vectorization method is used to convert the geometric data of the two-dimensional capacitor structure into vector data. Through this parameterization process, the capacitor structure can be represented as a standardized mathematical model, which is convenient for subsequent analysis and calculation.
[0051] Step 120: Input the parameterized layout data into a capacitance extraction model to obtain predicted parasitic capacitance parameters.
[0052] In step 120, the parameterized layout data obtained in step 110 is input into a capacitance extraction model to obtain predicted parasitic capacitance parameters. The capacitance extraction model is trained by a deep learning method and can predict corresponding parasitic capacitance parameters according to the input layout data.
[0053] During the training process of the capacitance extraction model, a large-scale training data set is used. The sample data in the data set contains different electromagnetic parameters, such as capacitance, current density of wires, electric field distribution, etc., as well as corresponding electromagnetic operation formulas. Through this model, the system can extract capacitance-related features from the input layout data and predict the parasitic value of the capacitor based on these features, including capacitance expressions and values.
[0054] In this embodiment, the capacitance extraction model uses deep symbolic learning technology, which is particularly suitable for processing symbolic mathematical expressions. This model can learn the calculation rules and characteristics of capacitance through an end-to-end training process and perform accurate parasitic capacitance prediction.
[0055] Step 130: Save the predicted parasitic capacitance parameters in a parasitic capacitance library.
[0056] After the capacitance extraction model completes the prediction of parasitic capacitance parameters, the prediction results are saved in the form of capacitance expressions and their corresponding capacitance values in the parasitic capacitance library. The library can be a database or other storage medium for storing and managing all predicted parasitic capacitance data. These parasitic capacitance parameters can be used for subsequent circuit simulation, optimization, and verification.
[0057] Specifically, the predicted parasitic capacitance parameters may include the capacitance expression of each capacitance unit and the corresponding capacitance value, and may be classified and saved according to different circuit layout features. Storing these data in the parasitic capacitance library can facilitate quick query and use in subsequent circuit design and simulation.
[0058] The capacitance extraction model is trained by the following steps:
[0059] Build deep symbolic learning models;
[0060] Acquire training sample data, wherein the training sample data includes electromagnetic parameters and operation formulas corresponding to the electromagnetic parameters;
[0061] The electromagnetic parameters and the operation formulas corresponding to the electromagnetic parameters are input into the deep symbolic learning model for training, wherein the electromagnetic parameters are used as input and the operation formulas corresponding to the electromagnetic parameters are used as output.
[0062] The training process of the capacitance extraction model includes the following steps:
[0063] By constructing a deep symbolic learning model, the capacitance extraction method of the present invention can realize symbolic mapping between input and output. The model uses the Transformer architecture, which is an efficient deep learning model that can process sequence data and perform information processing and transmission in a multi-layer network structure. The architecture is suitable for modeling the complex relationship between electromagnetic parameters and capacitance calculation.
[0064] The training sample data includes electromagnetic parameters and operation formulas corresponding to the electromagnetic parameters. In the present invention, the electromagnetic parameters generally include capacitance, wire current density, electric field strength, dielectric constant, etc. Each electromagnetic parameter has a corresponding operation formula, which is generally based on electromagnetic principles, such as Coulomb's law, electrostatic field equations, etc.
[0065] The training process includes taking the above electromagnetic parameters as input and the operation formula as output, and optimizing the weight parameters of the model through the gradient descent method and the back propagation algorithm. Through a large number of training samples, the model gradually learns the mapping relationship between the input electromagnetic parameters and the operation formula. The training process uses a loss function to measure the difference between the model's predicted results and the actual results, and ultimately minimizes the prediction error.
[0066] During the training process, gradient descent and back propagation algorithms are used to optimize the parameters of the model. The goal of the optimization is to minimize the difference between the predicted output and the actual output, so that the model can accurately predict the parasitic capacitance parameters when facing an unknown capacitor structure.
[0067] As a further optional embodiment, the step of parameterizing the layout data including the two-dimensional capacitor structure specifically includes:
[0068] Extracting parameters of the two-bit capacitor structure;
[0069] The layout data is converted into vector data using the parameters as vector elements.
[0070] In this embodiment, the layout data containing the two-dimensional capacitor structure needs to be processed and analyzed first. The data contains the geometric information of the two-dimensional capacitor, such as the shape, size, spacing of the electrodes, and other structural data related to the capacitor characteristics. Specifically, the following parameters can be extracted from the layout data:
[0071] The size and shape of the electrode: such as the length, width, thickness of the electrode, and the shape of the electrode (e.g. rectangular, circular, ring-shaped, etc.).
[0072] The distance between electrodes: that is, the distance between the electrodes of the capacitor, which is a key factor affecting the capacitance value.
[0073] Properties of dielectrics: The dielectric constant of a dielectric is an important parameter that affects the size of capacitance.
[0074] Layout of metal layers and wires: The relative positions of metal layers and wires in the capacitor structure.
[0075] These parameters can accurately describe the geometric characteristics of the two-dimensional capacitor structure and provide basic data for subsequent model training and capacitance value prediction.
[0076] The purpose of converting the extracted two-dimensional capacitor structure parameters into vector data is to convert the complex layout data into a format suitable for input into the machine learning model. In this process, the above-extracted capacitor structure parameters (such as electrode size, electrode spacing, dielectric properties, etc.) are first used as the elements of the vector. For example:
[0077] Electrode dimensions can be represented by a set of values in a vector, such as [electrode length, electrode width, electrode height].
[0078] The spacing between electrodes can be represented as another element in the vector.
[0079] The dielectric constant of a dielectric can also be given as an element of a vector.
[0080] These parameters are combined into a vector form to form a high-dimensional vector, which represents a specific capacitor structure. After the layout data of the entire two-dimensional capacitor structure is converted into vector data, it can be input into the subsequent capacitor extraction model for training and prediction.
[0081] This parameterization method enables complex two-dimensional capacitor structures to be simplified into standardized numerical data, which is convenient for machine learning models to process. Compared with traditional solutions based on image processing or manual calculations, the use of vectorized representation can improve data processing efficiency while reducing computational complexity.
[0082] As a further optional embodiment, the predicted parasitic capacitance parameters include a predicted capacitance expression and a predicted parasitic capacitance value, and the step of inputting the parameterized layout data into the capacitance extraction model to obtain the predicted parasitic capacitance parameters specifically includes:
[0083] The parameterized layout data is input into the capacitance extraction model to obtain a predicted capacitance expression;
[0084] The parasitic capacitance value is determined according to the predicted capacitance expression.
[0085] In this step, the layout data that has been converted into vector data through the parameterization step is input into the trained capacitance extraction model. The capacitance extraction model automatically extracts the corresponding capacitance expression from the input parameterized data through a deep learning algorithm (such as a neural network, a deep symbolic learning model, etc.).
[0086] Capacitance expression: Capacitance expression is a mathematical formula or expression used to describe the size of capacitance, usually including variables related to capacitor structure parameters (such as electrode size, spacing, dielectric properties, etc.). By training the input data, the model can generate a capacitance expression suitable for the current structure. The expression can be a polynomial, formula, or a mathematical equation derived from electromagnetic principles.
[0087] Model training: This step relies on a trained capacitance extraction model, which is trained with a large amount of training sample data (including electromagnetic parameters and corresponding capacitance values) so that the model can understand the mathematical relationship between the capacitance structure and its capacitance value. When new parameterized layout data is input, the model can quickly generate a suitable capacitance expression.
[0088] After the capacitance expression is extracted, the next step is to calculate the actual parasitic capacitance value based on the capacitance expression. This process uses the parameters and formulas in the capacitance expression to obtain a numerical result, which is the predicted parasitic capacitance value.
[0089] Calculate the parasitic capacitance value: Based on the parameters in the capacitance expression (such as electrode spacing, electrode area, dielectric constant, etc.), the parasitic capacitance value is calculated numerically. The parasitic capacitance value is an undesirable but unavoidable capacitance component in the circuit, which usually affects the circuit performance. This value is usually expressed in picofarads (pF) or farads (F).
[0090] Model validation: During the training process, the model is validated using real capacitance values to ensure that the predicted parasitic capacitance values are as close as possible to the actual measured values. The model parameters are adjusted through optimization algorithms (such as gradient descent) to reduce the gap between the predicted values and the actual values.
[0091] By automatically generating capacitance expressions from parameterized layout data, the model can accurately calculate parasitic capacitance values based on capacitance expressions, thereby improving the accuracy of parasitic capacitance prediction. Compared with traditional manual calculation methods, the automatically generated capacitance expressions can better capture the nonlinear relationship between complex capacitance structures and improve the accuracy of prediction.
[0092] As a further optional embodiment, the deep symbolic learning model adopts a Transformer architecture, maps input mathematical parameters to corresponding mathematical expressions through end-to-end training, and uses gradient descent and back-propagation algorithms to optimize model parameters to minimize the difference between predicted output and true output.
[0093] In this embodiment, the capacitance extraction model is trained by a deep symbolic learning model, and the deep symbolic learning model adopts the Transformer architecture. Transformer is a deep learning model based on the self-attention mechanism, which can show good performance when processing complex input data, and is particularly suitable for processing sequence data and complex mathematical formula generation tasks.
[0094] Specifically, this embodiment is implemented by the following steps:
[0095] The Transformer architecture is particularly good at processing long sequence dependencies and does not need to rely on the order of time series like traditional RNN or LSTM models, so it is very suitable for generating mathematical formulas with complex structures such as capacitance expressions. The Transformer architecture captures the global information of the input data through a multi-layer self-attention mechanism and a feedforward neural network, effectively processing the nonlinear relationship between electromagnetic parameters and capacitance expressions.
[0096] Self-attention mechanism: Transformer uses the self-attention mechanism to weight each element in the input sequence so that when generating the capacitance expression, the model can assign different weights according to the importance of different input features. This enables the model to better understand the impact of the input parameters and generate more accurate capacitance expressions.
[0097] Multi-head attention: Transformer also uses a multi-head attention mechanism to calculate the associations of different positions in parallel, thereby accelerating model training and improving expressiveness.
[0098] The end-to-end training process is as follows: The Transformer model is optimized through end-to-end training, which means that the entire capacitance extraction process from input data to output capacitance expression is completed directly through the same neural network, without the need to manually build intermediate processes. This method greatly improves the training efficiency of the model and reduces the complexity of the manual design steps in traditional methods.
[0099] Input data: Input data includes electromagnetic parameters (such as electrode size, dielectric constant, voltage, etc.) and the calculation formula between these parameters and capacitance value.
[0100] Output data: The output data is the corresponding capacitance expression, which can be a mathematical formula or algorithmic representation, describing the relationship between the capacitance size and the input parameters.
[0101] End-to-end training: The entire network optimizes the error between input and output data, allowing the model to automatically learn how to generate an accurate capacitance expression based on the input parameters during training.
[0102] In order to minimize the difference between the predicted output and the actual output, the Transformer model uses gradient descent and backpropagation algorithms to update the model parameters.
[0103] Gradient descent: Through the gradient descent algorithm, the model continuously adjusts its internal parameters (such as weights and biases) to minimize the loss function between the predicted capacitance expression and the actual capacitance expression. Gradient descent calculates the gradient of the loss function and adjusts the parameters along the gradient direction so that the model gradually converges to the optimal solution.
[0104] Back propagation: The back propagation algorithm adjusts the parameters of each layer based on the feedback of the error and gradually optimizes the capacitance extraction model. Through back propagation, the model can identify which parameters have a greater impact on the final result, so as to make targeted adjustments.
[0105] The loss function is used to measure the difference between the model prediction value and the actual value. In this embodiment, the loss function can be designed as a mean square error (MSE) or a cross entropy loss function, which is selected according to the specific requirements of the task. The optimization goal of the loss function is to minimize the error between the output capacitance expression and the true capacitance expression, thereby improving the prediction accuracy of the model.
[0106] Mean Square Error (MSE): For continuous capacitance prediction tasks, mean square error can effectively measure the difference between the predicted value and the true value. MSE is suitable for regression problems. By minimizing MSE, the model can improve the accuracy of prediction.
[0107] Cross-entropy loss function: If the output of predicting the capacitance expression is in categorical form (e.g., multiple possible expression types), a cross-entropy loss function can be used to measure the difference between the output and the true label.
[0108] Next, perform model optimization:
[0109] Optimization algorithm: Use optimization algorithms (such as Adam, RMSprop, etc.) to further improve the training efficiency of the model. The optimization algorithm can adaptively adjust the learning rate, making the training process more stable and converging to the optimal solution with fewer iterations.
[0110] Regularization technology: In order to avoid overfitting of the model, regularization techniques such as Dropout and L2 regularization are used to further improve the generalization ability of the model.
[0111] As a further optional embodiment, the step of inputting the electromagnetic parameters and the operation formulas corresponding to the electromagnetic parameters into the deep symbolic learning model for training specifically includes:
[0112] Defining a loss function of the deep symbolic learning model, wherein the loss function is used to measure the difference between the predicted output and the true output;
[0113] The electromagnetic parameters and the operation formulas corresponding to the electromagnetic parameters are input into the deep symbolic learning model for training to minimize the loss function.
[0114] In this embodiment, a loss function is first defined, which is used to measure the difference between the predicted output of the model and the actual output. The loss function is a key part of the training process for evaluating the prediction performance of the model. The goal is to make the prediction results of the model as close to the actual value as possible by minimizing the loss function. Specifically, the loss function is defined as:
[0115]
[0116] Where θ represents the network parameters, m is the dimension of the input parameters, and Y is the space of all possible mathematical expressions. Input mathematical parameters x i ∈R m , the model's predicted output is The actual mathematical expression y i ∈Y is the true output. Define the loss function Used to measure the predicted output and the true output y i The goal of training is to find the optimal parameter θ * , so that the loss function is minimized.
[0117] By defining an appropriate loss function and training the deep symbolic learning model through optimization algorithms such as back propagation and gradient descent, the mapping of electromagnetic parameters to capacitance expressions can be effectively achieved. This process not only ensures that the model can accurately predict the capacitance expression, but also improves the generalization ability of the model, enabling it to adapt to different capacitor structures and circuit design tasks.
[0118] As a further optional embodiment, the step of obtaining training sample data specifically includes:
[0119] Get layout training data;
[0120] A data enhancement operation is performed on the layout training data, wherein the data enhancement operation includes geometric transformation, noise addition and color disturbance.
[0121] As a further optional embodiment, after the step of saving the predicted parasitic capacitance parameter in a parasitic capacitance library, the method further includes:
[0122] Acquiring a target parasitic capacitance parameter in the parasitic capacitance library;
[0123] Based on the target parasitic capacitance parameters, circuit simulation is performed.
[0124] In this embodiment, it is first necessary to obtain layout training data containing a two-dimensional capacitor structure. The layout data is usually generated by an electronic design automation (EDA) tool and contains geometric information, layout information, and electrical properties related to the capacitor structure. Specifically, the layout data may include the area, shape, size, spacing, and hierarchy of the capacitor. In order to effectively train the capacitor extraction model, the training data needs to be representative and should include various types of capacitor structures and their corresponding electromagnetic parameters.
[0125] Ways to obtain layout training data may include:
[0126] Export the layout data of the capacitor from the circuit design tool.
[0127] Extract different types of capacitor layouts from existing electronic design libraries.
[0128] Virtual layout data generated by manual design or simulation.
[0129] Data augmentation is an effective way to improve the robustness, stability and generalization ability of the model, especially when the training data is limited. By augmenting the layout training data, the diversity of training samples can be increased, thereby improving the performance of the model in different situations and avoiding overfitting.
[0130] The following is a description of the device for extracting parameterized capacitance provided by the present invention. Figure 2 As shown, the device for extracting parameterized capacitance described below and the method for extracting parameterized capacitance described above can refer to each other.
[0131] A device for extracting parameterized capacitance, comprising:
[0132] A layout parameterization module 210, for parameterizing layout data including a two-dimensional capacitor structure;
[0133] The parameter prediction module 220 is used to input the parameterized layout data into the capacitance extraction model to obtain the predicted parasitic capacitance parameters;
[0134] A parameter saving module 230, used for saving the predicted parasitic capacitance parameters into a parasitic capacitance library;
[0135] The capacitance extraction model is trained by the following steps:
[0136] Build deep symbolic learning models;
[0137] Acquire training sample data, wherein the training sample data includes electromagnetic parameters and operation formulas corresponding to the electromagnetic parameters;
[0138] The electromagnetic parameters and the operation formulas corresponding to the electromagnetic parameters are input into the deep symbolic learning model for training, wherein the electromagnetic parameters are used as input and the operation formulas corresponding to the electromagnetic parameters are used as output.
[0139] Figure 3 An example of a physical structure diagram of an electronic device is shown in FIG. Figure 3 As shown, the electronic device may include: a processor 310, a communication interface 320, a memory 330 and a communication bus 340, wherein the processor 310, the communication interface 320 and the memory 330 communicate with each other through the communication bus 340. The processor 310 may call the logic instructions in the memory 330 to execute the parameterized capacitance extraction method, which includes:
[0140] parameterizing layout data including a two-dimensional capacitor structure;
[0141] Input the parameterized layout data into the capacitance extraction model to obtain the predicted parasitic capacitance parameters;
[0142] Saving the predicted parasitic capacitance parameters in a parasitic capacitance library;
[0143] The capacitance extraction model is trained by the following steps:
[0144] Build deep symbolic learning models;
[0145] Acquire training sample data, wherein the training sample data includes electromagnetic parameters and operation formulas corresponding to the electromagnetic parameters;
[0146] The electromagnetic parameters and the operation formulas corresponding to the electromagnetic parameters are input into the deep symbolic learning model for training, wherein the electromagnetic parameters are used as input and the operation formulas corresponding to the electromagnetic parameters are used as output.
[0147] In addition, the logic instructions in the above-mentioned memory 330 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.
[0148] On the other hand, the present invention further provides a computer program product, the computer program product comprising a computer program, the computer program can be stored on a non-transitory computer-readable storage medium, when the computer program is executed by a processor, the computer can execute the parameterized capacitance extraction method provided by the above methods, the method comprising:
[0149] parameterizing layout data including a two-dimensional capacitor structure;
[0150] Input the parameterized layout data into the capacitance extraction model to obtain the predicted parasitic capacitance parameters;
[0151] Saving the predicted parasitic capacitance parameters in a parasitic capacitance library;
[0152] The capacitance extraction model is trained by the following steps:
[0153] Build deep symbolic learning models;
[0154] Acquire training sample data, wherein the training sample data includes electromagnetic parameters and operation formulas corresponding to the electromagnetic parameters;
[0155] The electromagnetic parameters and the operation formulas corresponding to the electromagnetic parameters are input into the deep symbolic learning model for training, wherein the electromagnetic parameters are used as input and the operation formulas corresponding to the electromagnetic parameters are used as output.
[0156] In another aspect, the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon, which is implemented when the computer program is executed by a processor to perform the parameterized capacitance extraction method provided by the above methods, the method comprising:
[0157] parameterizing layout data including a two-dimensional capacitor structure;
[0158] Input the parameterized layout data into the capacitance extraction model to obtain the predicted parasitic capacitance parameters;
[0159] Saving the predicted parasitic capacitance parameters in a parasitic capacitance library;
[0160] The capacitance extraction model is trained by the following steps:
[0161] Build deep symbolic learning models;
[0162] Acquire training sample data, wherein the training sample data includes electromagnetic parameters and operation formulas corresponding to the electromagnetic parameters;
[0163] The electromagnetic parameters and the operation formulas corresponding to the electromagnetic parameters are input into the deep symbolic learning model for training, wherein the electromagnetic parameters are used as input and the operation formulas corresponding to the electromagnetic parameters are used as output.
[0164] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.
[0165] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.
[0166] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for extracting parameterized capacitance, characterized in that: include: parameterizing layout data including a two-dimensional capacitor structure; Input the parameterized layout data into the capacitance extraction model to obtain the predicted parasitic capacitance parameters; Saving the predicted parasitic capacitance parameters in a parasitic capacitance library; The capacitance extraction model is trained by the following steps: Build deep symbolic learning models; Acquire training sample data, wherein the training sample data includes electromagnetic parameters and operation formulas corresponding to the electromagnetic parameters; The electromagnetic parameters and the operation formulas corresponding to the electromagnetic parameters are input into the deep symbolic learning model for training, wherein the electromagnetic parameters are used as input and the operation formulas corresponding to the electromagnetic parameters are used as output.
2. The method for extracting parameterized capacitance according to claim 1, characterized in that: The step of parameterizing the layout data including the two-dimensional capacitor structure specifically includes: Extracting parameters of the two-bit capacitor structure; The layout data is converted into vector data using the parameters as vector elements.
3. The method for extracting parameterized capacitance according to claim 1, characterized in that: The predicted parasitic capacitance parameters include predicted capacitance expressions and predicted parasitic capacitance values. The step of inputting the parameterized layout data into the capacitance extraction model to obtain the predicted parasitic capacitance parameters specifically includes: The parameterized layout data is input into the capacitance extraction model to obtain a predicted capacitance expression; The parasitic capacitance value is determined according to the predicted capacitance expression.
4. The method for extracting parameterized capacitance according to claim 1, characterized in that: The deep symbolic learning model adopts the Transformer architecture to map the input mathematical parameters to the corresponding mathematical expressions through end-to-end training, and uses gradient descent and back-propagation algorithms to optimize the model parameters to minimize the difference between the predicted output and the true output.
5. The method for extracting parameterized capacitance according to claim 1, characterized in that: The step of inputting the electromagnetic parameters and the operation formulas corresponding to the electromagnetic parameters into the deep symbolic learning model for training specifically includes: Defining a loss function of the deep symbolic learning model, wherein the loss function is used to measure the difference between the predicted output and the true output; The electromagnetic parameters and the operation formulas corresponding to the electromagnetic parameters are input into the deep symbolic learning model for training to minimize the loss function.
6. The method for extracting parameterized capacitance according to claim 1, characterized in that: The step of obtaining training sample data specifically includes: Get layout training data; A data enhancement operation is performed on the layout training data, wherein the data enhancement operation includes geometric transformation, noise addition and color disturbance.
7. The method for extracting parameterized capacitance according to claim 1, characterized in that: After the step of saving the predicted parasitic capacitance parameter in a parasitic capacitance library, the method further includes: Acquiring a target parasitic capacitance parameter in the parasitic capacitance library; Based on the target parasitic capacitance parameters, circuit simulation is performed.
8. A device for extracting parameterized capacitance, characterized in that: include: A layout parameterization module, used for parameterizing layout data including a two-dimensional capacitor structure; A parameter prediction module is used to input the parameterized layout data into the capacitance extraction model to obtain the predicted parasitic capacitance parameters; A parameter saving module, used for saving the predicted parasitic capacitance parameters into a parasitic capacitance library; The capacitance extraction model is trained by the following steps: Build deep symbolic learning models; Acquire training sample data, wherein the training sample data includes electromagnetic parameters and operation formulas corresponding to the electromagnetic parameters; The electromagnetic parameters and the operation formulas corresponding to the electromagnetic parameters are input into the deep symbolic learning model for training, wherein the electromagnetic parameters are used as input and the operation formulas corresponding to the electromagnetic parameters are used as output.
9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the method for extracting parameterized capacitance according to any one of claims 1 to 7 is implemented.
10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method for extracting parameterized capacitance according to any one of claims 1 to 7 is implemented.