Monopulse neuron circuit and operation method thereof

Abstract

The invention discloses a monopulse neuron circuit and an operation method thereof, and belongs to the technical field of artificial neural networks. According to the monopulse neuron circuit, a single volatile threshold resistance change memristor is used for simulating neurodynamic behaviors, and a compact input truncation feedback circuit with an extremely small number of devices is combined to achieve monopulse issuing and encoding functions. The monopulse neuron circuit can be used for an edge end brain-like computing system, can simulate the pulse distribution function of neurons, cuts off a transmission tube at the input end of the neurons after detecting self pulse distribution, realizes a neural coding mode based on a single pulse, and improves the neural coding efficiency. The method and the device are used for solving the defects of traditional frequency coding in multiple aspects and the problem that a reported monopulse neuron circuit is too high in overhead, are beneficial to larger-scale integration in application scenes with relatively high requirements on energy efficiency and calculation speed, such as an edge-end brain-like calculation system, and have a great development prospect.

Description

Technical Field

[0001] The present invention belongs to the technical field of artificial neural networks, and relates to a single-pulse artificial neuron circuit, and specifically to a single-pulse artificial neuron circuit based on a volatile threshold resistive memristor for input coding and neural processing in edge brain computing. Background Art

[0002] With the booming development of machine learning and artificial intelligence, intelligent systems are increasingly being used in edge applications. These applications include autonomous driving, virtual reality and augmented reality, intelligent prosthetics, disease detection, human-machine collaboration, and more. The information processing in such edge computing systems should complete calculations at a high response rate under limited energy conditions. The storage unit and computing unit of the traditional von Neumann computing architecture are separated from each other and are no longer suitable for such edge intelligent systems for data-intensive computing. The brain-inspired brain-like computing architecture uses pulse sequences rich in timing information to complete computing tasks with event-driven and highly parallel computing modes at a lower power consumption, so it is suitable for the new generation of edge computing systems.

[0003] Current brain-like computing systems generally use pulse frequency as the neural coding mode. However, in this coding mode, neurons need to emit a large number of pulses to count the frequency, which is still insufficient in terms of energy consumption and computing speed. The biological nervous system has a rich variety of coding modes. Among them, the first pulse coding that exists simultaneously in the sensory end coding and the brain's sensory cortex is the fastest neural coding. This coding mode can be further optimized to a single-pulse neural coding that only needs to emit one pulse to achieve higher energy efficiency. Among the single-pulse coding circuits that have been reported, most of them are implemented in pure CMOS circuits. In order to simulate neural dynamics behavior, a large number of transistors need to be introduced, which has a large area overhead. At present, single-pulse neurons based on new neuromorphic devices still need to rely on complex and large feedback circuits, and the integration density also needs to be improved. So far, it has not been reported to combine a single device with neural dynamics with a simple feedback circuit to construct an efficient single-pulse neuron. Summary of the invention

[0004] In order to overcome the problem of high cost of single-pulse neurons mentioned above, the present invention provides a single-pulse neuron circuit based on a volatile threshold resistive memristor for input coding and neural processing in a marginal brain-like computing system. The single-pulse neuron circuit can cut off its own input port through the pulse emission of the neuron, cut off the input after issuing a pulse, and encode the information into the emission time of the pulse, thereby improving the speed and energy efficiency of neural coding.

[0005] The technical solution provided by the present invention is as follows:

[0006] A single-pulse neuron circuit, characterized in that it includes a leakage integrator circuit based on a volatile threshold resistive memristor, the leakage integrator circuit accumulates input stimuli and emits a voltage pulse when the emission threshold is reached, the voltage pulse is transmitted to an input cutoff feedback circuit, the input cutoff feedback circuit controls the voltage to remain in a low voltage state, cuts off the input path of the leakage integrator circuit, and generates a single pulse emission behavior.

[0007] Furthermore, the leakage integration circuit is composed of a volatile threshold resistance memristor connected in series with a pulse readout resistor R1, and then connected in parallel with a capacitor C1 simulating the neuron membrane capacitance, and the node connecting the memristor and C1 is the membrane potential V mem The node connected to R1 is the output pulse Spike node, and the leakage integration circuit receives the input signal through the NMOS transfer transistor M1.

[0008] Furthermore, the input cutoff feedback circuit is connected in series with a capacitor C2 and a pull-down NMOS transistor M2, and the capacitor C2 is also connected in parallel with a PMOS transistor M3 for controlling reset, and the node connected by the capacitor C2, the transistor M2 and the transistor M3 is the control node V ctrl , V ctrl The node is connected to the gate of M1 in the leakage integrator circuit and is used to control the gate electrode of transistor M1.

[0009] Furthermore, the drain of the transistor M1 is the neuron input terminal, and the input signal received is a current signal input I in , or a voltage signal input V with a series input resistor R2 in .

[0010] Furthermore, the memristor may be a Mott memristor based on Mott phase transition, a diffusive memristor based on metal conductive filaments, or an OTS memristor based on chalcogenide.

[0011] The present invention further provides an operating method of a single pulse neuron circuit, characterized in that:

[0012] 1) Initial moment, V ctrl is high level, transistor M1 is turned on;

[0013] 2) Apply input signal, charge accumulates on capacitor C1, V mem At the same time, the charge on capacitor C1 leaks to ground through the memristor and R1. mem The voltage drop of the memristor reaches the threshold voltage V th , the memristor changes to a low resistance state, capacitor C1 discharges rapidly, and a voltage pulse is generated on the Spike node. mem The voltage drop of the memristor is reduced to the holding voltage V hold, the memristor changes to a high-resistance state, and the pulse emission ends;

[0014] 3) The pulse is transmitted to transistor M2 and turns it on, charging capacitor C2, so that V ctrl Pull down to a low level, at this time, transistor M1 is turned off, disconnecting V mem The connection with the input signal makes the capacitor C1 unable to receive the input signal for accumulation, and the circuit can no longer emit pulses, thereby achieving single pulse emission.

[0015] Furthermore, the gate electrode of the transistor M3 receives a reset CLR signal, and a reset signal CLR is applied to the transistor M3 to discharge the capacitor C2, V ctrl Return to high level and repeat steps 1)-3) to receive the next input.

[0016] The beneficial effects of the present invention are as follows:

[0017] The present invention provides a single pulse neuron circuit based on a volatile threshold resistive memristor and an operation method thereof, which utilizes the dynamic behavior of the volatile threshold resistive memristor to simulate the basic leakage, accumulation and emission functions of biological neurons, and transmits the emitted pulse to an input cutoff feedback circuit, disconnects the input of the neuron through a pull-down control signal, and the neuron can no longer continuously emit pulses, thus generating a single pulse emission behavior. Compared with the existing single pulse neuron implementation scheme, the single pulse neuron circuit based on a volatile threshold resistive memristor of the present invention greatly reduces the hardware overhead, and is conducive to larger-scale integration in application scenarios with greater requirements for energy efficiency and computing speed, such as edge-end brain-like computing systems, and has great development prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 The single pulse neuron circuit diagram of the present invention for input coding and neural processing in edge brain computing based on volatile threshold resistive memristor, wherein R, C and M represent resistance, capacitance and transistor respectively, I in is the input current, V in is the input voltage, V dd is the supply voltage, V mem is the membrane potential, Spike is the output pulse voltage, V ctrl To cut off the control signal, CLR is a low-level active reset input signal.

[0019] Figure 2 This is a timing diagram of a single pulse neuron based on a volatile threshold resistive memristor of the present invention when it is working.

[0020] Figure 3The effect of circuit parameter values ​​on the single pulse emission time of a single pulse neuron based on VO2 volatile threshold resistive Mott memristor under constant electrical input in the present invention, wherein a) to d) are the single pulse emission time with the input current I in 、Input voltage V in , changes in input resistance R2 and membrane capacitance C1.

[0021] Figure 4 The effect of pulse parameters on the number of accumulated input pulses required for single pulse emission of a single pulse neuron based on VO2 volatile threshold resistive Mott memristor under electric pulse input is shown in the present invention. Here, current pulse input is taken as an example, where a) and b) are the required accumulated input pulse number versus input pulse amplitude I respectively. in and input pulse time interval t off changes.

[0022] Figure 5 The single pulse response of the single pulse neuron based on the VO2 volatile threshold resistive Mott memristor of the present invention under different input electric pulse sequences, where current pulse input is taken as an example, where a) to d) are the response results of whether a single pulse is emitted or not when the input electric pulse amplitude gradually increases, the amplitude gradually decreases, the time interval gradually decreases, and the time interval gradually increases, respectively. DETAILED DESCRIPTION

[0023] In order to more clearly illustrate the purpose, technical solutions and advantages of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings. The description here is only used to explain the present invention and is not used to limit the present invention.

[0024] Figure 1 The single pulse neuron circuit diagram based on the volatile threshold resistive memristor of the present invention is shown in FIG. The single pulse neuron consists of two parts. The first part is a leakage integration circuit based on the volatile threshold resistive memristor. Specifically, the leakage integration circuit is composed of a volatile memristor in series with a readout resistor R1 and a membrane capacitor C1 in parallel. The memristor and R1 form a resistor voltage divider circuit, and the voltage divider node is the voltage pulse output Spike node. The node where the memristor is connected to C1 is the membrane potential V mem Node, which is also connected to the source of NMOS input transistor M1. The drain of M1 is the neuron input terminal, and the input signal that can be received can be a current signal input I in , or it can be a voltage signal input V connected in series with input resistor R2 in The gate of M1 is the feedback control terminal, which can control the conduction state of M1. The second part is the input cutoff feedback circuit. Specifically, the input cutoff feedback circuit consists of a control capacitor C2 at the control node V ctrlThe upper end is connected to the drain of the NMOS pull-down transistor M2, and the other end of C2 is connected to the supply voltage V dd , the source and gate of M2 are connected to the ground and the Spike node of the leakage integrator circuit respectively. The drain, source and gate of the PMOS reset transistor M3 are connected to V ctrl Node, V dd and reset signal CLR. V ctrl The node is also connected to the gate of M1 in the leakage integrator circuit to control the conduction state of M1. The input cutoff feedback circuit detects the pulse output of the Spike node of the leakage integrator circuit. When the leakage integrator circuit issues a pulse, it controls M1 to turn off and disconnect V mem The connection with the input signal makes C1 unable to accumulate input, and the circuit can no longer emit pulses, thereby realizing single pulse emission behavior.

[0025] Figure 2 : is a timing diagram of the single pulse neuron operation method based on the volatile threshold resistive memristor of the present invention. Specifically, at the initial moment, V mem is 0, the memristor is in high impedance state, and V ctrl is high level, at this time, the gate-source voltage of M1 is V gs =V ctrl -V mem is greater than its turn-on voltage, M1 is in the on state, and the leakage integrator circuit is ready to accumulate input. in or V in Under this condition, the neuron enters the leakage integration stage, C1 is charged, and C1 is slowly discharged through the leakage path formed by the memristor and R1. Overall, V mem Increase. When V mem Increase until the voltage drop across the memristor is greater than its threshold voltage V th , the memristor changes resistance and enters a low-resistance state, the leakage path resistance decreases, C1 discharges rapidly, and a voltage pulse output is generated on the Spike node. At the same time, V mem Rapidly decreases. When V mem until the voltage drop across the memristor is less than its holding voltage V hold , the memristor returns to the high impedance state, and a pulse is released. In the process of releasing voltage pulses in the leakage integrator circuit, when the Spike node voltage increases until it is greater than the turn-on voltage of M2, M2 is turned on and forms a pull-down path to charge C2, making V ctrl Rapidly drops to a low potential. At this time, M1's V gs is lower than its turn-on voltage, M1 is turned off, disconnecting the input signal from V memThe leakage integrator circuit can no longer accumulate inputs. This means that the neuron can no longer continue to fire pulses after firing the first pulse, exhibiting a single pulse firing behavior and encoding information into the single pulse firing time. After the pulse is fired, the Spike node is low, M2 is turned off, and then V ctrl Always keep it at a low level, M1 always keeps off, and the neuron enters the input cutoff stage. By applying a low potential valid CLR signal to the gate of M3, M3 is turned on and C2 is discharged, V ctrl Increases to a high level, M1 turns on, restoring the input channel of the leaky integrator circuit, and the neuron is ready to receive the next input stimulus.

[0026] The volatile threshold resistive memristor based on the present invention can be a Mott memristor based on Mott phase transition, a diffusive memristor based on metal conductive filaments, and an OTS memristor based on chalcogenide. x The diffusive memristor can be a device based on active metals such as Ag and Cu, and the OTS memristor can be a chalcogenide device based on chalcogen elements such as Se and Te.

[0027] Specifically, taking the VO2 Mott memristor as an example, Figure 3 The effect of circuit parameter values ​​on the single pulse emission time of the single pulse neuron based on the VO2 volatile threshold resistive Mott memristor of the present invention under constant electrical input. It can be seen that if I in or V in The larger the value, the shorter the single pulse emission time. If R2 or C1 is larger, the longer the single pulse emission time. Specifically, the single pulse emission time t under current signal input can be described by formula (1):

[0028]

[0029] R in formula (1) eff,i is the equivalent resistance of the memristor and R1 in series. The single pulse emission time t under voltage signal input can be described by formula (2):

[0030]

[0031] R in formula (2) eff,v is the equivalent resistance of the memristor connected in series with R1 and in parallel with R2, β is V mem The node voltage division coefficient (R VO2 +R1) / (R VO2+R1+R2). Therefore, the single-pulse neuron based on the volatile threshold resistive memristor of the present invention can perform single-pulse encoding on analog signals in the form of voltage value, current value, resistance value or capacitance value, and these analog signals can be provided by sensors with outputs of current value, voltage value, resistance value or capacitance value. Specifically, the sensors with outputs of current value, voltage value, resistance value or capacitance value can replace the I in the circuit respectively. in , V in , R2 or C1, enables the circuit to single pulse encode these types of sensing signals.

[0032] Further, taking the VO2 Mott memristor as an example, Figure 4 This is the effect of pulse parameters on the number of accumulated input pulses required for single pulse emission of a single pulse neuron based on the VO2 volatile threshold resistive Mott memristor of the present invention under electric pulse input. Here, current pulse input is taken as an example. It can be seen that if the input pulse amplitude I in The larger the value, the smaller the number of input pulses required for a single pulse emission. If the input pulse time interval t off The larger the value, the greater the number of accumulated input pulses required for a single pulse emission. Specifically, the number of accumulated input pulses N required for a single pulse emission under current pulse input is spike It can be described by formula (3):

[0033]

[0034] In formula (3), t on is the input pulse width. The number of accumulated input pulses N required for a single pulse to be emitted under voltage pulse input spike It can be described by formula (4):

[0035]

[0036] Further, taking the VO2 Mott memristor as an example, Figure 5 The single pulse response of the single pulse neuron based on the VO2 volatile threshold resistive memristor of the present invention under different electrical pulse sequence inputs, where current pulse input is taken as an example. It can be seen that when the input electrical pulse amplitude gradually increases or the input electrical pulse time interval gradually decreases, the neuron can emit a single pulse, and when the input electrical pulse amplitude gradually decreases or the input electrical pulse time interval gradually increases, the neuron does not emit a pulse. Therefore, the single pulse neuron based on the volatile threshold resistive memristor of the present invention can distinguish different input pulse sequences, and can be used as a neuron responsible for information processing in a pulse neural network to construct a single pulse neural network.

[0037] The present invention proposes a new single-pulse neuron circuit that can be used for input coding and neural processing in edge brain-like computing. It uses a volatile threshold resistance variable memristor as the core device of the leakage integration circuit to simulate the neuron firing behavior, and introduces a transistor transmission tube at its input end to control the conduction state of the input path. When the neuron fires a pulse, the pulse is transmitted to the input truncation feedback circuit with simple design and low hardware overhead to control the transmission tube to turn off and disconnect the input path, thereby realizing the single-pulse firing behavior. Based on this, the information can be represented as the time required for the single pulse firing or the number of input electrical pulses. Compared with the reported single-pulse neurons, the present invention greatly reduces the hardware cost, is conducive to integration into large-scale edge computing systems, such as intelligent human-computer interaction systems, and realizes efficient computing in these resource-limited application scenarios, and has great development prospects.

[0038] The above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit the same. A person skilled in the art may modify or make equivalent substitutions for the technical solutions of the present invention without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to the claims.

Claims

1. A single pulse neuron circuit, characterized in that: The invention comprises a leakage integrator circuit based on a volatile threshold resistive memristor, which accumulates input stimulation and emits a voltage pulse when the emission threshold is reached. The voltage pulse is transmitted to an input cutoff feedback circuit, which controls the voltage to be kept in a low voltage state, cuts off the input path of the leakage integrator circuit, and generates a single pulse emission behavior.

2. The single pulse neuron circuit according to claim 1, characterized in that: The leakage integration circuit is composed of a volatile threshold resistance memristor connected in series with a pulse readout resistor R1, and then connected in parallel with a capacitor C1 simulating the neuron membrane capacitance. The node connecting the memristor and C1 is the membrane potential V mem The node connected to R1 is the output pulse Spike node, and the leakage integration circuit receives the input signal through the NMOS transistor M1.

3. The single pulse neuron circuit according to claim 2, characterized in that: The input cutoff feedback circuit is composed of a capacitor C2 connected in series with a pull-down NMOS transistor M2, and the capacitor C2 is also connected in parallel with a PMOS transistor M3 that controls the reset, and the node commonly connected by the capacitor C2, the transistor M2 and the transistor M3 is the control node V ctrl , used to control the gate electrode of transistor M1.

4. The single pulse neuron circuit according to claim 2, characterized in that: The input signal is a current signal input I in , or a voltage signal input V with a series input resistor R2 in .

5. The single pulse neuron circuit according to claim 2, characterized in that: The memristor is a diffusive memristor based on Ag and Cu active metals.

6. The single pulse neuron circuit according to claim 2, characterized in that: The memristor is an OTS device based on Se and Te chalcogenide elements.

7. The single pulse neuron circuit according to claim 2, characterized in that: The memristor is based on VO2, NbO x Memristor based on Mott insulator material.

8. A method for operating a single pulse neuron circuit as claimed in claim 3, characterized in that: 1) Initial moment, V ctrl is high level, transistor M1 is turned on; 2) Apply input signal, charge accumulates on capacitor C1, V mem At the same time, the charge on capacitor C1 leaks to ground through the memristor and R1. mem The voltage drop of the memristor reaches the threshold voltage V th , the memristor changes to a low resistance state, capacitor C1 discharges rapidly, and a voltage pulse is generated on the Spike node. mem The voltage drop of the memristor is reduced to the holding voltage V hold , the memristor changes to a high-resistance state, and the pulse emission ends; 3) The pulse is transmitted to transistor M2 and turns it on, charging capacitor C2, so that V ctrl Pull down to a low level, at this time, transistor M1 is turned off, disconnecting V mem The connection with the input signal makes the capacitor C1 unable to receive the input signal for accumulation, thereby realizing single pulse emission.

9. The operating method according to claim 8, characterized in that: A reset signal CLR is applied to transistor M3 to discharge capacitor C2, V ctrl Return to high level and repeat steps 1)-3) to receive the next input.

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