Semiconductor device and memory device including sampling circuit

Abstract

The invention relates to a semiconductor device and a memory device including a sampling circuit. The semiconductor device includes a sampling control circuit configured to select a coarse interval from a plurality of coarse intervals in accordance with a first mode signal during a sampling period, select a fine interval from a plurality of fine intervals in accordance with a second mode signal during the selected coarse interval, and generating first to third sampling control signals having an activated interval defined by the selected coarse interval and the selected fine interval; and a sampling circuit configured to sample an input address according to the first to third sampling control signals, respectively, to generate first to third sampling addresses, and to schedule the first to third sampling addresses according to sampling signals of a limited sampling period, to output an output address.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2023-0147662, filed on October 31, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate to semiconductor design technology, and more particularly, to a semiconductor device and a memory device including a sampling circuit for randomly sampling an input signal. Background Art

[0004] Recently, in addition to a normal refresh operation, an additional refresh operation (hereinafter referred to as a "target refresh operation") is performed on memory cells coupled to a specific word line that may lose data due to a row hammering phenomenon. The row hammering phenomenon refers to a phenomenon in which data of memory cells coupled to a specific word line or a neighboring word line disposed adjacent to the specific word line is damaged due to a large number of activations of the specific word line. In order to prevent the row hammering phenomenon, a target refresh operation is performed on a word line that has been activated more than a predetermined number of times and a neighboring word line disposed adjacent to the word line.

[0005] In a target refresh operation, a word line on which a target refresh operation is to be performed may be selected by randomly sampling addresses based on probability. Therefore, a sampling circuit for randomly sampling addresses has been studied. Summary of the invention

[0006] Embodiments of the present disclosure relate to a semiconductor device and a memory device including a sampling circuit capable of randomly sampling an address.

[0007] According to an embodiment of the present disclosure, a semiconductor device includes: a sampling control circuit configured to: select a coarse interval from a plurality of coarse intervals according to a first mode signal during a sampling period, select a fine interval from a plurality of fine intervals according to a second mode signal during the selected coarse interval, and generate first to third sampling control signals having activated intervals defined by the selected coarse interval and the selected fine interval; and a sampling circuit configured to: sample an input address according to the first to third sampling control signals, respectively, to generate first to third sampling addresses, and schedule the first to third sampling addresses to output output addresses according to the sampling signal defining the sampling period.

[0008] According to an embodiment of the present disclosure, a semiconductor device includes: a sampling control circuit configured to: generate a first mode signal and a second mode signal, the first mode signal and the second mode signal randomly pulsating with different periods according to a sampling signal; and generate first to third sampling control signals based on the first mode signal and the second mode signal; a first storage circuit configured to store an input address as one of a plurality of first preliminary addresses according to the first sampling control signal to generate a first sampling address; a second storage circuit configured to store the input address as one of a plurality of second preliminary addresses according to the second sampling control signal to generate a second sampling address; a shadow latch configured to latch the input address as a third sampling address according to a third sampling control signal; and an output control circuit configured to output an output address by selecting one of the first to third sampling addresses according to the sampling signal.

[0009] According to an embodiment of the present disclosure, a memory device includes: a refresh control circuit, which is configured to: select a coarse interval from a plurality of coarse intervals according to a first mode signal during a target refresh cycle, select a fine interval from a plurality of fine intervals according to a second mode signal during the selected coarse interval, generate a first sampling control signal to a third sampling control signal having an activated interval defined by the selected coarse interval and the selected fine interval, and sample an activated address according to the first sampling control signal to the third sampling control signal to output a target address; and a row control circuit, which is configured to refresh at least one row corresponding to the target address according to a target refresh command that defines the target refresh cycle.

[0010] Furthermore, according to embodiments of the present disclosure, the semiconductor device can maximize randomization by allowing the entire range of the sampling interval to be sampled. Furthermore, the semiconductor device can solve the periodicity problem of the sampling circuit by performing sampling using a dual-mode generation circuit operating at different periods / cycles.

[0011] Furthermore, according to an embodiment of the present disclosure, a semiconductor device can maximize the accuracy of address sampling and improve the efficiency of a target refresh operation by applying a sampling circuit to a memory device that performs a target refresh operation by sampling addresses based on probability. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a block diagram illustrating a memory device according to an embodiment of the present disclosure.

[0013] Figure 2 The present invention is a diagram showing an embodiment of the present invention. Figure 1 FIG. 5 is a diagram of the detailed configuration of the sampling control circuit and the sampling circuit.

[0014] Figure 3The present invention is a diagram showing an embodiment of the present invention. Figure 2 FIG. 1 is a diagram of a detailed configuration of a control signal generating circuit.

[0015] Figure 4 is a timing chart for describing the operation of the sampling control circuit according to an embodiment of the present disclosure.

[0016] Figure 5 It is shown Figure 2 FIG. 1 is a diagram of a detailed configuration of a first storage circuit.

[0017] Figure 6 It is shown Figure 5 FIG. 5 is a diagram of the detailed configuration of the latch control circuit.

[0018] Figure 7 It is shown Figure 2 Figure 4 is a diagram of the detailed configuration of the shadow latch.

[0019] Figure 8 It is shown Figure 2 FIG. 1 is a diagram of the detailed configuration of the output control circuit.

[0020] Fig. 9 is a diagram for describing the operation of the sampling circuit according to the embodiment of the present disclosure.

[0021] Fig.10 is a block diagram illustrating a memory device according to another embodiment of the present disclosure.

[0022] Fig.11 It is shown Fig.10 FIG. 1 is a diagram of the detailed configuration of the output control circuit of the sampling circuit.

[0023] Fig.12 is a block diagram illustrating a storage system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] Various embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. However, the embodiments of the present disclosure may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and the scope of the present disclosure will be fully conveyed to those skilled in the art. Throughout the present disclosure, the same reference numerals in the multiple figures and embodiments of the present disclosure refer to the same parts.

[0025] It should be understood that when an element is referred to as being "coupled" or "connected" to another element, this may mean that the two are directly coupled, or that the two are electrically connected to each other through another circuit interposed therebetween. It should also be understood that the terms "comprising", "including", and "having", etc., when used in this specification, indicate the presence of the features, numbers, steps, operations, elements, components, and / or combinations thereof, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and / or combinations thereof. In the present disclosure, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form.

[0026] Hereinafter, a memory device is described as a semiconductor device including a sampling circuit. However, the embodiments of the present disclosure are not limited thereto and may be applied to all semiconductor devices including a sampling circuit for randomly sampling an input address or an input signal.

[0027] Figure 1 is a block diagram illustrating a memory device 100 according to an embodiment of the present disclosure.

[0028] Reference Figure 1 , the memory device 100 may include a storage cell area 110, a row control circuit 120, a column control circuit 130, a target command generation circuit 140, a refresh control circuit 150, a command / address (CA) buffer 172, a command decoder 173, an address generation circuit 174 and a data input / output circuit 180.

[0029] The memory cell region 110 may include a plurality of memory cells MC respectively coupled to a plurality of word lines WL (hereinafter referred to as "a plurality of rows WL") and a plurality of bit lines BL (hereinafter referred to as "a plurality of columns BL"). The plurality of rows WL may extend in a first direction (e.g., a row direction) and may be sequentially arranged in a second direction (e.g., a column direction) perpendicular to the first direction. The plurality of columns BL may extend in the column direction and may be sequentially arranged in the row direction. The plurality of memory cells MC may be composed of memory cells that require a refresh operation to ensure data retention time. The memory cell region 110 may be composed of at least one memory body. The number of memory bodies or the number of memory cells MC and RHC may be determined according to the capacity of the memory device 100.

[0030] The CA buffer 172 may receive a command / address signal C / A from an external device (eg, a memory controller). The CA buffer 172 may buffer the command / address signal C / A to output an internal command ICMD and an internal address IADD.

[0031] The command decoder 173 may decode the internal command ICMD output from the CA buffer 172 to generate an active command ACT, a precharge command PCG, a read command RD, and a write command WT. In addition, the command decoder 173 may also decode the internal command ICMD to generate a normal refresh command REF that is periodically activated.

[0032] The address generation circuit 174 may classify the internal address IADD received from the CA buffer 172 into a row address RADD and a column address CADD. Depending on the embodiment, the address generation circuit 174 may interpret some bits of the internal address IADD as the row address RADD and the remaining bits as the column address CADD. The address generation circuit 174 may determine the internal address IADD as the row address RADD when an activation operation is indicated as a result of decoding by the command decoder 173, and determine the internal address IADD as the column address CADD when a read or write operation is indicated by the command decoder 173. A plurality of rows WL may be accessed according to the row address RADD, and a plurality of columns BL may be accessed according to the column address CADD.

[0033] The target command generation circuit 140 may generate a target refresh command TREF based on the normal refresh command REF. For example, whenever the number of inputs of the normal refresh command REF reaches a preset number of times or reaches a preset condition, the target command generation circuit 140 may generate a target refresh command TREF. The target refresh cycle described below may be determined by the target refresh command TREF, and one target refresh cycle may be defined as a period between adjacent target refresh commands TREF.

[0034] The refresh control circuit 150 may generate first to third sampling control signals SAM_EN1, SAM_EN2, and SAM_SH_EN that are randomly activated during a target refresh period. The refresh control circuit 150 may latch a row address RADD in response to an active command ACT to output an active address ADD_ACT, and store a plurality of sampling addresses by randomly sampling the active address ADD_ACT in response to the first to third sampling control signals SAM_EN1, SAM_EN2, and SAM_SH_EN. The refresh control circuit 150 may output a target address TADD by selecting one of the plurality of sampling addresses according to a target refresh command TREF.

[0035] In detail, the refresh control circuit 150 may include an activation latch 152 , a sampling control circuit 154 , and a sampling circuit 156 .

[0036] The active latch 152 may latch the internal address IADD in response to the active command ACT, and output as an active address ADD_ACT.

[0037] The sampling control circuit 154 may include at least two pattern generation circuits with different operation cycles to generate a first pattern signal and a second pattern signal, the first pattern signal and the second pattern signal randomly pulsating at different cycles during the target refresh cycle. The sampling control circuit 154 may randomly select one of a plurality of coarse intervals according to the first pattern signal during the target refresh cycle, and randomly select one of a plurality of fine intervals according to the second pattern signal during the selected coarse interval. The sampling control circuit 154 may generate first to third sampling control signals SAM_EN1, SAM_EN2, and SAM_SH_EN having activated intervals defined by the selected coarse interval and the selected fine interval. The sampling control circuit 154 may generate a first sampling control signal SAM_EN1, a second sampling control signal SAM_EN2, and a third sampling control signal SAM_SH_EN, the first sampling control signal and the second sampling control signal having activated intervals distinguished from each other by the selected fine interval during the target refresh cycle, and the third sampling signal having an activated interval defined by the selected coarse interval.

[0038] The sampling circuit 156 may store the first to third sampling addresses by sampling the activation address ADD_ACT according to the first to third sampling control signals SAM_EN1, SAM_EN2, and SAM_SH_EN, respectively, and output the target address TADD by scheduling the first to third sampling addresses according to the target refresh command TREF. According to an embodiment, the sampling circuit 156 may calculate an adjacent address using the sampling address to output the calculated adjacent address as the target address TADD.

[0039] The row control circuit 120 may be coupled to a plurality of memory cells MC of the memory cell region 110 through a plurality of rows WL. The row control circuit 120 may select or activate at least one row selected by the row address RADD when an activation command ACT is input, and deactivate the activated row when a precharge command PCG is input. In order to select a row to be refreshed during a normal refresh operation, a refresh counter (not shown) for generating a count address that increases sequentially according to a normal refresh command REF may be additionally provided. The row control circuit 120 may perform a normal refresh operation of sequentially refreshing a plurality of rows WL corresponding to the count address according to the normal refresh command REF. The row control circuit 120 may perform a target refresh operation of refreshing at least one adjacent row corresponding to a target address TADD according to a target refresh command TREF.

[0040] The column control circuit 130 may be coupled to a plurality of memory cells MC of the memory cell region 110 through a plurality of columns BL. The column control circuit 130 may select some columns from the columns BL according to the column address CADD, read the internal data DATA from the memory cells MC through the selected columns according to the read command RD, and write the internal data DATA provided through the data input / output circuit 180 to the memory cells MC through the selected columns according to the write command WT. The column control circuit 130 may be coupled to the data pad through the data input / output circuit 180 to transmit and receive data DQ to and from the memory controller.

[0041] The data input / output circuit 180 may be coupled between the column control circuit 130 and the data pad to send and receive internal data DATA to and from the memory controller. The data input / output circuit 180 may include a data output circuit 182 and a data input circuit 184. The data output circuit 182 may output the internal data DATA read from the memory cell region 110 to the data pad. The data input circuit 184 may receive the internal data DATA provided from the memory controller through the data pad.

[0042] Hereinafter, detailed configurations and operations of the sampling control circuit 154 and the sampling circuit 156 according to an embodiment of the present disclosure will be described with reference to the drawings.

[0043] Figure 2 The present invention is a diagram showing an embodiment of the present invention. Figure 1 FIG. 1 is a diagram of a detailed configuration of the sampling control circuit 154 and the sampling circuit 156 .

[0044] Reference Figure 2 , the sampling control circuit 154 may include at least two mode generation circuits 210 and 220 having different operation cycles to generate a first mode signal SOUT1 and a second mode signal SOUT2, which are randomly pulsed with different cycles during the target refresh cycle. The sampling control circuit 154 may generate first to third sampling control signals SAM_EN1, SAM_EN2, and SAM_SH_EN based on the first mode signal SOUT1 and the second mode signal SOUT2. The target refresh cycle may be determined by the target refresh command TREF, and one target refresh cycle may be defined as a cycle between adjacent target refresh commands TREF. In the case of a semiconductor device, the target refresh cycle may be defined as a sampling cycle, and the target refresh command TREF may be defined as a sampling signal. In addition, one sampling cycle may be defined as a cycle between adjacent sampling signals.

[0045] The sampling control circuit 154 may include a first pattern generation circuit 210 , a second pattern generation circuit 220 , a first interval control circuit 230 , a second interval control circuit 240 , and a control signal generation circuit 250 .

[0046] The first pattern generation circuit 210 may generate a first pattern signal SOUT1 that randomly pulses during a target refresh period. The first pattern generation circuit 210 may operate based on a target refresh command TREF. The first pattern generation circuit 210 may divide the target refresh period into a plurality of coarse and sparse intervals and generate a first pattern signal SOUT1 that pulses for each coarse and sparse interval. Each of the plurality of coarse and sparse intervals may have a random period (or length).

[0047] The second pattern generation circuit 220 may generate a second pattern signal SOUT2 that pulsates randomly during a target refresh period. The second pattern generation circuit 220 may operate based on the target refresh command TREF. The second pattern generation circuit 220 may divide the target refresh period into a plurality of fine intervals and generate a second pattern signal SOUT2 that pulsates for each fine interval. Each of the plurality of fine intervals has a random period and may have a shorter period than each of the plurality of coarse intervals. That is, the second pattern generation circuit 220 may operate in a shorter period than the first pattern generation circuit 210 to generate a second pattern signal SOUT2 that pulsates randomly in an interval shorter than the first pattern signal SOUT1.

[0048] Each of the first pattern generation circuit 210 and the second pattern generation circuit 220 can be implemented with a random pattern generator based on a pseudo-random binary sequence (PRBS) or a random pattern generator based on a linear feedback shift register (LFSR). For example, the first pattern generation circuit 210 and the second pattern generation circuit 220 can be implemented with a random pattern generator based on a PRBS. In this case, the first pattern generation circuit 210 and the second pattern generation circuit 220 can be implemented as a uniform random number sequence generator, which can generate a pattern signal that randomly pulsates the same number of times within a specific period, rather than a polling method.

[0049] The first interval control circuit 230 may randomly select a coarse interval from a plurality of coarse intervals according to the target refresh command TREF and the first mode signal SOUT1, and generate a coarse interval signal HIT1 for specifying the selected coarse interval. For example, the coarse interval signal HIT1 may be a signal having a logic high level during the selected coarse interval. According to an embodiment, the first interval control circuit 230 may generate a reference count value by counting the number of inputs of the target refresh command TREF, and generate a first count value by counting the number of triggers of the first mode signal SOUT1, and generate the coarse interval signal HIT1 by comparing the reference count value with the first count value. When the first count value matches the reference count value, the coarse interval signal HIT1 may be activated.

[0050] The second interval control circuit 240 may randomly select a fine interval from a plurality of fine intervals according to the target refresh command TREF and the second mode signal SOUT2 during the selected coarse interval, and generate a fine interval signal HIT2 for specifying the selected fine interval. For example, the fine interval signal HIT2 may be a signal having a logic high level during the selected fine interval. According to an embodiment, the second interval control circuit 240 may generate a second count value by counting the number of times the second mode signal SOUT2 is triggered, and generate the fine interval signal HIT2 by comparing a reference count value with the second count value. When the second count value matches the reference count value, the fine interval signal HIT2 may be activated.

[0051] The control signal generating circuit 250 may generate a first sampling control signal SAM_EN1 and a second sampling control signal SAM_EN2 having activated intervals distinguished from each other by the selected fine interval during the target refresh period. In addition, the control signal generating circuit 250 may generate a third sampling control signal SAM_SH_EN having an activated interval defined by the selected coarse interval during the target refresh period.

[0052] The sampling circuit 156 may sample the activation address ADD_ACT according to the first to third sampling control signals SAM_EN1, SAM_EN2, and SAM_SH_EN, respectively, to generate the first to third sampling addresses SAM_ADD1, SAM_ADD2, and SH_ADD. The sampling circuit 156 may schedule the first to third sampling addresses SAM_ADD1, SAM_ADD2, and SH_ADD according to the target refresh command TREF to output the target address TADD.

[0053] The sampling circuit 156 may include a first storage circuit 310 , a second storage circuit 320 , a shadow latch 330 , and an output control circuit 340 .

[0054] The first storage circuit 310 may receive the activation address ACT_ADD according to the first sampling control signal SAM_EN1 and store it as a plurality of first preliminary addresses, and output the first sampling address SAM_ADD1 by selecting one of the first preliminary addresses based on the number of times the first preliminary address is input (or stored). The first storage circuit 310 may provide the first input control signal L_IN1 and the first sampling address SAM_ADD1. That is, the first input control signal L_IN1 may be a signal indicating that the first sampling address SAM_ADD1 is valid data.

[0055] The second storage circuit 320 may receive the activation address ACT_ADD according to the second sampling control signal SAM_EN2 and store it as a plurality of second preliminary addresses, and output the second sampling address SAM_ADD2 by selecting one of the second preliminary addresses based on the number of times the second preliminary address is input (or stored). The second storage circuit 320 may provide the second input control signal L_IN2 and the second sampling address SAM_ADD2. That is, the second input control signal L_IN2 may be a signal indicating that the second sampling address SAM_ADD2 is valid data.

[0056] The shadow latch 330 may latch the activation address ACT_ADD according to the third sampling control signal SAM_SH_EN to output the third sampling address SH_ADD according to the third output control signal L_OUT3 provided from the output control circuit 340 .

[0057] The output control circuit 340 may output the target address TADD by scheduling the first to third sampling addresses SAM_ADD1, SAM_ADD2, and SH_ADD according to the target refresh command TREF. The output control circuit 340 may receive the first sampling address SAM_ADD1 according to the first input control signal L_IN1, and receive the second sampling address SAM_ADD2 according to the second input control signal L-IN2. In addition, the output control circuit 340 may provide the shadow latch 330 with a third output control signal L_OUT3 so as to receive the third sampling address SH_ADD from the shadow latch 330.

[0058] Below, refer to Figure 3 and Figure 4 , the detailed configuration and operation of each component of the sampling control circuit 154 will be described.

[0059] Figure 3 The present invention is a diagram showing an embodiment of the present invention. Figure 2 FIG. 2 is a diagram of a detailed configuration of the control signal generating circuit 250 .

[0060] Reference Figure 3 , the control signal generating circuit 250 may include a first signal generator 251 to a third signal generator 253 .

[0061] The first signal generator 251 may include a first inverter INV1 and a first SR latch S1. The first inverter INV1 may invert the fine interval signal HIT2 to output an inverted fine interval signal HITB2. The first SR latch S1 may output a first sampling control signal SAM_EN1 that is set according to the target refresh command TREF and reset according to the inverted fine interval signal HITB2. As a result, the first signal generator 251 may generate a first sampling control signal SAM_EN1 that becomes a logic high level according to a rising edge of the target refresh command TREF and becomes a logic low level according to a falling edge of the fine interval signal HIT2.

[0062] The second signal generator 252 may include a second SR latch S2. The second SR latch S2 may output a second sampling control signal SAM_EN2 that is set according to the inverted fine interval signal HITB2 and reset according to the target refresh command TREF. As a result, the second signal generator 252 may generate a second sampling control signal SAM_EN2 that becomes a logic high level according to a falling edge of the fine interval signal HIT2 and becomes a logic low level according to a rising edge of the target refresh command TREF.

[0063] The third signal generator 253 may include a second inverter INV2 and a third SR latch S3. The second inverter INV2 may invert the coarse interval signal HIT1 to output an inverted coarse interval signal HITB1. The third SR latch S3 may output a third sampling control signal SAM_SH_EN that is set according to the target refresh command TREF and reset according to the inverted coarse interval signal HITB1. As a result, the third signal generator 253 may generate a third sampling control signal SAM_SH_EN that becomes a logic high level according to a rising edge of the target refresh command TREF and becomes a logic low level according to a falling edge of the coarse interval signal HIT1.

[0064] Figure 4 is a timing chart for describing the operation of the sampling control circuit 154 according to an embodiment of the present disclosure.

[0065] Reference Figure 4 , the interval between adjacent target refresh commands TREF can be defined as a target refresh period tSP.

[0066] The first pattern generation circuit 210 may generate a first pattern signal SOUT1 that pulsates randomly during a target refresh period tSP. The first pattern generation circuit 210 may divide the target refresh period tSP into a plurality of coarse intervals tCOARSE having a random period (or length), and generate a first pattern signal SOUT1 that pulsates for each coarse interval. The second pattern generation circuit 220 may generate a second pattern signal SOUT2 that pulsates randomly during a target refresh period tSP. The second pattern generation circuit 220 may divide the target refresh period tSP into a plurality of fine intervals tFINE, and generate a second pattern signal SOUT2 that pulsates for each fine interval. The second pattern generation circuit 220 may generate a second pattern signal SOUT2 that pulsates randomly with a period shorter than that of the first pattern signal SOUT1.

[0067] The first interval control circuit 230 may generate a first count value S_CNT1 by counting the number of times the first mode signal SOUT1 is triggered, and generate a reference count value (e.g., 1) by counting the number of times the target refresh command TREF is input. When the first count value S_CNT1 is the same as the reference count value, the first interval control circuit 230 may activate the coarse interval signal HIT1. The second interval control circuit 240 may generate a second count value S_CNT2 by counting the number of times the second mode signal SOUT2 is triggered, and activate the fine interval signal HIT2 when the second count value S_CNT2 is the same as the reference count value. That is, the activated interval of the fine interval signal HIT2 may be sampled within the activated interval of the coarse interval signal HIT1.

[0068] The control signal generating circuit 250 may set the first sampling control signal SAM_EN1 and the third sampling control signal SAM_SH_EN to a logic high level according to the rising edge of the target refresh command TREF at which the target refresh period tSP starts. The control signal generating circuit 250 may reset the first sampling control signal SAM_EN1 to a logic low level and set the second sampling control signal SAM_EN2 to a logic high level according to the falling edge of the fine interval signal HIT2. The control signal generating circuit 250 may reset the third sampling control signal SAM_SH_EN to a logic low level according to the falling edge of the coarse interval signal HIT1. The control signal generating circuit 250 may reset the second sampling control signal SAM_EN2 to a logic low level according to the rising edge of the target refresh command TREF after the target refresh period tSP ends.

[0069] As described above, in the embodiment of the present disclosure, during the target refresh period tSP, the first sampling control signal SAM_EN1 and the second sampling control signal SAM_EN2 are mutually exclusively activated based on the selected fine interval, and the third sampling control signal SAM_SH_EN can cover the interval where the first sampling control signal SAM_EN1 and the second sampling control signal SAM_EN2 overlap. Therefore, randomization can be maximized by allowing the entire range of the sampling period (i.e., the target refresh period tSP) to be sampled.

[0070] Below, refer to Figures 5 to 8 , the detailed configuration and operation of each component of the sampling circuit 156 will be described.

[0071] Figure 5 It is shown Figure 2 FIG. 1 is a diagram of a detailed configuration of the first storage circuit 310 .

[0072] Reference Figure 5 The first storage circuit 310 may include a latch control circuit 312, a plurality of address latches, and a plurality of counters. The plurality of address latches and the plurality of counters may correspond one to one. Hereinafter, the case of setting the first address latch ADD_L1 to the fourth address latch ADD_L4 and the first counter C1 to the fourth counter C4 will be described as an example.

[0073] The latch control circuit 312 may receive the first sampling control signal SAM_EN1, the activation address ACT_ADD, the first latch address LADD1 to the fourth latch address LADD4, and the first count signal CNT1 to the fourth count signal CNT4, and output the first match signal M1 to the fourth match signal M4, the first reset signal R1 to the fourth reset signal R4, the first latch input signal PIN1 to the fourth latch input signal PIN4, and the first latch output signal POUT1 to the fourth latch output signal POUT4. When one of the first latch output signal POUT1 to the fourth latch output signal POUT4 is activated, the latch control circuit 312 may activate the first input control signal L_IN1 and provide the first input control signal L_IN1 to the output control circuit 340.

[0074] The first to fourth address latches ADD_L1 to ADD_L4 may store activation addresses ACT_ADD as first to fourth latch addresses LADD1 to LADD4 in response to first to fourth latch input signals PIN1 to PIN4, respectively, and output first sampling addresses SAM_ADD1 in response to first to fourth latch output signals POUT1 to POUT4, respectively. For example, the first address latch ADD_L1 may store activation address ACT_ADD1 as first latch address LADD1 when the first latch input signal PIN1 is activated, and output the stored first latch address LADD1 as first sampling address SAM_ADD1 when the first latch output signal POUT1 is activated. The first to fourth address latches ADD_L1 to ADD_L4 may provide first to fourth latch addresses LADD1 to LADD4 to the latch control circuit 312.

[0075] The first counter C1 to the fourth counter C4 may increase the values ​​of the first count signals CNT1 to the fourth count signals CNT4 according to the first match signals M1 to the fourth match signals M4, and respectively initialize the first count signals CNT1 to the fourth count signals CNT4 according to the first reset signals R1 to the fourth reset signals R4. For example, the first counter C1 may increase the value of the first count signal CNT1 by "+1" when the first match signal M1 is activated, and initialize the value of the first count signal NT1 to "0" when the first reset signal R1 is activated. The first counter C1 to the fourth counter C4 may provide the first count signals CNT1 to the fourth count signals CNT4 to the latch control circuit 312.

[0076] Figure 6 It is shown Figure 5 FIG. 3 is a diagram of a detailed configuration of the latch control circuit 312 .

[0077] Reference Figure 6 , the latch control circuit 312 may include first to third latch controllers 410 to 430 .

[0078] The first latch controller 410 may compare the activation address ACT_ADD with the first latch address LADD1 to the fourth latch address LADD4 according to the first sampling control signal SAM_EN1 to generate the first match signal M1 to the fourth match signal M4, respectively. For example, when the first sampling control signal SAM_EN1 is activated, the first latch controller 410 may compare the activation address ACT_ADD with the first latch address LADD1 to activate the first match signal M1 when the activation address ACT_ADD is the same as the first latch address LADD1. When the activation address ACT_ADD is different from all of the first latch address LADD1 to the fourth latch address LADD4, the first latch controller 410 may activate the mismatch signal UM_MATCH.

[0079] The second latch controller 420 may identify whether each value of the first to fourth count signals CNT1 to CNT4 is equal to or greater than a preset threshold value according to the first sampling control signal SAM_EN1 to generate the first to fourth latch output signals POUT1 to POUT4. In addition, the second latch controller 420 may selectively activate the first to fourth reset signals R1 to R4 according to the first to fourth latch output signals POUT1 to POUT4, and activate the first input control signal L_IN1 when one of the first to fourth reset signals R1 to R4 is activated. For example, when the first sampling control signal SAM_EN1 is activated, the second latch controller 420 may identify whether each value of the first to fourth count signals CNT1 to CNT4 is equal to or greater than a preset threshold value to activate the first latch output signal POUT1 when it is determined that the first count signal CNT1 is equal to or greater than the preset threshold value. The second latch controller 420 may activate the first reset signal R1 and the first input control signal L_IN1 according to when the first latch output signal POUT1 is activated.

[0080] The third latch controller 430 may generate first to fourth latch input signals PIN1 to PIN4 in response to the unmatch signal UM_MATCH and the first to fourth latch output signals POUT1 to POUT4. The third latch controller 430 may determine an empty address latch based on the first to fourth latch output signals POUT1 to POUT4, and activate a latch input signal corresponding to the empty address latch when the unmatch signal UM_MATCH is activated. For example, when the first latch output signal POUT1 is activated, the third latch controller 430 may determine that an invalid address is stored in the first address latch ADD_L1, that is, the first address latch ADD_L1 is empty. Thereafter, when the unmatch signal UM_MATCH is activated, the third latch controller 430 may activate the first latch input signal PIN1 corresponding to the first address latch ADD_L1, thereby controlling the first address ACT_ADD to be stored in the first address latch ADD_L1.

[0081] Reference Figure 5 and Figure 6 , the operation of the first storage circuit 310 will be described as follows.

[0082] When the activation address ACT_ADD is input while the first sampling control signal SAM_EN1 is activated, the address latches ADD_L1 to ADD_L4 may store the activation address ACT_ADD as the first preliminary address (i.e., the first latch address LADD1 to the fourth latch address LADD4). When the activation address ACT_ADD is the same as one of the first preliminary addresses LADD1 to LADD4 stored in the address latches ADD_L1 to ADD_L4, the corresponding counters in the counters C1 to C4 may increase their count values. That is, the counters C1 to C4 may count the number of inputs of the first preliminary addresses LADD1 to LADD4, respectively. When one of the count values ​​stored in the counters C1 to C4 is equal to or greater than the threshold value, the latch control circuit 312 may control the first preliminary address stored in the corresponding address latch to output it as the first sampling address SAM_ADD1.

[0083] That is, the first storage circuit 310 can store the activation address ACT_ADD as the first preliminary address (i.e., the first latch address LADD1 to the fourth latch address LADD4) according to the first sampling control signal SAM_EN1, and select the first sampling address SAM_ADD1 from the first preliminary addresses LADD1 to LADD4 based on the number of input times of the first preliminary addresses LADD1 to LADD4 to output the sampling address SAM_ADD1 together with the first input control signal L_IN1.

[0084] The second storage circuit 320 may have the same configuration and perform the same operation as the first storage circuit 310 except receiving the second sampling control signal SAM_EN2 and outputting the second sampling address SAM_ADD2 and the second input control signal L_IN2 .

[0085] Figure 7 It is shown Figure 2 FIG. 3 is a diagram of a detailed configuration of the shadow latch 330 .

[0086] Reference Figure 7 , the shadow latch 330 may store the activation address ACT_ADD according to the third sampling control signal SAM_SH_EN to output the third sampling address SH_ADD according to the third output control signal L_OUT3. Since the shadow latch 330 rewrites the activation address ACT_ADD during the activation interval of the third sampling control signal SAM_SH_EN, the finally stored activation address ACT_ADD may be provided as the third sampling address SH_ADD according to the third output control signal L_OUT3.

[0087] Figure 8 It is shown Figure 2 FIG. 3 is a diagram of a detailed configuration of the output control circuit 340 .

[0088] Reference Figure 8 , the output control circuit 340 may include a sequence control circuit 342 , a first output latch circuit 344 , and a second output latch circuit 346 .

[0089] The sequence control circuit 342 may generate the first output control signal L_OUT1 to the third output control signal L_OUT3 according to the target refresh command TREF. The sequence control circuit 342 may determine the activation order of the first output control signal L_OUT1 to the third output control signal L_OUT3 according to the number of input times of the target refresh command TREF. For example, each time the target refresh command TREF is input, the sequence control circuit 342 may sequentially activate the first output control signal L_OUT1 to the third output control signal L_OUT3 once. Alternatively, each time the target refresh command TREF is input, the sequence control circuit 342 may sequentially activate the first output control signal L_OUT1 twice, the second output control signal L_OUT2 twice, and the third output control signal L_OUT3 once. The activation order of the first output control signal L_OUT1 to the third output control signal L_OUT3 may be changed differently according to the embodiment.

[0090] The first output latch circuit 344 may sequentially store the first sampling address SAM_ADD1 according to the first input control signal L_IN1, and sequentially output the stored address as the target address TADD according to the first output control signal L_OUT1. The first output latch circuit 344 may be configured as a pipeline latch circuit including a plurality of address latches. Figure 8 In the embodiment, the case where the first output latch circuit 344 includes two address latches ADD_L11 and ADD_L12 is taken as an example for description, but the embodiments of the present disclosure are not limited thereto, and the first output latch circuit 344 may include two or more address latches.

[0091] The second output latch circuit 346 may sequentially store the second sampling address SAM_ADD2 according to the second input control signal L_IN2, and sequentially output the stored address as the target address TADD according to the second output control signal L_OUT2. The second output latch circuit 346 may be configured as a pipeline latch circuit including a plurality of address latches. Figure 8 In the embodiment, the case where the second output latch circuit 346 includes two address latches ADD_L21 and ADD_L22 is taken as an example for description, but the embodiments of the present disclosure are not limited thereto, and the second output latch circuit 344 may include two or more address latches.

[0092] The shadow latch 330 may provide the finally stored active address ACT_ADD as the third sampling address SH_ADD according to the third output control signal L_OUT3 .

[0093] With the above configuration, the output control circuit 340 can sequentially store the first and second sampling addresses SAM_ADD1 and SAM_ADD2 according to the input number of the target refresh command TREF, and output the target address TADD by scheduling the first and second sampling addresses SAM_ADD1 and SAM_ADD2 and the third sampling address SH_ADD.

[0094] Fig. 9 1 is a diagram for describing the operation of the sampling circuit 156 according to an embodiment of the present disclosure. Fig. 9 In the embodiment, the first storage circuit 310 and the second storage circuit 320 each have three address latches and a counter, and the first output latch circuit 344 and the second output latch circuit 346 each have two address latches.

[0095] Reference Fig. 9 Whenever the input number of the normal refresh command REF reaches a preset number, the target command generation circuit 140 may generate a target refresh command TREF. The target refresh cycle may be started by the target refresh command TREF.

[0096] The sampling control circuit 154 may randomly select a coarse interval according to the target refresh command TREF and the first mode signal SOUT1, and generate a coarse interval signal HIT1 specifying the selected coarse interval. In addition, the sampling control circuit 154 may randomly select a fine interval according to the target refresh command TREF and the second mode signal SOUT2 during the selected coarse interval, and generate a fine interval signal HIT2 specifying the selected fine interval. The sampling control circuit 154 may generate a first sampling control signal SAM_EN1 and a second sampling control signal SAM_EN2 having activated intervals separated from each other by a falling edge of the fine interval signal HIT2, and generate a third sampling control signal SAM_SH_EN having an activated interval defined by a falling edge of the coarse interval signal HIT1.

[0097] The first storage circuit 310 can operate during the activated interval of the first sampling control signal SAM_EN1. In this case, during the previous target refresh cycle, the 51st row address ADD_51 has been input 14 times, so that the count value "14" is stored in the first counter C1, and the 52nd row address ADD_52 and the 53rd row address ADD_53 have been input 15 times, so that the count value "15" is stored in the second counter C2 and the third counter C3, respectively.

[0098] When the 51st row address ADD_51 is input together with the activation command ACT during the activated interval of the first sampling control signal SAM_EN1, the first storage circuit 310 may store the 51st row address ADD_51 in the first address latch ADD_L1 and increase the count value of the first counter C1 to "15". Thereafter, when the 52nd row address ADD_52 is input together with the activation command ACT, the first storage circuit 310 may store the 52nd row address ADD_52 in the second address latch ADD_L2 and increase the count value of the second counter C2 to "16". In this case, the threshold is set to 16, the first storage circuit 310 may provide the 52nd row address ADD_52 stored in the second address latch ADD_L2 as the first sampling address SAM_ADD1, and the first output latch circuit 344 may store the first sampling address SAM_ADD1 in the address latch ADD_L11. Thereafter, when the 53rd row address ADD_53 is input together with the activation command ACT, the first storage circuit 310 may store the 53rd row address ADD_53 in the third address latch ADD_L3 and increase the count value of the third counter C3 to "16". The first storage circuit 310 may provide the 53rd row address ADD_53 stored in the third address latch ADD_L3 as the first sampling address SAM_ADD1, and the first output latch circuit 344 may store the first sampling address SAM_ADD1 in the address latch ADD_L12. For reference, even when the 54th row address ADD_54 is input, since all address latches are in use, the first storage circuit 310 does not store the 54th row address ADD_54.

[0099] During the activated interval of the third sampling control signal SAM_SH_EN, the shadow latch 330 may sequentially rewrite the 51st row address ADD_51, the 52nd row address ADD_52, the 53rd row address ADD_53, the 54th row address ADD_54, and the 55th row address ADD_55. Therefore, the shadow latch 330 may finally store the 55th row address ADD_55.

[0100] The second storage circuit 320 may operate during an activated interval of the second sampling control signal SAM_EN2 after the first sampling control signal SAM_EN1 is deactivated. In this case, during the previous target refresh cycle, the 56th row address ADD_56 has been input 14 times, so that the count value "14" is stored in the first counter C1, and the 57th row address ADD_57 and the 58th row address ADD_58 have been input 15 times, so that the count value "15" is stored in the second counter C2 and the third counter C3, respectively. During the activated interval of the second sampling control signal SAM_EN2, the 56th row address ADD_56, the 57th row address ADD-57, and the 58th row address ADD_58 are input together with the activation command ACT. The second storage circuit 320 may store the 56th row address ADD_56, the 57th row address ADD-57, and the 58th row address ADD_58 in the first address latch ADD_L1 to the third address latch ADD_L3, respectively, and increase the count values ​​of the first counter C1 to the third counter C3 to "15", "16", and "16", respectively. Therefore, the second storage circuit 320 may sequentially provide the 57th row address ADD_57 and the 58th row address ADD_58 as the second sampling address SAM_ADD2, and the second output latch circuit 346 may sequentially store the second sampling address SAM_ADD1 in the address latches ADD_L21 and ADD_L22.

[0101] Thereafter, when the target refresh command TREF is input, the addresses stored in the first output latch circuit 344 , the shadow latch 330 , and the second output latch circuit 346 may be output as the target address TADD in the order determined by the sequence control circuit 342 .

[0102] As described above, according to the embodiments of the present disclosure, in a memory device that performs a target refresh operation by sampling addresses based on probability, randomization can be maximized by allowing the entire range of sampling periods to be sampled. In addition, by performing sampling using a dual-mode generation circuit that operates at different periods / cycles, the periodicity of the sampling circuit can be eliminated and the efficiency of the target refresh operation can be improved.

[0103] In the above-described embodiment, the case where the target refresh operation is performed according to the internally generated target refresh command TREF is described as an example, but recently the target refresh operation is also performed according to the refresh management command RFM provided from an external device (eg, a memory controller).

[0104] Fig.10 is a block diagram illustrating a memory device 500 according to another embodiment of the present disclosure.

[0105] Reference Fig.10, the memory device 500 may include a storage cell area 510, a row control circuit 520, a column control circuit 530, a target command generation circuit 540, a refresh control circuit 550, a command / address (CA) buffer 572, a command decoder 573, an address generation circuit 574 and a data input / output circuit 580. Fig.10 The memory cell region 510, the column control circuit 530, the target command generation circuit 540, the CA buffer 572, the address generation circuit 574, and the data input / output circuit 580 may have the same Figure 1 Basically the same configuration.

[0106] The command decoder 573 may decode the internal command ICMD output from the CA buffer 572 to generate an activation command ACT, a precharge command PCG, a read command RD, and a write command WT. In addition, the command decoder 573 may decode the internal command ICMD to generate a normal refresh command REF that is periodically activated and a refresh management command RFM that is non-periodically activated. That is, the refresh management command RFM may be a command for a target refresh operation provided from the memory controller, and the target refresh command TREF may be a command for a target refresh operation generated by the memory device 500 itself.

[0107] The row control circuit 520 may be coupled to a plurality of memory cells MC of the memory cell region 510 through a plurality of rows WL. The row control circuit 520 may select or activate at least one row selected by the row address RADD when an activation command ACT is input, and deactivate the activated row when a precharge command PCG is input. The row control circuit 520 may perform a normal refresh operation of sequentially refreshing a plurality of rows WL corresponding to a count address according to a normal refresh command REF. The row control circuit 520 may perform a target refresh operation of refreshing at least one adjacent row corresponding to a target address TADD according to a target refresh command TREF or a refresh management command RFM.

[0108] The refresh control circuit 550 may generate first to third sampling control signals SAM_EN1, SAM_EN2, and SAM_SH_EN that are randomly activated during a target refresh period. The refresh control circuit 550 may latch an internal address IADD as an activation address ADD_ACT in response to an activation command ACT, and store a plurality of sampling addresses by randomly sampling the activation address ADD_ACT in response to the first to third sampling control signals SAM_EN1, SAM_EN2, and SAM_SH_EN. The refresh control circuit 550 may output a target address TADD by selecting one of the plurality of sampling addresses according to a target refresh command TREF or a refresh management command RFM.

[0109] In detail, the refresh control circuit 550 may include an activation latch 552 , a sampling control circuit 554 , and a sampling circuit 556 . Fig.10 The activation latch 552 and the sampling control circuit 554 may have Figure 1 Basically the same configuration.

[0110] The sampling circuit 556 may store the first to third sampling addresses by sampling the activation address ADD_ACT according to the first to third sampling control signals SAM_EN1, SAM_EN2, and SAM_SH_EN, respectively, and output the target address TADD by scheduling the first to third sampling addresses according to the target refresh command TREF or the refresh management command RFM. According to an embodiment, the sampling circuit 556 may include Figure 2 3. In addition to the output control circuit 340 outputting the target address TADD by scheduling the first to third sampling addresses SAM_ADD1, SAM_ADD2 and SH_ADD according to the target refresh command TREF or the refresh management command RFM, the sampling circuit 556 may have the same Figure 1 The sampling circuit 156 has basically the same configuration.

[0111] Hereinafter, the output control circuit included in the sampling circuit 556 will be described.

[0112] Fig.11 It is shown Fig.10 FIG. 5 is a diagram of a detailed configuration of the output control circuit 640 of the sampling circuit 556.

[0113] Reference Fig.11 The output control circuit 640 may include a first sequence control circuit 641 , a second sequence control circuit 642 , a first output latch circuit 644 , and a second output latch circuit 646 .

[0114] The first sequential control circuit 641 may generate the first output control signal L_OUT and the third output control signal L_OUT3 according to the target refresh command TREF. The first sequential control circuit 641 may determine the activation order of the first output control signal L_OUT and the third output control signal L_OUT3 according to the number of times the target refresh command TREF is input. For example, each time the target refresh command TREF is input, the first sequential control circuit 641 may sequentially activate the first output control signal L_OUT1 and the third output control signal L_OUT3 once. Alternatively, each time the target refresh command TREF is input, the first sequential control circuit 641 may sequentially activate the first output control signal L_OUT1 twice, and sequentially activate the third output control signal L_OUT3 once.

[0115] The second sequence control circuit 642 may generate the second output control signal L_OUT2 according to the refresh management command RFM. For example, the second sequence control circuit 642 may activate the second output control signal L_OUT2 each time the refresh management command RFM is input. Alternatively, the second sequence control circuit 642 may activate the second output control signal L_OUT2 each time the refresh management command RFM is input a predetermined number of times.

[0116] The first output latch circuit 644 and the second output latch circuit 646 may have Figure 8 The first output latch circuit 344 and the second output latch circuit 346 have substantially the same configuration and perform substantially the same operation.

[0117] With the above configuration, the output control circuit 640 may sequentially store the first and second sampling addresses SAM_ADD1 and SAM_ADD2 according to the target refresh command TREF and the refresh management command RFM, and output the target address TADD by scheduling the first and second sampling addresses SAM_ADD1 and SAM_ADD2 and the third sampling address SH_ADD.

[0118] In addition, the embodiments of the present disclosure are not limited thereto, and the first to third output control signals L_OUT1 to L_OUT3 may be generated in a variety of ways according to the target refresh command TREF and the refresh management command RFM. For example, the first sequence control circuit 641 may generate the first output control signal L_OUT1 according to the target refresh command TREF, and the second sequence control circuit 642 may generate the second output control signal L_OUT2 and the third output control signal L_OUT3 according to the refresh management command RFM.

[0119] Fig.12 is a block diagram illustrating a storage system 1000 according to an embodiment of the present disclosure.

[0120] Reference Fig.12 , a memory system 1000 includes a memory device 100 and a memory controller 200 .

[0121] The memory controller 200 may control the overall operation of the memory system 1000 and control the overall data communication between the host (i.e., an external device) and the memory device 100. The memory controller 200 may generate a command / address signal (C / A) in response to a request REQ from the host and provide it to the memory device 100. According to an embodiment, the memory controller 200 may provide a clock together with the command / address signal C / A to the memory device 100. The memory controller 200 may provide the memory device 100 with data DQ corresponding to the request REQ provided from the host. The memory controller 200 may provide the data DQ read from the memory device 100 to the host.

[0122] The command / address signal C / A provided to the memory device 100 from the memory controller 200 may include an activation command ACT, a precharge command PCG, a normal refresh command REF, a refresh management command RFM, a read command RD, and a write command WT. The memory controller 200 may apply a normal refresh command REF indicating a normal refresh operation between operations requested by the host. The memory controller 200 may apply the normal refresh command REF so that all rows are refreshed normally within the refresh window (tREFW) defined in the specification. In addition, the memory controller 200 may issue a refresh management command RFM at each time interval defined in the specification, or whenever the number of issuances of the activation command ACT reaches the number of times defined in the specification.

[0123] The memory device 100 may have Figure 1 The memory device 10 or Fig.10 The memory device 500 has substantially the same configuration as that of the memory device 500. That is, in an embodiment of the present disclosure, the memory device 100 may generate a target refresh command TREF defining a target refresh cycle according to a normal refresh command REF. The memory device 100 may select a coarse interval from a plurality of coarse intervals according to a first mode signal during a target refresh cycle, select a fine interval from a plurality of fine intervals according to a second mode signal during the selected coarse interval, generate first to third sampling control signals having an activation interval defined by the selected coarse interval and the selected fine interval, generate first to third sampling addresses by sampling the row address according to the first to third sampling control signals, respectively, and output the target address by scheduling the first to third sampling addresses according to the target refresh command TREF or the refresh management command RFM. The memory device 100 may refresh a row corresponding to the target address according to the target refresh command TREF or the refresh management command RFM. Therefore, an embodiment of the present disclosure may maximize randomization by allowing the entire range of the sampling cycle (i.e., the target refresh cycle) to be sampled.

[0124] Various embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms are used here, these terms are only used to describe the embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-mentioned embodiments, and there may be many changes within the spirit and scope of the present disclosure. It should be clear to those skilled in the art that in addition to the embodiments disclosed herein, various modifications may also be made based on the technical scope of the present disclosure. These embodiments may be combined to form additional embodiments.

[0125] It should be noted that although the technical spirit of the present disclosure has been described in conjunction with the embodiments of the present disclosure, this is only for descriptive purposes and should not be interpreted as limiting. It should be understood by those skilled in the art that various changes may be made to the technical spirit of the present disclosure and the appended claims without departing from the technical spirit of the present disclosure and the appended claims.

[0126] For example, for the logic gates and transistors provided as examples in the above embodiments, different positions and types may be implemented according to the polarity of the input signal.

Claims

1. A semiconductor device comprising: A sampling control circuit which: selecting a coarse interval from a plurality of coarse intervals according to a first mode signal during a sampling period, selecting a fine interval from a plurality of fine intervals according to a second mode signal during the selected coarse interval, and generating first to third sampling control signals, the first to third sampling control signals having activated intervals defined by the selected coarse interval and the selected fine interval; and A sampling circuit which: respectively sampling the input address according to the first sampling control signal to the third sampling control signal to generate the first sampling address to the third sampling address, and The first sampling address to the third sampling address are scheduled according to a sampling signal defining the sampling period to output an output address.

2. The semiconductor device according to claim 1, in, During the sampling period, the sampling control circuit generates the first sampling control signal and the second sampling control signal having the activated intervals separated from each other by the selected fine interval, and During the sampling period, the sampling control circuit generates the third sampling control signal having the activated interval defined by the selected coarse interval.

3. The semiconductor device according to claim 1, wherein The sampling control circuit comprises: A first interval control circuit, which: randomly selects the coarse interval from the plurality of coarse intervals according to the sampling signal and the first mode signal; A second interval control circuit, which: randomly selects the fine interval from the plurality of fine intervals according to the sampling signal and the second mode signal during the selected coarse interval; and A control signal generating circuit that generates the first and second sampling control signals having the activated intervals separated from each other by the selected fine interval, and generates the third sampling control signal having the activated interval defined by the selected coarse interval.

4. The semiconductor device according to claim 3, wherein: The first interval control circuit generates a coarse interval signal designating the selected coarse interval by comparing a first count value generated by counting the first pattern signal with a reference count value generated by counting the sampling signal.

5. The semiconductor device according to claim 4, wherein: The second interval control circuit generates a fine interval signal designating the selected fine interval by comparing a second count value generated by counting the second mode signal with the reference count value.

6. The semiconductor device according to claim 3, wherein: The control signal generating circuit comprises: a first signal generator, which: generates the first sampling control signal which is set according to the sampling signal and reset according to a fine interval signal which specifies the selected fine interval; A second signal generator, which: generates the second sampling control signal which is set according to the fine interval signal and reset according to the sampling signal; and A third signal generator is configured to generate the third sampling control signal which is set according to the sampling signal and reset according to a coarse interval signal which specifies the selected coarse interval.

7. The semiconductor device according to claim 1, further comprising: A first pattern generating circuit, which: generates the first pattern signal that pulses randomly during the sampling period; and A second pattern generating circuit generates the second pattern signal which randomly pulses at a shorter period than the first pattern signal during the sampling period.

8. The semiconductor device according to claim 1, wherein The sampling circuit comprises: a first storage circuit, which: receives the input address according to the first sampling control signal and stores it as one of a plurality of first preliminary addresses, and selects one of the first preliminary addresses to output the first sampling address based on the number of times the first preliminary address is input; a second storage circuit, which: receives the input address according to a second sampling control signal and stores it as one of a plurality of second preliminary addresses, and selects one of the second preliminary addresses to output a second sampling address based on the number of times the second preliminary address is input; a shadow latch storing the input address as the third sampling address according to the third sampling control signal; and An output control circuit outputs the output address by scheduling the first sampling address to the third sampling address according to the sampling signal.

9. The semiconductor device according to claim 8, wherein: The first storage circuit comprises: a plurality of address latches, which: store the input address as one of the plurality of first preliminary addresses according to the first sampling control signal; a plurality of counters, which: respectively count the number of times the first preliminary address is input; and A latch control circuit controls a corresponding first preliminary address to be output as the first sampling address when one of the count values ​​of the plurality of counters is equal to or greater than a threshold.

10. The semiconductor device according to claim 8, wherein The second storage circuit comprises: a plurality of address latches, which: store the input address as one of the plurality of second preliminary addresses according to the second sampling control signal; a plurality of counters, which: respectively count the number of times the second preliminary address is input; and A latch control circuit controls the corresponding second preliminary address to be output as the second sampling address when one of the count values ​​of the plurality of counters is equal to or greater than a threshold.

11. The semiconductor device according to claim 8, in, The output control circuit comprises: A sequence control circuit, which: determines the activation sequence of the first output control signal to the third output control signal according to the number of inputs of the sampling signal; a first output latch circuit which: sequentially stores the first sampling addresses to sequentially output the output addresses according to the first output control signal; and a second output latch circuit which: sequentially stores the second sampling addresses to sequentially output the output addresses according to a second output control signal, and Wherein, the shadow latch outputs the third sampling address as the output address according to the third output control signal.

12. A semiconductor device comprising: A sampling control circuit, which: generates a first mode signal and a second mode signal, wherein the first mode signal and the second mode signal randomly pulse with different periods according to a sampling signal; and generates a first sampling control signal to a third sampling control signal based on the first mode signal and the second mode signal; a first storage circuit, which: stores an input address as one of a plurality of first preliminary addresses according to the first sampling control signal to generate a first sampling address; a second storage circuit, which: stores the input address as one of a plurality of second preliminary addresses according to a second sampling control signal to generate a second sampling address; a shadow latch, which: latches the input address as a third sampling address according to the third sampling control signal; and An output control circuit is configured to output an output address by selecting one of the first sampling address to the third sampling address according to the sampling signal.

13. The semiconductor device according to claim 12, wherein: The sampling control circuit comprises: A first interval control circuit, which: randomly selects a coarse interval from a plurality of coarse intervals divided by the first mode signal according to the sampling signal; a second interval control circuit, which: during a selected coarse interval, randomly selects a fine interval from a plurality of fine intervals divided by the second pattern signal according to the sampling signal and the second pattern signal; and A control signal generating circuit that: generates the first sampling control signal and the second sampling control signal having activated intervals separated from each other by a selected fine interval; and generates the third sampling control signal having the activated interval defined by the selected coarse interval.

14. The semiconductor device according to claim 12, wherein: The first storage circuit comprises: a plurality of address latches, which: store the input address as one of the plurality of first preliminary addresses according to the first sampling control signal; a plurality of counters for respectively counting the number of times the first preliminary address is input; and The latch control circuit controls the corresponding first preliminary address to be output as the first sampling address when one of the count values ​​of the counter is equal to or greater than a threshold value.

15. The semiconductor device according to claim 12, wherein: The second storage circuit comprises: a plurality of address latches, which: store the input address as one of the plurality of second preliminary addresses according to the second sampling control signal; a plurality of counters for respectively counting the number of times the second preliminary address is input; and A latch control circuit controls the corresponding second preliminary address to be output as the second sampling address when one of the count values ​​of the counter is equal to or greater than a threshold.

16. The semiconductor device according to claim 12, in, The output control circuit comprises: A sequence control circuit, which: determines the activation sequence of the first output control signal to the third output control signal according to the number of inputs of the sampling signal; a first output latch circuit which: sequentially stores the first sampling addresses to sequentially output the output addresses according to the first output control signal; and a second output latch circuit which: sequentially stores the second sampling addresses to sequentially output the output addresses according to a second output control signal, and Wherein, the shadow latch outputs the third sampling address as the output address according to the third output control signal.

17. A memory device comprising: A refresh control circuit which: selecting a coarse interval from a plurality of coarse intervals according to a first mode signal during a target refresh period, selecting a fine interval from a plurality of fine intervals according to a second mode signal during the selected coarse interval, generating first to third sampling control signals having activated intervals defined by the selected coarse interval and the selected fine interval, and sampling an active address according to the first sampling control signal to the third sampling control signal to output a target address; and A row control circuit is configured to refresh at least one row corresponding to the target address according to a target refresh command defining the target refresh cycle.

18. The memory device according to claim 17, in, Each of the first mode signal and the second mode signal is randomly pulsed during the target refresh period, and The second mode signal pulsates randomly with a shorter period than the first mode signal.

19. The memory device of claim 17, wherein: The refresh control circuit comprises: a first storage circuit that: receives the activation address according to the first sampling control signal and stores it as one of a plurality of first preliminary addresses; and selects one of the first preliminary addresses to output the first sampling address based on the number of times the first preliminary address is input; a second storage circuit which: receives the activation address according to the second sampling control signal and stores it as one of a plurality of second preliminary addresses; and selects one of the second preliminary addresses to output the second sampling address based on the number of times the second preliminary address is input; a shadow latch, which: stores the activation address as the third sampling address according to the third sampling control signal; and An output control circuit is configured to output the target address by scheduling the first sampling address to the third sampling address according to the target refresh command.

20. The memory device of claim 19, wherein: The first storage circuit comprises: a plurality of address latches, which: store the activation address as one of the plurality of first preliminary addresses according to the first sampling control signal; a plurality of counters for respectively counting the number of times the first preliminary address is input; and A latch control circuit controls the corresponding first preliminary address to be output as the first sampling address when one of the count values ​​of the counter is equal to or greater than a threshold.

21. The memory device of claim 19, wherein: The second storage circuit comprises: a plurality of address latches, which: store the activation address as one of the plurality of second preliminary addresses according to a second sampling control signal; a plurality of counters for respectively counting the number of times the second preliminary address is input; and A latch control circuit controls the corresponding second preliminary address to be output as the second sampling address when one of the count values ​​of the counter is equal to or greater than a threshold.

22. The memory device according to claim 19, in, The output control circuit comprises: A sequence control circuit, which: determines the activation sequence of the first output control signal to the third output control signal according to the number of inputs of the target refresh command; a first output latch circuit which: sequentially stores the first sampling addresses to sequentially output the target addresses according to the first output control signal; and a second output latch circuit that: sequentially stores the second sampling addresses to sequentially output the target addresses according to the second output control signal, and The shadow latch outputs the third sampling address as the target address according to the third output control signal.

23. The memory device of claim 19, wherein: The output control circuit comprises: A first sequence control circuit, which: determines an activation sequence of the first output control signal and the third output control signal according to the number of inputs of the target refresh command; a second sequence control circuit, which: generates a second output control signal according to a refresh management command provided from the memory controller; a first output latch circuit which: sequentially stores the first sampling addresses to sequentially output the target addresses according to the first output control signal; and a second output latch circuit, which: sequentially stores the second sampling addresses to sequentially output the target addresses according to the second output control signal, The shadow latch outputs the third sampling address as the target address according to the third output control signal.

24. The memory device of claim 19, wherein: The output control circuit comprises: a first sequence control circuit, which generates a first output control signal according to the target refresh command; a second sequence control circuit, which: determines an activation sequence of the second output control signal and the third output control signal according to the number of inputs of the refresh management command provided from the memory controller; a first output latch circuit which: sequentially stores the first sampling addresses to sequentially output the target addresses according to the first output control signal; and a second output latch circuit, which: sequentially stores the second sampling addresses to sequentially output the target addresses according to the second output control signal, The shadow latch outputs the third sampling address as the target address according to the third output control signal.

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