On-chip random access memory on-line self-checking method

Abstract

The invention provides an on-chip random access memory online self-checking method. The method comprises the following steps of: performing static region division on an address field needing to be self-checked in an RAM (Random Access Memory) into a plurality of different types of independent regions in advance; in the operation process of the controller, the following steps are executed: step S1, carrying out sub-region division on each independent region; s2, randomly sorting all the sub-regions, sequentially taking each sorted sub-region as a to-be-detected sub-region, backing up data of the to-be-detected sub-region, executing RAM self-test, and recording a sub-region self-test result; and S3, when the self-inspection of all the sub-regions is completed, judging whether the self-inspection of the whole region is successful or not according to the self-inspection result of the sub-regions, if so, executing the step S4, clearing the self-inspection state and returning to the step S2, otherwise, executing the step S5, recording the self-inspection result of the whole region and triggering a fault response. The method is used for solving the problems that an existing self-checking method is high in cost and insufficient in self-checking coverage rate, and program running is interfered.

Description

Technical Field

[0001] The present invention relates to the technical field of memory fault diagnosis, and in particular to an on-chip random access memory online self-checking method. Background Art

[0002] Random Access Memory (RAM) is an indispensable memory in embedded control systems. The reliability of RAM directly affects the reliability of the system. In the prior art, hardware circuits are usually used to perform self-tests on RAM, but the cost is high, and RAM cannot be used during the self-test process, affecting the normal operation of the system.

[0003] In order to reduce costs and improve the efficiency of RAM self-test, software can be used to perform online self-test on RAM. However, existing software self-test methods have some shortcomings, such as the inability to cover the global variable area, stack area, cache area, etc., resulting in insufficient self-test coverage; at the same time, the self-test process may interfere with the normal operation of functional programs. Summary of the invention

[0004] The purpose of the present invention is to provide an on-chip random access memory online self-test method to solve the problems of high cost, insufficient self-test coverage, interference with program operation, etc. in the RAM self-test method in the prior art.

[0005] In order to achieve the above objectives, the present invention is implemented by the following technical solutions: An on-chip random access memory online self-test method is provided, which pre-divides the address segment in the RAM where the self-test needs to be performed into a static area to obtain a plurality of independent areas of different types; during the operation of the controller, the following steps are performed: Step S1, dividing each independent area into sub-areas to obtain multiple sub-areas; Step S2, randomly sorting all sub-areas, taking each sorted sub-area as a sub-area to be inspected in turn, backing up the data of the sub-area to be inspected according to the type of the independent area to which the sub-area to be inspected belongs, performing a RAM self-test test, and recording the sub-area self-test result of the sub-area to be inspected; Step S3, when all sub-areas have completed self-inspection, determine whether the self-inspection of the entire area is successful based on the self-inspection results of all sub-areas. If successful, execute step S4; otherwise, execute step S5; Step S4, clear the self-check state and return to execute step S2; Step S5, record the self-test results of the entire area and trigger a fault response.

[0006] Optionally, each independent area is stored in the form of a first structure array, in which the starting address start_address and ending address end_address of the address segment corresponding to the independent area, the area type ram_type and the maximum value max_size of the self-test sub-area address size are defined; the area type ram_type includes a global variable area, a stack area, a cache area, a backup data area, and a backup stack area.

[0007] Optionally, each sub-region is stored in the form of a second structure array, in which the starting address start_address and the ending address end_address of the address segment corresponding to the sub-region, the region type ram_type, the address size size, the self-test result test_result, and the next self-test sub-region number next_section_index are defined; In step S1, each independent area is divided into sub-areas, specifically including: For each independent region, according to the starting address start_address and the ending address end_address of the address segment defined by the first structure array and the maximum value max_size of the self-test sub-region address size, the independent region is divided into a plurality of sub-regions whose maximum value is the maximum value max_size of the self-test sub-region address size; The data index of the second structure array is used as the number of each sub-region.

[0008] Optionally, the address segment size (end_address – start_address) corresponding to the independent area is divided by the maximum value max_size of the self-test sub-area address size. If it is divisible, the sizes of the divided sub-areas are all the maximum value max_size of the self-test sub-area address size. If it is not divisible, the size of the last divided sub-area is the remainder of the address segment size (end_address – start_address) corresponding to the independent area divided by the maximum value max_size of the self-test sub-area address size, and the sizes of the remaining sub-areas are the maximum value max_size of the self-test sub-area address size.

[0009] Optionally, in step S2, all sub-regions are randomly sorted, specifically including: Step S21, taking the number of all sub-areas as the maximum random number max_num; Step S22, generating an integer random number random_num in the range of 0 to max_num-1; Step S23, taking the last sub-region number current_index currently sorted as the starting point, searching for the next sub-region number next_index to be sorted, where next_index is equal to the remainder of (current_index + random_num) divided by max_num. For the first sorting, current_index is set to 0; if the sub-region number corresponding to next_index has been sorted, then the next sub-region number is postponed until an unsorted sub-region number is found, and the found sub-region number is updated to the next_section_index of the second structure array corresponding to the last sub-region currently sorted; for the first sorting, the found sub-region number is recorded as start_index; Step S24, update current_index to next_index; Step S25, update max_num to max_num - 1. If max_num is not 0, return to step S22. If max_num is 0, all sub-regions have been sorted, and update next_section_index of the second structure array corresponding to the last sub-region currently found to the number of sub-regions.

[0010] Optionally, in step S2, each sorted sub-region is sequentially used as a sub-region to be inspected, specifically including: The sub-region number corresponding to start_index is used as the first sub-region to be inspected, and the subsequent sub-region to be inspected is determined according to the next self-inspection sub-region number next_section_index in the first structure array corresponding to the sub-region, and the address segment of the sub-region to be inspected is determined by the starting address start_address and the ending address End_address in the second structure array.

[0011] Optionally, in step S2, backing up data of the sub-region to be inspected according to the type of the independent region to which the sub-region to be inspected belongs specifically includes: If the area type ram_type of the independent area to which the sub-area to be inspected belongs is a global variable area, the data of the sub-area to be inspected is stored in a backup data area; If the area type ram_type of the independent area to which the sub-area to be inspected belongs is a stack area, firstly, the data of the sub-area to be inspected is stored in a backup stack area, and the stack pointer is switched to the backup stack area; If the area type ram_type of the independent area to which the sub-area to be inspected belongs is a cache area, the cache function is first disabled, and the data of the sub-area to be inspected is stored in the backup data area; If the area type ram_type of the independent area to which the sub-area to be inspected belongs is a backup data area or a backup stack area, no backup is required.

[0012] Optionally, in step S2, after performing the RAM self-test, the method further includes: If the area type ram_type of the independent area to which the sub-area to be inspected belongs is a global variable area, restoring the data in the backup data area to the sub-area to be inspected; If the area type ram_type of the independent area to which the sub-area to be inspected belongs is a stack area, restoring the data of the backup stack area to the sub-area to be inspected, and switching the stack pointer to the sub-area to be inspected; If the area type ram_type of the independent area to which the sub-area to be inspected belongs is a cache area, the data in the backup data area is restored to the sub-area to be inspected, and the cache function is re-enabled; If the area type ram_type of the independent area to which the sub-area to be inspected belongs is a backup data area or a backup stack area, no restoration is required.

[0013] Optionally, in step S2, recording the sub-region self-inspection result of the sub-region to be inspected specifically includes: If the RAM self-test of the sub-region to be tested fails, the self-test result test_result of the corresponding second structure array of the sub-region to be tested is updated to 0; If the RAM self-test is successfully executed in the sub-region to be inspected, the self-test result test_result of the corresponding second structure array of the sub-region to be inspected is updated to 1.

[0014] Optionally, in step S3, judging whether the full-area self-test is successful according to the self-test results of all sub-areas specifically includes: Retrieve the self-test results test_result in the second structure array of all sub-areas. If there is a sub-area with test_result equal to 0, the self-test of the entire area is unsuccessful. Otherwise, the self-test of the entire area is successful. In step S4, clearing the self-check state specifically includes: The self-test result test_result in the second structure array of all sub-areas is set to 0, and the next self-test sub-area number next_section_index is set to 0.

[0015] Compared with the prior art, the present invention has the following advantages: 1. The present invention uses software to perform RAM self-check, without relying on hardware circuits, thus reducing costs; 2. The present invention performs RAM self-check during the operation of the controller. During the self-check process, the data in the detected area will be backed up and restored after the detection is completed, covering the global variable area, stack area, cache area, etc., realizing RAM full area self-check and improving the reliability of RAM; 3. The self-checking process of the present invention will not interfere with the normal operation of the program, thus ensuring the normal operation of the system; 4. The detection algorithm of the software self-checking method of the present invention is optimized, which improves the detection speed and accuracy and meets the embedded products with higher performance requirements; 5. The software self-test method of the present invention adaptively selects the test program according to the running state of the RAM to be tested, thereby improving the efficiency and accuracy of the test; 6. The software self-checking method of the present invention uses a random sequence generation method to define the self-checking sequence, thereby improving the fault coverage of the detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for the description. Obviously, the drawings described below are an embodiment of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work: Figure 1 A flowchart of an on-chip random access memory online self-test method provided by an embodiment of the present invention; Figure 2 Schematic diagram of the inspection method for performing destructive testing on sub-areas. DETAILED DESCRIPTION

[0017] The scheme proposed by the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the implementation method of the present invention. In order to make the purposes, features and advantages of the present invention more obvious and easy to understand, please refer to the accompanying drawings. It should be noted that the structures, proportions, sizes, etc. illustrated in the accompanying drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no technical substantive significance. Any structural modification, change in proportional relationship or adjustment of size, without affecting the effects that the present invention can produce and the purposes that can be achieved, should still fall within the scope of the technical content disclosed by the present invention.

[0018] The present invention provides an on-chip random access memory online self-test method, which can be used for a vehicle controller with high functional safety requirements. The method can perform RAM self-test during the operation of the controller, back up the data of the detected area during the self-test and restore it after the test is completed, cover the global variable area, stack area, cache area, etc., and realize RAM full area self-test without interfering with program operation, thereby improving the reliability of RAM and reducing costs.

[0019] like Figure 1 As shown, an on-chip random access memory online self-test method provided by an embodiment of the present invention comprises the following steps: Step S0, pre-dividing the address segment in the RAM where self-test needs to be performed into static areas to obtain a plurality of independent areas of different types.

[0020] In this embodiment, the address segment that needs to perform self-test refers to the area where key safety-related data is stored. In some systems, if it is not an area where key safety-related data is stored, the test may not be performed. Specifically, the address segment that needs to perform self-test in the RAM can be statically divided into areas in combination with the RAM usage scenario. The RAM usage scenarios include the global variable area, stack area, cache area, backup data area, and backup stack area.

[0021] Each independent area is stored in the form of a first structure array, and the starting address start_address and the ending address end_address of the address segment corresponding to the independent area, the area type ram_type, and the maximum value max_size of the self-test sub-area address size are defined in the first structure array. The area type ram_type may include a global variable area, a stack area, a cache area, a backup data area, and a backup stack area. The first structure array can be stored in flash (data is not lost when the flash is powered off), and the configuration information in the first structure array is read when the RAM self-test program is executed.

[0022] The first structure array is defined as follows: typedef struct { uint32 start_address; uint32 end_address; uint8 ram_type; uint32 max_size; }memory_region; Among them, start_address is the starting address of the address segment; end_address is the ending address of the address segment; ram_type is the RAM type; max_size is the maximum value of the self-test sub-area address size.

[0023] Then, during the operation of the controller, the RAM self-test program is run to execute the following steps S1 to S5. The RAM self-test program is integrated into the controller software and is periodically scheduled by the operating system (OS) to achieve continuous detection of the RAM.

[0024] Step S1, dividing each independent area into sub-areas to obtain a plurality of sub-areas.

[0025] In this embodiment, each sub-region is stored in the form of a second structure array, and the starting address start_address and the ending address end_address, the region type ram_type, the address size size, the self-test result test_result, and the next self-test sub-region number next_section_index of the address segment corresponding to the sub-region are defined in the second structure array. Among them, the region type ram_type of the sub-region is inherited from the region type ram_type of the independent region to which it belongs.

[0026] The second structure array is defined as follows: typedef struct { uint32 start_address; uint32 end_address; uint8 ram_type; uint32 size; uint8 test_result; uint8 next_section_index; }memory_region; Among them, size is the address size of the sub-area, test_result is the self-test result of the sub-area, and next_section_index indicates the number of the next self-test sub-area.

[0027] In step S1, each independent area is divided into sub-areas, specifically including: For each independent area, according to the starting address start_address and the ending address end_address of the address segment defined by its first structure array and the maximum value max_size of the self-test sub-area address size, the independent area is divided into a number of sub-areas with a maximum value max_size of the self-test sub-area address size; and the data index of the second structure array is used as the number of each sub-area.

[0028] It can be understood that, for each independent area, the address segment size (end_address - start_address) corresponding to the independent area is divided by the maximum value max_size of the self-test sub-area address size. If it is divisible, the sizes of the divided sub-areas are all the maximum value max_size of the self-test sub-area address size. If it is not divisible, the size of the last divided sub-area is the remainder of the address segment size (end_address -start_address) corresponding to the independent area divided by the maximum value max_size of the self-test sub-area address size, and the sizes of the remaining sub-areas are the maximum value max_size of the self-test sub-area address size.

[0029] Thus, all independent regions are traversed, each independent region is divided into a plurality of sub-regions, and a corresponding second structure array is generated for each sub-region. At the same time, each sub-region is numbered, and for ease of processing, the data index of the second structure array can be used as the number of the sub-region. In this embodiment, each independent region is further subdivided into sub-regions, and only a part of the region is detected each time, thereby improving the detection speed.

[0030] Step S2, randomly sort all sub-areas, and take each sorted sub-area as a sub-area to be inspected in turn. According to the type of independent area to which the sub-area to be inspected belongs, back up the data of the sub-area to be inspected, perform a RAM self-test test, and record the sub-area self-test result of the sub-area to be inspected.

[0031] First, all sub-regions are randomly sorted so that all sub-regions can be detected in sequence according to the sorting. In one implementation, all sub-regions are randomly sorted, specifically including the following steps S21 to S25: Step S21, taking the number of all sub-areas as the maximum random number max_num; Step S22, generating an integer random number random_num in the range of 0 to max_num-1; Step S23, taking the last sub-region number current_index currently sorted as the starting point, searching for the next sub-region number next_index to be sorted, where next_index is equal to the remainder of (current_index + random_num) divided by max_num. For the first sorting, current_index is set to 0; if the sub-region number corresponding to next_index has been sorted, then the next sub-region number is postponed until an unsorted sub-region number is found, and the found sub-region number is updated to the next_section_index of the second structure array corresponding to the last sub-region currently sorted; for the first sorting, the found sub-region number is recorded as start_index; Step S24, update current_index to next_index; Step S25, update max_num to max_num - 1. If max_num is not 0, return to step S22. If max_num is 0, all sub-regions have been sorted, and update next_section_index of the second structure array corresponding to the last sub-region currently found to the number of sub-regions.

[0032] The following example illustrates the random sorting method. Assuming that the number of all sub-regions is 5, the maximum value of the random number max_num is 5. Step S22 generates an integer random number random_num in the range of 0-4, for example, 2. Since it is the first sorting, current_index is 0, then next_index is calculated to be 2, and the sub-region numbered 2 is used as the first sub-region to be sorted, and the sub-region numbered 2 is recorded as start_index. Then, update current_index to 2, update max_num to 4 (not 0), and return to step S22, generate an integer random number random_num in the range of 0-3, for example, 1, then the value of next_index calculated in step S23 is 3, so the sub-region numbered 3 is used as the second sub-region to be sorted, thereby updating the next_section_index of the second structure array corresponding to the first sorted sub-region (numbered 2) to 3 (indicating that after the detection of the sub-region numbered 2 is completed, it points to the detection of the sub-region numbered 3). Then, update current_index to 3, update max_num to 3 (not 0), and return to step S22, generate an integer random number random_num in the range of 0-2, for example, it is 1, then the value of next_index calculated in step S23 is 1, and the sub-region numbered 1 is used as the third sub-region to be sorted, thereby updating the next_section_index of the second structure array corresponding to the second sorted sub-region (numbered 3) to 1 (indicating that after the detection of the sub-region numbered 3 is completed, it points to the detection of the sub-region numbered 1). Then, update current_index to 1, update max_num to 2 (not 0), and return to step S22, generate an integer random number random_num in the range of 0-1. For example, if it is 0, the value of next_index calculated in step S23 is 1, then defer to the next unsorted sub-region number 4, and use the sub-region numbered 4 as the fourth sorted sub-region, thereby updating the next_section_index of the second structure array corresponding to the third sorted sub-region (numbered 1) to 4 (indicating that after the detection of the sub-region numbered 1 is completed, it points to the detection of the sub-region numbered 4).Then, update current_index to 4, update max_num to 1 (not 0), and return to step S22, generate an integer random number random_num in the range of 0-0, that is, 0, then the value of next_index calculated in step S23 is still 0, then postpone to the next unsorted sub-region number 5, and use the sub-region numbered 5 as the fifth sub-region to be sorted, thereby updating the next_section_index of the second structure array corresponding to the fourth sorted sub-region (numbered 4) to 5 (indicating that after the sub-region numbered 4 is detected, it points to the sub-region numbered 5 for detection). Then, update current_index to 5, update max_num to 0, then all sub-regions have been sorted at this time, therefore, update the next_section_index of the second structure array corresponding to the last sorted sub-region (numbered 5, that is, the last sub-region currently found) to the number of sub-regions 5, indicating that all sub-regions have been sorted.

[0033] Further, each of the sorted sub-regions is sequentially used as a sub-region to be inspected, specifically including: using the sub-region number corresponding to start_index as the first sub-region to be inspected, determining the subsequent sub-region to be inspected according to the next self-inspection sub-region number next_section_index in the first structure array corresponding to the sub-region, and determining the address segment of the sub-region to be inspected by the starting address start_address and the ending address End_address in the second structure array. In this embodiment, since the number of the first self-inspected sub-region is uncertain each time, it is necessary to record the number of the first sub-region that needs to perform self-inspection through the configuration parameter start_index, and then, the second and subsequent sub-region self-inspection order is obtained through the next_section_index in the second structure array of each sub-region.

[0034] The random ordering method described above can make the order of each self-test different, with greater randomness, thereby improving the fault coverage of the detection. In other embodiments, other methods can also be used for random ordering.

[0035] In order to implement RAM self-test during the operation of the controller, the data of the detected area is backed up during the self-test and restored after the test is completed, covering the global variable area, stack area, cache area, etc., and implementing RAM full area self-test without interfering with program operation, thereby improving RAM reliability and reducing costs. Therefore, before testing the sub-area to be tested, it is necessary to back up the data of the sub-area to be tested according to the type of independent area to which the sub-area to be tested belongs, specifically including: If the area type ram_type of the independent area to which the sub-area to be inspected belongs is a global variable area, the data of the sub-area to be inspected is stored in a backup data area; If the area type ram_type of the independent area to which the sub-area to be inspected belongs is a stack area, firstly, the data of the sub-area to be inspected is stored in a backup stack area, and the stack pointer is switched to the backup stack area; If the area type ram_type of the independent area to which the sub-area to be inspected belongs is a cache area, the cache function is first disabled, and the data of the sub-area to be inspected is stored in the backup data area; If the area type ram_type of the independent area to which the sub-area to be inspected belongs is a backup data area or a backup stack area, no backup is required.

[0036] Then perform destructive testing on the sub-area to be inspected. For specific testing methods, see Figure 2 The method shown. Figure 2 The destructive test is performed using the IFA9 algorithm. In practical applications, other algorithms may be used for destructive testing. This embodiment can cover more RAM faults by using a destructive test self-checking algorithm, thereby improving the detection accuracy.

[0037] After the self-test of each sub-area to be inspected is completed, the sub-area self-test result of the sub-area to be inspected is recorded, specifically including: if the sub-area to be inspected fails to perform the RAM self-test test (the RAM self-test program can return an error address), then the self-test result test_result of the corresponding second structure array of the sub-area to be inspected is updated to 0; if the sub-area to be inspected succeeds in performing the RAM self-test test, then the self-test result test_result of the corresponding second structure array of the sub-area to be inspected is updated to 1.

[0038] Accordingly, after the RAM self-test is completed, the data in the sub-area to be tested is restored, which specifically includes: If the area type ram_type of the independent area to which the sub-area to be inspected belongs is a global variable area, restoring the data in the backup data area to the sub-area to be inspected; If the area type ram_type of the independent area to which the sub-area to be inspected belongs is a stack area, restoring the data of the backup stack area to the sub-area to be inspected, and switching the stack pointer to the sub-area to be inspected; If the area type ram_type of the independent area to which the sub-area to be inspected belongs is a cache area, the data in the backup data area is restored to the sub-area to be inspected, and the cache function is re-enabled; If the area type ram_type of the independent area to which the sub-area to be inspected belongs is a backup data area or a backup stack area, no restoration is required.

[0039] Therefore, this embodiment ensures that the data is not destroyed after the test is completed by backing up, destructive testing, and restoring data, and adaptively selects the detection program according to the operating status of the sub-area to be tested, thereby improving the efficiency and accuracy of the detection.

[0040] According to the above method, all sub-areas are self-checked in turn, and the method for judging whether all sub-areas have completed self-checking is as follows: if the next_section_index in the second structure array corresponding to the current sub-area to be checked is the number of sub-areas, it means that the current sub-area to be checked is the last sub-area, and it is judged that all sub-areas have completed self-checking; if not, the sub-area corresponding to next_section_index is numbered as the next sub-area to be checked, and the self-checking of the sub-area to be checked continues.

[0041] Step S3, when all sub-areas have completed self-inspection, determine whether the full-area self-inspection is successful based on the self-inspection results of all sub-areas. If successful, execute step S4; otherwise, execute step S5.

[0042] Step S4, clear the self-check state and return to execute step S2.

[0043] Step S5, record the self-test results of the entire area and trigger a fault response.

[0044] In step S3, judging whether the self-test of the entire region is successful based on the self-test results of all sub-regions specifically includes: retrieving the self-test results test_result in the second structure array of all sub-regions, if there is a sub-region with test_result being 0, the self-test of the entire region is unsuccessful, if not, the self-test of the entire region is successful. Therefore, in step S4, clearing the self-test state specifically includes: setting the self-test results test_result in the second structure array of all sub-regions to 0, and setting the next self-test sub-region number next_section_index to 0.

[0045] In step S5, the self-test result of the entire area is recorded, and the recording method may be to store the error sub-area number in FLASH or EEPROM; and a fault response is triggered, and the fault response may be: resetting the controller or reporting the fault through the communication bus.

[0046] Based on the same inventive concept, this embodiment further provides an electronic device, including a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the method described above is implemented.

[0047] Based on the same inventive concept, this embodiment further provides a readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the method described above is implemented.

[0048] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the embodiments of the electronic device and the readable storage medium, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0049] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0050] Although the content of the present invention has been described in detail through the above preferred embodiments, it should be appreciated that the above description should not be considered as a limitation of the present invention. After reading the above content, it will be apparent to those skilled in the art that various modifications and substitutions of the present invention will occur. Therefore, the protection scope of the present invention should be limited by the appended claims.

Claims

1. An on-chip random access memory online self-test method, characterized in that: The address segment in the RAM that needs to perform self-test is divided into static areas in advance to obtain multiple independent areas of different types; during the operation of the controller, the following steps are performed: Step S1, dividing each independent area into sub-areas to obtain multiple sub-areas; Step S2, randomly sorting all sub-areas, taking each sorted sub-area as a sub-area to be inspected in turn, backing up the data of the sub-area to be inspected according to the type of the independent area to which the sub-area to be inspected belongs, performing a RAM self-test test, and recording the sub-area self-test result of the sub-area to be inspected; Step S3, when all sub-areas have completed self-inspection, determine whether the self-inspection of the entire area is successful based on the self-inspection results of all sub-areas. If successful, execute step S4; otherwise, execute step S5; Step S4, clear the self-check state and return to execute step S2; Step S5, record the self-test results of the entire area and trigger a fault response.

2. The on-chip random access memory online self-test method according to claim 1, characterized in that: Each independent area is stored in the form of a first structure array, and the starting address start_address and the ending address end_address of the address segment corresponding to the independent area, the area type ram_type and the maximum value max_size of the self-test sub-area address size are defined in the first structure array; the area type ram_type includes a global variable area, a stack area, a cache area, a backup data area, and a backup stack area.

3. The on-chip random access memory online self-test method according to claim 2, characterized in that: Each sub-region is stored in the form of a second structure array, and the starting address start_address and the ending address end_address, the region type ram_type, the address size size, the self-test result test_result, and the next self-test sub-region number next_section_index of the address segment corresponding to the sub-region are defined in the second structure array; In step S1, each independent area is divided into sub-areas, specifically including: For each independent region, according to the starting address start_address and the ending address end_address of the address segment defined by the first structure array and the maximum value max_size of the self-test sub-region address size, the independent region is divided into a plurality of sub-regions whose maximum value is the maximum value max_size of the self-test sub-region address size; The data index of the second structure array is used as the number of each sub-region.

4. The on-chip random access memory online self-test method according to claim 3, characterized in that: Divide the address segment size (end_address – start_address) corresponding to the independent area by the maximum value max_size of the self-test sub-area address size. If it is evenly divisible, the sizes of the divided sub-areas are all the maximum value max_size of the self-test sub-area address size. If it is not evenly divisible, the size of the last divided sub-area is the remainder of the address segment size (end_address – start_address) corresponding to the independent area divided by the maximum value max_size of the self-test sub-area address size, and the sizes of the remaining sub-areas are the maximum value max_size of the self-test sub-area address size.

5. The on-chip random access memory online self-test method as claimed in claim 3, characterized in that: In step S2, all sub-regions are randomly sorted, specifically including: Step S21, taking the number of all sub-areas as the maximum random number max_num; Step S22, generating an integer random number random_num in the range of 0 to max_num-1; Step S23, taking the last sub-region number current_index currently sorted as the starting point, searching for the next sub-region number next_index to be sorted, where next_index is equal to the remainder of (current_index + random_num) divided by max_num. For the first sorting, current_index is set to 0; if the sub-region number corresponding to next_index has been sorted, then the next sub-region number is postponed until an unsorted sub-region number is found, and the found sub-region number is updated to the next_section_index of the second structure array corresponding to the last sub-region currently sorted; for the first sorting, the found sub-region number is recorded as start_index; Step S24, update current_index to next_index; Step S25, update max_num to max_num - 1. If max_num is not 0, return to step S22. If max_num is 0, all sub-regions have been sorted, and update next_section_index of the second structure array corresponding to the last sub-region currently found to the number of sub-regions.

6. The on-chip random access memory online self-test method according to claim 5, characterized in that: In step S2, each sorted sub-region is sequentially used as a sub-region to be inspected, specifically including: The sub-region number corresponding to start_index is used as the first sub-region to be inspected, and the subsequent sub-region to be inspected is determined according to the next self-inspection sub-region number next_section_index in the first structure array corresponding to the sub-region, and the address segment of the sub-region to be inspected is determined by the starting address start_address and the ending address End_address in the second structure array.

7. The on-chip random access memory online self-test method according to claim 3, characterized in that: In step S2, according to the type of the independent area to which the sub-area to be inspected belongs, backing up the data of the sub-area to be inspected specifically includes: If the area type ram_type of the independent area to which the sub-area to be inspected belongs is a global variable area, the data of the sub-area to be inspected is stored in a backup data area; If the area type ram_type of the independent area to which the sub-area to be inspected belongs is a stack area, firstly, the data of the sub-area to be inspected is stored in a backup stack area, and the stack pointer is switched to the backup stack area; If the area type ram_type of the independent area to which the sub-area to be inspected belongs is a cache area, the cache function is first disabled, and the data of the sub-area to be inspected is stored in the backup data area; If the area type ram_type of the independent area to which the sub-area to be inspected belongs is a backup data area or a backup stack area, no backup is required.

8. The on-chip random access memory online self-test method according to claim 7, characterized in that: In step S2, after performing the RAM self-test, the following steps are also included: If the area type ram_type of the independent area to which the sub-area to be inspected belongs is a global variable area, restoring the data in the backup data area to the sub-area to be inspected; If the area type ram_type of the independent area to which the sub-area to be inspected belongs is a stack area, restoring the data of the backup stack area to the sub-area to be inspected, and switching the stack pointer to the sub-area to be inspected; If the area type ram_type of the independent area to which the sub-area to be inspected belongs is a cache area, the data in the backup data area is restored to the sub-area to be inspected, and the cache function is re-enabled; If the area type ram_type of the independent area to which the sub-area to be inspected belongs is a backup data area or a backup stack area, no restoration is required.

9. The on-chip random access memory online self-test method according to claim 3, characterized in that: In step S2, recording the sub-region self-inspection result of the sub-region to be inspected specifically includes: If the RAM self-test of the sub-region to be tested fails, the self-test result test_result of the corresponding second structure array of the sub-region to be tested is updated to 0; If the RAM self-test is successfully executed in the sub-region to be inspected, the self-test result test_result of the corresponding second structure array of the sub-region to be inspected is updated to 1.

10. The on-chip random access memory online self-test method according to claim 9, characterized in that: In step S3, judging whether the full-area self-test is successful based on the self-test results of all sub-areas specifically includes: Retrieve the self-test results test_result in the second structure array of all sub-areas. If there is a sub-area with test_result equal to 0, the self-test of the entire area is unsuccessful. Otherwise, the self-test of the entire area is successful. In step S4, clearing the self-check state specifically includes: The self-test result test_result in the second structure array of all sub-areas is set to 0, and the next self-test sub-area number next_section_index is set to 0.

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