Preparation method of semiconductor structure and semiconductor structure

Abstract

The invention discloses a preparation method of a semiconductor structure and the semiconductor structure, belongs to the technical field of semiconductor processing, and particularly relates to pixel manufacturing of a CMOS image sensor. The problem that in an existing CIS technology, due to the fact that thick photoresist spin coating is adopted, an isolated photoresist pattern with the high depth-to-width ratio (the depth-to-width ratio gt: 3: 1) is likely to collapse and laterally move under the action of centrifugal force in the spin-drying process is solved. The processing method of the isolated photoresist patterns in the preparation method of the semiconductor structure comprises the following steps: exposing and developing a photoresist coating to form a plurality of initial isolated photoresist patterns; the periphery of each initial isolated photoresist pattern is an exposure position, and photoresist with a given thickness at the bottom of the exposure position is reserved, so that the bottoms of the plurality of initial isolated photoresist patterns are connected into a whole. The preparation method of the semiconductor structure is suitable for preparing the CMOS image sensor.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor processing technology, and in particular to the processing technology of CMOS image sensors. Background Art

[0002] With the widespread application of CMOS image sensors in consumer electronics and the rapid update and iteration of consumer electronics, people have higher and higher requirements for the performance of CMOS image sensors in terms of pixel size and full well capacity (FWC). Specifically, professional photography and video need to take into account both high resolution and high dynamic range (HDR), requiring that a single pixel can still improve the charge storage capacity through a deep photodiode or back-illuminated (BSI) structure when the size is reduced. For example, autonomous driving LiDAR and machine vision require sensors to work under extreme lighting conditions (such as strong backlight and nighttime), and ultra-high FWC is required to avoid saturation, while relying on small pixels to achieve high spatial resolution (such as identifying distant objects).

[0003] As pixel size continues to shrink, adjacent pixels are required to use deeper P-wells to achieve electrical isolation, which will inevitably lead to the use of thicker photoresist (photoresist coating) combined with high-energy ion implantation in the pixel manufacturing process of CMOS image sensors to produce deep P-wells. Specifically: Smaller pixel sizes require deeper P-wells: When pixel sizes shrink to sub-micron levels (such as below 0.8μm), the depletion regions of adjacent pixels may overlap, resulting in leakage current and charge crosstalk. Deep P-wells expand the depletion region width and junction depth to form a thicker space charge region, inhibiting carriers (such as electrons) from diffusing or drifting across the isolation region.

[0004] A deeper P-well requires a thicker photoresist: The range of high-energy ions (such as boron ions at 500 keV) in the photoresist can reach several microns. If the photoresist thickness is not enough, the ions will penetrate the photoresist layer, resulting in unintended doping of non-implanted areas (such as metal wiring layers or gates), causing device failure. Calculation of photoresist thickness: According to the ion stopping power formula, the photoresist must at least cover the maximum range of the ions. For example, for 1 MeV boron ion implantation, a photoresist thickness of >3μm is required.

[0005] In the existing CIS (CMOS Image Sensor, complementary metal oxide semiconductor image sensor) process, in order to avoid electrical crosstalk between PDs (Photo diodes, photodiodes), shallow trench isolation STI and P+ type side isolation are usually used between PDs. As the pixel size continues to shrink, in order to obtain the required full well capacity, the vertical depth of the PD continues to increase, and the resulting electrical isolation also requires the P+ type side isolation to be deeper and deeper. P+ ion implantation is generally deeper and requires a thick photoresist (i.e., thick photoresist spin coating). At present, with the reduction of pixel size and the increase of the vertical depth of the photodiode (PD), the process needs to use thick photoresist to form an isolated photoresist pattern with a high aspect ratio (>3:1) to achieve deep P+ isolation, specifically: Ion implantation depth matching: Deep P+ isolation requires high-energy ion implantation (such as boron ions, energy > 500 keV) to form a deep junction (> 2μm), and the photoresist thickness must at least cover the maximum range of the ions (according to the stopping power formula). For example, the photoresist thickness must be ≥ 3μm to block 1 MeV boron ions from penetrating.

[0006] Lateral size constraints: When the pixel size is reduced to sub-micron level (such as 0.8μm), the lateral width of the isolation area needs to be ≤0.3μm (to avoid occupying too much PD area), resulting in an aspect ratio of >3:1 (3μm thick photoresist / 0.3μm wide pattern).

[0007] Resolution and lithography capabilities: The diffraction effect of deep ultraviolet (DUV) lithography limits the minimum line width. Thick photoresist requires optical proximity correction (OPC) or multiple exposures to achieve narrow isolation areas. High aspect ratio is the inevitable result of a compromise between resolution and thickness.

[0008] Because the thickness of the photoresist is too thick, the isolated photoresist pattern with a high aspect ratio (aspect ratio>3:1) formed by directly exposing the photoresist to the bottom and developing it is prone to collapse and shift sideways during the drying process (i.e., drying the developer). Specifically: Centrifugal force: The centrifugal force F = m·ω²·r (m is the mass of the photoresist, ω is the angular velocity, and r is the rotation radius) generated by high-speed rotation (usually 3000-6000 rpm) during the drying process. The isolated figure is subjected to large force on the top and small supporting area at the bottom, resulting in a bending moment exceeding the bending strength of the photoresist.

[0009] Structural fragility: Graphics with high aspect ratios (e.g., 3μm high / 0.3μm wide) have extremely high slenderness ratios, similar to slender columns, and are prone to Euler buckling.

[0010] Developer residue and surface tension: The developer residue in the gap between patterns forms capillary force, and the evaporation of the liquid during the drying process generates shrinkage stress, which aggravates the lateral displacement of the pattern. At the same time, the roughness of the photoresist sidewall (LWR) and uneven development (such as insufficient bottom development) will reduce the structural strength.

[0011] The collapse and lateral shift of isolated photoresist patterns will affect the subsequent ion implantation dose and thus the performance of CIS. Specifically: Ion implantation dose offset: Collapse causes the photoresist mask pattern to deform, and the effective blocking area changes. For example, the lateral shift of the photoresist can expand the actual implantation window, resulting in excessive lateral diffusion of the P+ region and increased leakage current.

[0012] Implantation angle deviation: Collapsed patterns may cause the ion beam incident angle to deviate from the designed value, resulting in insufficient junction depth or abnormal doping distribution.

[0013] Electrical isolation failure: Photoresist collapse reduces the distance between the P+ isolation region and the PD (e.g., from 0.3μm to 0.2μm), increasing the risk of depletion region overlap, leading to charge crosstalk and, in turn, a decrease in the signal-to-noise ratio. Insufficient deep well isolation depth (due to uncontrolled injection dose) can lead to an increase in dark current, which seriously affects low-light performance.

[0014] Full Well Capacity (FWC) and Dynamic Range (DR) Degradation: Isolation failure leads to reduced PD charge storage capacity, resulting in a decrease in dynamic range.

[0015] In addition, due to the excessive thickness of the photoresist and the large aspect ratio, the exposure levels of the upper and lower surfaces are different, resulting in poor verticality of the side walls of the isolated photoresist pattern, and even causing the bottom of the isolated photoresist pattern to not be exposed and cause a bridging phenomenon (that is, the bottom is not completely disconnected and there is still residual photoresist connected). Summary of the invention

[0016] The present invention provides a method for preparing a semiconductor structure, which solves the problem that isolated photoresist patterns with high aspect ratio (aspect ratio>3:1) caused by spin coating of thick photoresist in the existing CIS process are prone to collapse and shift sideways due to centrifugal force during the spin drying process.

[0017] The method for preparing the semiconductor structure of the present invention has the following technical solution: The preparation method includes a processing step of an isolated photoresist pattern, and the processing step of the isolated photoresist pattern includes: On the surface of the semiconductor wafer, a thick photoresist is spin-coated to form a photoresist coating; The photoresist coating is exposed and developed to form a plurality of initial isolated photoresist patterns; the periphery of each initial isolated photoresist pattern is an exposure position, and during the exposure, a given thickness of photoresist is ensured to be retained at the bottom of the exposure position, so that the bottoms of the plurality of initial isolated photoresist patterns are connected as one; The ashing process is used to remove the photoresist of a given thickness at the bottom of the exposure position, exposing the surface of the semiconductor wafer below, and obtaining multiple isolated photoresist patterns that are processed and not connected at the bottom.

[0018] Optionally, a feature size of the initial isolated photoresist pattern reserves redundancy.

[0019] Optionally, the given thickness is 500 to 2000 angstroms.

[0020] Optionally, the thickness of the photoresist coating is 3.0 to 5.0 microns.

[0021] Optionally, the feature size of the processed isolated photoresist pattern is less than 1.5 microns.

[0022] Optionally, the aspect ratio of the processed isolated photoresist pattern is greater than 3:1.

[0023] Optionally, after the ashing process, the method further includes an ion implantation step.

[0024] Optionally, the photoresist coating is a positive photoresist layer; The surroundings of each initial isolated photoresist pattern are exposure positions, and a photoresist of a given thickness is retained at the bottom of the exposure position, so that the bottoms of the multiple initial isolated photoresist patterns are connected as one. The steps are: Control the exposure dose and focus so that the photoresist of a given thickness at the bottom of the exposure position is not exposed.

[0025] Optionally, the photoresist with a given thickness at the bottom of the exposure position is a negative photoresist layer; and the photoresist coating above the negative photoresist layer is a positive photoresist layer; The surroundings of each initial isolated photoresist pattern are exposure positions, and a photoresist of a given thickness is retained at the bottom of the exposure position, so that the bottoms of the multiple initial isolated photoresist patterns are connected as one. The steps are: The exposure dose and focal length are controlled to expose the positive photoresist layer and the negative photoresist layer at the exposure position.

[0026] The present invention also proposes a semiconductor structure, and its technical solution is as follows: A semiconductor structure is prepared by using any one of the above-mentioned methods for preparing a semiconductor structure.

[0027] The present invention has the following beneficial effects: The method for preparing a semiconductor structure described in the present invention, in the processing steps of isolated photoresist patterns, during exposure and development, by retaining a given thickness of photoresist at the bottom of the exposure position, the bottom of the isolated photoresist pattern remains connected during the development process, thereby ensuring the stability of each isolated photoresist pattern, thereby improving the problem that the isolated photoresist pattern formed by directly exposing the photoresist to the bottom and developing in the traditional method is prone to collapse during the drying process due to the action of centrifugal force.

[0028] The method for preparing the semiconductor structure of the present invention is suitable for preparing a CMOS image sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0030] Figure 1 Schematic diagram of the change of photoresist coating thickness and P-well depth in CIS process before and after pixel size reduction; in the figure, the left side is before pixel size reduction, and the right side is after pixel size reduction. By comparison, it can be determined that the photoresist coating thickness and P-well depth are significantly increased; Figure 2 This is a top view of an isolated photoresist pattern before it collapses and moves sideways; in the figure, all isolated photoresist patterns form a matrix and are arranged at equal intervals; Figure 3 It is a top view of an isolated light-resistance pattern when it collapses and moves sideways; in the figure, two isolated light-resistance patterns collapse and move sideways, and their tops have overlapped with other adjacent isolated light-resistance patterns; Figure 4 A cross-sectional schematic diagram of the bridging phenomenon at the bottom of an isolated photoresist pattern; in the figure, several adjacent isolated photoresist patterns have obvious bridging phenomena at the bottom, see the red circle position in the figure; Figure 5 is a schematic flow chart of a method for preparing a semiconductor structure in one embodiment; wherein, Figure 5 (a) is a schematic diagram of the semiconductor structure after thick photoresist spin coating, from bottom to top are P-sub layer, EPI layer, sacrificial oxide layer, photoresist layer PR; Figure 5 (b) is a schematic diagram of PR exposure. The middle position between the two black lines in the upper part of the figure is the exposure position, the dark area below this position is the exposure area, and a given thickness area is reserved at the bottom below this position and is not exposed. Figure 5(c) is a state diagram after development, where the bottoms of adjacent isolated photoresist patterns are connected by the photoresist of a given thickness, making them relatively stable. Figure 5 (d) shows the state after the photoresist of a given thickness at the bottom is removed by an ashing process; Figure 5 (e) in it is ion implantation; Figure 6 is a schematic flow chart of a method for preparing a semiconductor structure in one embodiment; wherein, Figure 6 (a) is a schematic diagram of a semiconductor structure after a thick photoresist is spin-coated once, in which the P-sub layer, the EPI layer, the sacrificial oxide layer, and the negative photoresist layer are arranged from bottom to top, and the thickness of the negative photoresist layer is a given thickness; Figure 6 (b) is a schematic diagram of the semiconductor structure after secondary thick photoresist spin coating, where a positive photoresist layer is added on top of the negative photoresist layer; Figure 6 (c) is a schematic diagram of exposure. The exposure depth in this step does not need to be strictly controlled, and the positive photoresist layer and the negative photoresist layer at the exposure position can be exposed at the same time; Figure 6 (d) is a state diagram after development, in which the negative photoresist at the bottom between adjacent isolated photoresist patterns is still retained, achieving the effect of connecting the isolated photoresist patterns; Figure 6 (e) is the state after the photoresist of a given thickness at the bottom is removed by an ashing process; Figure 6 (f) in the figure is ion implantation; Figure 7 A schematic diagram of the position of the first focal depth plane when the photoresist coating is exposed for the first time; Figure 8 A schematic diagram of the position of the second focal depth plane when the photoresist coating is exposed for the second time.

[0031] Reference numerals: 2, photoresist coating (photoresist PR); 201, negative photoresist layer; 202, positive photoresist layer; 3, sacrificial oxide layer; 4, PW, i.e. P well, is a doped area with a certain depth made in the surface layer of the substrate; 5, EPI, i.e. epitaxial layer, the part grown and deposited on the wafer substrate, with a thickness of generally 5.4 microns; 6, P-sub, i.e. p-type substrate, silicon wafer used for epitaxy (Epi), with a thickness of generally 770 microns; d1, the thickness of the photoresist coating, is 3.0 to 5.0 microns; d2, given thickness, is 500 to 2000A; d3 = 2.0 microns; 10, exposure; 11, ashing process; 13, IMP, i.e. ion implantation; 21, mask; 22, lens; 25a, first focal depth plane (fous1); 25b, second focal depth plane (fous2). DETAILED DESCRIPTION

[0032] In order to make the technical solutions and advantages of the present invention more clearly described, the specific implementation methods of the present invention will be further described in detail and completely in conjunction with the accompanying drawings. The various implementation methods described below are only part of the preferred solutions of the present invention, rather than all implementation methods; the various implementation methods described below are intended to explain the present invention and cannot be understood as limitations on the present invention; the reasonable combination of technical features defined in the various implementation methods of the present invention, and all other implementation methods obtained by ordinary technicians in the field without creative work based on the implementation methods of the present invention, are within the scope of protection of the present invention.

[0033] In one embodiment, a method for preparing a semiconductor structure is provided, the method comprising a processing step of an isolated photoresist pattern, the processing step being specifically as follows: On the surface of the semiconductor wafer, a thick photoresist is spin-coated to form a photoresist coating; The photoresist coating is exposed and developed to form a plurality of initial isolated photoresist patterns; the periphery of each initial isolated photoresist pattern is an exposure position, and during the exposure, the exposure position is ensured to retain a given thickness of photoresist at the bottom, so that the bottoms of the plurality of initial isolated photoresist patterns are connected as one; The ashing process is used to remove the photoresist of a given thickness at the bottom of the exposure position, exposing the surface of the semiconductor wafer below, and obtaining multiple isolated photoresist patterns that are processed and not connected at the bottom.

[0034] In this embodiment, a semiconductor wafer refers to a silicon (Si) chip used for manufacturing silicon semiconductor integrated circuits and is a carrier used for producing integrated circuits.

[0035] In this embodiment, an isolation pattern refers to a microstructure formed on a photoresist coating layer by a photolithography process and used to isolate different functional areas.

[0036] In this embodiment, thick photoresist spin coating refers to uniformly coating the photoresist on the semiconductor wafer by spin coating to form a photoresist layer of a certain thickness. The "thick photoresist" here means that the thickness of the photoresist layer is relatively thick. The preparation method described in this embodiment is suitable for the case where the thick photoresist is greater than 3.0 microns, and the optimal thick photoresist is between 3.0 microns and 5.0 microns. Multiple coatings can achieve uniformity of thick glue without sacrificing resolution.

[0037] In this embodiment, exposure: a wafer coated with a photoresist coating is exposed using a mask (or photomask); during the exposure process, light is irradiated onto the photoresist coating through an exposure position on the mask (i.e., the transparent part of the mask / photomask), and the photoresist is processed into a pattern (i.e., an initial isolated photoresist pattern).

[0038] During the exposure process, the quality and effect of exposure can be controlled by controlling the exposure dose and focal length. For example, for a photoresist coating with a thickness of 3.5 microns, compared with the conventional exposure process, by shifting the exposure focal length up by 0.4 microns, it is ensured that a given thickness (500 to 2000A) of photoresist is retained at the bottom of the exposure position; in practice, the specific parameters of the focus shift may vary depending on the manufacturer of the lithography machine.

[0039] In this embodiment, the development includes the steps of pre-development preparation, development process and post-development processing: Preparation before development: Select a developer according to the type of photoresist. In this embodiment, a weak alkaline solution (such as tetramethylammonium hydroxide [TMAH]) is selected as the developer to dissolve the photoresist.

[0040] Development process: In this embodiment, a rotary development method is used to achieve development. Rotary development refers to using a dedicated coating developer to rotate the semiconductor structure and spray the developer to achieve automatic control of the development process.

[0041] Post-development treatment: rinse the developer with deionized water and spin dry to dilute the developer and prevent excessive development. During the spin dry, the moisture on the semiconductor structure is removed by spinning or centrifugation.

[0042] In the conventional method, the isolated photoresist pattern is formed by directly exposing the photoresist to the bottom and developing it. During the drying process, the isolated photoresist pattern is prone to collapse due to the centrifugal force. In the present embodiment, the photoresist of a given thickness is retained at the bottom of the exposure position so that the bottoms of the isolated photoresist pattern remain interconnected, thereby improving the stability of the isolated photoresist pattern and improving the phenomenon that the isolated photoresist pattern is prone to collapse and shift sideways due to the centrifugal force during the drying process.

[0043] In addition, in one embodiment, a feature size of the initial isolated photoresist pattern reserves redundancy.

[0044] In this embodiment, the feature size of the initial isolated photoresist pattern is reserved as redundancy, which means that the feature size of the initial isolated photoresist pattern is larger than the feature size of the processed isolated photoresist pattern.

[0045] It should be noted that the characteristic size of the isolated photoresist pattern, usually also called line width or critical dimension (CD), can reflect the pattern processing accuracy of integrated circuit photomask manufacturing and photolithography process. The smaller the characteristic size, the higher the resolution and the more difficult the process. There are many factors to consider in its processing, such as ensuring the ion implantation amount, ion implantation process, electrical isolation performance, and the feasibility of existing photolithography process and equipment. The preparation method described in this embodiment is suitable for processing semiconductor structures with a characteristic size of less than 1.5 microns.

[0046] It should be noted that the use of thick photoresist spin coating will also bring the following problems: Due to the thickness of the photoresist and the large aspect ratio, the exposure degree of the upper and lower surfaces is different. The bottom of the isolated photoresist pattern is prone to standing wave effect, resulting in uneven exposure of the photoresist, which becomes jagged after development, resulting in poor verticality of the side walls of the isolated photoresist pattern, and even causing the bottom of the isolated photoresist pattern to not be exposed and cause bridge phenomenon (that is, the bottom is not completely disconnected and there is still residual photoresist connected). See Figure 4 As shown in the figure, the red circle is the location where the bridging phenomenon occurs. There is currently no effective technical means to effectively detect this phenomenon during the processing process, and the repair technology for detection is also relatively difficult. This phenomenon will affect subsequent steps such as ion implantation, and once it occurs, it will affect the quality of the processed product, and can cause circuit short circuits, signal transmission problems, and device failures.

[0047] In response to the above problems, in this embodiment, an ashing process is used to remove the photoresist of a given thickness that remains after development. The ashing process is a stable process that can effectively ensure the removal of the photoresist of the given thickness, thereby solving the problem of uneven photoresist exposure caused by thick photoresist spin coating, which in turn causes poor verticality of the side walls of isolated photoresist patterns and even bridging at the bottom.

[0048] It should be noted that when the ashing process is used to remove the photoresist of a given thickness at the bottom of the exposure position, the photoresist will be eroded, thereby affecting the characteristic size of the isolated photoresist pattern. To address this problem, in this embodiment, by reserving redundancy for the characteristic size of the initial isolated photoresist pattern, that is, reserving a margin for the erosion in the ashing process, the influence of the erosion in the ashing process is overcome, so that the characteristic size of the isolated photoresist pattern obtained meets the design requirements.

[0049] In addition, in one embodiment, the feature size of the initial isolated photoresist pattern is reserved for redundancy, and there are two implementation methods: One way: Before exposure, use a mask (or photomask) to design the feature size and reserve redundancy; Another way: during exposure, by controlling the exposure dose and focal length, redundancy is reserved when adjusting the feature size of the initial isolated photoresist pattern.

[0050] In addition, in one embodiment, the ashing process is an O2 light asher process.

[0051] The oxidation photoashing process is a process that uses oxygen and ultraviolet light (or other light sources) to ash the photoresist. Compared with the traditional ashing process, the process temperature needs to be controlled within a given range to avoid deformation of isolated photoresist patterns. Generally, the process temperature of the oxidation ashing process is controlled within 150°C.

[0052] In addition, in one embodiment, the given thickness is 500 to 2000 angstroms.

[0053] In addition, in one embodiment, the thickness of the photoresist coating is 3.0 to 5.0 microns.

[0054] In addition, in one embodiment, the feature size of the processed isolated photoresist pattern is less than 1.5 microns.

[0055] In addition, in one embodiment, the aspect ratio of the processed isolated photoresist pattern is greater than 3:1.

[0056] In addition, in one embodiment, after the ashing process, the method further includes an ion implantation step.

[0057] The ion implantation process can be implemented using existing technologies, for example: In addition, in one embodiment, the photoresist coating is a positive photoresist layer, in which case; The surroundings of each initial isolated photoresist pattern are exposure positions, and a photoresist of a given thickness is retained at the bottom of the exposure position, so that the bottoms of the multiple initial isolated photoresist patterns are connected as one. The steps are: Control the exposure dose and focus so that the photoresist of a given thickness at the bottom of the exposure position is not exposed.

[0058] In this embodiment, the exposure dose and focus are controlled so that the photoresist of a given thickness at the bottom of the exposure position is not exposed, as follows: Expose the photoresist coating (positive photoresist layer) twice, and adjust the exposure focus so that the photoresist of a given thickness at the bottom of the exposure position is not exposed; There are two ways to adjust the exposure focus: One method: in the first exposure, the exposure focal length remains unchanged; in the second exposure, the second focal depth plane is moved upward (i.e., the focal length is adjusted upward) so that the photoresist of a given thickness at the bottom of the exposure position is not exposed; Another method: during the first exposure, the first focal depth plane is moved upward; at the same time, during the second exposure, the second focal depth plane is moved upward so that the photoresist of a given thickness at the bottom of the exposure position is not exposed; By adjusting the exposure dose, the feature size can be adjusted.

[0059] In addition, in one embodiment, the photoresist coating is divided into two layers, the bottom is a negative photoresist layer, and the positive photoresist layer is above the negative photoresist layer; the thickness of the negative photoresist layer is a given thickness; in this case: The surroundings of each initial isolated photoresist pattern are exposure positions, and a photoresist of a given thickness is retained at the bottom of the exposure position, so that the bottoms of the multiple initial isolated photoresist patterns are connected as one. The steps are: The exposure dose and focal length are controlled to expose the positive photoresist layer and the negative photoresist layer at the exposure position.

[0060] It should be noted that the photoresist coating is composed of a positive photoresist layer on the top and a negative photoresist layer on the bottom. Since the positive photoresist layer and the negative photoresist layer react differently to light, during the exposure process, the positive photoresist layer disappears when dissolved in the developer, while the negative photoresist layer is insoluble in the developer and remains, thereby achieving a negative photoresist layer of a given thickness after exposure and development.

[0061] In addition, in one embodiment, before exposure, a baking process is performed to ensure that the negative photoresist layer and the positive photoresist layer are more closely bonded together, and at the same time, the baking process is performed to remove moisture in the positive photoresist layer and the negative photoresist layer.

[0062] It should be noted that the effects of removing moisture from the positive photoresist layer and the negative photoresist layer are mainly as follows: Improve photolithography accuracy: Moisture may affect the uniformity and stability of photoresist, and thus affect the accuracy of isolated photoresist patterns. Removing moisture can improve the performance of photoresist to maintain stability during exposure and development.

[0063] Preventing defects: Moisture may evaporate during the baking process and cause bubbles or cracks to form inside the photoresist. These defects can seriously affect the performance of subsequent process steps and the final product. Therefore, removing moisture from the positive and negative photoresist layers through the baking process can improve the overall processing quality and ensure the quality of the final product.

[0064] Improve adhesion: Removing moisture can also help the photoresist adhere better to the wafer surface, improve the bonding force between the photoresist and the wafer, and thus enhance the stability and reliability of the isolated photoresist pattern.

[0065] In addition, in one embodiment, a semiconductor structure is provided, which is prepared by using any one of the above-mentioned methods for preparing a semiconductor structure.

[0066] In this embodiment, the isolated photoresist pattern refers to a pattern (design) formed in the photolithography process for isolating different circuit areas, rather than a single plane pattern, and includes the entire three-dimensional structure formed by the photoresist after exposure and development.

[0067] In this embodiment, by retaining a given thickness of photoresist at the bottom of the exposure position, the bottom of the initial isolated photoresist pattern is hinged together by the photoresist of the given thickness, so that in the subsequent development process, the initial isolated photoresist pattern is protected from lateral displacement and collapse due to the centrifugal force of the development rotation.

[0068] After development and drying, there is no high-speed rotation process in the subsequent process. At this time, the ashing process is used to remove the photoresist of a given thickness at the bottom of the exposure position, which can effectively improve the bridging phenomenon at the bottom of the isolated photoresist pattern.

[0069] It should be noted that an isolated photoresist pattern is a microscopic structure. During the processing, it may generate stress due to factors such as internal material non-uniformity, temperature differences, humidity changes, chemical treatment or physical effects (such as centrifugal force during the spin-drying process). This stress manifests itself as tension or pressure on the structure (which can be called photoresist pattern tension), which may affect the stability and integrity of the structure.

[0070] During the spin-drying process, due to the centrifugal force, the photoresist material (usually liquid or semi-solid) will be subjected to a strong outward pulling force. At the same time, if the surrounding isolated photoresist patterns have been solidified and have a certain rigidity, they may produce additional pulling or squeezing effects on the photoresist material due to the internal stress (i.e., photoresist pattern tension). This combined effect may cause the photoresist material to deform, collapse or fall off during the drying process, thus affecting the quality and performance of the final product.

[0071] In this embodiment, the bottom hinge of the initial isolated photoresist pattern is integrated by applying a photoresist of a given thickness at the bottom of the exposure position. Regardless of whether a single positive photoresist layer or a photoresist coating including a negative photoresist layer is used, the material properties of the photoresist coating are basically the same, so that the internal material properties of the initial isolated photoresist pattern with an integrated bottom hinge remain uniform, reducing the stress caused by factors such as temperature differences, humidity changes, chemical treatments, and physical effects, thereby overcoming the combined effect of the tension of the photoresist pattern on the centrifugal force, making the initial isolated photoresist pattern less likely to collapse and shift sideways.

[0072] It should be noted that, see Figure 1 In the existing photolithography technology, before applying the photoresist coating, the surface of the semiconductor wafer (silicon chip) usually has a sacrificial oxide layer (SiO 2), its thickness is basically between 50 and 100A (angstroms), its main function is to isolate the photoresist from the substrate, and at the same time serve as a protective layer for EPI in subsequent ion implantation. The photoresist coating is coated on the sacrificial oxide layer.

[0073] It should be noted that the semiconductor wafer preparation process involves dozens of photolithography processes. Each time the photoresist is removed, a portion of the sacrificial oxide layer will be etched by the acidic stripping solution. After multiple photolithography processes, the adhesion between the sacrificial oxide layer and the photoresist coating will become worse and worse, leading to the collapse of the isolated photoresist pattern.

[0074] It should be noted that in order to solve the above-mentioned problem of isolated photoresist pattern collapse caused by adhesion, the prior art usually coats a layer of HMDS (hexamethyldisilazane, a chemical substance used to improve the surface properties of the substrate) on the substrate surface to increase the adhesion between the photoresist coating and the substrate. In addition: Some existing technologies also maintain the adhesion between the photoresist coating and the sacrificial oxide layer by growing a new layer after removing the sacrificial oxide layer; Some prior art also uses ashing to activate the sacrificial oxide layer before applying the photoresist coating to improve the adhesion between the photoresist coating and the sacrificial oxide layer; Some existing technologies also use thin film growth technology and oxidation technology to generate an adhesive oxide layer (essentially a part of the sacrificial oxide layer) to improve the adhesion between the photoresist coating and the sacrificial oxide layer; The above existing technologies all start from the perspective of improving the adhesion of the interface between the photoresist coating and the sacrificial oxide layer, and start to improve the problem of isolated photoresist pattern collapse.

[0075] It should be noted that the adhesion between the isolated photoresist pattern and the sacrificial oxide layer is limited. The technical solution of improving the adhesion cannot solve the problem of collapse and lateral shift of the isolated photoresist pattern caused by centrifugal force during the development and drying process in the case of high aspect ratio (>3:1).

[0076] It should be noted that the strong adhesion between the photoresist coating and the substrate is one of the reasons for the photoresist residue, which in turn causes the bridging at the bottom of the isolated photoresist pattern. Therefore, the technical solution of improving the adhesion between the isolated photoresist pattern and the sacrificial oxide layer may increase the probability of the bridging phenomenon, which is not conducive to the subsequent process.

[0077] In the present embodiment, by retaining a given thickness of photoresist at the bottom of the exposure position, the bottoms of multiple initial isolated photoresist patterns are connected together, and the problem of isolated photoresist patterns being easily collapsed and shifted sideways can be solved without increasing the adhesion between the isolated photoresist patterns and the sacrificial oxide layer. At the same time, the problem of bridging due to enhanced adhesion will not occur.

[0078] In this embodiment, the method for preparing the semiconductor structure for the pixel manufacturing process of the CMOS image sensor focuses on solving the problem of pattern collapse and bridging at the bottom of the isolated photoresist pattern due to centrifugal force during the development and drying process when thick photoresist (3-5μm) forms an isolated photoresist pattern with a high aspect ratio (>3:1). The technical effect is directly related to the stability of the photoresist pattern and the accuracy of ion implantation, and belongs to the optimization of structural stability in the photolithography process.

[0079] 1. Process steps and parameters of the method for preparing the semiconductor structure: 1. Process steps: Exposure and development to retain the bottom photoresist (500-2000 angstroms); ashing process to remove the bottom photoresist; 2. Photoresist structure: double-layer structure (positive photoresist + negative photoresist) is optional.

[0080] 3. Key parameters: photoresist coating thickness of 3.0 to 5.0 microns, aspect ratio (>3:1), feature size (<1.5μm), and retaining the bottom photoresist given thickness of 500 to 2000 angstroms.

[0081] 4. Subsequent process: high-energy ion implantation (deep P-well formation).

[0082] 2. Uniqueness of the technical effect of the method for preparing the semiconductor structure: 1. Bottom hinge integration: The bottom photoresist is retained for physical connection (bottom hinge integration) to solve the problem of pattern collapse and lateral shift, specifically: (1) Reduce the effect of moment concentration: ① Increase the support width: retain the bottom photoresist and expand the support width of the isolated photoresist pattern from the photoresist line width to the entire bottom glue layer area to overcome the centrifugal force; ② Optimize stress distribution: significantly reduce root stress, retain the bottom photoresist as a "flexible substrate", absorb part of the centrifugal energy through elastic deformation, and avoid stress concentration at the root of the pattern.

[0083] (2) Suppressing Euler buckling: reducing the effective slenderness ratio: ① Shorten the effective length: the photoresist pattern changes from a free cantilever to a bottom fixed, and the effective length is reduced.

[0084] ② Increase the cross-sectional moment of inertia: Retaining the bottom photoresist changes the cross-section from a rectangle to a T-shape, thereby increasing the moment of inertia.

[0085] ③ Transformation of buckling mode: When the bottom photoresist is not retained, the buckling mode is first-order bending (overall tilt); when the bottom photoresist is retained, the buckling mode is transformed into local micro-bending (energy is absorbed by the adhesive layer), and the critical buckling load is increased.

[0086] (3) Eliminating capillary forces: interface regulation and stress release: ① Control of developer residue: retain the bottom photoresist by adjusting the surface hydrophilicity (increasing the contact angle), reducing the amount of developer residue in the pattern gap, and reducing the capillary force.

[0087] ② Drying stress release path: retain the bottom photoresist as a stress buffer layer, allowing the pattern to undergo micron-level elastic deformation during the drying process to avoid brittle fracture.

[0088] (4) Compensation for roughness defects: mechanical reinforcement and crack suppression: ① Neutralization of the effect of sidewall roughness (LWR): The roughness of the photoresist sidewall will cause local stress concentration, and the reserved glue layer can compensate in two ways: Filling the groove: The adhesive layer covers the rough area at a certain height at the bottom of the side wall to form a smooth transition; Crack passivation: The high fracture toughness of the adhesive layer prevents the propagation of microcracks.

[0089] ② Correction of development non-uniformity: Insufficient bottom development will lead to a sudden change in local hardness. Retaining the bottom photoresist as a homogenized transition layer can reduce the modulus gradient at the development interface and avoid sudden stress changes.

[0090] In short. The bottom residual layer of the photoresist needs to act as a "hinge structure" (mechanical hinge) to resist the pulling of the photoresist sidewall by the centrifugal force when the high aspect ratio (>3:1) graphics are dried, connect the bottom of multiple graphics as a whole, and disperse the centrifugal force through the bottom connection during drying. A given thickness of 500 to 2000 angstroms can provide sufficient elastic modulus (about 3-5 GPa) and tensile strength to prevent the graphics from collapsing.

[0091] It should be noted that for photoresist coatings with a thickness of 3.0 to 5.0 microns, feature sizes <1.5 μm, and high aspect ratios >3:1, the given thickness should be neither too thin nor too thick, and 500 to 2000 angstroms is the optimal design: On the one hand, if the thickness is too thin (<500 angstroms), it will lead to insufficient mechanical support, unable to resist centrifugal force and stress, and unable to prevent the collapse of the graphics.

[0092] On the other hand, if the thickness is too thick (>2000 angstroms): the rigidity of the glue layer is too high, resulting in increased overall brittleness of the photoresist and reduced fracture toughness; the thickness needs to match the ashing rate, and a too thick glue layer requires a longer ashing time. Long ashing time causes thermal deformation of the photoresist, affecting the accuracy of the ion implantation mask, or resulting in the glue layer not being completely removed, with residual glue hindering ion implantation.

[0093] In summary, the given thickness of 500 to 2000 angstroms is the result of comprehensive optimization of mechanical design, ion blocking requirements and process compatibility.

[0094] 2. The ashing process removes the residual photoresist at the bottom to avoid bridging at the bottom: In the traditional thick photoresist process, the bottom of the isolated photoresist pattern is prone to bridging due to uneven exposure. However, this embodiment uses the ashing process to accurately remove the residual photoresist at the bottom, avoiding ion implantation deviation caused by bridging and improving the electrical isolation performance of the CMOS sensor. At the same time, by reserving redundancy in the initial photoresist pattern feature size, the influence of the ashing process on the pattern size is solved, ensuring that the final feature size is less than the accuracy requirement of 1.5 microns.

[0095] 3. Process compatibility and yield improvement: Ashing process (such as O 2 The low temperature characteristic (<150°C) of oxidation ashing avoids thermal deformation of the photoresist pattern and is compatible with existing CMOS processes without the need for additional equipment investment.

[0096] The ashing process has no risk of metal layer exposure and does not introduce the risk of metal contamination in the etching process, and is suitable for high-precision ion implantation scenarios.

[0097] The ashing process removes photoresist through oxidation reaction, which has less impact on the verticality of the side walls and is suitable for structures with aspect ratios >3:1.

[0098] The technical solution provided by the present invention is further described in detail above through several specific implementation modes in order to highlight the advantages and benefits of the technical solution provided by the present invention. However, the several specific implementation modes described above are not intended to be used as limitations on the present invention. Any reasonable changes and improvements to the present invention, reasonable combinations of implementation modes and equivalent substitutions based on the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing a semiconductor structure, the method comprising the step of processing an isolated photoresist pattern, characterized in that: The processing steps of the isolated photoresist pattern include: On the surface of the semiconductor wafer, a thick photoresist is spin-coated to form a photoresist coating; The photoresist coating is exposed and developed to form a plurality of initial isolated photoresist patterns; the periphery of each initial isolated photoresist pattern is an exposure position, and during the exposure, a given thickness of photoresist is ensured to be retained at the bottom of the exposure position, so that the bottoms of the plurality of initial isolated photoresist patterns are connected as one; The ashing process is used to remove the photoresist of a given thickness at the bottom of the exposure position, exposing the surface of the semiconductor wafer below, and obtaining multiple isolated photoresist patterns that are processed and not connected at the bottom.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The feature size of the initial isolated photoresist pattern reserves redundancy.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that: The given thickness is 500 to 2000 angstroms.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that: The thickness of the photoresist coating is 3.0 to 5.0 microns.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that: The feature size of the processed isolated photoresist pattern is less than 1.5 microns.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that: The aspect ratio of the processed isolated photoresist pattern is greater than 3:

1.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that: After the ashing process, the method further includes an ion implantation step.

8. The method for preparing a semiconductor structure according to any one of claims 1 to 7, characterized in that: The photoresist coating is a positive photoresist layer; The surroundings of each initial isolated photoresist pattern are exposure positions, and a photoresist of a given thickness is retained at the bottom of the exposure position, so that the bottoms of the multiple initial isolated photoresist patterns are connected as one. The steps are: Control the exposure dose and focus so that the photoresist of a given thickness at the bottom of the exposure position is not exposed.

9. The method for preparing a semiconductor structure according to any one of claims 1 to 7, characterized in that: The photoresist with a given thickness at the bottom of the exposure position is a negative photoresist layer; the photoresist coating above the negative photoresist layer is a positive photoresist layer; The surroundings of each initial isolated photoresist pattern are exposure positions, and a photoresist of a given thickness is retained at the bottom of the exposure position, so that the bottoms of the multiple initial isolated photoresist patterns are connected as one. The steps are: The exposure dose and focal length are controlled to expose the positive photoresist layer and the negative photoresist layer at the exposure position.

10. A semiconductor structure, characterized in that: The semiconductor structure is prepared by the method for preparing the semiconductor structure according to any one of claims 1 to 7.

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