Semiconductor structure with double deep trench isolation and preparation method thereof

Abstract

The present invention relates to the field of semiconductors, and the present invention provides a semiconductor structure with double deep trench isolation and a preparation method thereof. The method comprises the following steps: providing a first type substrate, performing ion implantation to form a first type deep buried layer; forming a second type deep buried layer and a first type light plate lightly doped region on the surface of the first type substrate, and the first type light plate lightly doped region is located above the first type deep buried layer, and the second type deep buried layer is located on both sides of the first type light plate lightly doped region; growing a first epitaxial layer on the surface of the first type substrate; forming a first type and a second type deep injection region in the first epitaxial layer, and the first type deep injection region is located above the first type light plate lightly doped region, and the second type deep injection region is located above the second type deep buried layer; growing a second epitaxial layer on the surface of the first epitaxial layer; forming two deep trench isolations extending from the surface of the second epitaxial layer to the first type substrate. The above technical scheme solves the problem of weak recombination ability of the base region for carriers in a relatively low-cost manner.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a semiconductor structure with double deep trench isolation and a preparation method thereof. Background Art

[0002] Deep Trench Oxide Isolation (DTI) is a process that etches a deep trench and fills it with oxide to achieve high voltage isolation. Figure 1 , which is a schematic diagram of a semiconductor structure with single deep trench oxide isolation in the prior art. Common DTI morphologies are as follows: Figure 1 As shown, a single deep trench oxide isolation 12 is added between the first buried layer 111 and the second buried layer 112 (NN or PP) to form an N-oxide-N isolation structure.

[0003] See also Figure 2 , which is a schematic diagram of a semiconductor structure with dual deep trench oxide isolation in the prior art. For the bipolar-complementary metal oxide semiconductor-double diffused metal oxide semiconductor (BCD) platform, the operating voltage difference between devices is large, and the isolation performance requirements are high, such as parasitic NPN leakage performance, etc. The single DTI structure can easily lead to the punch-through effect from N-type buried layer (NBL) to N-type buried layer (NBL). Therefore, the BCD platform usually adopts a dual deep trench oxide isolation 22 structure, such as Figure 2 The simulation and measured data show that although the depletion region from the first N-type buried layer 211 to the second N-type buried layer 212 does not penetrate, the parasitic transistor base concentration is low and deep, and the base region has a weak recombination ability for carriers, causing the current to flow from the collector to the emitter, resulting in a larger amplification factor (Alfa).

[0004] See also Figure 3 , which is a schematic diagram of a semiconductor structure with double deep trench oxide isolation using a P+ substrate in the prior art. In order to improve the above problems, Figure 3 As shown, the prior art increases the carrier recombination capacity of the base region of the parasitic bipolar junction transistor (BJT) by adding a P-type heavily doped (P+) epitaxial substrate 33 on the basis of the double deep trench oxide isolation 22, so that the current basically flows away from the base region, thereby reducing Alfa. However, the process cost of the prior art is relatively high, and it is necessary to purchase an epitaxial substrate with a P-type heavily doped substrate.

[0005] Therefore, how to solve the problem of the base region's weak recombination ability for carriers, which leads to a large amplification factor, in a low-cost way is a problem that needs to be solved at present. Summary of the invention

[0006] The technical problem to be solved by the present invention is how to solve the problem of large amplification factor caused by weak recombination ability of the base region for carriers in a relatively low-cost manner, and to provide a semiconductor structure with double deep trench isolation and a preparation method thereof.

[0007] In order to solve the above problems, the present invention provides a method for preparing a semiconductor structure with double deep trench isolation, comprising the following steps: providing a first type substrate, and performing ion implantation in the first type substrate to form a first type deep buried layer; performing ion implantation on the surface of the first type substrate to form a second type deep buried layer and a first type light plate lightly doped region, and the first type light plate lightly doped region is located above the first type deep buried layer, and the second type deep buried layer is located on both sides of the first type light plate lightly doped region; growing a first epitaxial layer on the surface of the first type substrate; performing ion implantation in the first epitaxial layer to form a first type deep injection region and a second type deep injection region, and the first type deep injection region is located above the first type light plate lightly doped region, and the second type deep injection region is located above the second type deep buried layer; growing a second epitaxial layer on the surface of the first epitaxial layer; forming two deep trench isolations, which are respectively located on both sides of the first type light plate lightly doped region, and extend from the surface of the second epitaxial layer to the first type substrate.

[0008] In some embodiments, the step of growing the second epitaxial layer on the surface of the first epitaxial layer further includes: defining a plurality of active regions on the surface of the second epitaxial layer, wherein the spacing regions between the active regions correspond one-to-one to the first type deep implantation regions and the second type deep implantation regions, respectively.

[0009] In some embodiments, the deep trench isolation penetrates the active area.

[0010] In some embodiments, the step of forming two deep trench isolations further includes: sequentially forming a first type well region and a first type highly doped region above the first type deep injection region, and sequentially forming a second type well region and a second type highly doped region above the second type deep injection region.

[0011] In some embodiments, surfaces of the first-type highly doped region and the second-type highly doped region are flush with a surface of the active region.

[0012] In order to solve the above problems, the present invention also provides a semiconductor structure with double deep trench isolation, including: a first type substrate, a first type deep buried layer is formed in the first type substrate, a second type deep buried layer and a first type light plate lightly doped region are formed on the surface of the first type substrate, and the first type light plate lightly doped region is located above the first type deep buried layer, and the second type deep buried layer is located on both sides of the first type light plate lightly doped region; a first epitaxial layer, located on the surface of the first type substrate, a first type deep injection region and a second type deep injection region are formed in the first epitaxial layer, and the first type deep injection region is located above the first type light plate lightly doped region, and the second type deep injection region is located above the second type deep buried layer; a second epitaxial layer, located on the surface of the first epitaxial layer; two deep trench isolations, respectively located on both sides of the first type light plate lightly doped region, and extending from the surface of the second epitaxial layer to the first type substrate.

[0013] In some embodiments, the first type is P type and the second type is N type.

[0014] In some embodiments, a plurality of active regions are defined on the surface of the second epitaxial layer, and the spacing regions between the active regions correspond one-to-one to the first-type deep implantation regions and the second-type deep implantation regions, respectively.

[0015] In some embodiments, the deep trench isolation penetrates the active area.

[0016] In some embodiments, a first-type well region and a first-type highly doped region are sequentially formed above the first-type deep injection region, and a second-type well region and a second-type highly doped region are sequentially formed above the second-type deep injection region; wherein the surfaces of the first-type highly doped region and the second-type highly doped region are flush with the surface of the active region.

[0017] The above technical solution adopts a semiconductor structure with double deep trench isolation, and optimizes the layout between the deep trench isolations based on the platform's own process, introduces several P-type deep injections, and effectively isolates the influence between high-voltage devices. The deep trench isolation structure has a higher isolation withstand voltage (>180V) than the junction isolation structure, but leakage is easily formed between devices. The present invention provides a process method that effectively reduces the amplification factor of the NPN parasitic transistor formed between the two isolation structures, thereby reducing the leakage between the isolation structures. In addition, the process avoids the use of P-type heavily doped epitaxial substrates, reducing the procurement cost of raw wafers. The above process method is simple to prepare, and the semiconductor structure with double deep trench isolation formed has good isolation effect, and can be applied to high-voltage and high-power related platforms such as BCD. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following is a brief introduction to the drawings required for the description of the specific embodiments. Obviously, the drawings described below are only some specific embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 The schematic diagram is a structural diagram of a semiconductor structure with single deep trench oxide isolation in the prior art.

[0020] Figure 2 The schematic diagram is a structural diagram of a semiconductor structure with double deep trench oxide isolation in the prior art.

[0021] Figure 3 The schematic diagram is a structural diagram of a semiconductor structure with double deep trench oxide isolation using a P+ substrate in the prior art.

[0022] Figure 4 The present invention is a flowchart of one embodiment of a method for preparing a semiconductor structure with double deep trench isolation.

[0023] Figure 5 A process structure diagram of a first type substrate is provided for one embodiment of a method for preparing a semiconductor structure with double deep trench isolation according to the present invention.

[0024] Figure 6 This is a process structure diagram of an embodiment of a method for preparing a semiconductor structure with double deep trench isolation according to the present invention, in which ion implantation is performed on the surface of the first-type substrate to form a second-type deep buried layer and a first-type light-doped region.

[0025] Figure 7 A process structure diagram of growing a first epitaxial layer and performing ion implantation in the first epitaxial layer to form a first type deep implantation region and a second type deep implantation region in an embodiment of a method for preparing a semiconductor structure with double deep trench isolation according to the present invention.

[0026] Figure 8 This is a process structure diagram for growing a second epitaxial layer in an embodiment of a method for preparing a semiconductor structure with double deep trench isolation according to the present invention.

[0027] Fig. 9 The present invention is a process structure diagram for forming two deep trench isolations according to an embodiment of a method for preparing a semiconductor structure with double deep trench isolations.

[0028] Fig.10The present invention is a process structure diagram of forming a first-type well region, a first-type highly doped region, a second-type well region and a second-type highly doped region in accordance with an embodiment of a method for preparing a semiconductor structure with double deep trench isolation described in the present invention.

[0029] Description of Reference Numerals

[0030] 111, first buried layer;

[0031] 112, the second buried layer;

[0032] 12. Single deep trench oxide isolation;

[0033] 211, a first N-type buried layer;

[0034] 212, second N-type buried layer;

[0035] 22. Double deep trench oxide isolation;

[0036] 33. Epitaxial substrate;

[0037] 50. A first type substrate;

[0038] 501, Type I deep buried layer;

[0039] 502, Type II deep buried layer;

[0040] 503, first type light plate lightly doped region;

[0041] 51. The first epitaxial layer;

[0042] 511, Type I deep injection region;

[0043] 512, Type II deep injection region;

[0044] 52. Second epitaxial layer;

[0045] 520, active area;

[0046] 521, interval area;

[0047] 53. Deep trench isolation;

[0048] 531, first type well region;

[0049] 532, second type well region;

[0050] 541, first type highly doped region;

[0051] 542. Type II highly doped region. DETAILED DESCRIPTION

[0052] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0053] The present invention is based on a double deep trench oxide isolation (DTI) structure, which increases the P-type concentration in the base region of the parasitic transistor, improves the recombination capacity of the base carriers, and reduces the leakage caused by the drift to the collector carriers. The process avoids the use of P-type heavily doped epitaxial layers, reduces the process cost, and provides more solutions to the problem.

[0054] See also Figure 4 , which is a flowchart of the steps of an embodiment of a method for preparing a semiconductor structure with double deep trench isolation according to the present invention. Figure 4 As shown, the preparation method of the semiconductor structure with double deep trench isolation includes the following steps: step S41, providing a first type substrate, and performing ion implantation in the first type substrate to form a first type deep buried layer; step S42, performing ion implantation on the surface of the first type substrate to form a second type deep buried layer and a first type light plate lightly doped region, and the first type light plate lightly doped region is located above the first type deep buried layer, and the second type deep buried layer is located on both sides of the first type light plate lightly doped region; step S43, growing a first epitaxial layer on the surface of the first type substrate; step S44, performing ion implantation in the first epitaxial layer to form a first type deep implantation region and a second type deep implantation region, and the first type deep implantation region is located above the first type light plate lightly doped region, and the second type deep implantation region is located above the second type deep buried layer; step S45, growing a second epitaxial layer on the surface of the first epitaxial layer; step S46, forming two deep trench isolations, which are respectively located on both sides of the first type light plate lightly doped region and extend from the surface of the second epitaxial layer to the first type substrate.

[0055] See also Figure 5~Figure 10 ,in, Figure 5 A process structure diagram of providing a first type substrate for an embodiment of a method for preparing a semiconductor structure with double deep trench isolation according to the present invention; Figure 6 This is a process structure diagram of an embodiment of a method for preparing a semiconductor structure with double deep trench isolation according to the present invention, in which ion implantation is performed on the surface of the first-type substrate to form a second-type deep buried layer and a first-type light-doped region; Figure 7 A process structure diagram of growing a first epitaxial layer and performing ion implantation in the first epitaxial layer to form a first type deep implantation region and a second type deep implantation region according to an embodiment of a method for preparing a semiconductor structure with double deep trench isolation of the present invention; Figure 8 A process structure diagram of growing a second epitaxial layer in an embodiment of a method for preparing a semiconductor structure with double deep trench isolation according to the present invention; Fig. 9 A process structure diagram of forming two deep trench isolations in one embodiment of a method for preparing a semiconductor structure with double deep trench isolations according to the present invention; Fig.10 The present invention is a process structure diagram of forming a first-type well region, a first-type highly doped region, a second-type well region and a second-type highly doped region in accordance with an embodiment of a method for preparing a semiconductor structure with double deep trench isolation described in the present invention.

[0056] See also Figure 5 And step S41 , providing a first type substrate 50 , and performing ion implantation in the first type substrate 50 to form a first type buried layer 501 .

[0057] In this embodiment, the first-type substrate 50 is a P-type substrate, and the first-type deep buried layer 501 is a P-type deep buried layer (DPW for short). The P-type deep buried layer is a semiconductor structure with a specific doping type and position, and is formed by doping P-type impurities (such as boron, etc.) at a deeper position of the first-type substrate 50. The first-type deep buried layer 501 can be formed by ion implantation or diffusion process, and is used to increase the P-type concentration of the first-type substrate 50, improve the recombination ability of the base carriers, and reduce the leakage formed by drifting to the collector carriers.

[0058] See also Figure 6 And step S42, ion implantation is performed on the surface of the first type substrate 50 to form a second type deep buried layer 502 and a first type light plate lightly doped area 503, and the first type light plate lightly doped area 503 is located above the first type deep buried layer 501, and the second type deep buried layer 502 is located on both sides of the first type light plate lightly doped area 503.

[0059] In this embodiment, the second-type deep buried layer 502 is an N-type buried layer (NBL). The N-type buried layer is an N-type doped region formed on the first-type substrate 50 by ion implantation or diffusion during semiconductor manufacturing, and is used to improve device performance, such as reducing collector resistance.

[0060] See also Figure 7And step S43 ~ step S44, grow the first epitaxial layer 51 on the surface of the first type substrate 50; and perform ion implantation in the first epitaxial layer 51 to form a first type deep implantation region 511 and a second type deep implantation region 512, and the first type deep implantation region 511 is located above the first type light plate lightly doped region 503, and the second type deep implantation region 512 is located above the second type deep buried layer 502. In this embodiment, the first epitaxial layer 51 is a first type epitaxial layer, that is, a P type epitaxial layer, which is the same type as the first type substrate 50.

[0061] See also Figure 8 And step S45 , growing a second epitaxial layer 52 on the surface of the first epitaxial layer 51 . In this embodiment, the second epitaxial layer 52 is a first-type epitaxial layer, that is, a P-type epitaxial layer, which is the same type as the first-type substrate 50 .

[0062] In some embodiments, after the step of growing the second epitaxial layer 52 on the surface of the first epitaxial layer 51, the step also includes: defining a plurality of active areas 520 on the surface of the second epitaxial layer 52, and the spacing areas 521 between the active areas 520 correspond one-to-one to the first type deep injection area 511 and the second type deep injection area 512 respectively.

[0063] See also Fig. 9 And step S46 , forming two deep trench isolations 53 , which are respectively located on both sides of the first-type optical plate lightly doped region 503 and extend from the surface of the second epitaxial layer 52 to the first-type substrate 50 .

[0064] In some embodiments, the deep trench isolation 53 penetrates the active region 520 .

[0065] See also Fig.10 After the step of forming two deep trench isolations 53, the step also includes: sequentially forming a first-type well region 531 and a first-type highly doped region 541 above the first-type deep injection region 511, and sequentially forming a second-type well region 532 and a second-type highly doped region 542 above the second-type deep injection region 512.

[0066] In some embodiments, the surfaces of the first-type highly doped region 541 and the second-type highly doped region 542 are flush with the surface of the active region 520 .

[0067] The above technical solution adopts a semiconductor structure with double deep trench isolation, and optimizes the layout between the deep trench isolations based on the platform's own process, introduces several P-type deep injections, and effectively isolates the influence between high-voltage devices. The deep trench isolation structure has a higher isolation withstand voltage (>180V) than the junction isolation structure, but leakage is easily formed between devices. The present invention provides a process method that effectively reduces the amplification factor of the NPN parasitic transistor formed between the two isolation structures, thereby reducing the leakage between the isolation structures. In addition, the process avoids the use of P-type heavily doped epitaxial substrates, reducing the procurement cost of raw wafers. The above process method is simple to prepare, and the semiconductor structure with double deep trench isolation formed has good isolation effect, and can be applied to high-voltage and high-power related platforms such as BCD.

[0068] Based on the same inventive concept, an embodiment of the present invention also provides a semiconductor structure with dual deep trench isolation, which increases the isolation withstand voltage while reducing the area occupied by the isolation structure, improves the parasitic transistor base concentration, reduces the leakage of the parasitic transistor, and effectively improves the DTI isolation performance.

[0069] See also Fig.10 The semiconductor structure with double deep trench isolation includes: a first type substrate 50, a first epitaxial layer 51, a second epitaxial layer 52, and two deep trench isolations 53. A first type deep buried layer 501 is formed in the first type substrate 50, and a second type deep buried layer 502 and a first type light plate lightly doped region 503 are formed on the surface of the first type substrate 50, and the first type light plate lightly doped region 503 is located above the first type deep buried layer 501, and the second type deep buried layer 502 is located on both sides of the first type light plate lightly doped region 503. The first epitaxial layer 51 is located on the surface of the first type substrate 50, and a first type deep injection region 511 and a second type deep injection region 512 are formed in the first epitaxial layer 51, and the first type deep injection region 511 is located above the first type light plate lightly doped region 503, and the second type deep injection region 512 is located above the second type deep buried layer 502. The second epitaxial layer 52 is located on the surface of the first epitaxial layer 51. The two deep trench isolations 53 are respectively located at two sides of the first-type optical plate lightly doped region 503 , and extend from the surface of the second epitaxial layer 52 to the first-type substrate 50 .

[0070] In some embodiments, the first type is P type and the second type is N type.

[0071] In this embodiment, both the first epitaxial layer 51 and the second epitaxial layer 52 are first-type epitaxial layers, that is, P-type epitaxial layers, which are the same type as the first-type substrate 50 .

[0072] In some embodiments, a plurality of active regions 520 are defined on the surface of the second epitaxial layer 52 , and the spacing regions 521 between the active regions 520 correspond to the first type deep implantation regions 511 and the second type deep implantation regions 512 , respectively.

[0073] In some embodiments, the deep trench isolation 53 penetrates the active region 520 .

[0074] In some embodiments, a first-type well region 531 and a first-type highly doped region 541 are sequentially formed above the first-type deep injection region 511, and a second-type well region 532 and a second-type highly doped region 542 are sequentially formed above the second-type deep injection region 512; wherein the surfaces of the first-type highly doped region 541 and the second-type highly doped region 542 are flush with the surface of the active region 520.

[0075] The above technical solution adopts a semiconductor structure with double deep trench isolation, and optimizes the layout between deep trench isolation based on the platform's own process, introduces several P-type deep injections, and effectively isolates the influence between high-voltage devices. The present invention provides a semiconductor structure with double deep trench isolation, which effectively reduces the amplification factor of the NPN parasitic transistor formed between the two deep trench isolation structures, thereby reducing the leakage between the deep trench isolation structures. In addition, the use of P-type heavily doped epitaxial substrates is avoided, reducing the procurement cost of raw wafers.

[0076] It should be noted that references in the specification to "an embodiment", "an embodiment", "an exemplary embodiment", "some embodiments", etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of a technician in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments.

[0077] Typically, a term can be understood at least in part from usage in context. For example, the term "one or more" as used herein depends at least in part on the context and can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or features in a plural sense. Similarly, terms such as "one", "a" or "the" can also be understood to express singular usage or to express plural usage, depending at least in part on the context. In addition, the term "based on" can be understood to not necessarily be intended to express a set of exclusive factors, but can alternatively, also at least in part depending on the context, allow for the presence of other factors that are not necessarily explicitly described. It should also be noted in this specification that "connected / coupled" refers not only to the direct coupling of one component to another component, but also to the indirect coupling of one component to another component through an intermediate component.

[0078] It should be noted that the terms "including" and "having" and their variations involved in the documents of the present invention are intended to cover non-exclusive inclusions. The terms "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Unless the context clearly indicates otherwise, it should be understood that the data used in this way can be interchanged under appropriate circumstances. In addition, the embodiments of the present invention and the features in the embodiments can be combined with each other unless there is a conflict. In addition, in the above description, the description of well-known components and technologies is omitted to avoid unnecessary confusion of the concepts of the present invention. In the above embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to each other.

[0079] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for preparing a semiconductor structure with double deep trench isolation, characterized in that: The steps include: Providing a first type substrate, and performing ion implantation in the first type substrate to form a first type buried layer; Ion implantation is performed on the surface of the first-type substrate to form a second-type deep buried layer and a first-type light-doped region, wherein the first-type light-doped region is located above the first-type deep buried layer, and the second-type deep buried layer is located on both sides of the first-type light-doped region; growing a first epitaxial layer on the surface of the first type substrate; Performing ion implantation in the first epitaxial layer to form a first type deep implantation region and a second type deep implantation region, wherein the first type deep implantation region is located above the first type light plate lightly doped region, and the second type deep implantation region is located above the second type deep buried layer; growing a second epitaxial layer on a surface of the first epitaxial layer; Two deep trench isolations are formed, which are respectively located at two sides of the lightly doped region of the first type optical plate and extend from the surface of the second epitaxial layer to the first type substrate.

2. The method according to claim 1, characterized in that: After the step of growing the second epitaxial layer on the surface of the first epitaxial layer, the method further comprises: A plurality of active regions are defined on the surface of the second epitaxial layer, and the spacing regions between the active regions correspond one-to-one to the first-type deep implantation regions and the second-type deep implantation regions respectively.

3. The method according to claim 2, characterized in that The deep trench isolation penetrates the active area.

4. The method according to claim 2, characterized in that: After the step of forming two deep trench isolations, the method further comprises: A first-type well region and a first-type highly doped region are sequentially formed above the first-type deep implantation region, and a second-type well region and a second-type highly doped region are sequentially formed above the second-type deep implantation region.

5. The method according to claim 4, characterized in that Surfaces of the first-type highly doped region and the second-type highly doped region are flush with a surface of the active region.

6. A semiconductor structure with double deep trench isolation, characterized in that: include: A first-type substrate, wherein a first-type deep buried layer is formed in the first-type substrate, a second-type deep buried layer and a first-type light-plate lightly doped region are formed on the surface of the first-type substrate, and the first-type light-plate lightly doped region is located above the first-type deep buried layer, and the second-type deep buried layers are located on both sides of the first-type light-plate lightly doped region; A first epitaxial layer is located on the surface of the first-type substrate, wherein a first-type deep injection region and a second-type deep injection region are formed in the first epitaxial layer, and the first-type deep injection region is located above the first-type light-doped region, and the second-type deep injection region is located above the second-type deep buried layer; A second epitaxial layer, located on a surface of the first epitaxial layer; Two deep trench isolations are respectively located at two sides of the lightly doped region of the first type optical plate and extend from the surface of the second epitaxial layer to the first type substrate.

7. The semiconductor structure with double deep trench isolation according to claim 6, characterized in that: The first type is P type, and the second type is N type.

8. The semiconductor structure with double deep trench isolation according to claim 6, characterized in that: A plurality of active regions are defined on the surface of the second epitaxial layer, and the spacing regions between the active regions correspond one-to-one to the first-type deep implantation regions and the second-type deep implantation regions respectively.

9. The semiconductor structure with double deep trench isolation according to claim 8, characterized in that: The deep trench isolation penetrates the active area.

10. The semiconductor structure with double deep trench isolation according to claim 8, characterized in that: A first-type well region and a first-type highly doped region are sequentially formed above the first-type deep injection region, and a second-type well region and a second-type highly doped region are sequentially formed above the second-type deep injection region; wherein the surfaces of the first-type highly doped region and the second-type highly doped region are flush with the surface of the active region.

Images