Packaging method of IGCT device and packaging structure of IGCT device

Abstract

The present application relates to a packaging method for an IGCT device and a packaging structure of an IGCT device. The packaging method for the IGCT device includes: providing an electrode and a wafer; forming a patterned interconnect material layer on the surface of the electrode, the interconnect material layer including a plurality of spaced-apart interconnect material units; disposing the wafer on a side of the interconnect material layer away from the electrode; using a bonding process or a welding process to deform the interconnect material units to connect the wafer and the electrode; wherein at least two adjacent and deformed interconnect material units are partially connected. The present application provides space for releasing thermal stress during the interconnection between the wafer and the electrode, reducing or avoiding the risk of warping deformation due to thermal stress during the interconnection, thereby improving the reliability of the packaging structure of the IGCT device without affecting the thermal resistance optimization effect.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technologies, and particularly to a packaging method and a packaging structure for an IGCT device. Background Art

[0002] As a fully controlled power device with the largest single-tube capacity, the Integrated Gate-Commutated Thyristor (IGCT) has excellent performance such as large capacity, fast switching speed, low switching loss, and high tolerance to the current rise rate (di / dt). It is widely used in fields such as DC power transmission, smart grid, power converters, and power inverters, with broad prospects and huge future development space.

[0003] The IGCT device mainly consists of a Gate-Commutated Thyristor (GCT) element and a drive circuit board connected to its lead electrodes. Among them, the GCT element is the core component of the IGCT device, mainly composed of a semiconductor chip and a packaging case. The packaging case includes a case base, a gate assembly, a cathode plate, an anode plate, a case upper cover, etc. Among them, the gate assembly mainly consists of a gasket, an elastic support, an insulating seat, and a gate lead ring.

[0004] A general packaging structure is a five-layer structure composed of an anode copper electrode, an anode molybdenum sheet, a silicon chip, a cathode molybdenum sheet, and a cathode copper electrode, and electrical connection is achieved through rigid contact by mechanical pressure. However, with the continuous improvement of the power level of IGCT devices, higher requirements are put forward for the packaging thermal resistance of semiconductor devices. Therefore, how to reduce the thermal resistance of semiconductor devices during the whole-wafer packaging process of GCT elements or other power semiconductor devices, while avoiding the problem of sample warping and deformation under the action of thermal stress, has become a technical problem to be solved urgently. Summary of the Invention

[0005] Based on this, it is necessary to provide a packaging method and a packaging structure for an IGCT device to reduce or avoid the warping and deformation problems during the interconnection process, while reducing the thermal resistance of the IGCT device and improving the reliability of the packaging structure of the IGCT device.

[0006] In a first aspect, the present application provides a packaging method for an IGCT device, including:

[0007] Providing an electrode and a wafer;

[0008] Forming a patterned interconnect material layer on the surface of the electrode, the interconnect material layer including a plurality of spaced-apart interconnect material units;

[0009] Place the wafer on the side of the interconnect material layer away from the electrode;

[0010] Adopt a bonding process or a welding process to deform the interconnect material units to connect the wafer and the electrode;

[0011] Wherein, at least two adjacent and deformed interconnect material units are partially connected.

[0012] In one embodiment, forming a patterned interconnect material layer on the surface of the electrode includes:

[0013] Arrange each of the interconnect material units on the surface of the electrode according to a set trajectory to form the interconnect material layer.

[0014] In one embodiment, the set trajectory is symmetrically arranged on the surface of the electrode based on the central axis, and the central axis is parallel to the surface of the electrode and passes through the geometric center of the electrode.

[0015] In one embodiment, the shape of the set trajectory includes at least one of a concentric circular ring shape, a spiral shape, a radial pattern, and a grid pattern.

[0016] In one embodiment, the distance between two adjacent interconnect material units ranges from 50 μm to 100 μm.

[0017] In one embodiment, the orthographic projection area of the interconnect material layer facing the electrode is 80% - 90% of the total area of the electrode.

[0018] In one embodiment, after providing an electrode and a wafer and before forming a patterned interconnect material layer on the surface of the electrode, the packaging method of the IGCT device includes:

[0019] Perform pre - metallization treatment on the wafer and the electrode to form a first pre - metal layer covering the wafer and a second pre - metal layer covering the electrode, wherein the first pre - metal layer covers the surface of the wafer on the side close to the electrode, and the second pre - metal layer covers the surface of the electrode on the side close to the wafer.

[0020] In one embodiment, the materials of the first pre - metal layer and the second pre - metal layer are bondable with the material of the interconnect material units.

[0021] In one embodiment, the materials of the first pre - metal layer and the second pre - metal layer include at least one of metallic gold and metallic silver.

[0022] In one embodiment, the first pre-metal layer, the second pre-metal layer, and the interconnect material unit are made of at least one material.

[0023] In one embodiment, the material of the interconnect material unit has electrical conductivity.

[0024] In one embodiment, the material of the interconnect material unit includes one of a tin-based material, a solder-based material, and a nano-silver material.

[0025] In a second aspect, the present application also provides a semiconductor interconnect structure, which is made by using the packaging method of the IGCT device provided in the first aspect of the present application.

[0026] In a third aspect, the present application also provides a packaging structure of an IGCT device, including:

[0027] An electrode;

[0028] An interconnect material layer located on one side surface of the electrode; wherein, the interconnect material layer includes a plurality of interconnect material units; the interconnect material units have variable morphologies;

[0029] A wafer located on a side of the interconnect material layer away from the electrode.

[0030] In one embodiment, the interconnect material units have a first morphology and a second morphology; wherein,

[0031] When the interconnect material unit is in the first morphology, the interconnect material unit has a first height, and the area of the cross-section of the interconnect material unit parallel to the electrode gradually decreases in the direction of the surface away from the electrode;

[0032] When the interconnect material unit is in the second morphology, the electrode is connected to the wafer, the interconnect material unit has a second height, and the second height is less than the first height.

[0033] In one embodiment, the shape of the interconnect material unit includes a cylindrical shape and a frustum shape;

[0034] When the interconnect material unit is cylindrical, the ratio of the area of the cross-section of the interconnect material unit parallel to the electrode to the height of the interconnect material unit ranges from 0.5 to 1;

[0035] When the interconnect material unit is frustum-shaped, the interconnect material unit includes a first top surface and a second top surface parallel to the electrode, and the ratio of the average value of the areas of the first top surface and the second top surface to the height of the interconnect material unit ranges from 0.5 to 1.

[0036] The packaging method and packaging structure of the IGCT device provided by the embodiment of the present application realize the effective connection between the wafer and the electrode by forming a patterned interconnect material layer on the electrode and then connecting the interconnect material layer to the wafer; the patterned interconnect material layer is formed by multiple spaced interconnect material units, which provides space for releasing thermal stress during the interconnect process and absorbs thermal stress by using the deformation process of the interconnect material units during the connection process, thereby reducing or avoiding the problem of warping and deformation of the wafer due to thermal stress during the interconnect process, while reducing the thermal resistance of the IGCT device and improving the reliability of the packaging structure of the IGCT device. Description of the Drawings

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0038] Figure 1 It is a flowchart of the packaging method of the IGCT device provided by an embodiment of the present application.

[0039] Figure 2 It is a schematic structural diagram corresponding to the step of forming a patterned interconnect material layer on the electrode surface in the packaging method of the IGCT device provided by an embodiment of the present application.

[0040] Figure 3 It is a schematic structural diagram corresponding to the case where the shape of the set trajectory is a concentric circular ring in the packaging method of the IGCT device provided by an embodiment of the present application.

[0041] Figure 4 It is a schematic structural diagram corresponding to the case where the shape of the set trajectory is a grid-like pattern in the packaging method of the IGCT device provided by an embodiment of the present application.

[0042] Figure 5 It is a schematic structural diagram corresponding to the case where the shape of the set trajectory is a radial pattern in the packaging method of the IGCT device provided by an embodiment of the present application.

[0043] Figure 6 It is a schematic structural diagram of the step of deforming the interconnect material unit to connect the wafer and the electrode in the packaging method of the IGCT device provided by an embodiment of the present application.

[0044] Description of the reference numerals: 200 - electrode; 210 - interconnect material layer; 220 - wafer; X1, X2 - interconnect material units; a - first top surface; b - second top surface. Detailed Embodiments

[0045] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present application is more thorough and comprehensive.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used in the specification of this application herein are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0047] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type or part discussed below may be referred to as the second element, component, region, layer or part; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types. For example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0048] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. can be used herein to describe the relationship of one element or feature shown in the figures with other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the attached drawings is flipped, an element or feature described as "under other elements" or "beneath them" or "under it" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both the upper and lower orientations. In addition, the device may also include additional orientations (such as rotating 90 degrees or other orientations), and the spatial descriptors used herein are accordingly interpreted.

[0049] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that terms such as "comprises / include" or "has" etc. specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0050] In a general semiconductor manufacturing process, a nano-silver low-temperature bonding technology with excellent heat transfer performance is usually adopted for the whole-wafer packaging of GCT devices or other power devices to significantly reduce the thermal resistance of semiconductor devices. However, when using the low-temperature bonding technology for the whole-wafer packaging of semiconductor devices, problems such as serious warping and deformation of the samples may occur, and in severe cases, it may even affect the thermal resistance optimization effect and the long-term reliability of semiconductor devices.

[0051] In view of this, the present application provides a packaging method for an IGCT device and a packaging structure for an IGCT device to reduce or avoid warping deformation or thermal stress deformation problems during the interconnection process of the wafer, thereby improving the reliability of the packaging structure of the IGCT device while reducing the thermal resistance of the IGCT device.

[0052] Figure 1 It is a flowchart of the packaging method for an IGCT device provided by an embodiment of the present application. Refer to Figure 1 , the packaging method for an IGCT device provided by the embodiment of the present application includes the following steps S1 to step S4.

[0053] Step S1: Provide an electrode and a wafer.

[0054] Exemplarily, the material of the electrode is a metal material or an alloy material. For example, the material of the electrode includes one of metallic copper, metallic molybdenum, molybdenum-copper alloy, tungsten-copper alloy, and copper diamond. Exemplarily, the material of the wafer includes single-crystalline silicon or silicon carbide.

[0055] Step S2: Form a patterned interconnect material layer on the surface of the electrode. The interconnect material layer includes a plurality of spaced-apart interconnect material units.

[0056] Step S3: Dispose the wafer on a side of the interconnect material layer away from the electrode.

[0057] Step S4: Adopt a bonding process or a welding process to deform the interconnect material units to connect the wafer and the electrode; wherein, at least two adjacent and deformed interconnect material units are partially connected.

[0058] It should be noted that during the process of Step S4, the thermal stress of the interconnect material layer is released as the interconnect material units deform and spread; meanwhile, since the adjacent interconnect material units are spaced apart, the interconnect material units have sufficient space to release the thermal stress, thereby reducing or avoiding the warping deformation problem of the IGCT device caused by excessive thermal stress.

[0059] Meanwhile, it should be emphasized that the specific process method for deforming the interconnect material units to connect the wafer and the electrode can be adjusted according to actual process requirements. Those skilled in the art can select a suitable interconnect process according to the operation difficulty and other actual factors, as long as it is ensured that the selected process can meet the technical effects of "connecting the wafer and the electrode through the interconnect material layer" and "the interconnect material units can reduce or eliminate the thermal stress through deformation during the connection process". This application does not limit this.

[0060] It can be seen that for the packaging method of the IGCT device as described above, by forming a patterned interconnect material layer on the electrode and then connecting the interconnect material layer with the wafer, an effective connection between the wafer and the electrode is achieved; by forming a patterned interconnect material layer with a plurality of spaced-apart interconnect material units, a space for releasing thermal stress is provided during the interconnect process, and the thermal stress is absorbed by the deformation process of the interconnect material units during the connection process, thereby reducing or avoiding the problem that the wafer warps and deforms due to thermal stress during the interconnect process, while reducing the thermal resistance of the IGCT device and improving the reliability of the packaging structure of the IGCT device.

[0061] Refer to Figure 2, in one embodiment, the process of forming the patterned interconnect material layer 210 on the surface of the electrode 200 includes: arranging each interconnect material unit X1 on the surface of the electrode 200 according to a set trajectory to form the interconnect material layer 210, thereby improving the accuracy and uniformity of the arrangement positions of the interconnect material units X1 on the electrode 200, and further reducing or even avoiding the probability that the position deviation of the interconnect material units X1 has a negative impact on the stress relaxation ability of the interconnect material layer 210.

[0062] In one embodiment, the interconnect material units are cylindrical or frustum-shaped; wherein, when the interconnect material units are cylindrical, the ratio of the area of the cross-section of the interconnect material unit parallel to the electrode to the height of the interconnect material unit ranges from 0.5 to 1; when the interconnect material units are frustum-shaped (see Figure 2 ), the interconnect material unit X1 includes a first top surface a and a second top surface b parallel to the electrode 200, and the ratio of the average value of the areas of the first top surface a and the second top surface b to the height of the interconnect material unit X1 (i.e., Figure 2 the first height H1 in is in the range of 0.5 to 1, that is, is the area of the first top surface a, is the area of the second top surface b). It should be noted that in other embodiments of the present application, the specific shapes and dimensional parameters of the interconnect material units can be adjusted according to actual needs, and the present application does not limit this.

[0063] In one embodiment, the material of the interconnect material units has conductivity. Preferably, the material of the interconnect material units includes one of tin-based materials, brazing-based materials, and nano-silver to ensure that the interconnect material layer has good conductivity, thereby ensuring the stable performance of the packaging structure of the IGCT device.

[0064] Continuing to refer to Figure 2 , in one embodiment, the orthographic projection area of the interconnect material layer 210 facing the electrode 200 is 80% to 90% of the total area of the electrode 200 to ensure that the interconnect material layer 210 has sufficient stress relaxation space while ensuring that the electrical conductivity and thermal conductivity of the semiconductor device after the interconnect process meet the process requirements.

[0065] In one embodiment, the distance between adjacent two interconnect material units ranges from 50 μm to 100 μm to provide sufficient deformation space and stress relaxation space for the interconnect material units in the subsequent interconnect process, thereby reducing or even avoiding the warping deformation problem caused by thermal stress in the subsequent interconnect process.

[0066] In one embodiment, during the process of arranging all the interconnect material units on the surface of the electrode according to a set track, the shape of the set track can be set as at least one of a concentric circular ring shape, a spiral shape, a radial pattern, and a grid pattern. Alternatively, the shape of the set track can also be a track pattern formed by combining several common geometric figures, so as to disperse the thermal stress suffered by the wafer during the interconnect process by adjusting the distribution modes of different interconnect material units, thereby reducing or even eliminating the warping deformation problem caused by thermal stress.

[0067] It should be emphasized that the specific shape of the set track can be comprehensively considered in combination with factors such as the size parameters of the wafer and the electrode, relevant process requirements, the difficulty of setting the interconnect material layer according to the set track, and the absorption effect of different track patterns on thermal stress, so as to select a suitable set track pattern to prepare the interconnect material layer. This application does not limit this. When selecting the set track, those skilled in the art only need to ensure that the interconnect material layer formed according to the set track satisfies the two conditions of "the orthographic projection area of the interconnect material layer facing the electrode is 80% - 90% of the total area of the electrode" and "the interconnect material layer after interconnecting does not overflow from the area between the wafer and the electrode".

[0068] In one embodiment, the set track can be symmetrically arranged on the surface of the electrode based on a central axis, where the central axis is parallel to the surface of the electrode and passes through the geometric center of the electrode. Exemplarily, when the shape of the set track is a concentric circular ring shape (refer to Figure 3 ), a grid pattern (refer to Figure 4 ), or a radial pattern (refer to Figure 5 ), the set track is symmetrically arranged on the surface of the electrode 200 along the central axis MN, so as to improve the distribution uniformity of the interconnect material unit X1 on the electrode 200, thereby using the interconnect material unit X1 to evenly absorb the thermal stress of each part of the wafer (not shown in the figure) and improving the thermal stress absorption effect of the interconnect material layer.

[0069] Refer to Figure 3 , in the case where the shape of the set track is a concentric circular ring shape, the diameter of each circular ring track can be set according to the thermal stress distribution of the wafer, so as to relieve the thermal stress of different parts of the wafer specifically, thereby reducing or avoiding the risk of the wafer being deformed due to thermal stress.

[0070] Refer to Figure 4 , in the case where the shape of the set track is a grid pattern, the length and width of each grid pattern can be set according to the thermal stress distribution of the wafer, so as to improve the thermal stress dispersion effect and dispersion uniformity of the interconnect material layer, thereby reducing or avoiding the risk of the wafer being deformed due to thermal stress.

[0071] Refer to Figure 5, when the shape of the set track is a radial pattern, the pattern density of the radial pattern can be set according to the thermal stress distribution of the wafer, so as to improve the thermal stress dispersion effect and dispersion uniformity of the interconnect material layer, thereby reducing or avoiding the risk of deformation of the wafer caused by thermal stress.

[0072] It should be noted that in the set track as described above and other set tracks that meet the process requirements, the distance between any two adjacent interconnect material units in the direction parallel to the electrode surface is between 50 μm and 100 μm, so as to ensure that each interconnect material unit has sufficient deformation space.

[0073] In one embodiment, the interconnect material units can be disposed on the electrode surface along the set track with the aid of a special tool to improve the setting efficiency and accuracy of the interconnect material units. Among them, the special tool includes one of a wire mesh, a dispenser or a coater.

[0074] Continue to refer to Figure 2 , in one embodiment, after providing an electrode 200 and a wafer 220 (i.e., after step S1), and before forming a patterned interconnect material layer 210 on the surface of the electrode 200 (i.e., before step S2), the packaging method of the IGCT device further includes: performing a pre-metallization treatment on the wafer 220 and the electrode 200 to form a first pre-metal layer (not shown in the figure) covering the wafer 220 and a second pre-metal layer (not shown in the figure) covering the electrode 200. Among them, the first pre-metal layer covers the surface of the wafer 220 close to the electrode 200, and the second pre-metal layer covers the surface of the electrode 200 close to the wafer 220, thereby improving the connection effect between the wafer 220 and the electrode 200 in the interconnect process.

[0075] It should be noted that the materials of the first pre-metal layer and the second pre-metal layer have bondability with the material of the interconnect material unit. Optionally, the materials of the first pre-metal layer and the second pre-metal layer include at least one of silver metal and gold metal.

[0076] In one embodiment, the first pre-metal layer, the second pre-metal layer and the interconnect material unit are made of at least one material. Exemplarily, when the materials selected for the first pre-metal layer, the second pre-metal layer and the interconnect material unit are not completely the same, for example, when the materials of the first pre-metal layer and the second pre-metal layer are the same and different from the material of the interconnect material unit, or, for example, when the materials of the first pre-metal layer, the second pre-metal layer and the interconnect material unit are all different, due to the bondability between the materials of the first pre-metal layer, the second pre-metal layer and the interconnect material unit, therefore, the three can still be connected to each other through the bonding process, thereby ensuring the yield and stability of the packaging structure of the IGCT device structure.

[0077] Exemplarily, when the first pre-metal layer, the second pre-metal layer, and the interconnect material unit are made of the same material (for example, all are nano-silver materials), since the bonding effect is optimal when the same metal materials are bonded to each other, therefore, the bonding effect between the respective film layers in the package structure of the IGCT device fabricated at this time is the best.

[0078] Referring to Figure 6 , in one embodiment, the wafer 220 is disposed on the interconnect material layer 210; by using a bonding process or a soldering process, the interconnect material unit X2 is deformed (the interconnect material unit is deformed from Figure 2 X1 in Figure 6 to X2 in

[0079] ), so as to connect the wafer 220 and the electrode 200, thereby effectively reducing the thermal resistance of the semiconductor device; wherein, at least two adjacent interconnect material units X2 after deformation are at least partially connected (not shown in the figure).

[0080] Correspondingly, continue to refer to Figure 2 and Figure 6 , one embodiment of the present application further provides a package structure of an IGCT device, including an electrode 200, an interconnect material layer 210, and a wafer 220; wherein, the interconnect material layer 210 is located on one side surface of the electrode 200, the interconnect material layer 210 includes a plurality of interconnect material units, and the interconnect material unit has a variable form (for example, Figure 2 X1 in Figure 6 and

[0081] X2 in

[0082] ); the wafer 220 is located on the side of the interconnect material layer 210 away from the electrode 200. The package structure of the IGCT device as described above, by providing a plurality of interconnect material units with variable forms, uses the form change of the interconnect material units to reduce or eliminate the thermal stress generated during the packaging process of the IGCT device, thereby reducing or even avoiding the problems of thermal stress deformation or wafer warpage deformation, and improving the reliability of the package structure of the IGCT device while reducing the thermal resistance.In one embodiment, the material of the electrode is a metal material or an alloy material. For example, the material of the electrode includes one of copper, molybdenum, molybdenum-copper alloy, tungsten-copper alloy, and copper-diamond. Optionally, the material of the wafer includes silicon or silicon carbide.

[0083] Referring to Figure 2 and Figure 6 , in one embodiment, the interconnect material unit has a first form and a second form; wherein, when the interconnect material unit is in the first form (referring to Figure 2 ), the interconnect material unit X1 has a first height H1, and the area of the cross-section of the interconnect material unit X1 parallel to the electrode 200 gradually decreases in the direction away from the surface of the electrode 200 (i.e., the X direction); when the interconnect material unit is in the second form (referring to Figure 6 ), the electrode 200 is connected to the wafer 220, the interconnect material unit X2 has a second height H2, and the second height H2 is less than the first height H1, that is, H2 < H1.

[0084] It should be noted that during the process of the interconnect material unit changing from the first form to the second form, the thermal stress of the interconnect material layer is released as the interconnect material unit deforms and spreads; at the same time, the multiple interconnect material units are arranged at intervals, which can provide enough space for the interconnect material unit to release the thermal stress, thereby avoiding the problem of warping deformation of the packaging structure of the IGCT device due to excessive thermal stress.

[0085] In one embodiment, the first form of the interconnect material unit is cylindrical or frustum-shaped; wherein, when the interconnect material unit is cylindrical, the ratio of the area of the cross-section of the interconnect material unit parallel to the electrode to the height of the interconnect material unit ranges from 0.5 to 1; when the interconnect material unit is frustum-shaped (referring to Figure 2 ), the interconnect material unit X1 includes a first top surface a and a second top surface b parallel to the electrode 200, and the ratio of the average value of the areas of the first top surface a and the second top surface b to the first height H1 of the interconnect material unit X1 ranges from 0.5 to 1, that is, (where is the area of the first top surface a, is the area of the second top surface b). It should be noted that in other embodiments of the present application, the specific shape and size parameters of the interconnect material unit can be adjusted according to actual needs, and the present application does not limit this.

[0086] In one embodiment, the projected area of the interconnect material layer facing the electrode is 80% - 90% of the total area of the electrode, so as to ensure that while the interconnect material layer has enough stress release space, the packaging structure of the IGCT device meets the process requirements in both electrical conductivity and thermal conductivity.

[0087] In one embodiment, the distance between two adjacent interconnect material units (in the first form) ranges from 50 μm to 100 μm to ensure sufficient stress release space within the interconnect material layer. Optionally, the material of the interconnect material unit has conductivity. Preferably, the material of the interconnect material unit includes one of a tin-based material, a solder-based material, and nano silver.

[0088] In one embodiment, the interconnect material units in the first form are arranged in the interconnect material layer along a set trajectory. The shape of the set trajectory can be set as at least one of a concentric circular ring, a spiral, a radial pattern, and a grid pattern. Alternatively, the shape of the set trajectory can also be a trajectory pattern formed by combining several common geometric figures, so as to disperse the thermal stress received by the wafer during the interconnect process by adjusting the distribution mode of different interconnect material units, thereby reducing or even eliminating the warping deformation problem caused by thermal stress. The specific shape and setting rules of the set trajectory have been discussed in detail in the foregoing content, and are not elaborated herein in this application.

[0089] In one embodiment, a first pre-metal layer (not shown in the figure) is further provided on the surface of the wafer close to the electrode side, and a second pre-metal layer (not shown in the figure) is provided on the surface of the electrode close to the wafer side, and the second pre-metal layer covers the interconnect material layer on the electrode to improve the connection effect between the wafer and the electrode. It should be noted that the materials of the first pre-metal layer and the second pre-metal layer have bondability with the material of the interconnect material unit. Optionally, the materials of the first pre-metal layer and the second pre-metal layer include at least one of metallic silver and metallic gold.

[0090] In one embodiment, the first pre-metal layer, the second pre-metal layer, and the interconnect material unit are made of at least one material. Exemplarily, when the materials selected for the first pre-metal layer, the second pre-metal layer, and the interconnect material unit are not completely the same, for example, when the materials of the first pre-metal layer and the second pre-metal layer are the same, and the materials of the two are different from the material of the interconnect material unit, or, for example, when the materials of the first pre-metal layer, the second pre-metal layer, and the interconnect material unit are all different, due to the bondability between the materials of the first pre-metal layer, the second pre-metal layer, and the interconnect material unit, therefore, the three can still be interconnected through a bonding process, thereby ensuring the yield and stability of the packaging structure of the IGCT device.

[0091] Exemplarily, when the first pre-metal layer, the second pre-metal layer, and the interconnect material unit select the same material (such as all being nano silver materials), since the bonding effect is optimal when the same metal materials are bonded to each other, therefore, the bonding effect between the respective film layers in the packaging structure of the IGCT device made at this time is the best.

[0092] The present application also provides a packaging structure of an IGCT device, which is made by using the packaging method of the IGCT device as described above. Since the packaging structure of the IGCT device made by using the packaging method of the IGCT device has been described in detail above, the present application will not elaborate herein. At the same time, it should be emphasized that the packaging structure of the IGCT device made by using the packaging method of the IGCT device provided by the present application reduces or eliminates the thermal stress generated during the interconnection process of the wafer and the electrode by utilizing the morphological change of the interconnection material unit, thereby avoiding the problems of thermal stress deformation or wafer warpage deformation and improving the reliability of the packaging structure of the IGCT device.

[0093] The packaging method of the IGCT device and the packaging structure of the IGCT device provided by the embodiments of the present application realize the effective connection between the wafer and the electrode by forming a patterned interconnection material layer on the electrode and then connecting the interconnection material layer to the wafer; a patterned interconnection material layer is formed by a plurality of spaced-apart interconnection material units, which provides a space for releasing thermal stress during the interconnection process, and absorbs the thermal stress by utilizing the deformation process of the interconnection material units during the connection process, thereby reducing or avoiding the problem of the wafer warping and deforming due to thermal stress during the interconnection process, and improving the reliability of the packaging structure of the IGCT device without affecting the thermal resistance optimization effect.

[0094] It should be understood that although the steps in the above flowcharts are shown in sequence according to the illustration, these steps are not necessarily executed in the order shown in the illustration. Unless there is a clear indication in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, at least a part of the steps in each figure may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least a part of other steps or steps in other steps.

[0095] In the description of this specification, the descriptions referring to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. mean that the specific features, structures, materials or features described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0096] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered that the scope described in this specification.

[0097] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A packaging method for an IGCT device, characterized in that: include: providing an electrode and a wafer; forming a patterned interconnect material layer on the surface of the electrode, wherein the interconnect material layer comprises a plurality of interconnect material units arranged at intervals; placing the wafer on a side of the interconnect material layer away from the electrode; Using a bonding process or a welding process to deform the interconnect material unit so as to connect the wafer and the electrode; wherein at least two adjacently disposed and deformed interconnected material units are partially connected; The step of forming a patterned interconnect material layer on the surface of the electrode comprises: Arranging each of the interconnect material units on the surface of the electrode according to a set track to form the interconnect material layer; The set trajectory is symmetrically arranged on the surface of the electrode based on a central axis, and the central axis is parallel to the surface of the electrode and passes through the geometric center of the electrode.

2. The packaging method of the IGCT device according to claim 1, characterized in that: The shape of the set trajectory includes at least one of a concentric ring shape, a spiral shape, a radial shape, and a grid shape.

3. The packaging method of the IGCT device according to claim 1, characterized in that: The distance between two adjacent interconnection material units ranges from 50 μm to 100 μm.

4. The packaging method of the IGCT device according to claim 1, characterized in that: The orthographic projection area of ​​the interconnect material layer toward the electrode is 80% to 90% of the total area of ​​the electrode.

5. The packaging method of the IGCT device according to claim 1, characterized in that: After providing an electrode and a wafer, and before forming a patterned interconnect material layer on the surface of the electrode, the packaging method of the IGCT device includes: The wafer and the electrode are pre-metallized to form a first pre-metal layer covering the wafer and a second pre-metal layer covering the electrode, wherein the first pre-metal layer covers the surface of the wafer close to the electrode, and the second pre-metal layer covers the surface of the electrode close to the wafer.

6. The packaging method of the IGCT device according to claim 5, characterized in that: The materials of the first pre-metal layer and the second pre-metal layer are bondable with the material of the interconnection material unit.

7. The packaging method of the IGCT device according to claim 6, characterized in that: The materials of the first pre-metal layer and the second pre-metal layer include at least one of metal gold and metal silver.

8. The packaging method of the IGCT device according to claim 6 or 7, characterized in that: The first pre-metal layer, the second pre-metal layer and the interconnect material unit are made of at least one material.

9. The packaging method of the IGCT device according to claim 1 or 6, characterized in that: The material of the interconnection material unit has conductivity.

10. The packaging method of the IGCT device according to claim 9, characterized in that: The material of the interconnection material unit includes one of a tin-based material and a nano-silver material.

11. A packaging structure of an IGCT device, characterized in that: The IGCT device is manufactured by the packaging method of any one of claims 1 to 10.

12. A packaging structure of an IGCT device, manufactured by the packaging method of an IGCT device according to any one of claims 1 to 10, characterized in that: include: electrode; An interconnect material layer, located on one side surface of the electrode; wherein the interconnect material layer comprises a plurality of interconnect material units; the interconnect material units have a variable shape; The wafer is located on a side of the interconnect material layer away from the electrode.

13. The packaging structure of the IGCT device according to claim 12, characterized in that: The interconnect material unit has a first form and a second form; wherein, When the interconnect material unit is in the first form, the interconnect material unit has a first height, and an area of ​​a cross section of the interconnect material unit parallel to the electrode gradually decreases in a direction away from the surface of the electrode; When the interconnect material unit is in the second form, the electrode is connected to the wafer, and the interconnect material unit has a second height, and the second height is smaller than the first height.

14. The packaging structure of the IGCT device according to claim 12, characterized in that: The shapes of the interconnected material units include cylindrical and truncated cone; When the interconnect material unit is cylindrical, a ratio of an area of ​​a cross section of the interconnect material unit parallel to the electrode to a height of the interconnect material unit is in a range of 0.5 to 1; When the interconnect material unit is in a truncated cone shape, the interconnect material unit includes a first top surface and a second top surface parallel to the electrode, and a ratio of an average area of ​​the first top surface and the second top surface to a height of the interconnect material unit is in a range of 0.5 to 1.

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