Manufacturing method of semiconductor structure and semiconductor structure

Abstract

The invention provides a manufacturing method of a semiconductor structure and the semiconductor structure. The manufacturing method comprises the following steps: forming an intermediate structure, wherein the intermediate structure comprises a carrier plate, a conductive frame and a to-be-packaged structure; the bearing part of the conductive frame and the conductive column are mounted on the carrier plate; the to-be-packaged structure is located on the bearing part and comprises at least one electrical element, and an electrode of the to-be-packaged structure is electrically connected with the bearing part; forming a plastic package layer, wherein the plastic package layer packages the conductive frame and the to-be-packaged structure; removing the carrier plate, wherein the surface, away from the to-be-packaged structure, of the bearing part and the surface, located on the same side, of the conductive column are exposed; a first chip is arranged on the side, away from the to-be-packaged structure, of the bearing part, a plurality of welding pads are arranged on the front face of the first chip, and the back face of the chip faces the bearing part; forming an insulating layer, wherein the insulating layer at least covers the chip side surface of the first chip; and forming a re-wiring layer on one side, far away from the plastic packaging layer, of the insulating layer, wherein the re-wiring layer is electrically connected with the welding pad and is electrically connected with the electrical element through the conductive frame.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art

[0002] Common semiconductor packaging technologies, such as system-level packaging technology, mainly include the following process: first, the front side of the chip is bonded to the carrier and hot-pressed to form a plastic layer; then the board is transferred and a rewiring layer is formed on the front side of the chip; then an insulating layer covering the rewiring layer is formed; then the board is transferred and a rewiring layer is formed on the plastic layer; then the carrier is separated and the obtained structure is cut; then the cut structure is mounted on the carrier and electrical components are welded on the rewiring layer; then an encapsulation layer encapsulating the electrical components is formed. The transfer of the board refers to separating the intermediate structure on the carrier from the carrier and re-mounting it on another carrier to change the exposed surface of the intermediate structure.

[0003] The above-mentioned semiconductor packaging process requires multiple board transfers, and the preparation process is complicated and the preparation cost is high. Summary of the invention

[0004] Embodiments of the present application provide a method for manufacturing a semiconductor structure and a semiconductor structure.

[0005] In a first aspect of an embodiment of the present application, a method for manufacturing a semiconductor structure is provided, the method comprising:

[0006] An intermediate structure is formed, wherein the intermediate structure includes a carrier, a conductive frame and a structure to be packaged; the conductive frame includes a bearing portion and a conductive column, and the bearing portion and the conductive column are mounted on the carrier; the structure to be packaged includes at least one electrical component, the structure to be packaged includes an electrode, the structure to be packaged is located on the bearing portion, and the electrode of the structure to be packaged is electrically connected to the bearing portion;

[0007] forming a plastic encapsulation layer, wherein the plastic encapsulation layer encapsulates the conductive frame and the structure to be encapsulated;

[0008] The carrier is removed, and the surface of the carrier portion away from the structure to be packaged and the surface of the conductive pillar located on the same side are exposed;

[0009] A first chip is arranged on a side of the carrier away from the structure to be packaged, the first chip comprising a chip front, a chip back opposite to the chip front, and a chip side surface connecting the chip front and the chip back, the chip front is provided with a plurality of pads; the chip back faces the carrier;

[0010] forming an insulating layer, wherein the insulating layer at least covers a side surface of the chip;

[0011] A rewiring layer is formed on a side of the insulating layer away from the plastic encapsulation layer. The rewiring layer is electrically connected to the pad and is electrically connected to the electrode of the structure to be packaged through the conductive frame.

[0012] In one embodiment, forming the intermediate structure comprises:

[0013] Arranging the structure to be packaged on the bearing part of the conductive frame, and welding the electrodes of the structure to be packaged to the bearing part by using a reflow soldering process;

[0014] An adhesive layer is arranged on the carrier board, and the conductive frame is attached to the carrier board through the adhesive layer.

[0015] In one embodiment, mounting the conductive frame on the carrier through an adhesive layer includes:

[0016] The plurality of conductive frames are mounted on the carrier through an adhesive layer.

[0017] In one embodiment, the orthographic projection of the first chip on the conductive frame entirely falls on the conductive frame.

[0018] In one embodiment, after forming the plastic encapsulation layer, the method for manufacturing the semiconductor structure further includes:

[0019] The surface of the plastic packaging layer away from the bearing portion is thinned to expose the surface of the conductive column away from the bearing portion.

[0020] In one embodiment, the first chip is arranged on a side of the carrier away from the structure to be packaged, including:

[0021] A conductive material is disposed on a surface of the conductive frame and a surface of the bearing portion that are located on the same side away from the structure to be packaged, wherein the conductive material includes at least one of silver paste and solder paste;

[0022] The first chip is placed on the conductive material, and the conductive material is cured.

[0023] In one embodiment, the structure to be packaged is arranged on the bearing portion of the conductive frame, and the electrodes of the structure to be packaged are welded to the bearing portion using a reflow soldering process, including:

[0024] Using a screen printing process to arrange solder on the bearing portion;

[0025] The structure to be packaged is placed on the solder, and the electrodes of the structure to be packaged are welded to the supporting part by using a reflow soldering process.

[0026] In one embodiment, the structure to be packaged includes only the electrical component, the electrical component is a passive device, and the electrodes of the structure to be packaged are pins of the electrical component; the passive device includes at least one of an inductor, a resistor and a capacitor.

[0027] In one embodiment, the structure to be packaged also includes an encapsulation layer that encapsulates the electrical component and a conductive structure that exposes the encapsulation layer, the conductive structure is an electrode of the structure to be packaged, and the conductive structure is electrically connected to the pin of the electrical component; the electrical component includes at least one of an inductor, a resistor, a capacitor and a second chip.

[0028] In one embodiment, the conductive frame includes a conductive block; the redistribution layer includes a plurality of trace structures, and at least two of the trace structures are electrically connected to the same conductive block through through holes penetrating the insulating layer.

[0029] According to a second aspect of an embodiment of the present application, a semiconductor structure is provided, wherein the semiconductor structure comprises:

[0030] A conductive frame, comprising a bearing portion and a conductive column;

[0031] A packaging structure, comprising at least one electrical component, the packaging structure being located on the carrier, the packaging structure comprising electrodes, and the electrodes of the packaging structure being welded to the carrier;

[0032] A plastic encapsulation layer encapsulating the conductive frame and the packaging structure, wherein a surface of the bearing portion away from the packaging structure and a surface of the conductive column on the same side are exposed;

[0033] A first chip is located on a side of the carrier away from the packaging structure; the first chip comprises a chip front, a chip back opposite to the chip front, and a chip side connecting the chip front and the chip back, the chip front is provided with a plurality of pads; the chip back faces the carrier;

[0034] An insulating layer, covering at least a side surface of the chip;

[0035] The rewiring layer is located on a side of the insulating layer away from the plastic packaging layer. The rewiring layer is electrically connected to the welding pad and is electrically connected to the electrode of the packaging structure through the conductive frame.

[0036] The main technical effects achieved by the embodiments of the present application are:

[0037] The manufacturing method and semiconductor structure of the semiconductor structure provided in the embodiments of the present application, when manufacturing the semiconductor structure, firstly form an intermediate structure, the conductive frame of the intermediate structure is mounted on a carrier, the structure to be packaged is located on the carrier part, and the electrode of the structure to be packaged is electrically connected to the carrier part, and then a plastic sealing layer is formed to encapsulate the conductive frame and the structure to be packaged, after removing the carrier, the surface of the carrier part away from the structure to be packaged and the surface on the same side of the conductive column are exposed; since the first chip, the insulating layer and the rewiring layer are all located on the side of the carrier part away from the structure to be packaged, there is no need to transfer the board in the steps of setting the first chip, forming the insulating layer and forming the rewiring layer, that is, only one transfer is required in the manufacturing process of the semiconductor structure, which can simplify the process steps and reduce the manufacturing cost; since the conductive frame is prefabricated, the thickness of the carrier part and the size of the conductive column can be set to be larger, which helps to improve the heat dissipation capacity of the semiconductor structure and reduce the internal resistance of the semiconductor structure, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 is a flow chart of a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application;

[0039] Figure 2 is a partial cross-sectional view of a first intermediate structure provided by an exemplary embodiment of the present application;

[0040] Figure 3 is a partial cross-sectional view of a second intermediate structure provided by an exemplary embodiment of the present application;

[0041] Figure 4 is a partial cross-sectional view of a third intermediate structure provided by an exemplary embodiment of the present application;

[0042] Figure 5 is a partial cross-sectional view of a fourth intermediate structure provided by an exemplary embodiment of the present application;

[0043] Figure 6 is a partial cross-sectional view of a fifth intermediate structure provided by an exemplary embodiment of the present application;

[0044] Figure 7 is a partial cross-sectional view of a sixth intermediate structure provided by an exemplary embodiment of the present application;

[0045] Figure 8 is a partial cross-sectional view of a seventh intermediate structure provided by an exemplary embodiment of the present application;

[0046] Fig. 9 is a partial cross-sectional view of an eighth intermediate structure provided by an exemplary embodiment of the present application;

[0047] Fig.10 is a partial cross-sectional view of a ninth intermediate structure provided by an exemplary embodiment of the present application;

[0048] Fig.11 is a partial cross-sectional view of a tenth intermediate structure provided by an exemplary embodiment of the present application;

[0049] Fig.12 is a cross-sectional view of a semiconductor structure provided by an exemplary embodiment of the present application;

[0050] Fig.13 is a cross-sectional view of a semiconductor structure provided by another exemplary embodiment of the present application. Specific embodiments

[0051] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0052] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0053] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0054] Some embodiments of the present application are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0055] The present application provides a method for manufacturing a semiconductor structure. Figure 1 As shown, the manufacturing method includes the following steps 110 to 160.

[0056] In step 110, an intermediate structure is formed, which includes a carrier, a conductive frame and a structure to be packaged; the conductive frame includes a bearing portion and a conductive column, and the bearing portion and the conductive column are mounted on the carrier; the structure to be packaged includes at least one electrical component, and the structure to be packaged includes an electrode, the structure to be packaged is located on the bearing portion, and the electrode of the structure to be packaged is electrically connected to the bearing portion.

[0057] In step 120 , a plastic encapsulation layer is formed, wherein the plastic encapsulation layer encapsulates the conductive frame and the structure to be encapsulated.

[0058] In step 130 , the carrier is removed, and a surface of the carrier portion away from the structure to be packaged and a surface of the conductive pillar located on the same side are exposed.

[0059] In step 140, a first chip is arranged on a side of the carrier portion away from the structure to be packaged, the first chip including a chip front side, a chip back side opposite to the chip front side, and a chip side side connecting the chip front side and the chip back side, the chip front side is provided with a plurality of solder pads; the chip back side faces the carrier portion.

[0060] In step 150 , an insulating layer is formed, wherein the insulating layer at least covers the side surface of the chip.

[0061] In step 160, a rewiring layer is formed on a side of the insulating layer away from the plastic encapsulation layer, the rewiring layer is electrically connected to the pad, and is electrically connected to the electrode of the structure to be packaged through the conductive frame.

[0062] The manufacturing method of the semiconductor structure provided in the embodiment of the present application first forms an intermediate structure, in which a conductive frame is mounted on a carrier, the structure to be packaged is located on a bearing portion, and the electrode of the structure to be packaged is electrically connected to the bearing portion, and then a plastic sealing layer is formed to encapsulate the conductive frame and the structure to be packaged, and after removing the carrier, the surface of the bearing portion away from the structure to be packaged and the surface on the same side where the conductive column is located are exposed; since the first chip, the insulating layer and the rewiring layer are all located on the side of the bearing portion away from the structure to be packaged, there is no need to transfer the plate in the steps of setting the first chip, forming the insulating layer and forming the rewiring layer, that is, only one transfer is required in the manufacturing process of the semiconductor structure, which can simplify the process steps and reduce the manufacturing cost; since the conductive frame is prefabricated, the thickness of the bearing portion and the size of the conductive column can be set to be larger, which helps to improve the heat dissipation capacity of the semiconductor structure and reduce the internal resistance of the semiconductor structure, thereby improving the performance of the semiconductor structure.

[0063] The following is a detailed introduction to each step of the method for manufacturing a semiconductor structure provided in an embodiment of the present application.

[0064] In step 110, an intermediate structure is formed, which includes a carrier, a conductive frame and a structure to be packaged; the conductive frame includes a bearing portion and a conductive column, and the bearing portion and the conductive column are mounted on the carrier; the structure to be packaged includes at least one electrical component, and the structure to be packaged includes an electrode, the structure to be packaged is located on the bearing portion, and the electrode of the structure to be packaged is electrically connected to the bearing portion.

[0065] In one embodiment, the step of forming the intermediate structure may include the following process:

[0066] First, the structure to be packaged is arranged on the bearing part of the conductive frame, and the electrodes of the structure to be packaged are welded to the bearing part by using a reflow soldering process.

[0067] Through this step, we can obtain Figure 2 The first intermediate structure shown. Figure 2 As shown, the conductive frame 10 includes a carrier 11, a conductive column 12 and a conductive block 13, each carrier 11 is connected to a conductive column 12; the conductive block 13 can be connected to the carrier 11 or the conductive column 12; a structure to be packaged 20 can be located on multiple carriers 11, and the electrodes of the structure to be packaged 20 are welded to the carrier 11 through solder 22. Specifically, the structure to be packaged 20 may include multiple electrodes, each of which is welded to a carrier 11. The surface of the structure to be packaged 20 and the conductive column 12 away from the carrier 11 is located on the same side of the carrier 11.

[0068] Subsequently, an adhesive layer is provided on the carrier, and the conductive frame is attached to the carrier through the adhesive layer.

[0069] Through this step, we can obtain Figure 3 The second intermediate structure shown is the intermediate structure described in step 110. Figure 3 As shown, the conductive frame 10 is mounted on the carrier 32 through the adhesive layer 31; the distance between the surface of the structure 20 to be packaged and away from the carrier 32 is smaller than the distance between the surface of the conductive column 12 to be packaged and away from the carrier 32, so that in the subsequent steps, after the plastic sealing layer is formed, the plastic sealing layer is thinned to expose the surface of the conductive column 12 away from the carrier 32, and the structure 20 to be packaged can be avoided from being damaged. In some embodiments, the adhesive layer 31 can be made of an easily peelable material so that the carrier 32 can be peeled off later. For example, the adhesive layer 31 can be a thermal release film layer, which can lose its viscosity by heating.

[0070] In the present embodiment, the electrode of the structure to be packaged 20 in the structure to be packaged is first welded to the bearing portion 11 of the conductive frame 10, and then the conductive frame 10 is mounted on the carrier 32 through the adhesive layer 31. Compared with the solution of first mounting the conductive frame 10 on the carrier and then welding the structure to be packaged and the conductive frame, it can be avoided that the adhesive layer 31 will lose its viscosity due to heat during the welding process, resulting in the carrier being unable to provide support in the reflow soldering process, thereby affecting the reflow soldering process.

[0071] In one embodiment, the conductive frame is made of metal, such as copper, so that the conductive frame has good heat dissipation capability and low resistivity, which is more helpful to improve the heat dissipation capability and internal resistance of the semiconductor structure.

[0072] In one embodiment, Figure 2 and Figure 3 As shown, the structure to be packaged 20 only includes the electrical component 21, which is a passive device. The electrodes of the structure to be packaged 20 are pins of the electrical component 21; the passive device includes at least one of an inductor, a resistor and a capacitor.

[0073] In another embodiment, the structure to be packaged further includes an encapsulation layer encapsulating the electrical component and a conductive structure exposing the encapsulation layer, the conductive structure is an electrode of the structure to be packaged, and the conductive structure is electrically connected to a pin of the electrical component; the electrical component includes at least one of an inductor, a resistor, a capacitor, and a second chip. When the electrical component is a second chip, the pad of the second chip is the pin of the electrical component. The second chip may be of the same type as the first chip or may be of a different type.

[0074] In one embodiment, the step of arranging the structure to be packaged on the bearing portion of the conductive frame and welding the electrodes of the structure to be packaged to the bearing portion using a reflow soldering process comprises the following process:

[0075] First, solder is disposed on the carrier portion by using a screen printing process.

[0076] Subsequently, the structure to be packaged is placed on the solder, and a reflow process is used to weld the electrodes of the structure to be packaged to the supporting part.

[0077] By using the screen printing process to set solder on the bearing part, the area where the solder is set is the area where the structure to be packaged is subsequently welded. Using the screen printing process to set solder can play a role in positioning the structure to be packaged, preventing the setting position of the structure to be packaged from being greatly offset, and improving the position accuracy of the structure to be packaged. The position of the mesh of the screen used in the screen printing process can be determined according to the design position of the structure to be packaged, so as to improve the position accuracy of the solder set on the bearing part.

[0078] In one embodiment, the solder is solder paste, which is easy to remove. If the position of the structure to be packaged is greatly offset, the solder paste between the structure to be packaged and the conductive frame can be removed, and the structure to be packaged can be repositioned and soldered to correct its position.

[0079] In one embodiment, the step of mounting the conductive frame on the carrier through an adhesive layer comprises the following process: mounting a plurality of conductive frames on the carrier through an adhesive layer.

[0080] The size of the conductive frame can be set to be smaller, for example, its size is not greater than 300mm*300mm. In this way, the electrical components can be mounted on the conductive frame using SMT (Surface Mounted Technology). Mounting multiple conductive frames on a carrier board can achieve large-sized board-level packaging, which helps to improve the manufacturing efficiency of semiconductor structures.

[0081] In step 120 , a plastic encapsulation layer is formed, wherein the plastic encapsulation layer encapsulates the conductive frame and the structure to be encapsulated.

[0082] Through step 120, the following can be obtained: Figure 4 The third intermediate structure shown. Figure 4 As shown, the plastic encapsulation layer 40 encapsulates the side of the carrying portion 11, the surface of the carrying portion 11 facing the carrier 32, the side of the conductive column 12, the side of the conductive block 13 and the surface facing the carrier 32, and the surface of the conductive column 12 away from the carrier 32 is flush with the surface of the plastic encapsulation layer 40 away from the carrier 32, that is, the surface of the conductive column 12 away from the carrier 32 is exposed from the plastic encapsulation layer 40; the plastic encapsulation layer 40 encapsulates the side of the structure 20 to be packaged, the surface facing the carrier 32 and the surface away from the carrier 32.

[0083] In one embodiment, the initially formed plastic encapsulation layer can encapsulate the surface of the conductive column away from the carrier. After the plastic encapsulation layer is formed, the method for manufacturing the semiconductor structure further includes: thinning the surface of the plastic encapsulation layer away from the bearing portion to expose the surface of the conductive column away from the bearing portion. The surface of the conductive column away from the bearing portion exposes the plastic encapsulation layer, and the heat dissipation effect of the conductive column is better, which can further improve the heat dissipation capacity of the semiconductor structure. In some embodiments, a grinding process can be used to thin the surface of the plastic encapsulation layer away from the carrier.

[0084] In one embodiment, before forming the plastic encapsulation layer 40, some pre-treatment steps, such as chemical cleaning, plasma cleaning, etc., can be performed to remove impurities on the surface of the conductive frame 10, the structure to be packaged 20 and the bonding layer 31, so that the plastic encapsulation layer 40 can be more closely connected to the conductive frame 10, the structure to be packaged 20 and the bonding layer 31 without delamination or cracking.

[0085] In one embodiment, the material of the plastic encapsulation layer 40 may be a polymer resin, a resin composite material, a polymer composite material, etc. For example, the plastic encapsulation layer 40 may be a resin with a filler, wherein the filler may be an inorganic particle. The plastic encapsulation layer 40 may be formed by injection molding, compression molding, or transfer molding.

[0086] In step 130 , the carrier is removed, and a surface of the carrier portion away from the structure to be packaged and a surface of the conductive pillar located on the same side are exposed.

[0087] In one embodiment, when the adhesive layer 31 is a thermal release film layer, the carrier is removed by heating.

[0088] In one embodiment, after step 130 and before step 140 , the method for manufacturing the semiconductor structure further includes: mounting the structure obtained in step 130 on a carrier, with the exposed surface of the carrier portion being away from the carrier.

[0089] Through this step, we can obtain Figure 5 The fourth intermediate structure shown. Figure 5 As shown, the structure obtained in step 130 is mounted on a carrier 34 via an adhesive layer 33 , and the carrier portion 11 is exposed away from the surface of the structure to be packaged 20 .

[0090] In step 140, a first chip is arranged on a side of the carrier portion away from the structure to be packaged, the first chip including a chip front side, a chip back side opposite to the chip front side, and a chip side side connecting the chip front side and the chip back side, the chip front side is provided with a plurality of solder pads; the chip back side faces the carrier portion.

[0091] Through step 140, the following can be obtained: Figure 6 The fifth intermediate structure shown. Figure 6 As shown, the back side of the first chip 50 faces the carrier 11, and the front side of the first chip 50 is further provided with a protective layer 52, and the protective layer 52 is provided with a plurality of openings 521, and each opening 521 exposes at least a portion of the surface of a pad 51. The openings 521 and the pads 51 may correspond one to one, and each opening 521 exposes the corresponding pad 51.

[0092] In one embodiment, Figure 6As shown, the orthographic projection of the first chip 50 on the conductive frame 10 all falls on the conductive frame 10. Among them, the orthographic projection of the first chip 50 on the conductive frame 10 all falls on the conductive frame 10, which means that the orthographic projection of the first chip 50 on the conductive frame 10 all falls on the physical structure of the conductive frame 10, and the gap between two adjacent structures of the conductive frame 10 does not belong to the physical structure of the conductive frame 10. With this arrangement, the contact area between the first chip 50 and the conductive frame 10 is the largest, which is more conducive to the conductive frame 10 to discharge the heat generated by the first chip 50. Among them, the orthographic projection of part of the back of the chip of the first chip 50 on the conductive frame 10 falls on the bearing portion 11, and the orthographic projection of other areas on the conductive frame 10 falls on the conductive column 12.

[0093] In one embodiment, the step of arranging the first chip on a side of the carrier away from the structure to be packaged includes the following process:

[0094] First, a conductive material is disposed on a surface of the conductive frame and a surface of the bearing portion that are located on the same side away from the structure to be packaged, wherein the conductive material includes at least one of silver paste and solder paste;

[0095] Then, the first chip is placed on the conductive material, and the conductive material is cured.

[0096] In this way, the back side of the first chip 50 is fixed on the conductive frame 10 by silver paste and / or solder paste, so that the first chip 50 can be fixed on the conductive frame 10 more firmly; the silver paste and / or solder paste has good thermal conductivity, which helps to transfer the heat generated by the first chip 50 to the conductive frame 10.

[0097] In step 150 , an insulating layer is formed, wherein the insulating layer at least covers the side surface of the chip.

[0098] Through this step, we can obtain Figure 7 The sixth intermediate structure shown. Figure 7 As shown, the insulating layer 60 covers the chip side and chip front of the first chip 50. When a protection layer 52 is provided on the chip front of the first chip 50, the insulating layer 60 partially fills the opening 521 of the protection layer 52.

[0099] In one embodiment, the insulating layer 60 may be formed by injection molding, compression molding, or transfer molding. In other embodiments, the insulating layer 60 may be formed by coating an insulating material.

[0100] In step 160, a rewiring layer is formed on a side of the insulating layer away from the plastic encapsulation layer, the rewiring layer is electrically connected to the pad, and is electrically connected to the electrode of the structure to be packaged through the conductive frame.

[0101] In one embodiment, before the step of forming a rewiring layer on a side of the insulating layer away from the plastic encapsulation layer, the method for manufacturing the semiconductor structure further comprises the following steps:

[0102] A through hole is formed on the insulating layer and passes through the insulating layer; at least one of the through holes exposes a portion of the surface of the carrier where the electrical component is located, and / or the carrier where the structure to be packaged is located is connected to the conductive column, and at least one of the through holes exposes a portion of the surface of the conductive column connected to the carrier where the structure to be packaged is located.

[0103] Through this step, we can obtain Figure 8 The seventh intermediate structure shown. Figure 8 As shown, the supporting part 11 where the structure to be packaged 20 is located is connected to the conductive pillar 12, the surface portion of the supporting part 11 where the structure to be packaged 20 is located away from the carrier 34 is exposed by the through hole 62, the surface portion of the conductive pillar 12 connected to the supporting part 11 where the structure to be packaged 20 is located away from the carrier 34 is exposed by the through hole 62; the surface portion of the conductive block 13 away from the carrier is exposed by the through hole 62.

[0104] In one embodiment, Figure 8 As shown, the insulating layer 60 is partially located on the surface of the first chip 50 away from the carrier 34, and the manufacturing method of the semiconductor structure further includes the following steps: forming an opening 61 exposing the pad 51 on the insulating layer 60. The opening 61 penetrates the portion of the insulating layer 60 located on the side of the protective layer 52 away from the carrier 34 and the portion of the insulating layer 60 located in the opening 521. The opening 61 and the pad 51 may correspond one to one, and each opening 61 exposes a portion of the corresponding pad 51.

[0105] In one embodiment, the opening 61 and the through hole 62 may be formed by a laser etching process.

[0106] Through step 160, the following can be obtained: Fig. 9 The eighth intermediate structure shown. Fig. 9 As shown, the rewiring layer 70 includes a trace structure 71, the conductive frame 10 is electrically connected to the trace structure 71 via a conductive portion 64 located in the through hole 62, and the pad 51 of the first chip 50 is electrically connected to the trace structure 71 via a conductive portion 63 located in the opening 61, so that the electrical components of the structure 20 to be packaged are electrically connected to the pad 51 of the first chip 50 through the trace structure 71.

[0107] In one embodiment, the conductive portion 64 in the through hole 62 and the conductive portion 63 in the opening 61 and the trace structure 71 can be formed simultaneously in the same process step.

[0108] In one embodiment, at least two of the trace structures 71 are electrically connected to the same conductive block 13 through the through holes 62 penetrating the insulating layer. With such a configuration, among the trace structures electrically connected to the same conductive block 13, as long as there is one trace structure 71 connected to the pad of the first chip, the other trace structures can be electrically connected to the pad of the first chip through the trace structure. Compared with the scheme of setting the conductive block 13 on the same layer as the trace structure 71, the density of the trace structure of the rewiring layer 70 can be reduced, solving the problem of high manufacturing process difficulty caused by the high density of the trace structure of the rewiring layer; since the conductive block 13 is part of the conductive frame, the configuration of the conductive frame simultaneously achieves the effect of reducing the number of board transfers during the manufacturing process, improving the heat dissipation capacity of the semiconductor structure and reducing the internal resistance of the semiconductor structure, and reducing the density of the trace structure of the rewiring layer to simplify the manufacturing process.

[0109] In one embodiment, after step 160, the semiconductor structure further comprises the following step: forming a rewiring structure on a side of the rewiring layer away from the chip, wherein the rewiring structure is electrically connected to the rewiring layer, and the rewiring structure comprises at least one rewiring layer.

[0110] In one embodiment, before the step of forming a rewiring structure on a side of the rewiring layer away from the chip, the method for manufacturing the semiconductor structure further includes the following steps: forming an insulating material layer covering the rewiring layer 70, and forming a through hole on the insulating material layer, wherein a portion of the surface of at least one trace structure 71 is exposed by the through hole.

[0111] Through this step, we can obtain Fig.10 The ninth intermediate structure shown. Fig.10 As shown, the insulating material layer 81 covers the side surfaces of each trace structure 71 of the redistribution layer 70 and the surface away from the carrier 34 . The insulating material layer 81 is formed with a plurality of through holes 811 , and each through hole 811 exposes a portion of the surface of a trace structure 71 .

[0112] By forming a rewiring structure on the side of the rewiring layer away from the chip, the following can be obtained: Fig.11 The tenth intermediate structure shown. Fig.11 As shown, the rewiring structure includes a rewiring layer 90, which is located on the surface of the insulating material layer 81 away from the carrier 34. The rewiring layer 90 includes a plurality of trace structures 91, and each trace structure 91 is electrically connected to the trace structure 71 through a conductive portion 82 located in a through hole 811. In other embodiments, the rewiring structure may include two or more rewiring layers.

[0113] In one embodiment, the method for manufacturing the semiconductor structure further comprises the following steps: removing the carrier, and cutting the obtained structure to obtain a plurality of semiconductor structures. Each semiconductor structure comprises at least one chip.

[0114] Through this step, we can obtain Fig.12 The semiconductor structure shown. Fig.12 As shown, the semiconductor structure includes a first chip 50 and a structure to be packaged 20 , and the electrical element 21 of the structure to be packaged 20 is electrically connected to the pad 51 of the first chip 50 through a conductive frame 10 and a trace structure 71 .

[0115] In one embodiment, before the step of removing the carrier and cutting the obtained structure, the method for manufacturing the semiconductor structure further comprises the following step: forming a plurality of conductive balls on the surface of the redistribution layer which is the largest distance from the first chip. In this embodiment, the semiconductor structure finally obtained is as follows Fig.13 As shown, at least one conductive ball 93 is formed on the surface of each trace structure 91. The semiconductor structure can be soldered on the circuit board through the conductive ball 93, which facilitates the connection between the semiconductor structure and the circuit board. The material of the conductive ball 93 can be solder paste, metal tin, tin alloy or nickel gold.

[0116] In one embodiment, Fig.13 As shown, the semiconductor structure further includes an insulating layer 83 , the insulating film layer 83 covers the rewiring layer 90 , and the trace structure 91 of the rewiring layer 90 is away from the surface of the first chip 50 and exposed from the insulating film layer 83 . The insulating film layer 83 can protect the rewiring layer 90 .

[0117] The present application also provides a semiconductor structure, such as Fig.12 and Fig.13 As shown, the semiconductor structure includes a conductive frame 10 , a packaging structure 20 , a plastic packaging layer 40 , a first chip 50 , an insulating layer 60 and a redistribution layer 70 .

[0118] The conductive frame 10 includes a carrier 11 and a conductive column 12. The package structure 20 includes at least one electrical element 21. The package structure 20 is located on the carrier 11. The package structure 20 includes electrodes, and the electrodes of the package structure 20 are welded to the carrier 11. The plastic encapsulation layer 40 encapsulates the conductive frame 10 and the package structure 20, and the surface of the carrier 11 away from the package structure 20 and the surface of the conductive column 12 on the same side are exposed to the plastic encapsulation layer 40. The first chip 50 is located on the side of the carrier 11 away from the package structure 20; the first chip 50 includes a chip front, a chip back opposite to the chip front, and a chip side connecting the chip front and the chip back, and a plurality of pads 51 are provided on the chip front; the chip back faces the carrier 11. The insulating layer 60 at least covers the chip side. The rewiring layer 70 is located on a side of the insulating layer 60 away from the plastic layer 40 . The rewiring layer 70 is electrically connected to the pad 51 , and is electrically connected to the electrode of the packaging structure 20 through the conductive frame 10 .

[0119] The embodiment of the semiconductor structure provided in the embodiment of the present application and the embodiment of the method for manufacturing the semiconductor structure belong to the same inventive concept, and the description of the relevant details and beneficial effects can be referred to each other, and will not be repeated here.

[0120] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It is also understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it is understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it may be the only layer between the two layers or two elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0121] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the disclosure disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0122] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: The manufacturing method comprises: An intermediate structure is formed, wherein the intermediate structure includes a carrier, a conductive frame and a structure to be packaged; the conductive frame includes a bearing portion and a conductive column, and the bearing portion and the conductive column are mounted on the carrier; the structure to be packaged includes at least one electrical component, the structure to be packaged includes an electrode, the structure to be packaged is located on the bearing portion, and the electrode of the structure to be packaged is electrically connected to the bearing portion; forming a plastic encapsulation layer, wherein the plastic encapsulation layer encapsulates the conductive frame and the structure to be encapsulated; The carrier is removed, and the surface of the carrier portion away from the structure to be packaged and the surface of the conductive pillar located on the same side are exposed; A first chip is arranged on a side of the carrier away from the structure to be packaged, the first chip comprising a chip front, a chip back opposite to the chip front, and a chip side surface connecting the chip front and the chip back, the chip front is provided with a plurality of pads; the chip back faces the carrier; forming an insulating layer, wherein the insulating layer at least covers a side surface of the chip; A rewiring layer is formed on a side of the insulating layer away from the plastic encapsulation layer. The rewiring layer is electrically connected to the pad and is electrically connected to the electrode of the structure to be packaged through the conductive frame.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The forming of the intermediate structure comprises: Arranging the structure to be packaged on the bearing part of the conductive frame, and welding the electrodes of the structure to be packaged to the bearing part by using a reflow soldering process; An adhesive layer is arranged on the carrier board, and the conductive frame is attached to the carrier board through the adhesive layer.

3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that: The step of mounting the conductive frame on the carrier through the adhesive layer comprises: The plurality of conductive frames are mounted on the carrier through an adhesive layer.

4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The orthographic projection of the first chip on the conductive frame entirely falls on the conductive frame.

5. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: After the plastic encapsulation layer is formed, the method for manufacturing the semiconductor structure further includes: The surface of the plastic packaging layer away from the bearing portion is thinned to expose the surface of the conductive column away from the bearing portion.

6. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The first chip is arranged on a side of the carrier away from the structure to be packaged, comprising: A conductive material is disposed on a surface of the conductive frame and a surface of the bearing portion that are located on the same side away from the structure to be packaged, wherein the conductive material includes at least one of silver paste and solder paste; The first chip is placed on the conductive material, and the conductive material is cured.

7. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The structure to be packaged is arranged on the bearing part of the conductive frame, and the electrodes of the structure to be packaged are welded to the bearing part by a reflow soldering process, including: Using a screen printing process to arrange solder on the bearing portion; The structure to be packaged is placed on the solder, and the electrodes of the structure to be packaged are welded to the supporting part by using a reflow soldering process.

8. The method for manufacturing a semiconductor structure according to claim 1, wherein: The structure to be packaged only includes the electrical component, the electrical component is a passive device, and the electrodes of the structure to be packaged are pins of the electrical component; the passive device includes at least one of an inductor, a resistor and a capacitor; or, The structure to be packaged also includes an encapsulation layer that encapsulates the electrical component and a conductive structure that exposes the encapsulation layer. The conductive structure is an electrode of the structure to be packaged and is electrically connected to the pins of the electrical component. The electrical component includes at least one of an inductor, a resistor, a capacitor and a second chip.

9. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The conductive frame includes a conductive block; the rewiring layer includes a plurality of trace structures, and at least two of the trace structures are electrically connected to the same conductive block through through holes penetrating the insulating layer.

10. A semiconductor structure, characterized in that: The semiconductor structure comprises: A conductive frame, comprising a bearing portion and a conductive column; A packaging structure, comprising at least one electrical component, the packaging structure being located on the carrier, the packaging structure comprising electrodes, and the electrodes of the packaging structure being welded to the carrier; A plastic encapsulation layer encapsulating the conductive frame and the packaging structure, wherein a surface of the bearing portion away from the packaging structure and a surface of the conductive column on the same side are exposed; A first chip is located on a side of the carrier away from the packaging structure; the first chip comprises a chip front, a chip back opposite to the chip front, and a chip side connecting the chip front and the chip back, the chip front is provided with a plurality of pads; the chip back faces the carrier; An insulating layer, covering at least a side surface of the chip; The rewiring layer is located on a side of the insulating layer away from the plastic packaging layer. The rewiring layer is electrically connected to the welding pad and is electrically connected to the electrode of the packaging structure through the conductive frame.

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